repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
nickg/nvc
|
test/lower/record1.vhd
| 1 | 355 |
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
p1: process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
end process;
end architecture;
|
gpl-3.0
|
52864fb84c8e8bd97095ee5d12f4771b
| 0.501408 | 3.380952 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/ret01/tb_ret03.vhdl
| 1 | 570 |
entity tb_ret03 is
end tb_ret03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ret03 is
signal d : std_logic_vector (7 downto 0);
signal r : integer;
begin
dut: entity work.ret03
port map (d, r);
process
begin
d <= x"01";
wait for 1 ns;
assert r = 0 severity failure;
d <= x"1f";
wait for 1 ns;
assert r = 4 severity failure;
d <= x"e2";
wait for 1 ns;
assert r = 7 severity failure;
d <= x"00";
wait for 1 ns;
assert r = -1 severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
39f4dc53c121e340eb3a1550ad0c6d8d
| 0.601754 | 3.149171 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug035/vectors.vhdl
| 2 | 36,548 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
package vectors is
-- ==========================================================================
-- Type declarations
-- ==========================================================================
-- STD_LOGIC_VECTORs
subtype T_SLV_2 is STD_LOGIC_VECTOR(1 downto 0);
subtype T_SLV_3 is STD_LOGIC_VECTOR(2 downto 0);
subtype T_SLV_4 is STD_LOGIC_VECTOR(3 downto 0);
subtype T_SLV_8 is STD_LOGIC_VECTOR(7 downto 0);
subtype T_SLV_12 is STD_LOGIC_VECTOR(11 downto 0);
subtype T_SLV_16 is STD_LOGIC_VECTOR(15 downto 0);
subtype T_SLV_24 is STD_LOGIC_VECTOR(23 downto 0);
subtype T_SLV_32 is STD_LOGIC_VECTOR(31 downto 0);
subtype T_SLV_48 is STD_LOGIC_VECTOR(47 downto 0);
subtype T_SLV_64 is STD_LOGIC_VECTOR(63 downto 0);
subtype T_SLV_96 is STD_LOGIC_VECTOR(95 downto 0);
subtype T_SLV_128 is STD_LOGIC_VECTOR(127 downto 0);
subtype T_SLV_256 is STD_LOGIC_VECTOR(255 downto 0);
subtype T_SLV_512 is STD_LOGIC_VECTOR(511 downto 0);
-- STD_LOGIC_VECTOR_VECTORs
-- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx
type T_SLVV_2 is array(NATURAL range <>) of T_SLV_2;
type T_SLVV_3 is array(NATURAL range <>) of T_SLV_3;
type T_SLVV_4 is array(NATURAL range <>) of T_SLV_4;
type T_SLVV_8 is array(NATURAL range <>) of T_SLV_8;
type T_SLVV_12 is array(NATURAL range <>) of T_SLV_12;
type T_SLVV_16 is array(NATURAL range <>) of T_SLV_16;
type T_SLVV_24 is array(NATURAL range <>) of T_SLV_24;
type T_SLVV_32 is array(NATURAL range <>) of T_SLV_32;
type T_SLVV_48 is array(NATURAL range <>) of T_SLV_48;
type T_SLVV_64 is array(NATURAL range <>) of T_SLV_64;
type T_SLVV_128 is array(NATURAL range <>) of T_SLV_128;
type T_SLVV_256 is array(NATURAL range <>) of T_SLV_256;
type T_SLVV_512 is array(NATURAL range <>) of T_SLV_512;
-- STD_LOGIC_MATRIXs
type T_SLM is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC;
-- ATTENTION:
-- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
-- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z'));
-- 2. Xilinx iSIM work-around: DON'T use myMatrix'range(n) for n >= 2
-- because: myMatrix'range(2) returns always myMatrix'range(1); tested with ISE/iSIM 14.2
-- USAGE NOTES:
-- dimmension 1 => rows - e.g. Words
-- dimmension 2 => columns - e.g. Bits/Bytes in a word
-- ==========================================================================
-- Function declarations
-- ==========================================================================
-- slicing boundary calulations
function low (lenvec : T_POSVEC; index : NATURAL) return NATURAL;
function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL;
-- Assign procedures: assign_*
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL); -- assign vector to complete row
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL); -- assign short vector to row starting at position
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL); -- assign short vector to row in range high:low
procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL); -- assign vector to complete column
-- ATTENTION: see T_SLM definition for further details and work-arounds
-- Matrix to matrix conversion: slm_slice*
function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width
function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all rows in RowIndex range high:low
function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all columns in ColIndex range high:low
-- Matrix concatenation: slm_merge_*
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
-- Matrix to vector conversion: get_*
function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix column
function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix row
function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR; -- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR; -- get a sub vector of a matrix row at high:low
-- Convert to vector: to_slv
function to_slv(slvv : T_SLVV_2) return STD_LOGIC_VECTOR; -- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_4) return STD_LOGIC_VECTOR; -- ...
function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR; -- ...
function to_slv(slvv : T_SLVV_12) return STD_LOGIC_VECTOR; -- ...
function to_slv(slvv : T_SLVV_16) return STD_LOGIC_VECTOR; -- ...
function to_slv(slvv : T_SLVV_24) return STD_LOGIC_VECTOR; -- ...
function to_slv(slvv : T_SLVV_32) return STD_LOGIC_VECTOR; -- ...
function to_slv(slvv : T_SLVV_64) return STD_LOGIC_VECTOR; -- ...
function to_slv(slvv : T_SLVV_128) return STD_LOGIC_VECTOR; -- ...
function to_slv(slm : T_SLM) return STD_LOGIC_VECTOR; -- convert matrix to flatten vector
-- Convert flat vector to avector-vector: to_slvv_*
function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4; --
function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8; --
function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12; --
function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16; --
function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32; --
function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64; --
function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128; --
function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256; --
function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512; --
-- Convert matrix to avector-vector: to_slvv_*
function to_slvv_4(slm : T_SLM) return T_SLVV_4; --
function to_slvv_8(slm : T_SLM) return T_SLVV_8; --
function to_slvv_12(slm : T_SLM) return T_SLVV_12; --
function to_slvv_16(slm : T_SLM) return T_SLVV_16; --
function to_slvv_32(slm : T_SLM) return T_SLVV_32; --
function to_slvv_64(slm : T_SLM) return T_SLVV_64; --
function to_slvv_128(slm : T_SLM) return T_SLVV_128; --
function to_slvv_256(slm : T_SLM) return T_SLVV_256; --
function to_slvv_512(slm : T_SLM) return T_SLVV_512; --
-- Convert vector-vector to matrix: to_slm
function to_slm(slv : STD_LOGIC_VECTOR; ROWS : POSITIVE; COLS : POSITIVE) return T_SLM; -- create matrix from vector
function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector
-- Change vector direction
function dir(slvv : T_SLVV_8) return T_SLVV_8;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4;
function rev(slvv : T_SLVV_8) return T_SLVV_8;
function rev(slvv : T_SLVV_12) return T_SLVV_12;
function rev(slvv : T_SLVV_16) return T_SLVV_16;
function rev(slvv : T_SLVV_32) return T_SLVV_32;
function rev(slvv : T_SLVV_64) return T_SLVV_64;
function rev(slvv : T_SLVV_128) return T_SLVV_128;
function rev(slvv : T_SLVV_256) return T_SLVV_256;
function rev(slvv : T_SLVV_512) return T_SLVV_512;
-- TODO:
function resize(slm : T_SLM; size : POSITIVE) return T_SLM;
-- to_string
function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING;
function to_string(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'b') return STRING;
end package vectors;
package body vectors is
-- slicing boundary calulations
-- ==========================================================================
function low(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
variable pos : NATURAL := 0;
begin
for i in lenvec'low to index - 1 loop
pos := pos + lenvec(i);
end loop;
return pos;
end function;
function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
variable pos : NATURAL := 0;
begin
for i in lenvec'low to index loop
pos := pos + lenvec(i);
end loop;
return pos - 1;
end function;
-- Assign procedures: assign_*
-- ==========================================================================
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL) is
variable temp : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); tested with ISE/iSIM 14.2
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL) is
variable temp : STD_LOGIC_VECTOR(Position + slv'length - 1 downto Position);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL) is
variable temp : STD_LOGIC_VECTOR(High downto Low);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL) is
variable temp : STD_LOGIC_VECTOR(slm'range(1));
begin
temp := slv;
for i in temp'range loop
slm(i, ColIndex) <= temp(i);
end loop;
end procedure;
-- Matrix to matrix conversion: slm_slice*
-- ==========================================================================
function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM is
variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to Height - 1 loop
for j in 0 to Width - 1 loop
Result(i, j) := slm(RowIndex + i, ColIndex + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is
variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to High - Low loop
for j in 0 to slm'length(2) - 1 loop
Result(i, j) := slm(Low + i, slm'low(2) + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is
variable Result : T_SLM(slm'length(1) - 1 downto 0, High - Low downto 0) := (others => (others => '0'));
begin
for i in 0 to slm'length(1) - 1 loop
for j in 0 to High - Low loop
Result(i, j) := slm(slm'low(1) + i, Low + j);
end loop;
end loop;
return Result;
end function;
-- Matrix concatenation: slm_merge_*
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
constant ROWS : POSITIVE := slm1'length(1) + slm2'length(1);
constant COLUMNS : POSITIVE := slm1'length(2);
variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
begin
for i in slm1'range(1) loop
for j in slm1'low(2) to slm1'high(2) loop
slm(i, j) := slm1(i, j);
end loop;
end loop;
for i in slm2'range(1) loop
for j in slm2'low(2) to slm2'high(2) loop
slm(slm1'length(1) + i, j) := slm2(i, j);
end loop;
end loop;
return slm;
end function;
function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
constant ROWS : POSITIVE := slm1'length(1);
constant COLUMNS : POSITIVE := slm1'length(2) + slm2'length(2);
variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
begin
for i in slm1'range(1) loop
for j in slm1'low(2) to slm1'high(2) loop
slm(i, j) := slm1(i, j);
end loop;
for j in slm2'low(2) to slm2'high(2) loop
slm(i, slm1'length(2) + j) := slm2(i, j);
end loop;
end loop;
return slm;
end function;
-- Matrix to vector conversion: get_*
-- ==========================================================================
-- get a matrix column
function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(slm'range(1));
begin
for i in slm'range(1) loop
slv(i) := slm(i, ColIndex);
end loop;
return slv;
end function;
-- get a matrix row
function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR is
begin
return get_row(slm, RowIndex, (Length - 1), 0);
end function;
-- get a sub vector of a matrix row at high:low
function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(High downto Low); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_2) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 2) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 2) + 1 downto (i * 2)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_4) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 4) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 4) + 3 downto (i * 4)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 8) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 8) + 7 downto (i * 8)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_12) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 12) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 12) + 11 downto (i * 12)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_16) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 16) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 16) + 15 downto (i * 16)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_24) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 24) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 24) + 23 downto (i * 24)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_32) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 32) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 32) + 31 downto (i * 32)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_64) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 64) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 64) + 63 downto (i * 64)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_128) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 128) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 128) + 127 downto (i * 128)) := slvv(i);
end loop;
return slv;
end function;
-- convert matrix to flatten vector
function to_slv(slm : T_SLM) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slm'length(1) * slm'length(2)) - 1 downto 0);
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop -- Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); tested with ISE/iSIM 14.2
slv((i * slm'length(2)) + j) := slm(i, j);
end loop;
end loop;
return slv;
end function;
-- Convert flat vector to a vector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from vector (4 bit)
function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4 is
variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0);
begin
if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 4) + 3 downto (i * 4));
end loop;
return Result;
end function;
-- create vector-vector from vector (8 bit)
function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8 is
variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0);
begin
if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 8) + 7 downto (i * 8));
end loop;
return Result;
end function;
-- create vector-vector from vector (12 bit)
function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12 is
variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0);
begin
if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 12) + 11 downto (i * 12));
end loop;
return Result;
end function;
-- create vector-vector from vector (16 bit)
function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16 is
variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0);
begin
if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 16) + 15 downto (i * 16));
end loop;
return Result;
end function;
-- create vector-vector from vector (32 bit)
function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32 is
variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0);
begin
if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 32) + 31 downto (i * 32));
end loop;
return Result;
end function;
-- create vector-vector from vector (64 bit)
function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64 is
variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0);
begin
if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 64) + 63 downto (i * 64));
end loop;
return Result;
end function;
-- create vector-vector from vector (128 bit)
function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128 is
variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0);
begin
if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 128) + 127 downto (i * 128));
end loop;
return Result;
end function;
-- create vector-vector from vector (256 bit)
function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256 is
variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0);
begin
if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 256) + 255 downto (i * 256));
end loop;
return Result;
end function;
-- create vector-vector from vector (512 bit)
function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512 is
variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0);
begin
if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 512) + 511 downto (i * 512));
end loop;
return Result;
end function;
-- Convert matrix to avector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from matrix (4 bit)
function to_slvv_4(slm : T_SLM) return T_SLVV_4 is
variable Result : T_SLVV_4(slm'range(1));
begin
if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (8 bit)
function to_slvv_8(slm : T_SLM) return T_SLVV_8 is
variable Result : T_SLVV_8(slm'range(1));
begin
if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (12 bit)
function to_slvv_12(slm : T_SLM) return T_SLVV_12 is
variable Result : T_SLVV_12(slm'range(1));
begin
if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (16 bit)
function to_slvv_16(slm : T_SLM) return T_SLVV_16 is
variable Result : T_SLVV_16(slm'range(1));
begin
if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (32 bit)
function to_slvv_32(slm : T_SLM) return T_SLVV_32 is
variable Result : T_SLVV_32(slm'range(1));
begin
if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (64 bit)
function to_slvv_64(slm : T_SLM) return T_SLVV_64 is
variable Result : T_SLVV_64(slm'range(1));
begin
if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (128 bit)
function to_slvv_128(slm : T_SLM) return T_SLVV_128 is
variable Result : T_SLVV_128(slm'range(1));
begin
if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (256 bit)
function to_slvv_256(slm : T_SLM) return T_SLVV_256 is
variable Result : T_SLVV_256(slm'range);
begin
if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (512 bit)
function to_slvv_512(slm : T_SLM) return T_SLVV_512 is
variable Result : T_SLVV_512(slm'range(1));
begin
if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- Convert vector-vector to matrix: to_slm
-- ==========================================================================
-- create matrix from vector
function to_slm(slv : STD_LOGIC_VECTOR; ROWS : POSITIVE; COLS : POSITIVE) return T_SLM is
variable slm : T_SLM(ROWS - 1 downto 0, COLS - 1 downto 0);
begin
for i in 0 to ROWS - 1 loop
for j in 0 to COLS - 1 loop
slm(i, j) := slv((i * COLS) + j);
end loop;
end loop;
return slm;
end function;
-- create matrix from vector-vector
function to_slm(slvv : T_SLVV_4) return T_SLM is
variable slm : T_SLM(slvv'range, 3 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_4'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_8) return T_SLM is
-- variable test : STD_LOGIC_VECTOR(T_SLV_8'range);
-- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down
-- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimmension 2
variable slm : T_SLM(slvv'range, 7 downto 0);
begin
-- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE;
-- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE;
-- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE;
for i in slvv'range loop
for j in T_SLV_8'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_12) return T_SLM is
variable slm : T_SLM(slvv'range, 11 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_12'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_16) return T_SLM is
variable slm : T_SLM(slvv'range, 15 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_16'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_32) return T_SLM is
variable slm : T_SLM(slvv'range, 31 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_32'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_48) return T_SLM is
variable slm : T_SLM(slvv'range, 47 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_48'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_64) return T_SLM is
variable slm : T_SLM(slvv'range, 63 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_64'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_128) return T_SLM is
variable slm : T_SLM(slvv'range, 127 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_128'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_256) return T_SLM is
variable slm : T_SLM(slvv'range, 255 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_256'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_512) return T_SLM is
variable slm : T_SLM(slvv'range, 511 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_512'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
-- Change vector direction
-- ==========================================================================
function dir(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'reverse_range);
begin
Result := slvv;
return Result;
end function;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4 is
variable Result : T_SLVV_4(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_12) return T_SLVV_12 is
variable Result : T_SLVV_12(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_16) return T_SLVV_16 is
variable Result : T_SLVV_16(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_32) return T_SLVV_32 is
variable Result : T_SLVV_32(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_64) return T_SLVV_64 is
variable Result : T_SLVV_64(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_128) return T_SLVV_128 is
variable Result : T_SLVV_128(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_256) return T_SLVV_256 is
variable Result : T_SLVV_256(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_512) return T_SLVV_512 is
variable Result : T_SLVV_512(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
-- Resize functions
-- ==========================================================================
-- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input
-- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for
-- value-preserving resizes of the signed and unsigned data types.
function resize(slm : T_SLM; size : POSITIVE) return T_SLM is
variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0'));
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i, j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING is
constant hex_len : POSITIVE := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1);
variable Result : STRING(1 to hex_len) := (others => sep);
variable pos : POSITIVE := 1;
begin
for i in slvv'range loop
Result(pos to pos + 1) := to_string(slvv(i), 'h');
pos := pos + ite((sep = C_POC_NUL), 2, 3);
end loop;
return Result;
end function;
function to_string_bin(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'h') return STRING is
variable PerLineOverheader : POSITIVE := div_ceil(slm'length(2), groups);
variable Result : STRING(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10);
variable Writer : POSITIVE;
variable GroupCounter : NATURAL;
begin
Result := (others => C_POC_NUL);
Result(1) := LF;
Writer := 2;
GroupCounter := 0;
for i in slm'low(1) to slm'high(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(Writer) := to_char(slm(i, j));
Writer := Writer + 1;
GroupCounter := GroupCounter + 1;
if (GroupCounter = groups) then
Result(Writer) := ' ';
Writer := Writer + 1;
GroupCounter := 0;
end if;
end loop;
Result(Writer - 1) := LF;
GroupCounter := 0;
end loop;
return str_trim(Result);
end function;
function to_string(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'b') return STRING is
begin
if (format = 'b') then
return to_string_bin(slm, groups);
else
return "Format not supported.";
end if;
end function;
end package body;
|
gpl-2.0
|
7d3f07f07678c77f6a45b5defefca0ca
| 0.623098 | 2.985216 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dispin01/tb_rec03.vhdl
| 1 | 671 |
entity tb_rec03 is
end tb_rec03;
library ieee;
use ieee.std_logic_1164.all;
use work.rec03_pkg.all;
architecture behav of tb_rec03 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec03
port map (inp => inp, o => r);
process
begin
inp.a <= s0;
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= s2;
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= s2;
inp.b <= '0';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= s3;
inp.b <= '0';
wait for 1 ns;
assert r = '1' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
3c92ef3ffc5dceac3c7712250e4395b8
| 0.567809 | 2.904762 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue736/simple_fsm.vhdl
| 1 | 880 |
--Standard Library
library ieee;
--Standard Packages
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity simple_fsm is
port (
clk : in std_logic;
rst : in std_logic;
valid : in std_logic;
invalid : in std_logic
);
end simple_fsm;
architecture rtl of simple_fsm is
type t_states is (e_IDLE, e_S1);
signal p_state : t_states := e_IDLE;
signal n_state : t_states;
begin
p_sync_fsm : process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
p_state <= e_IDLE;
else
p_state <= n_state;
end if;
end if;
end process;
p_comb_fsm : process (all)
begin
case p_state is
when e_IDLE =>
n_state <= e_S1 when valid = '1' else e_IDLE;
when e_S1 =>
n_state <= e_IDLE when (valid = '0' and invalid = '1') else e_S1;
end case;
end process;
end rtl;
|
gpl-2.0
|
6d63dbdb38fc4e43741cbbd904531a15
| 0.581818 | 3.013699 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc485.vhd
| 4 | 5,887 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc485.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p19n01i00485ent_a IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END c03s02b01x01p19n01i00485ent_a;
architecture c03s02b01x01p19n01i00485ent_a of c03s02b01x01p19n01i00485ent_a is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00485ent IS
END c03s02b01x01p19n01i00485ent;
ARCHITECTURE c03s02b01x01p19n01i00485arch OF c03s02b01x01p19n01i00485ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
type array_rec_2cons is array (integer range <>) of record_2cons_array;
function resolution12(i:in array_rec_2cons) return record_2cons_array is
variable temp : record_2cons_array := C52;
begin
return temp;
end resolution12;
subtype array_rec_2cons_state is resolution12 record_2cons_array;
constant C66 : array_rec_2cons_state:= C52;
function complex_scalar(s : array_rec_2cons_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_2cons_state is
begin
return C66;
end scalar_complex;
component c03s02b01x01p19n01i00485ent_a1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : c03s02b01x01p19n01i00485ent_a1 use entity work.c03s02b01x01p19n01i00485ent_a(c03s02b01x01p19n01i00485ent_a);
signal S1 : array_rec_2cons_state;
signal S2 : array_rec_2cons_state;
signal S3 : array_rec_2cons_state:= C66;
BEGIN
T1: c03s02b01x01p19n01i00485ent_a1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00485"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00485 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00485arch;
|
gpl-2.0
|
4d96daf95f2dbf7e26f96eddabfcb121
| 0.636827 | 3.36016 | false | false | false | false |
nickg/nvc
|
test/regress/signal21.vhd
| 1 | 1,648 |
package pack is
type nat_vector is array (natural range <>) of natural;
end package;
-------------------------------------------------------------------------------
entity sub1 is
port ( x : out natural );
end entity;
architecture test of sub1 is
begin
p1: process is
begin
x <= 1;
wait for 0 ns;
assert x'event;
assert x'active;
wait for 0 ns;
x <= 5;
wait for 0 ns;
assert x'event;
assert x'active;
x <= 5;
wait for 0 ns;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub2 is
port ( z : in nat_vector(1 to 3) );
end entity;
architecture test of sub2 is
begin
p2: process is
begin
assert z = (0, 2, 3);
wait for 0 ns;
assert z = (1, 2, 3);
assert z'active;
assert z'event;
assert z(1)'event;
wait for 0 ns ;
assert not z'active;
assert not z'event;
wait for 0 ns;
assert z = (5, 2, 3);
assert z'active;
assert z'event;
wait for 0 ns ;
assert z'active;
assert not z'event;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity signal21 is
end entity;
architecture test of signal21 is
signal y : natural;
begin
u1: entity work.sub1
port map ( y );
u2: entity work.sub2
port map (
z(1) => y,
z(2) => 2,
z(3) => 3 );
end architecture;
|
gpl-3.0
|
1b7f630be217ae3b355a62527de198e0
| 0.445388 | 4.069136 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jnsth.vhd
| 4 | 3,873 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-jnsth.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library qsim;
use std.textio.all;
architecture join_synth of test_bench is
use qsim.qsim_types.all;
constant num_outputs : positive := 4;
signal fork_arc : arc_vector(1 to num_outputs);
signal join_arc : arc_type;
signal info_detail : info_detail_type := trace;
begin
generator : process is
begin
fork_arc(1) <= (true, ("generator ", 9, 0, now));
fork_arc(2) <= (true, ("generator ", 9, 1, now)); wait for 0 ns;
fork_arc(3) <= (true, ("generator ", 9, 2, now));
fork_arc(4) <= (true, ("generator ", 9, 3, now)); wait for 10 ns;
fork_arc(1) <= (false, ("generator ", 9, 4, now));
fork_arc(2) <= (false, ("generator ", 9, 5, now)); wait for 0 ns;
fork_arc(3) <= (false, ("generator ", 9, 6, now));
fork_arc(4) <= (false, ("generator ", 9, 7, now)); wait for 0 ns;
fork_arc(1) <= (true, ("generator ", 9, 8, now));
fork_arc(2) <= (true, ("generator ", 9, 9, now)); wait for 0 ns;
fork_arc(3) <= (true, ("generator ", 9, 10, now));
fork_arc(4) <= (true, ("generator ", 9, 11, now)); wait for 0 ns;
fork_arc(1) <= (false, ("generator ", 9, 12, now));
fork_arc(2) <= (false, ("generator ", 9, 13, now)); wait for 0 ns;
fork_arc(3) <= (false, ("generator ", 9, 14, now));
fork_arc(4) <= (false, ("generator ", 9, 15, now)); wait for 10 ns;
wait;
end process generator;
join1 : entity qsim.join(behavior)
generic map ( name => "join1",
time_unit => ns,
info_file_name => "join1.dat" )
port map ( in_arc => fork_arc,
out_arc => join_arc,
info_detail => info_detail );
sink1 : entity qsim.sink(behavior)
generic map ( name => "sink1",
time_unit => ns,
info_file_name => "sink1.dat" )
port map ( in_arc => join_arc,
info_detail => info_detail );
forks : for index in 1 to num_outputs generate
constant index_string : string := integer'image(index);
begin
fork_monitor : process
variable L : line;
begin
wait on fork_arc(index);
write(L, string'("fork_monitor(" & index_string & "): at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, fork_arc(index).token, ns);
writeline(output, L);
end process fork_monitor;
end generate forks;
sink_monitor : process
variable L : line;
begin
wait on join_arc;
write(L, string'("sink_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, join_arc.token, ns);
writeline(output, L);
end process sink_monitor;
end architecture join_synth;
|
gpl-2.0
|
ae54e97a20b1d752b9e3a7223df5b150
| 0.542732 | 3.549954 | false | false | false | false |
nickg/nvc
|
test/parse/process.vhd
| 1 | 388 |
entity b is
end entity;
architecture a of b is
signal x : integer := 0;
begin
p: process is
begin
end process;
process
variable y : integer := 5;
begin
x <= y;
end process;
process (x) is
begin
x <= x + 1;
end process;
postponed process is
begin
end process;
postponed assert x = 1;
end architecture;
|
gpl-3.0
|
a893fcdccf422e96ef45dadb9f2f0c2b
| 0.554124 | 3.959184 | false | false | false | false |
tgingold/ghdl
|
libraries/openieee/v87/numeric_std.vhdl
| 2 | 10,556 |
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
type UNSIGNED is array (natural range <>) of STD_LOGIC;
type SIGNED is array (natural range <>) of STD_LOGIC;
function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED;
function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED;
-- Convert 'H' and '1' to '1', 'L' and '0' to '0'.
-- If any other value is present, return (others => XMAP)
-- Issue a warning in that case, and if S is a null array.
-- Result index range is S'Length - 1 downto 0.
function std_match (l, r : std_ulogic) return boolean;
function std_match (l, r : std_ulogic_vector) return boolean;
function std_match (l, r : std_logic_vector) return boolean;
function std_match (l, r : UNSIGNED) return boolean;
function std_match (l, r : SIGNED) return boolean;
-- Return True iff L and R matches.
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
function TO_INTEGER (ARG : SIGNED) return INTEGER;
-- Convert ARG to an integer.
-- Simulation is aborted in case of overflow.
-- Issue a warning in case of non-logical value.
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
-- Convert ARG to unsigned.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
-- Convert ARG to signed.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED;
-- Result index range is NEW_SIZE - 1 downto 0 (unless null array).
-- For SIGNED, the sign of the result is the sign of ARG.
function "=" (L, R : UNSIGNED) return BOOLEAN;
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "/=" (L, R : UNSIGNED) return BOOLEAN;
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<" (L, R : UNSIGNED) return BOOLEAN;
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<=" (L, R : UNSIGNED) return BOOLEAN;
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">" (L, R : UNSIGNED) return BOOLEAN;
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">=" (L, R : UNSIGNED) return BOOLEAN;
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "=" (L, R : SIGNED) return BOOLEAN;
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "/=" (L, R : SIGNED) return BOOLEAN;
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<" (L, R : SIGNED) return BOOLEAN;
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<=" (L, R : SIGNED) return BOOLEAN;
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">" (L, R : SIGNED) return BOOLEAN;
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">=" (L, R : SIGNED) return BOOLEAN;
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Issue a warning in case of non-logical value.
function "-" (ARG : SIGNED) return SIGNED;
-- Compute -ARG.
-- Result index range is Arg'length - 1 downto 0.
function "abs" (ARG : SIGNED) return SIGNED;
-- Compute abs ARG.
-- Result index range is Arg'length - 1 downto 0.
function "+" (L, R : UNSIGNED) return UNSIGNED;
function "+" (L, R : SIGNED) return SIGNED;
function "-" (L, R : UNSIGNED) return UNSIGNED;
function "-" (L, R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is max (L'Length, R'Length) - 1 downto 0.
-- Issue a warning in case of non-logical value.
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "+" (L : SIGNED; R : INTEGER) return SIGNED;
function "+" (L : INTEGER; R : SIGNED) return SIGNED;
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "-" (L : SIGNED; R : INTEGER) return SIGNED;
function "-" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is V'Length - 1 downto 0, where V is the vector
-- parameter.
-- Issue a warning in case of non-logical value.
-- Issue a warning if value is truncated.
function "*" (L, R : UNSIGNED) return UNSIGNED;
function "*" (L, R : SIGNED) return SIGNED;
-- Compute L * R
-- Result index range is L'Length + R'Length - 1 downto 0.
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "*" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L * R
-- R is converted to a vector of length L'length
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "*" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L * R
-- L is converted to a vector of length R'length
function "/" (L, R : UNSIGNED) return UNSIGNED;
function "/" (L, R : SIGNED) return SIGNED;
function "rem" (L, R : UNSIGNED) return UNSIGNED;
function "rem" (L, R : SIGNED) return SIGNED;
function "mod" (L, R : UNSIGNED) return UNSIGNED;
function "mod" (L, R : SIGNED) return SIGNED;
-- Compute L op R
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "/" (L : SIGNED; R : INTEGER) return SIGNED;
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "rem" (L : SIGNED; R : INTEGER) return SIGNED;
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "mod" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L op R.
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "/" (L : INTEGER; R : SIGNED) return SIGNED;
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "rem" (L : INTEGER; R : SIGNED) return SIGNED;
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "mod" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L op R.
-- Result index range is R'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
-- Result may be truncated.
function "not" (l : UNSIGNED) return UNSIGNED;
function "not" (l : SIGNED) return SIGNED;
function "and" (l, r : UNSIGNED) return UNSIGNED;
function "and" (l, r : SIGNED) return SIGNED;
function "nand" (l, r : UNSIGNED) return UNSIGNED;
function "nand" (l, r : SIGNED) return SIGNED;
function "or" (l, r : UNSIGNED) return UNSIGNED;
function "or" (l, r : SIGNED) return SIGNED;
function "nor" (l, r : UNSIGNED) return UNSIGNED;
function "nor" (l, r : SIGNED) return SIGNED;
function "xor" (l, r : UNSIGNED) return UNSIGNED;
function "xor" (l, r : SIGNED) return SIGNED;
--function "xnor" (l, r : UNSIGNED) return UNSIGNED;
--function "xnor" (l, r : SIGNED) return SIGNED;
-- Compute L OP R.
-- Result index range is L'Length - 1 downto 0.
-- No specific handling of null array: the index range of the result
-- would be -1 downto 0 (without warning). This it not what is specified
-- in 1076.3, but corresponds to the standard implementation.
-- No specific handling of non-logical values. Behaviour is compatible
-- with std_logic_1164.
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function rotate_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function rotate_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
--function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
--function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
--function "rol" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "rol" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
--function "ror" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
--function "ror" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
end NUMERIC_STD;
|
gpl-2.0
|
a1eece9a59468ae06a35ed3e853bfd2a
| 0.648352 | 3.579518 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/v_split3.vhd
| 2 | 1,357 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split3 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split3;
architecture augh of v_split3 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
gpl-2.0
|
8c27b18323930030139a18efb94fa847
| 0.668386 | 2.856842 | false | false | false | false |
tgingold/ghdl
|
libraries/openieee/v93/numeric_bit-body.vhdl
| 1 | 68,342 |
-- This -*- vhdl -*- file was generated from numeric_bit-body.proto
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric bit package body.
-- The implementation is based only on the specifications.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package body NUMERIC_BIT is
constant NO_WARNING : Boolean := False;
constant null_unsigned : unsigned (0 downto 1) := (others => '0');
constant null_signed : signed (0 downto 1) := (others => '0');
subtype nat1 is natural range 0 to 1;
type nat1_to_sl_type is array (nat1) of bit;
constant nat1_to_01 : nat1_to_sl_type := (0 => '0', 1 => '1');
subtype sl_01 is bit;
type carry_array is array (sl_01, sl_01, sl_01) of sl_01;
constant compute_carry : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '0'),
'1' => ('0' => '0', '1' => '1')),
'1' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '1')));
constant compute_sum : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '0')),
'1' => ('0' => ('0' => '1', '1' => '0'),
'1' => ('0' => '0', '1' => '1')));
type compare_type is (compare_unknown,
compare_lt,
compare_eq,
compare_gt);
function MAX (L, R : natural) return natural is
begin
if L > R then
return L;
else
return R;
end if;
end MAX;
function TO_INTEGER (ARG : UNSIGNED) return NATURAL
is
variable res : natural := 0;
begin
if arg'length = 0 then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
for i in arg'range loop
res := res + res;
if arg (i) = '1' then
res := res + 1;
end if;
end loop;
return res;
end TO_INTEGER;
function TO_INTEGER (ARG : SIGNED) return INTEGER
is
alias argn : SIGNED (ARG'Length -1 downto 0) is arg;
variable res : integer := 0;
variable b : bit;
begin
if argn'length = 0 then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
if argn (argn'left) = '1' then
-- Negative value
b := '0';
else
b := '1';
end if;
for i in argn'range loop
res := res + res;
if argn (i) = b then
res := res + 1;
end if;
end loop;
if b = '0' then
-- Avoid overflow.
res := -res - 1;
end if;
return res;
end TO_INTEGER;
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED
is
variable res : UNSIGNED (SIZE - 1 downto 0);
variable a : natural := arg;
variable d : nat1;
begin
if size = 0 then
return null_unsigned;
end if;
for i in res'reverse_range loop
d := a rem 2;
res (i) := nat1_to_01 (d);
a := a / 2;
end loop;
if a /= 0 then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED
is
variable res : SIGNED (SIZE - 1 downto 0);
variable v : integer := arg;
variable b0, b1 : bit;
variable d : nat1;
begin
if size = 0 then
return null_signed;
end if;
if arg < 0 then
-- Use one complement to avoid overflow:
-- -v = (not v) + 1
-- not v = -v - 1
-- not v = -(v + 1)
v := -(arg + 1);
b0 := '1';
b1 := '0';
else
v := arg;
b0 := '0';
b1 := '1';
end if;
for i in res'reverse_range loop
d := v rem 2;
v := v / 2;
if d = 0 then
res (i) := b0;
else
res (i) := b1;
end if;
end loop;
if v /= 0 or res (res'left) /= b0 then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_SIGNED;
function "+" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := la (i);
end if;
if i > ra'left then
rb := '0';
else
rb := ra (i);
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := la (i);
end if;
if i > ra'left then
rb := r (r'left);
else
rb := ra (i);
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := la (i);
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := ra (i);
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := la (i);
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := ra (i);
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "-" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := la (i);
end if;
if i > ra'left then
rb := '0';
else
rb := ra (i);
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := la (i);
end if;
if i > ra'left then
rb := r (r'left);
else
rb := ra (i);
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := la (i);
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := ra (i);
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := la (i);
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : bit;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := ra (i);
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "*" (L, R : UNSIGNED) return UNSIGNED
is
alias la : UNSIGNED (L'Length - 1 downto 0) is l;
alias ra : UNSIGNED (R'Length - 1 downto 0) is r;
variable res : UNSIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : bit;
begin
if la'length = 0 or ra'length = 0 then
return null_UNSIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left loop
rb := ra (i);
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Propagate carry.
for j in i + la'length to res'left loop
exit when carry = '0';
vb := res (j);
res (j) := carry xor vb;
carry := carry and vb;
end loop;
end if;
end loop;
return res;
end "*";
function "*" (L, R : SIGNED) return SIGNED
is
alias la : SIGNED (L'Length - 1 downto 0) is l;
alias ra : SIGNED (R'Length - 1 downto 0) is r;
variable res : SIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : bit;
begin
if la'length = 0 or ra'length = 0 then
return null_SIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left - 1 loop
rb := ra (i);
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Sign extend and propagate carry.
lb := la (la'left);
for j in i + l'length to res'left loop
vb := res (j);
res (j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
end if;
end loop;
if ra (ra'left) = '1' then
-- R is a negative number. It is considered as:
-- -2**n + (Rn-1 Rn-2 ... R0).
-- Compute res := res - 2**n * l.
carry := '1';
for i in la'reverse_range loop
vb := res (ra'length - 1 + i);
lb := not la (i);
res (ra'length - 1+ i) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
vb := res (res'left);
lb := not la (la'left);
res (res'left) := compute_sum (carry, vb, lb);
end if;
return res;
end "*";
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return l * to_UNSIGNED (r, size);
end "*";
function "*" (L : SIGNED; R : INTEGER) return SIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return l * to_SIGNED (r, size);
end "*";
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return r * to_UNSIGNED (l, size);
end "*";
function "*" (L : INTEGER; R : SIGNED) return SIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return r * to_SIGNED (l, size);
end "*";
function has_0x (a : UNSIGNED) return bit
is
variable res : bit := '0';
begin
for i in a'range loop
res := res or a (i);
end loop;
return res;
end has_0x;
-- All index range are normalized (N downto 0).
-- NUM and QUOT have the same range.
-- DEM and REMAIN have the same range.
-- No 'X'.
procedure divmod (num, dem : UNSIGNED; quot, remain : out UNSIGNED)
is
variable reg : unsigned (dem'left + 1 downto 0) := (others => '0');
variable sub : unsigned (dem'range) := (others => '0');
variable carry, d : bit;
begin
for i in num'range loop
-- Shift
reg (reg'left downto 1) := reg (reg'left - 1 downto 0);
reg (0) := num (i);
-- Substract
carry := '1';
for j in dem'reverse_range loop
d := not dem (j);
sub (j) := compute_sum (carry, reg (j), d);
carry := compute_carry (carry, reg (j), d);
end loop;
carry := compute_carry (carry, reg (reg'left), '1');
-- Test
if carry = '0' then
-- Greater than
quot (i) := '0';
else
quot (i) := '1';
reg (reg'left) := '0';
reg (sub'range) := sub;
end if;
end loop;
remain := reg (dem'range);
end divmod;
function size_unsigned (n : natural) return natural
is
-- At least one bit (even for 0).
variable res : natural := 1;
variable n1 : natural := n;
begin
while n1 > 1 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_unsigned;
function size_signed (n : integer) return natural
is
variable res : natural := 1;
variable n1 : natural;
begin
if n >= 0 then
n1 := n;
else
-- Use /N = -X -1 = -(X + 1) (No overflow).
n1 := -(n + 1);
end if;
while n1 /= 0 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_signed;
function "/" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : bit := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return quot;
end "/";
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return l / to_unsigned (r, r_size);
end "/";
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return resize (to_unsigned (l, l_size) / r, r'length);
end "/";
function "rem" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : bit := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "rem";
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l rem to_unsigned (r, r_size), l'length);
end "rem";
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) rem r;
end "rem";
function "mod" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : bit := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "mod";
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l mod to_unsigned (r, r_size), l'length);
end "mod";
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) mod r;
end "mod";
function has_0x (a : SIGNED) return bit
is
variable res : bit := '0';
begin
for i in a'range loop
res := res or a (i);
end loop;
return res;
end has_0x;
function "-" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : bit;
begin
if arga'length = 0 then
return null_signed;
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "-";
function "abs" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : bit;
begin
if arga'length = 0 then
return null_signed;
end if;
if arga (arga'left) = '0' then
return arga;
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "abs";
function "/" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : bit := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
if (ra (ra'left) xor la (la'left)) = '1' then
return -signed (quot);
else
return signed (quot);
end if;
end "/";
function "/" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return l / to_signed (r, r_size);
end "/";
function "/" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return resize (to_signed (l, max (l_size, r'length)) / r, r'length);
end "/";
function "rem" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : bit := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of rem has the sign of the dividend.
if la (la'left) = '1' then
return -signed (rema);
else
return signed (rema);
end if;
end "rem";
function "rem" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l rem to_signed (r, r_size), l'length);
end "rem";
function "rem" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) rem r;
end "rem";
function "mod" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : bit := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of mod has the sign of the divisor.
if rema = r_utype'(others => '0') then
-- If the remainder is 0, then the modulus is 0.
return signed (rema);
else
if ra (ra'left) = '1' then
if la (la'left) = '1' then
return -signed (rema);
else
return ra + signed (rema);
end if;
else
if la (la'left) = '1' then
return ra - signed (rema);
else
return signed (rema);
end if;
end if;
end if;
end "mod";
function "mod" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l mod to_signed (r, r_size), l'length);
end "mod";
function "mod" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) mod r;
end "mod";
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED
is
alias arg1 : UNSIGNED (ARG'length - 1 downto 0) is arg;
variable res : UNSIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_UNSIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res := arg1 (res'range);
else
-- Expansion
res (arg1'range) := arg1;
end if;
return res;
end resize;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED
is
alias arg1 : SIGNED (ARG'length - 1 downto 0) is arg;
variable res : SIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_SIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res (res'left) := arg1 (arg1'left);
res (res'left - 1 downto 0) := arg1 (res'left - 1 downto 0);
else
-- Expansion
res (arg1'range) := arg1;
res (res'left downto arg1'length) := (others => arg1 (arg1'left));
end if;
return res;
end resize;
function "not" (l : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "not" (l : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "and" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "and" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "nand" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "nand" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "or" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "or" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "nor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "nor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function "xor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function "xnor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xnor"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) xnor ra (I);
end loop;
end if;
return res;
end "xnor";
function "xnor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xnor"": arguments are not of the same length"
severity failure;
res := (others => '0');
else
for I in res_type'range loop
res (I) := la (I) xnor ra (I);
end loop;
end if;
return res;
end "xnor";
function ucompare (l, r : UNSIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable lb, rb : bit;
variable res : compare_type;
begin
res := compare_eq;
for i in 0 to sz loop
if i > la'left then
lb := '0';
else
lb := la (i);
end if;
if i > ra'left then
rb := '0';
else
rb := ra (i);
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end ucompare;
function scompare (l, r : SIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable lb, rb : bit;
variable res : compare_type;
begin
-- Consider sign bit as S * -(2**N).
lb := la (la'left);
rb := ra (ra'left);
if lb = '1' and rb = '0' then
return compare_lt;
elsif lb = '0' and rb = '1' then
return compare_gt;
else
res := compare_eq;
end if;
for i in 0 to sz - 1 loop
if i > la'left then
lb := l (l'left);
else
lb := la (i);
end if;
if i > ra'left then
rb := r (r'left);
else
rb := ra (i);
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end scompare;
function ucompare (l : UNSIGNED; r : NATURAL) return compare_type
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable lb, rb : bit;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := la (i);
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if r1 /= 0 then
res := compare_lt;
end if;
return res;
end ucompare;
function scompare (l : SIGNED; r : INTEGER) return compare_type
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable lb, rb : bit;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := la (i);
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if l (l'left) = '1' then
if r >= 0 then
res := compare_lt;
end if;
else
if r < 0 then
res := compare_gt;
end if;
end if;
return res;
end scompare;
function "=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res = compare_eq;
end "=";
function "=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res = compare_eq;
end "=";
function "=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res = compare_eq;
end "=";
function "=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
return compare_eq = res;
end "=";
function "=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res = compare_eq;
end "=";
function "=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
return compare_eq = res;
end "=";
function "/=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res /= compare_eq;
end "/=";
function "/=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res /= compare_eq;
end "/=";
function "/=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res /= compare_eq;
end "/=";
function "/=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
return compare_eq /= res;
end "/=";
function "/=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res /= compare_eq;
end "/=";
function "/=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
return compare_eq /= res;
end "/=";
function ">" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res > compare_eq;
end ">";
function ">" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res > compare_eq;
end ">";
function ">" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res > compare_eq;
end ">";
function ">" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
return compare_eq > res;
end ">";
function ">" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res > compare_eq;
end ">";
function ">" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
return compare_eq > res;
end ">";
function ">=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res >= compare_eq;
end ">=";
function ">=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res >= compare_eq;
end ">=";
function ">=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res >= compare_eq;
end ">=";
function ">=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
return compare_eq >= res;
end ">=";
function ">=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res >= compare_eq;
end ">=";
function ">=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
return compare_eq >= res;
end ">=";
function "<" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res < compare_eq;
end "<";
function "<" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res < compare_eq;
end "<";
function "<" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res < compare_eq;
end "<";
function "<" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
return compare_eq < res;
end "<";
function "<" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res < compare_eq;
end "<";
function "<" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
return compare_eq < res;
end "<";
function "<=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res <= compare_eq;
end "<=";
function "<=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res <= compare_eq;
end "<=";
function "<=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
return res <= compare_eq;
end "<=";
function "<=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
return compare_eq <= res;
end "<=";
function "<=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
return res <= compare_eq;
end "<=";
function "<=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
return compare_eq <= res;
end "<=";
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
elsif count < 0 and count >= -arg1'left then
res (res'left + count downto 0) := arg1 (arg1'left downto -count);
end if;
return res;
end "sll";
function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
elsif count < 0 and count >= -arg1'left then
res (res'left downto -count) := arg1 (arg1'left + count downto 0);
end if;
return res;
end "srl";
function "rol" (ARG : UNSIGNED; COUNT: integer) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count mod res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end "rol";
function "ror" (ARG : UNSIGNED; COUNT: integer) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count mod res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end "ror";
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => arg1 (arg1'left));
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
elsif count < 0 and count >= -arg1'left then
res (res'left + count downto 0) := arg1 (arg1'left downto -count);
end if;
return res;
end "sll";
function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
elsif count < 0 and count >= -arg1'left then
res (res'left downto -count) := arg1 (arg1'left + count downto 0);
end if;
return res;
end "srl";
function "rol" (ARG : SIGNED; COUNT: integer) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count mod res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end "rol";
function "ror" (ARG : SIGNED; COUNT: integer) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count mod res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end "ror";
function rising_edge (signal s : bit) return boolean is
begin
return s'event and s = '1';
end rising_edge;
function falling_edge (signal s : bit) return boolean is
begin
return s'event and s = '0';
end falling_edge;
end NUMERIC_BIT;
|
gpl-2.0
|
ce65e967d52094cd71f7aab3f0fa75d1
| 0.548813 | 3.605296 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3080.vhd
| 4 | 4,178 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3080.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03080pkg is
type positive_cons_vector is array (15 downto 0) of positive;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
constant C19 : positive_cons_vectorofvector := (others => (others => 3));
end c12s06b02x00p06n01i03080pkg;
use work.c12s06b02x00p06n01i03080pkg.all;
ENTITY c12s06b02x00p06n01i03080ent_a IS
PORT
(
F1: OUT integer ;
F3: IN positive_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03080ent_a;
ARCHITECTURE c12s06b02x00p06n01i03080arch_a OF c12s06b02x00p06n01i03080ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03080arch_a;
use work.c12s06b02x00p06n01i03080pkg.all;
ENTITY c12s06b02x00p06n01i03080ent IS
END c12s06b02x00p06n01i03080ent;
ARCHITECTURE c12s06b02x00p06n01i03080arch OF c12s06b02x00p06n01i03080ent IS
function scalar_complex(s : integer) return positive_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN positive_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03080ent_a(c12s06b02x00p06n01i03080arch_a);
signal S1 : positive_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03080"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03080 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03080arch;
|
gpl-2.0
|
31643825631e26d013c1d03e8f9547d3
| 0.667544 | 3.355823 | false | true | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_wr_status_cntl.vhd
| 7 | 57,339 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
gpl-3.0
|
2eb7bf313fa02189ff57442b942468ac
| 0.411988 | 5.089562 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug061/dictp08.vhdl
| 2 | 5,539 |
library ieee;
use ieee.std_logic_1164.all;
package corelib_Dict is
generic (
type KEY_TYPE;
type VALUE_TYPE;
function to_hash(d : in KEY_TYPE; size : positive) return natural;
INIT_SIZE : natural := 128
);
type PT_DICT is protected
procedure Set (constant key : in KEY_TYPE; constant data : in VALUE_TYPE);
procedure Get (constant key : in KEY_TYPE; data : out VALUE_TYPE);
impure function Get (constant key : KEY_TYPE) return VALUE_TYPE;
procedure Del (constant key : in KEY_TYPE);
procedure Clear;
impure function HasKey (constant key : KEY_TYPE) return boolean;
impure function Count return natural;
end protected PT_DICT;
procedure Merge(d0 : inout PT_DICT; d1 : inout PT_DICT; dout : inout PT_DICT);
end package corelib_Dict;
package body corelib_Dict is
type t_key_ptr is access KEY_TYPE;
type t_data_ptr is access VALUE_TYPE;
type PT_DICT is protected body
type t_entry;
type t_entry_ptr is access t_entry;
type t_entry is record
key : t_key_ptr;
data : t_data_ptr;
last_entry : t_entry_ptr;
next_entry : t_entry_ptr;
end record t_entry;
type t_entry_array is array (0 to INIT_SIZE-1) of t_entry_ptr;
variable head : t_entry_array := (others => null);
variable entry_count : integer_vector(0 to INIT_SIZE-1) := (others => 0);
-- Private method to find entry stored in dictionary
impure function Find (constant key : KEY_TYPE) return t_entry_ptr;
impure function Find (constant key : KEY_TYPE) return t_entry_ptr is
variable entry : t_entry_ptr := head(to_hash(key, INIT_SIZE));
begin
while (entry /= null) loop
if (entry.key.all = key) then
return entry;
end if;
entry := entry.last_entry;
end loop;
return null;
end function Find;
procedure Set (constant key : in KEY_TYPE; constant data : in VALUE_TYPE) is
variable addr : natural := 0;
variable entry : t_entry_ptr := Find(key);
begin
if (entry = null) then
addr := to_hash(key, INIT_SIZE);
if (head(addr) /= null) then
entry := new t_entry;
entry.key := new KEY_TYPE'(key);
entry.data := new VALUE_TYPE'(data);
entry.last_entry := head(addr);
entry.next_entry := null;
head(addr) := entry;
head(addr).last_entry.next_entry := head(addr);
else
head(addr) := new t_entry;
head(addr).key := new KEY_TYPE'(key);
head(addr).data := new VALUE_TYPE'(data);
head(addr).last_entry := null;
head(addr).next_entry := null;
end if;
entry_count(addr) := entry_count(addr) + 1;
else
entry.data.all := data;
end if;
end procedure Set;
procedure Get (constant key : in KEY_TYPE; data : out VALUE_TYPE) is
variable entry : t_entry_ptr := Find(key);
begin
assert entry /= null
report PT_DICT'instance_name & ": ERROR: key not found"
severity failure;
data := entry.data.all;
end procedure Get;
impure function Get (constant key : KEY_TYPE) return VALUE_TYPE is
variable entry : t_entry_ptr := Find(key);
begin
assert entry /= null
report PT_DICT'instance_name & ": ERROR: key not found"
severity failure;
return entry.data.all;
end function Get;
procedure Del (constant key : in KEY_TYPE) is
variable entry : t_entry_ptr := Find(key);
variable addr : natural := 0;
begin
if (entry /= null) then
addr := to_hash(key, INIT_SIZE);
-- remove head entry
if(entry.next_entry = null and entry.last_entry /= null) then
entry.last_entry.next_entry := null;
head(addr) := entry.last_entry;
-- remove start entry
elsif(entry.next_entry /= null and entry.last_entry = null) then
entry.next_entry.last_entry := null;
-- remove from between
elsif(entry.next_entry /= null and entry.last_entry /= null) then
entry.last_entry.next_entry := entry.next_entry;
entry.next_entry.last_entry := entry.last_entry;
else
head(addr) := null;
end if;
deallocate(entry.key);
deallocate(entry.data);
deallocate(entry);
entry_count(addr) := entry_count(addr) - 1;
end if;
end procedure Del;
procedure Clear is
variable entry : t_entry_ptr;
variable entry_d : t_entry_ptr;
begin
for i in t_entry_array'range loop
entry := head(i);
while (entry /= null) loop
entry_d := entry;
Del(entry_d.key.all);
entry := entry.last_entry;
end loop;
end loop;
end procedure Clear;
impure function HasKey (constant key : KEY_TYPE) return boolean is
begin
return Find(key) /= null;
end function HasKey;
impure function Count return natural is
variable value : natural := 0;
begin
for i in entry_count'range loop
value := value + entry_count(i);
end loop;
return value;
end function Count;
end protected body PT_DICT;
procedure Merge(d0 : inout PT_DICT; d1 : inout PT_DICT; dout : inout PT_DICT) is
begin
end procedure Merge;
end package body corelib_Dict;
|
gpl-2.0
|
f3070185f2d97b3533d82c27de391ab8
| 0.581332 | 3.85993 | false | false | false | false |
nickg/nvc
|
test/regress/array14.vhd
| 1 | 1,810 |
entity array14 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
architecture test of array14 is
-- Reduced from UVVM string_methods_pkg.vhd
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function adjust_leading_0(
val : string
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
return a_val(leftmost_non_zero to val'length);
end function;
function to_string(
val : std_logic_vector) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val)))));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
begin
p1: process is
variable v : std_logic_vector(1 to 8) := X"42";
begin
assert to_string(v) = "66";
wait;
end process;
end architecture;
|
gpl-3.0
|
072c6b209c47b65c6d51c3dd08c61020
| 0.60221 | 3.333333 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/sub_189.vhd
| 2 | 1,740 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_189 is
port (
lt : out std_logic;
sign : in std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_189;
architecture augh of sub_189 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
lt <= not(tmp_ge);
end architecture;
|
gpl-2.0
|
abb86166ae64e4d9722f3cc7ab904a01
| 0.626437 | 2.593145 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1218/tb_top.vhdl
| 1 | 753 |
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_top is
signal ch : integer range 0 to 7;
signal din : unsigned(7 downto 0);
signal dout : unsigned(7 downto 0);
begin
dut: entity work.top
port map (ch, din, dout);
process
begin
report "test shift by 0 + 1";
ch <= 0;
din <= x"e7";
wait for 1 ns;
assert dout = x"73" severity failure;
report "test shift by 3 + 1";
ch <= 3;
din <= x"7e";
wait for 1 ns;
assert dout = x"07" severity failure;
report "test shift by 7 + 1";
ch <= 7;
din <= x"9b";
wait for 1 ns;
assert dout = x"00" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
ab40e3d51e034779a237cfeb75186a19
| 0.589641 | 3.24569 | false | true | false | false |
pleonex/Efponga
|
Pong/bola.vhd
| 1 | 4,339 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY bola IS
PORT(
-- Variables de dibujado
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Control de bola
bola_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rebote_xIzq : IN STD_LOGIC;
rebote_xDer : IN STD_LOGIC;
rebote_y : IN STD_LOGIC;
gol1 : OUT STD_LOGIC;
gol2 : OUT STD_LOGIC
);
END bola;
ARCHITECTURE funcional OF bola IS
-- Constantes de la pantalla
CONSTANT PANTALLA_ANCHO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(640, 10);
CONSTANT PANTALLA_ALTO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(480, 10);
-- Constantes y variables de movimiento
CONSTANT SIZE : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(8, 10);
CONSTANT VELO_POSI : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(2, 10);
CONSTANT VELO_NEGA : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(-2, 10);
SIGNAL velo_x : STD_LOGIC_VECTOR(9 DOWNTO 0) := VELO_POSI;
SIGNAL velo_y : STD_LOGIC_VECTOR(9 DOWNTO 0) := VELO_NEGA;
SIGNAL pos_x : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(320, 10);
SIGNAL pos_y : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL red_data : STD_LOGIC;
SIGNAL green_data : STD_LOGIC;
SIGNAL blue_data : STD_LOGIC;
SIGNAL estado1 : STD_LOGIC := '0';
SIGNAL estado2 : STD_LOGIC := '0';
BEGIN
Red <= red_data;
Green <= green_data;
Blue <= blue_data;
bola_x <= pos_x;
bola_y <= pos_y;
bola_size_x <= Size;
bola_size_y <= Size;
gol1 <= estado1;
gol2 <= estado2;
--------------------------------
-- Proceso para determinar si --
-- se ha de pintar la pelota. --
--------------------------------
PintaBola: PROCESS (pos_X, pos_Y, pixel_column, pixel_row)
BEGIN
-- Comprueba que el pixel a pintar es de la pelota
IF (pixel_column + SIZE >= pos_x) AND (pixel_column <= pos_x + SIZE) AND
(pixel_row + SIZE >= pos_y) AND (pixel_row <= pos_y + SIZE) THEN
red_data <= '1';
green_data <= '1';
blue_data <= '1';
ELSE
red_data <= '0';
green_data <= '0';
blue_data <= '0';
END IF;
END process PintaBola;
--------------------------------
-- Proceso para mover la --
-- pelota. --
--------------------------------
MueveBola: PROCESS (vert_sync)
BEGIN
-- Mover la bola cada vert_sync
IF VERT_SYNC'EVENT AND vert_sync = '1' THEN
-- Detectar los bordes superior e inferior de la pantalla
IF pos_y <= SIZE or pos_y >= CONV_STD_LOGIC_VECTOR(1000, 10) THEN
velo_y <= VELO_POSI;
ELSIF pos_y >= CONV_STD_LOGIC_VECTOR(480, 10) - SIZE THEN
velo_y <= VELO_NEGA;
END IF;
-- Detectar los bordes laterales
IF pos_x <= SIZE + CONV_STD_LOGIC_VECTOR(5, 10) or pos_x >= CONV_STD_LOGIC_VECTOR(1000, 10) THEN
estado1 <= '1';
ELSIF rebote_xDer = '1' THEN
velo_x <= VELO_POSI;
ELSIF rebote_xIzq = '1' THEN
velo_x <= VELO_NEGA;
ELSIF pos_x >= CONV_STD_LOGIC_VECTOR(640, 10) - SIZE - CONV_STD_LOGIC_VECTOR(5, 10) THEN
estado2 <= '1';
--ELSIF rebote_y = '1' THEN
-- velo_x <= VELO_NEGA;
ELSE
estado1 <= '0';
estado2 <= '0';
END IF;
-- Calcular la siguiente posicion de la bola
IF estado1 = '0' and estado2 = '0' THEN
pos_y <= pos_y + velo_y;
pos_x <= pos_x + velo_x;
ELSE
pos_x <= CONV_STD_LOGIC_VECTOR(320, 10);
END IF;
END IF;
END process MueveBola;
END funcional;
|
gpl-3.0
|
35220e3f5ed38ddda26e2b34851df602
| 0.529615 | 3.408484 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1317/repro.vhdl
| 1 | 425 |
library ieee;
use ieee.std_logic_1164.all;
entity simple01 is
port (a, b, c : in std_logic;
z : out std_logic);
end simple01;
architecture behav of simple01 is
begin
process(A, B, C)
variable temp : std_logic;
begin
case a is
when '1' =>
assert b = '0';
z <= '0';
when '0' =>
z <= '1';
when others =>
z <= 'X';
end case;
end process;
end behav;
|
gpl-2.0
|
a4f968f6da016acbd1fb87e3038bac49
| 0.527059 | 3.148148 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc460.vhd
| 4 | 3,677 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc460.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00460ent IS
END c03s02b01x01p19n01i00460ent;
ARCHITECTURE c03s02b01x01p19n01i00460arch OF c03s02b01x01p19n01i00460ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
subtype word is bit_vector(0 to 15);
constant size :integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_module is
record
enable :binary;
memory_number :primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module;
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
function complex_scalar(s : whole_memory) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return whole_memory is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : whole_memory;
signal S2 : whole_memory;
signal S3 : whole_memory:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00460"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00460 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00460arch;
|
gpl-2.0
|
92291cea2756cb418d2aa9be3fba7995
| 0.636116 | 3.636993 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/issue690/source.vhdl
| 1 | 1,528 |
library ieee;
use ieee.std_logic_1164.all;
entity source is
generic(
type data_type;
procedure read(l: inout std.textio.line; value: out data_type; good: out boolean);
stm_file: string
);
port(
clk: in std_logic;
resetn: in std_logic;
data: out data_type;
valid: out std_logic;
ready: in std_logic;
valid_i: in std_logic := '1'
);
end entity source;
architecture behav of source is
file stimuli: std.textio.text open read_mode is stm_file;
type packet_t is record
data: data_type;
valid: std_logic;
end record;
impure function next_packet(file stimuli: std.textio.text) return packet_t is
variable stimuli_line: std.textio.line;
variable packet: packet_t;
variable good: boolean := false;
begin
while not std.textio.endfile(stimuli) and not good loop
std.textio.readline(stimuli, stimuli_line);
read(stimuli_line, packet.data, good);
end loop;
packet.valid := '1' when good else '0';
return packet;
end function;
signal packet: packet_t;
signal init: std_logic;
begin
process(clk) is
begin
if rising_edge(clk) then
if resetn = '0' then
packet.valid <= '0';
init <= '0';
else
if init = '0' or (packet.valid = '1' and valid_i = '1' and ready = '1') then
packet <= next_packet(stimuli);
init <= '1';
end if;
end if;
end if;
end process;
data <= packet.data;
valid <= packet.valid and valid_i;
end architecture behav;
|
gpl-2.0
|
3eede2383b96b78447f02b7abf0a719d
| 0.624346 | 3.472727 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_lite_if.vhd
| 3 | 61,580 |
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
library lib_cdc_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
|
gpl-3.0
|
ef89e32fac5c2f67d57bc6de945ddc57
| 0.42634 | 4.120717 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/LFSR/lfsr_internal.vhd
| 1 | 3,132 |
-------------------------------------------------------------------------------------
-- FILE NAME : lfsr_internal.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity lfsr_internal is
generic (
WIDTH : natural := 8
);
port (
clk_in : in std_logic;
rst_in : in std_logic;
reg_out : out std_logic_vector(WIDTH-1 downto 0)
);
end lfsr_internal;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of lfsr_internal is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant INIT_VALUE : std_logic_vector(WIDTH-1 downto 0) := (2 => '1', others => '0');
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal shift_reg : std_logic_vector(WIDTH-1 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
process(clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
shift_reg <= INIT_VALUE;
else
-- right shift the registers
--shift_reg(WIDTH-2 downto 0) <= shift_reg(WIDTH-1 downto 1);
-- xor bits to generate new value comming in from the msb
--shift_reg(WIDTH-1) <= shift_reg(2) xor (shift_reg(1) xor (shift_reg(0) xor shift_reg(0)));
shift_reg(0) <= shift_reg(2);
shift_reg(1) <= shift_reg(2) xor shift_reg(0);
shift_reg(2) <= shift_reg(1);
end if;
end if;
reg_out <= shift_reg;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
b5331fdb2ac855513dde0b9b8384c2f3
| 0.304278 | 5.684211 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/case02/tb_case02.vhdl
| 1 | 456 |
entity tb_case02 is
end tb_case02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_case02 is
signal a : std_logic_vector (1 downto 0);
signal o : std_logic;
begin
dut: entity work.case02
port map (a, o);
process
begin
a <= "00";
wait for 1 ns;
assert o = '0';
a <= "01";
wait for 1 ns;
assert o = '1';
a <= "10";
wait for 1 ns;
assert o = '0';
wait;
end process;
end behav;
|
gpl-2.0
|
0eb794ea46a808826414dcb431b9608b
| 0.576754 | 2.980392 | false | false | false | false |
nickg/nvc
|
test/sem/record2008.vhd
| 1 | 3,176 |
entity record2008 is
end entity;
architecture test of record2008 is
type rec1 is record
x : bit_vector; -- OK
end record;
constant c1 : rec1 := ( x => "101" ); -- OK
signal s1 : rec1; -- Error
signal r1 : rec1(x(1 to 3)); -- OK
signal r2 : rec1(y(1 to 3)); -- Error
signal r3 : rec1(r2(1 to 2)); -- Error
type rec2 is record
x, y : bit_vector; -- OK
a : bit_vector(1 to 3);
b : integer;
end record;
signal r4 : rec2(x(1 to 3), y(1 to 4)); -- OK
signal r5 : rec2(x(1 to 3), x(1 to 4)); -- Error
signal r6 : rec2(x(1 to 3), p(1 to 4)); -- Error
signal r7 : rec2(b(1 to 3)); -- Error
signal r8 : rec2(x(1 to 3)); -- Error
subtype t1 is rec1(x(1 to 3)); -- OK
signal r9 : t1; -- OK
subtype t2 is rec1; -- OK
signal r10 : t2; -- Error
subtype t3 is rec2(x(1 to 5)); -- OK
signal r11 : t3(y(1 to 2)); -- OK
subtype t4 is t3(y(1 to 1)); -- OK
subtype t5 is t4(x(1 to 2)); -- Error
type rec3 is record
r : rec1; -- OK
s : bit_vector; -- OK
end record;
signal r12 : rec3; -- Error
signal r13 : rec3(r(x(1 to 3)), s(1 to 2)); -- OK
signal r14 : rec3(s(1 to 2)); -- Error
begin
p1: process is
begin
r4.x <= (others => '0'); -- OK
end process;
-- From UVVM
p2: process is
type unsigned is array(natural range <>) of bit ;
type some_config is record
a : unsigned ;
b : integer ;
end record ;
constant FINAL_CONFIG : some_config(a(0 downto 0)) := (
a => (others =>'0'), -- OK
b => 20 ) ;
constant c2 : some_config(a(0 downto 0)) := (
(others =>'0'), 20 ) ; -- OK
begin
end process;
p3: process is
type rec1_vec is array (natural range <>) of rec1;
constant c1 : rec1_vec(0 to 0)(x(1 to 3)) := ( -- OK
0 => (x => "111") );
begin
end process;
-- From "abc" test case provided by Brian Padalino
p4: process is
type Parameters_t is record
BW : natural;
PAIRS : natural;
end record;
type Indices_t is array (natural range <>) of bit_vector;
type Bus_t is record
Indices : Indices_t;
end record;
function Test(
abc_bus : Bus_t;
indices : Indices_t
) return Bus_t is
variable result : Bus_t(
Indices(abc_bus.Indices'range)(abc_bus.Indices'element'range)
); -- OK
begin
return result;
end function;
begin
end process;
p5: process is
procedure test (r : rec1) is
variable y : r'subtype; -- OK
alias yx : y.x'subtype is y.x; -- OK
begin
end procedure;
begin
end process;
end architecture;
|
gpl-3.0
|
6d54c2c06a4e207d240ce6a17ddd091f
| 0.456549 | 3.568539 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1041/ent.vhdl
| 1 | 576 |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
reset : in std_logic;
clk : in std_logic
);
end ent;
architecture rtl of ent is
function const return natural is
begin
return 1;
end const;
constant MAX_COUNT : natural := const;
signal countdown : natural;
signal x : std_logic;
signal y : std_logic;
begin
x <= '1';
y <= '1';
process(reset, clk)
begin
if reset then
countdown <= MAX_COUNT;
elsif rising_edge(clk) then
if x then
if y then
countdown <= MAX_COUNT;
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
d2db22dfd92f7b1116504e429cca7d10
| 0.647569 | 2.823529 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/mem2d01/memmux04.vhdl
| 1 | 996 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux04 is
port (
wen : std_logic;
waddr : std_logic_vector (3 downto 0);
wdat : std_logic_vector (31 downto 0);
raddr : std_logic_vector (3 downto 0);
rsel : std_logic_vector (1 downto 0);
rdat : out std_logic_vector(7 downto 0);
clk : std_logic);
end memmux04;
architecture rtl of memmux04 is
begin
process (clk)
is
type mem_type is array(0 to 15) of std_logic_vector(31 downto 0);
variable mem : mem_type;
variable ad : natural range 0 to 15;
variable sd : natural range 0 to 3;
variable w : std_logic_vector (31 downto 0);
begin
if rising_edge(clk) then
-- Read
ad := to_integer(unsigned(raddr));
w := mem (ad);
sd := to_integer(unsigned(rsel));
rdat <= w (sd*8 + 7 downto sd*8);
ad := to_integer(unsigned(waddr));
if wen = '1' then
mem (ad) := wdat;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
32734c665b1f2da4633c2e6eedccadec
| 0.60743 | 3.276316 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1798.vhd
| 4 | 1,898 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1798.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01798ent IS
END c07s01b00x00p02n01i01798ent;
ARCHITECTURE c07s01b00x00p02n01i01798arch OF c07s01b00x00p02n01i01798ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if -x + z < y + x and x * z > y - x then -- No_failure_here
x := x - z;
end if;
assert NOT(x=-6)
report "***PASSED TEST: c07s01b00x00p02n01i01798"
severity NOTE;
assert (x=-6)
report "***FAILED TEST: c07s01b00x00p02n01i01798 - The expression is a valid expression according to the rules of the syntactic diagram."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p02n01i01798arch;
|
gpl-2.0
|
0a0a3c6a8834f88546882837026f1c38
| 0.656481 | 3.615238 | false | true | false | false |
hubertokf/VHDL-Fast-Adders
|
CLAH/CLA4bits/8bits/CLAH8bits/CLAH8bits.vhd
| 1 | 2,217 |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH8bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CLAH8bits;
ARCHITECTURE strc_CLAH8bits of CLAH8bits is
SIGNAL Cin_sig, Cout_sig, P0_sig, P1_sig, G0_sig, G1_sig: STD_LOGIC;
SIGNAL Cout_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SomaT1,SomaT2:STD_LOGIC_VECTOR(3 DOWNTO 0);
Component CLA4bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg8Bit
PORT (
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(3 DOWNTO 0),
val2(3 DOWNTO 0) => B_sig(3 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout_temp_sig,
Cout2=>Cout_sig
);
Som2: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(7 DOWNTO 4),
val2(3 DOWNTO 0) => B_sig(7 DOWNTO 4),
CarryIn=>Cout_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Out_sig <= SomaT2 & SomaT1;
END strc_CLAH8bits;
|
mit
|
e95ac6b28d6bfea13b9c344d03d73a44
| 0.645918 | 2.396757 | false | false | false | false |
tgingold/ghdl
|
libraries/ieee2008/numeric_bit_unsigned.vhdl
| 2 | 25,675 |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package NUMERIC_BIT_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright IEEE P1076 WG. Licensed Apache 2.0";
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit bit_vector
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Bit_Vector is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_Bit_Vector is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
end package NUMERIC_BIT_UNSIGNED;
|
gpl-2.0
|
15c02448dd929a8e0939097cf229be3a
| 0.552405 | 4.207637 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/block01/tb_block01.vhdl
| 1 | 730 |
entity tb_block01 is
end tb_block01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_block01 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.block01
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
ba5f76a1220b600e37e6ec3e0e26def8
| 0.572603 | 3.42723 | false | false | false | false |
nickg/nvc
|
test/sem/integer.vhd
| 1 | 1,704 |
entity b is
end entity;
architecture a of b is
type my_int1 is range 0 to 10;
type my_int2 is range -20 to 30;
signal x : my_int1 := 2;
begin
process is
variable z : my_int1;
begin
z := x;
end process;
process is
variable y : my_int2;
begin
-- Should generate error as my_int1 and my_int2 incompatible
y := x;
end process;
process is
subtype my_int2_sub is my_int2 range 0 to 10;
variable yy : my_int2_sub;
begin
yy := 6; -- OK
-- Should fail even though the range is the same
yy := x;
end process;
process is
-- Base type is undefined
subtype bad is nothing range 1 to 2;
begin
end process;
process is
subtype my_int2_same is my_int2;
subtype another_one is my_int2_same range 0 to 10;
variable yyy : another_one;
variable foo : my_int2 range 0 to 10;
begin
yyy := foo; -- OK
yyy := foo * 2; -- OK
yyy := 5 * (2 + 4) / 2; -- OK
yyy := (yyy + 5) * x + 2; -- Cannot convert my_int1 to my_int2
end process;
process is
variable b : my_int2 := my_int2'left; -- OK
begin
b := my_int2'low; -- OK
b := my_int2'high; -- OK
b := my_int2'right; -- OK
b := my_int2'cake; -- Error
end process;
process is
type bad is range 1 to 2.0; -- Error
type x is array (boolean) of boolean;
type bad2 is range x'range; -- Error
begin
end process;
end architecture;
|
gpl-3.0
|
059e16104301525d8ce9fe0afdacb72a
| 0.495305 | 3.720524 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd
| 4 | 2,080 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity CalcBuckParams is
generic ( Vin : voltage range 1.0 to 50.0 := 42.0; -- input voltage [volts]
Vout : voltage := 4.8; -- output voltage [volts]
Vd : voltage := 0.7; -- diode voltage [volts]
Imin : current := 15.0e-3; -- min output current [amps]
Vripple : voltage range 1.0e-6 to 100.0
:= 100.0e-3 ); -- output voltage ripple [volts]
port ( quantity Fsw : in real range 1.0 to 1.0e6
:= 2.0; -- switching frequency [Hz]
quantity Lmin : out inductance; -- minimum inductance [henries]
quantity Cmin : out capacitance ); -- minimum capacitance [farads]
end entity CalcBuckParams;
----------------------------------------------------------------
architecture behavioral of CalcBuckParams is
constant D : real := (Vout + Vd) / Vin; -- duty cycle
quantity Ts : real; -- period
quantity Ton : real; -- on time
begin
Ts == 1.0 / Fsw;
Ton == D * Ts;
Lmin == (Vin - Vout) * Ton / (2.0 * Imin);
Cmin == (2.0 * Imin) / (8.0 * Fsw * Vripple);
end architecture behavioral;
|
gpl-2.0
|
da5bf4553391967401633193fb1d1b05
| 0.598558 | 4.023211 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd
| 4 | 5,648 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity D_flipflop is
port ( clk : in std_logic; d : in std_logic;
q : out std_logic );
end entity D_flipflop;
architecture synthesized of D_flipflop is
begin
q <= d when not clk'stable and (To_X01(clk) = '1') and
(To_X01(clk'last_value) = '0');
end architecture synthesized;
library ieee; use ieee.std_logic_1164.all;
entity tristate_buffer is
port ( a : in std_logic;
en : in std_logic;
y : out std_logic );
end entity tristate_buffer;
architecture synthesized of tristate_buffer is
begin
y <= 'X' when is_X(en) else
a when To_X01(en) = '1' else
'Z';
end architecture synthesized;
-- code from book (in Figure 14-1)
library ieee; use ieee.std_logic_1164.all;
entity register_tristate is
generic ( width : positive );
port ( clock : in std_logic;
out_enable : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity register_tristate;
--------------------------------------------------
architecture cell_level of register_tristate is
component D_flipflop is
port ( clk : in std_logic; d : in std_logic;
q : out std_logic );
end component D_flipflop;
component tristate_buffer is
port ( a : in std_logic;
en : in std_logic;
y : out std_logic );
end component tristate_buffer;
begin
cell_array : for bit_index in 0 to width - 1 generate
signal data_unbuffered : std_logic;
begin
cell_storage : component D_flipflop
port map ( clk => clock, d => data_in(bit_index),
q => data_unbuffered );
cell_buffer : component tristate_buffer
port map ( a => data_unbuffered, en => out_enable,
y => data_out(bit_index) );
end generate cell_array;
end architecture cell_level;
-- end code from book (in Figure 14-1)
-- code from book (in Figure 14-11)
library cell_lib;
configuration identical_cells of register_tristate is
for cell_level
for cell_array
for cell_storage : D_flipflop
use entity cell_lib.D_flipflop(synthesized);
end for;
for cell_buffer : tristate_buffer
use entity cell_lib.tristate_buffer(synthesized);
end for;
end for;
end for;
end configuration identical_cells;
-- code from book (in Figure 14-11)
library ieee; use ieee.std_logic_1164.all;
entity fg_14_01 is
end entity fg_14_01;
architecture test of fg_14_01 is
signal clk, en : std_logic;
signal d_in, d_out : std_logic_vector(0 to 3);
begin
dut : configuration work.identical_cells
generic map ( width => d_in'length )
port map ( clock => clk, out_enable => en,
data_in => d_in, data_out => d_out );
stimulus : process is
begin
wait for 10 ns;
d_in <= "0000"; en <= '0'; clk <= '0'; wait for 10 ns;
clk <= '1', '0' after 5 ns; wait for 10 ns;
en <= '1', '0' after 5 ns; wait for 10 ns;
d_in <= "0101"; wait for 10 ns;
clk <= '1', '0' after 5 ns; wait for 10 ns;
en <= 'H', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
|
gpl-2.0
|
ec8bdc27f68cb7a7d78d826b8b3f5b68
| 0.462642 | 4.802721 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd
| 4 | 2,877 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity data_logger is
end entity data_logger;
-- code from book
architecture high_level of data_logger is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (integer range <>) of byte;
function resolver ( bytes : byte_array ) return byte is
begin
if bytes'length > 0 then
return bytes( bytes'left );
else
return X"00";
end if;
end function resolver;
subtype resolved_byte is resolver byte;
procedure reg ( signal clock, out_enable : in bit;
signal d : in byte;
-- workaround for MTI bugs mt027/mt028
-- signal q : out resolved_byte ) is
signal q : out resolved_byte bus ) is
-- end workaround
variable stored_byte : byte;
begin
loop
if clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
wait on clock, out_enable, d;
end loop;
end procedure reg;
signal data_bus : resolved_byte bus;
-- . . .
-- not in book
signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
signal port_a, port_b : byte := X"00";
-- end not in book
begin
a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
-- . . .
-- not in book
stimulus : process is
begin
port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
b_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns;
b_reg_read <= '1', '0' after 5 ns;
wait;
end process stimulus;
-- end not in book
end architecture high_level;
-- end code from book
|
gpl-2.0
|
e23336c048d3c89b8aa2fa813d8119f2
| 0.586722 | 3.534398 | false | false | false | false |
lfmunoz/vhdl
|
toplevel_template.vhd
| 1 | 5,296 |
-------------------------------------------------------------------------------------
-- FILE NAME : toplevel_template.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - toplevel_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- This entity is template for writing test benches
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity toplevel_template is
generic (
SIM_ONLY : natural := 0;
CLK_FREQ : natural := 250
);
port (
clk_in : in std_logic;
rst_in : in std_logic;
debug_out : out std_logic_vector(63 downto 0)
);
end toplevel_template;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of toplevel_template is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant DEBUG_ENABLE : boolean := FALSE;
attribute keep : string;
attribute S : string;
type state_type is (led1, led2, led3 ,led4);
signal state_reg : state_type;
type bus04 is array(natural range <>) of std_logic_vector( 3 downto 0);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal counter_in : std_logic_vector(33 downto 0);
attribute keep of counter_in : signal is "true";
attribute S of counter_in : signal is "true";
--***********************************************************************************
begin
--***********************************************************************************
--process (clk, rst)
--begin
-- if rising_edge(clk) then
-- if rst = '1' then
-- state_reg <= led1;
-- end if;
-- else
-- case state_reg is
-- when led1 =>
-- led <= "0001";
-- state_reg <= led2;
-- when led2 =>
-- led <= "0010";
-- state_reg <= led2;
-- when led3 =>
-- led <= "0100";
-- state_reg <= led2;
-- when led4 =>
-- led <= "1000";
-- state_reg <= led1;
-- when others =>
-- led <= "0000";
-- state_reg <= led1;
-- end case;
-- end if;
--end process;
-- immediate response
--data <= "00" when led = "0001" else
-- "01" when led = "0010" else
-- "10" when led = "0100" else
-- "11" when led = "0100";
-------------------------------------------------------------------------------------
-- Counter process
-------------------------------------------------------------------------------------
--process(clk, rst)
--begin
-- if rising_edge(clk) then
-- if rst = '1' then
--
-- else
--
--
-- end if;
-- end if;
--end process;
-------------------------------------------------------------------------------------
-- Component Instance
-------------------------------------------------------------------------------------
--inst0_vp680_nnn_lx130t:
--entity work.vp680_nnn_lx130t
--generic map (
-- DEBUG => FALSE,
-- ADDRESS => "00010111111"
--)
--port map (
-- gpio_led_8 => ,
-- sys_clk_p_8 => ,
-- sys_clk_n_8 => ,
-- sys_reset_n_8 => ,
-- pci_exp_rxn_8 => ,
-- pci_exp_rxp_8 => ,
-- pci_exp_txn_8 => ,
-- pci_exp_txp_8 => ,
-- fp_cp_8 => ,
-- host_if_i2c_scl_8 =>
--);
-------------------------------------------------------------------------------------
-- Debug
-------------------------------------------------------------------------------------
--generate_debug:
--if (DEBUG_ENABLE = TRUE) generate
--begin
--
--end generate;
--generate_add_loop:
--for I in 0 to 7 generate
-- SUM(I) <= A(I) xor B(I) xor C(I);
-- C(I+1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
--end generate;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
2f2d8a14a84e1496c9c63869857c50db
| 0.309668 | 4.83653 | false | false | false | false |
nickg/nvc
|
test/lower/signal4.vhd
| 1 | 335 |
entity signal4 is
end entity;
architecture test of signal4 is
signal s : bit_vector(3 downto 0) := (1 => '1', others => '0');
begin
p1: process is
variable v : bit_vector(3 downto 0) := (others => '1');
begin
v(2) := s(3);
s <= v;
v := s;
wait;
end process;
end architecture;
|
gpl-3.0
|
39e228db3a24961772b9df3399949a32
| 0.522388 | 3.284314 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/synth27/dff.vhdl
| 1 | 787 |
library ieee;
use ieee.std_logic_1164.all;
entity dff is
generic(
formal_g : boolean := true
);
port(
reset : in std_logic;
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity dff;
architecture rtl of dff is
signal q_int : std_logic;
begin
dff_proc : process(clk, reset)
begin
if reset = '1' then
q_int <= '0';
elsif rising_edge(clk) then
q_int <= d;
end if;
end process dff_proc;
-- drive q_int to output port
q <= q_int;
formal_gen : if formal_g = true generate
begin
-- set all declarations to run on clk
default clock is rising_edge(clk);
d_in_check : assert always {d} |=> {q_int};
not_d_in_check : assert always {not d} |=> {not q_int};
end generate formal_gen;
end rtl;
|
gpl-2.0
|
b1097101fe19444a2395de7ec180bd87
| 0.603558 | 3.135458 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/sns01/tb_add03.vhdl
| 1 | 625 |
entity tb_add03 is
end tb_add03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_add03 is
signal a, b : std_logic_vector(8 DOWNTO 0);
signal borrow : std_logic;
signal res : std_logic_vector(8 DOWNTO 0);
begin
dut: entity work.add03
port map (a, b, borrow, res);
process
begin
a <= b"00000_0100";
b <= b"00000_0001";
borrow <= '0';
wait for 1 ns;
assert res = b"00000_0011" severity failure;
a <= b"00000_0010";
b <= b"00000_0001";
borrow <= '1';
wait for 1 ns;
assert res = b"00000_0000" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
6bf3f2c9b11b545c098a313beee75bdc
| 0.6208 | 3.094059 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_cmdsts_if.vhd
| 3 | 22,874 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_cmdsts_if is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_ENABLE_QUEUE : integer range 0 to 1 := 1
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : out std_logic ; --
--
s2mm_packet_eof : out std_logic ; --
--
s2mm_sts_received_clr : in std_logic ; --
s2mm_sts_received : out std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8)-1 downto 0); --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
s2mm_brcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_done : out std_logic ; --
s2mm_error : out std_logic ; --
s2mm_interr : out std_logic ; --
s2mm_slverr : out std_logic ; --
s2mm_decerr : out std_logic ; --
s2mm_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_s2mm_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal s2mm_slverr_i : std_logic := '0';
signal s2mm_decerr_i : std_logic := '0';
signal s2mm_interr_i : std_logic := '0';
signal s2mm_error_or : std_logic := '0';
signal s2mm_packet_eof_i : std_logic := '0';
signal smpl_dma_overflow : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s2mm_slverr <= s2mm_slverr_i;
s2mm_decerr <= s2mm_decerr_i;
s2mm_interr <= s2mm_interr_i or smpl_dma_overflow;
s2mm_packet_eof <= s2mm_packet_eof_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when s2mm_desc_cmplt = '1' and s2mm_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_HOLD_NO_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
-- s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
end generate GEN_HOLD_NO_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
elsif(sts_tready = '1' and m_axis_s2mm_sts_tvalid = '1')then
sts_tready <= '0';
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_s2mm_sts_tready <= sts_tready;
log_status <= '1' when m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0'
else '0';
-- Status stream is included, and using the rxlength from the status stream and in Scatter Gather Mode
DETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_SG_USE_STSAPP_LENGTH = 1
and C_INCLUDE_SG = 1) or (C_MICRO_DMA = 1) generate
begin
-- Bytes received not available in determinate byte mode
s2mm_brcvd <= (others => '0');
-- Simple DMA overflow not used in Scatter Gather Mode
smpl_dma_overflow <= '0';
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on status received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGEOF_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
end generate DETERMINATE_BTT_MODE;
-- No Status Stream or not using rxlength from status stream or in Simple DMA Mode
INDETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_SG_USE_STSAPP_LENGTH = 0
or C_INCLUDE_SG = 0) and (C_MICRO_DMA = 0) generate
-- Bytes received MSB index bit
constant BRCVD_MSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - C_SG_LENGTH_WIDTH);
-- Bytes received LSB index bit
constant BRCVD_LSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - 1);
begin
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_brcvd <= m_axis_s2mm_sts_tdata(BRCVD_MSB_BIT downto BRCVD_LSB_BIT);
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on statis received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
-- If in Simple DMA mode then generate overflow flag
GEN_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 0 generate
REG_OVERFLOW : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_dma_overflow <= '0';
-- If status received and TLAST bit is NOT set then packet is bigger than
-- BTT value commanded which is an invalid command
elsif(log_status = '1' and m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT) = '0')then
smpl_dma_overflow <= '1';
end if;
end if;
end process REG_OVERFLOW;
end generate GEN_OVERFLOW_SMPL_DMA;
-- If in Scatter Gather Mode then do NOT generate simple dma mode overflow flag
GEN_NO_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 1 generate
begin
smpl_dma_overflow <= '0';
end generate GEN_NO_OVERFLOW_SMPL_DMA;
end generate INDETERMINATE_BTT_MODE;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
s2mm_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error_or <= s2mm_slverr_i or s2mm_decerr_i or s2mm_interr_i or smpl_dma_overflow;
-- Log errors into a global error output
S2MM_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((s2mm_error_or = '1')
or (stale_desc = '1' and s2mm_cmnd_wr='1'))then
s2mm_error <= '1';
end if;
end if;
end process S2MM_ERROR_PROCESS;
end implementation;
|
gpl-3.0
|
cf5cc27d4375dad960301de4ceffb879
| 0.451954 | 4.289947 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd
| 4 | 4,416 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity alu is
end entity alu;
architecture test of alu is
constant Tpd : delay_length := 2 ns;
function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
return result;
end function "+";
function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
return result;
end function "-";
type alu_function_type is (alu_pass_a, alu_add, alu_sub,
alu_add_unsigned, alu_sub_unsigned,
alu_and, alu_or);
signal alu_function : alu_function_type := alu_pass_a;
signal a, b : bit_vector(15 downto 0);
signal functional_result, equivalent_result : bit_vector(15 downto 0);
begin
functional_alu : block is
port ( result : out bit_vector(15 downto 0) );
port map ( result => functional_result );
begin
-- code from book
alu : with alu_function select
result <= a + b after Tpd when alu_add | alu_add_unsigned,
a - b after Tpd when alu_sub | alu_sub_unsigned,
a and b after Tpd when alu_and,
a or b after Tpd when alu_or,
a after Tpd when alu_pass_a;
-- end code from book
end block functional_alu;
--------------------------------------------------
equivalent_alu : block is
port ( result : out bit_vector(15 downto 0) );
port map ( result => equivalent_result );
begin
-- code from book
alu : process is
begin
case alu_function is
when alu_add | alu_add_unsigned => result <= a + b after Tpd;
when alu_sub | alu_sub_unsigned => result <= a - b after Tpd;
when alu_and => result <= a and b after Tpd;
when alu_or => result <= a or b after Tpd;
when alu_pass_a => result <= a after Tpd;
end case;
wait on alu_function, a, b;
end process alu;
-- end code from book
end block equivalent_alu;
--------------------------------------------------
stimulus : process is
begin
alu_function <= alu_add; wait for 10 ns;
a <= X"000A"; wait for 10 ns;
b <= X"0003"; wait for 10 ns;
alu_function <= alu_sub; wait for 10 ns;
alu_function <= alu_and; wait for 10 ns;
alu_function <= alu_or; wait for 10 ns;
alu_function <= alu_pass_a; wait for 10 ns;
wait;
end process stimulus;
verifier :
assert functional_result = equivalent_result
report "Functional and equivalent models give different results";
end architecture test;
|
gpl-2.0
|
3ceee2c58faf7ada9c62d05371d62fe4
| 0.605978 | 3.742373 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1225/tb_top.vhdl
| 1 | 861 |
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal en : std_logic;
signal a, b : std_logic;
signal p, q : std_logic;
begin
dut: entity work.top
port map (clk, en, a, b, p, q);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
a <= '1';
b <= '0';
en <= '0';
pulse;
assert p = '0' severity failure;
assert q = '0' severity failure;
a <= '1';
b <= '1';
en <= '0';
pulse;
assert p = '0' severity failure;
assert q = '1' severity failure;
a <= '1';
b <= '1';
en <= '1';
pulse;
assert p = '1' severity failure;
assert q = '1' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
1b3b71d18b5e6b68733f51d2784e395c
| 0.52381 | 3.108303 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue328/uncons1.vhdl
| 1 | 253 |
entity uncons1 is
end;
architecture behav of uncons1 is
signal s1, s2 : bit;
begin
b : block
-- port (p : bit_vector := (others => '1'));
port (p : bit_vector := "01110");
port map (p(0) => s1, p(1) => s2);
begin
end block;
end;
|
gpl-2.0
|
1f0776a3ce6f966b8cbf1824700df6a3
| 0.557312 | 2.78022 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/UART_LIMITER.vhd
| 1 | 2,742 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY UART_LIMITER IS
PORT(
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
WR_REQ : IN STD_LOGIC;
INHIBIT : OUT STD_LOGIC
);
END UART_LIMITER;
ARCHITECTURE a OF UART_LIMITER IS
signal packet_time : integer range 0 to 2000;
signal byte_time : integer range 0 to 14;
signal byte_count : integer range 0 to 9;
signal last_count : integer range 0 to 9;
signal running : std_logic;
signal inhibit_int : std_logic;
signal inhibit_bt : std_logic;
signal inhibit_bc : std_logic;
constant limit_ot : integer := 4900; -- repeat rate of packets
constant limit_bt : integer := 2; -- all bytes within this time of eachother
constant limit_bc : integer := 33; -- limit of number of bytes
BEGIN
-- If the byte count or timing is exceeded, the
-- inhibit signal will precent further bytes from
-- being sent through the UART.
inhibit_int <= inhibit_bt OR inhibit_bc;
process(inhibit_int, running)
begin
if running = '0' then
INHIBIT <= '0';
elsif rising_edge(inhibit_int) then
INHIBIT <= '1';
end if;
end process;
-- Start tracking information on first write.
process(RESET, WR_REQ, packet_time)
begin
if (RESET='1') or (packet_time > limit_ot) then
running <= '0';
elsif rising_edge(WR_REQ) then
running <= '1';
end if;
end process;
-- Time entire packet.
-- Once started, this timer will not reset until it reaches the
-- allowed re-send time. The other parameters are tracked only
-- while this timer is running.
process(CLOCK, RESET, running)
begin
if (RESET = '1') or (running='0') then
packet_time <= 0;
elsif rising_edge(CLOCK) then
packet_time <= packet_time+1;
end if;
end process;
-- Time each byte.
-- Each byte must be received within a certain time in order for the
-- serial module to include them all in the same packet.
process(RESET, CLOCK, running, WR_REQ)
begin
if (RESET = '1') or (running='0') or (WR_REQ='1') then
byte_time <= 0;
inhibit_bt <= '0';
elsif rising_edge(CLOCK) then
byte_time <= byte_time+1;
if byte_time >= limit_bt then
inhibit_bt <= '1';
end if;
end if;
end process;
-- Count the number of bytes written.
-- Only a certain number of bytes can be sent in order
-- to keep packet size down.
process(running, WR_REQ)
begin
if running = '0' then
byte_count <= 0;
inhibit_bc <= '0';
elsif falling_edge(WR_REQ) then
byte_count <= byte_count + 1;
if byte_count > limit_bc then
inhibit_bc <= '1';
end if;
end if;
end process;
end architecture;
|
mit
|
4c13d231957c16e3fbd48dc03c2c5cb1
| 0.643326 | 3.144495 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1069/tdp_ram.vhdl
| 1 | 3,939 |
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH_A : positive := 12;
WIDTH_A : positive := 8;
ADDRWIDTH_B : positive := 10;
WIDTH_B : positive := 32;
COL_WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
byteen_a : in std_logic_vector(WIDTH_A/COL_WIDTH - 1 downto 0);
addr_a : in std_logic_vector(ADDRWIDTH_A - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH_A - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH_A - 1 downto 0);
clk_b : in std_logic;
read_b : in std_logic;
write_b : in std_logic;
byteen_b : in std_logic_vector(WIDTH_B/COL_WIDTH - 1 downto 0);
addr_b : in std_logic_vector(ADDRWIDTH_B - 1 downto 0);
data_read_b : out std_logic_vector(WIDTH_B - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH_B - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
function log2(val : INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
res := i;
exit;
end if;
end loop;
return res;
end function log2;
function eq_assert(x : integer; y : integer) return integer is
begin
assert x = y;
return x;
end function eq_assert;
constant COLS_A : positive := WIDTH_A / COL_WIDTH;
constant COLS_B : positive := WIDTH_B / COL_WIDTH;
constant TOTAL_COLS : positive := eq_assert(COLS_A * 2 ** ADDRWIDTH_A, COLS_B * 2 ** ADDRWIDTH_B);
constant EXTRA_ADDR_BITS_A : positive := log2(COLS_A);
constant EXTRA_ADDR_BITS_B : positive := log2(COLS_B);
type ram_t is array(0 to TOTAL_COLS - 1) of std_logic_vector(COL_WIDTH - 1 downto 0);
shared variable store : ram_t := (others => (others => '0'));
signal reg_a : std_logic_vector(WIDTH_A - 1 downto 0);
signal reg_b : std_logic_vector(WIDTH_B - 1 downto 0);
begin
assert WIDTH_A mod COL_WIDTH = 0 and
WIDTH_B mod COL_WIDTH = 0 and
2 ** (ADDRWIDTH_A + EXTRA_ADDR_BITS_A) = TOTAL_COLS and
2 ** (ADDRWIDTH_B + EXTRA_ADDR_BITS_B) = TOTAL_COLS
report "Both WIDTH_A and WIDTH_B have to be a power-of-two multiple of COL_WIDTH"
severity failure;
process(clk_a)
begin
if rising_edge(clk_a) then
for i in 0 to COLS_A - 1 loop
if write_a = '1' and byteen_a(i) = '1' then
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A))) :=
data_write_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_a = '1' then
reg_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A)));
end if;
end loop;
data_read_a <= reg_a;
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
for i in 0 to COLS_B - 1 loop
if write_b = '1' and byteen_b(i) = '1' then
store(to_integer(unsigned(addr_b) & to_unsigned(i, EXTRA_ADDR_BITS_B))) :=
data_write_b((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_b = '1' then
reg_b((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_b) & to_unsigned(i, EXTRA_ADDR_BITS_B)));
end if;
end loop;
data_read_b <= reg_b;
end if;
end process;
end behavioral;
|
gpl-2.0
|
358b000f977719120ad0e57e8507d4c2
| 0.520691 | 3.422242 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_cmdsts_if.vhd
| 3 | 15,457 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
gpl-3.0
|
52aa24a29ce50643bda109225e0d60fd
| 0.44323 | 4.387454 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0.vhd
| 1 | 91,022 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZL7oeWarhtoR7KLssV+CCfaVphOrbqyk28tPzaF4MGX9aqyfbCXawOWXF9Gr81KlrfueTholbVRQ
kuRSuN1fww==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RsFJ5sb+3Bv4vyhk6jwtCcuqY/adjXk03FocDaQTYhsjZw/ExJNF0jy6RJxp43sZIptcUIDyTfzm
vsRR4lXOjhc0Lv1DqSEhA0XNMEQLl5Q5yPSGfvgS6rz7wzGPg5Nf4KFcgfdd0ZZmCvRAz0tHfuGY
Qu5cjvzsptk1/C70BcU=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vHmmDCV6Nrkxv8ElK4lSHeoX75Y9nyFQxe/0TlldiYfwXR+j5X0W4mScOnZ8yLQ+KiY5oIMqrQGx
J6ohSlthuqjWB8hmsXRC+loycd+VjJNIeHoV9tH3iUmRaOE3cLRSKpa0SQd0zAaA+D5p27S9++45
aLZrVINjblAyf7T088U=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NS/ujq3AMwr1Wep+BjDkn4XKliXwai3BAu/WDqMr/dE1NqWuvl6/FhLkq0nPVDIKJjE19DnJAg/C
rK4QLHC0jFopTBpr1d67Ju6h0y4vd3ln97sRp8sv+9woF63dSYAn8wTpgMCA2U93/ft2a6l5ifMB
LhYe8maRAD1dttsj5xkHBXSr4u7/7t3zMSvMCvpvVy5SI8uDB0G7QL6AnrTMr/5ia5zZKCcKSWqN
bw4LfohDHuQhSQdgEOK0pKot5r1r8Rgl7yUW7mL5/P+vfExPDfG803be55dkcL2H5aFGvgCOknNw
0xj6Rxcier6i2p8xWUp59CVGYT9vI7TccZD5Rg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
N+XEHEXX1tvDSy6c+xproO9lZuLc4dc6d23CVtx/G/gWQlr0uG3KTFFJMBQYr0N3y9sTw+veI5m3
RVQ+p5lvFdkuM0MPY9dLLnnWWAuMJkeTwm9wcbywilawYs250Euzq/1j5SmbhOXjMzp0z2dMmofa
SsNG380+HYUAJ0aDHSHK1l0i49Fd2mSKA+P5M+bgJXudlDtyKgFSRsMakE+8ymA5GRGwucD5vofl
A4dsCNGL7FeiDIEcIFyb783h8+5chj/e8GYqvEENdMzmPimLJIZbEViA7lhr1u7ONigt0dNz6ELJ
gJFFTVxOEAT669stZCyVzwPxbg2w+l4jIQc2DA==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IT6t8jfDLQDjfT3kFwS/b0S6Xl15h2EopIJZI0O6K3Yf1pcttliQ4fZqZ+4xr+/EV1KWYX9xZ+Oo
/Bb+D/BgPq4rD7nGpFnCs0zHI3Wf4mvboC6eGowSl15tcfcQF2CfU8kPpuEfZWpqG6JY5mKVfTX6
oI03sMHJ684HYfla/qjJ11vyMoNVAQVI0NgKLve5rLDcZiD4Kl1TzBGlCTFeBIx49yAFa6lvjl4z
HxWjta/dJVRaHA9SqwX9I/uHtzs4UpK23JiivHyYnRZBI693XGo9/12Mta/s9VFnqO5Cm3l/gaN+
uPO++ckXU6vVv4Bhh0mVyz0seT5MIFawmd8PkQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65248)
`protect data_block
lKoIjkk+hN4kX6XOT7qPATyQ++yVsqPLKcbvjzbnub+pA5LECmxcl+u0ANC1bghsjmhw0xiu+Ys7
F1DZjtdaqbfJF/VPppUAHtzruyFWtTOt+SnvcgT+9LzRVwOzcPiFE/VJjgPI/dnoLs89Blf7kdoX
5dS9A+hMfu2m+MVX8Ulf82Nh5jB1VHRz53xzG483rzf6EOkz715ZovyCCPqlcWn+7SxC8Pk+PgMq
+BSHrv03YOW5HvYCTa4hnxZTi5uDXAgYDvaRYq3ukCNGnL8RnRGHV6yvCfsymcjRwVMxDX5EYB+4
L1sZ3ItOGLjA1o9w9gaCXGhDyrHi5VGLjvTQWRGCpAtb2LavBBk/kNVRTRmVDlXcbLMnLPcxp1wH
iGb+zj8dfgAUT8Pyr1AOMKts5mw3oVcGx+YCR67kTyA7DLyH2YvkZ9NEInEl1NfefyPnjIrDet/3
Trn1rjz2R8/jYP9kdlxwuPPqpv1JhqcgquURLmyNOKVmIpfVA++aMOdO8XCmIpWDhau1Wqgs+87K
5Ct1vK8fTdW/Zv/yQTQaIAexCou2ekdFfQZFlfTyw0PesAOEi2niMgGus8KZMYQeH7VMeiEEsyRe
eE2UUkAsiw0pXQcEqhe+QWKFADPVqq81ZK3N1LuApTb4rZT6qmziyRr9SOIwa3UfVARdKYIyMSOC
ENpqBrPmzasgGvSo/v9pfnLHYGv1BhoqrOQJKpr1r/mfDVNsA8t7zVy3pCh+kkuFNnn0yKKCLthJ
SXOwEKedK8g12gzTJ9QFiD5UyTfGHmpL3pygKqogLcHcFu0ouwLmW+5GpSc5Pu2smO/KnZBlOISG
jmv/MZCMPFXLnQtjp0k25dRktf0CqglwhRk0Et3ef4s/J22BX+TqsrVSDYJi3/Ao9jEVkQR4Xj1Q
UhePkOH35sqrVRxvVrvTSRi+OlXo/DW5fRlVvoJO2VWD4QkJ7L60emwa7YVLPHy0JoqTiv5zaWc9
nYFbDc7rFB0WVlMQR/zj03Bl/SVWewId2dhitWe+aZ6vSAtHk/7tRKfFOMZpmzPSyfVYSD6Bp4qW
NRG/Krd62YstSWAh5Gpq0be4idfExymYhYMbeE2hDKROSH2Ifasdl278FV5k/noXEjzopjfusPaa
ZyCCUta5GB+Swel9H9JreR19MMPwznNXv7gar14BhnTs5TMXtnhPrnJzpw4KRha+BEP/iiW/bsKa
m7zSFeScsNcGyrSd5VGQvCFXsguTvaWfpP1jnHX3ySqAT73nQRaWSfgp3JmW1aDaIIP+XZniXY7U
dL6r0idKaLZPqXsFlqlXeblEX9LLOfVmX9YH3ggOIeSpDvwhxPHmSjEXXslLyOpoX66DFv0PHoyL
rdrX4WOGES1dZi1T/azis5MSArIS5PRYFobez0r8WISmYhL8rqyVzyUjd20MfKbZCbHCtJPopXG+
rGAbfkZUZ8RS4tiBAtgTJSYtw2eaSRzfGB3CFmTWrg3/LyV08cKBgANd1C3cjdr/1JE5RA3i8FRK
rpU20H3bivRj4KuZbvXfcqW5uUxzBRmLzR2hYfUEnXwB9JUlZ10pFX8BlbP2t2OBcIKcZgZQsrb1
1rXJ8+M2H3qpPa3aefooms3jJtGeXxQzQuSPOKUB38YHiUaYuKV63etAxXAQt2UszsiLoxTl62mm
YW42T3C4O1X6Yt6Q+TrE4KQjujBjfAjLt6DIebsuBdhJWOB2lowQioL1zu5HNT2cX19eECI1Re3B
ufPdxA86qIRgev/BoGaSdJCxiNPIgr9jlGkKmDX+w0NBBe4sUCos5dqXw4Scc9sp0+CEJ0lYBKM5
LFZGcPt6Vq57+eMQQS37gzjHu77VYNXyiIwyW/Pk92UXmfza+Fs9K3QwJnFKP8Gnq8HtoFWa5xQf
jZKi5Wg5fUQn7nQ5952Fmu6PSd0rESnjWzK+7AvRq9Azln3sFxfeZ0RQc5yqd7s9xuzMbXmedNZ2
fQmWdZfgHYYu2GVPLUDNk8N7Xm01Pw/21sAA3WtShP/gMneAy3TjgZw27hT+JZ/Gtp7X16HAeutW
2PiZ5JYw5lwTAlrfvOElz9JBHSY3PdMcX7D/I8WTi6cYnCZaL6lLMw2J6SWq7Q6mO4uxxycsAmXQ
75YdBE+G8yukgSKz7fin85p+V0hA7cuE2eMNp5yDd97INzn5Wzu07LKJfBhPhxb2k6ng/nIG0N9v
2zGEcr33rLomcCTpVvHzBQASGCAONO8V86eypy38ph492aLrcaKO09DHw7wlrx3XMj6LYLBya/JR
zW3DKQmtfKp/VR14GOcyvZjHngu5VZg/Zx4rNw9rMuNV07l6OnK61VwT4EpMp9fZHyJXmosUjRgq
1k05ttk9GZii0A4DQjqHp9TRDqvZr6V4aIR8EDwjFj5ftiMHK++u5EZ7pQG+xtiXiuHLS6Qaj8D2
dGrHS4S//RrBVjIpkNt33mjdfkHysw3DhQsu+dMkZg2f8iHMFjp6pSBrC9m/TykIFWhdSipJ4SH9
Uh44aJv3uuBnX5RSZCU5LmTSdfIwEJKkmsIBXOb2Gj6irJbycwYtAOW7UXMytyDAfcdfQ4yUQ4WC
ne8RBh4t7Pkyd1xAwEL7vNk0q5easBfkvFI1dC2yVcQm+90ZNDiB635zq3LHR1VeQuLyeWIXINML
6NdwWSykBWy/MDeaoTjM25neQx+0Vdd9LM8xblrxXB1sr9yhUpUx5HX3OqKCghSnzxoQdIUyPahF
+ovVacufoMoYfahvwG3W3cjadPMqPG4NCQ/N7YNOJgUvL59MD07mdpNd5jj8o0CjTQ1UaEjNAK2J
ZA2Dt6QSAadfkWjWjAtooT475cEL/0PoNYTTMVn7RlIlbZLg5r9mY4O0z0y5u4SAj13k3swR8nev
O/dQ0JdeEUZ3u53FYCxDWr4yUHVQqV9e75EoC3bfqxhJs8p4wOKpV/3mWYiyOw0WkpHljF05nvO/
f3SpexmLilXdjXJONFr0maJQ1biId0VEDqBbum5BxA37wIlz92qqAz0AqF8l/iah7l0BZZ/mQ4HQ
JWp2R6GHJsM3nXwgrQ0EQEPeXY/X0J++4zpiW8s09sycACTDo8m21XxTwhQotxdWVSaHWTARZ6fQ
WbunhS1kh9Jsgu9hIbOBKZ5RxO8ImOuWWym3NIpgWdJ0gKkaU+nlJgDtJKjif/mi/5nxPm+50DzE
XdzC+3Xf8q4HA4PE5waBq72dBD9H8fDGFcAGL2n1Htm9wxB+vTCg2H9PsVoA00MvFXN+pzss41/2
ZJU6M77AgghfleChxMY/RobWJ99u06Z/vpy6EXVjEttH3e6dgQSRO485jFNTz7mD3LdOHE1KA2ul
X7XjdA0H1SZoeWe4qMxflbf5xcgv+LmtPNwvvUyF7ES5w5KHzj3hb0Y0z5BO12ttaIDi/7BECm24
PozJRc/KgsoJ4GAhdUlUo8zfljRmlMnc5RB5HiuwSUzsCTiDs7+nB6u5krhaCjuWmPqS3GAs3/tG
yMeYok5FUmLNX1IcLzCUuuSo7oRftwLGuT7ZxJdjlv9ry4oQbHoH4HvOYeRZ4YK2v9SQ5/VIHhZi
XPEpvooL5mrxDZAVcY7gQCMYgk1AQDb4JWwr4JN2ySTYG940hFDPB3P+h/RWQ4NOkIKYKQEV50Ew
jcE+ZTVmhncFR206CgILuc5r1IvlllOE6p77LqP4hCKFQ4sIP5u5nmKFTV2BNKuIzJs2qrQwmTsl
90RpWt2WELbqoPh9hGrz9h8KeCzZPDF6+3Oo6wYnTFnoAiHtS8APGNRpauWhNGNfVO6UhxY9T0kE
0fidmIS9nGwasLAphbUcVEUsR0CCZ7qGuAH7ZPWvtj2F7bgMfJsZ/oSlEaLTyxsKeu05cDIB73HE
Hy8uafoaOul2qs6y5K8bTjXJ3VRd8KYbPyBjRs5Rh1Cf+8jfbwkVSzExIk1rzmLfJ3rJbAhyFY8y
lXH4GcS2pE3GpSPH1vITNSHamk6PgN67v+HHT6s5EmhTFh54kHSQLsH8O6ealjjYbyizEsAViEYE
PniuDOy2pNBIjqlxOc3rWxgBryf7UlA88dA41LnIzeiaYOnQ2Bomn/d5yItNYFTMqkLxduCVFN/3
WUrYxE8/PG6Nry0spz1Fl9CuACGUA5KrMTsyoFWupp/e8GJ1m02DqFnzQk/i0SNgvY7hzXW8cyrk
zQ0Lsnc6e1abLAk0dkjNPIB/VMMa+OQFA+6BGfYaH1xrma70DuYAuK8oITgS87xtHk6tZhRfLxpG
cpHUg0LboPOWNyMc+ZnaVEYbfS4PiD5sO71E18j+mlOFB1BcmT9SX8QUdCOIwRsF2RzVVoezODrX
Tfu0W2P3ncUAIJGu4cS6Ri+Ov48Di/wczKE6veLN/IPYSXGQ8zKh+Gy5Bwo+8V+RwWQDsPVIvRaa
uMXRf0ZENMOTL0QyZNms0bpuJgKoSmU4EpN/au6SnIVUifdbTBPNZgorsSSHFU/uqV1A/YBtRqW6
LDelmYHxMlkMXMlFFd4lWSYY2aq7SM1RKHQ68lsMcTZ+RUAD05HOitp3HI2QxZN1mZSo5QrGUrL4
NAhcCdn/tZSUUw5RqfYXs22PWGPdD5iPsd16iAspitUfEmYm5ESpKGZYTwoDdSS4r72Re/hcwEOc
tpMXelYKq6C/0MVZyE+EUbWpMltTtslMTxRumXa+PDYzffwAhSdddYusrHbT5amiqmJEV31IqnXz
lpjD0ydNG45Kto9SROk/tBmrFbovn6Xi/ZkGjmv0KpCmotEgNi7vTgPNE+FEFKUrjfjse64PxEUP
SdvsG01evemyYSTEwiSce8oPz/Xk39kPHeGCDcrj8iQFZP6ldQjTQ3SxBwF0h6JqT01Ju4rOO+FX
PrwGYw5jOd8F6vtjBV7tXPfLF1f3Bp6RhXRfw2qglwci//dv8lMFLWJrB7fWFVAra05PkwiripSB
TH4Z33s49mACAR8+aRLle4VIDRfCRGTk+4JLjc1y9XsbtW7+1sOyzIHb9IxOrAzTLupmJbv7wQxH
+GMAjpvytGWvxBoffNIDbZJoLT5BRPPjdU+JImGjDl790INVuRwPUVUkBRYaga9FPoFyOmS3JkSc
k7rj4yPiPM1tS3LQfr2d850F/L6D88c8TQQBDnh5QjzIpEbp9Qm6LcaoPn9NfIzSGGRunwpVZd/f
v4SHP901cb4zKZpccJ7HrBbBO1V4a1Zjxn3AkuHdPuhRZ7/yDRU3pbaBLycMuyJU2cpGjfUo+5KQ
UGQoylwM/cT6xA5FvrROeT8ceD5i6HTdYj/IDgxGJftMPmmqIlRUOUp8lNr/mXO7y0C805FT5bh/
F5fq99J8OmDkBelcQnqQqjMYlIs8k8nzmiya/6egnfpkeBST/ZW9ERc8ruTKVFm9KHtAR6K4xW8F
eZIx3ajk83BFzEUgbt68H575JrIjhxW3WgPWC3B2Cl9x3DLYiEmmhh8tKZT2ALUP5qH1cIDvlj/h
tl02BUefi5o7KyBb3SChFAEJYdudJT+DW4ZP7BXVdXYo+3Q6Y8lfcjM1kVUFQreO88twYvUAG/6X
Ub/51we9vnE1zQR2Z320F5qBSe2RF8B3ctu/hW77VlWHukJRMzYgHgFOzznCFPtbAvbX5i7X6P0/
48XClucF539+gMDKTmVYsrQ/TFDizINAIex+AsRylTlrfMlFG3TIzE/G6bsMSZ+uSvq1P3HXzIdB
qd97I/KudbzK/acvlzMUeIhgK3YCnDxw1/ghkP44W2TfHOJ60FISeKBpY2jdpyTGbxwXlWpeQjTS
u80qkATeMSTggngQKbj0b/cluss5PY0w221srwKOsHOgocpTx5RTVnKO7R5gpdw37XL34kpw9qqP
JeOrrU1euNr9Xg0ovFU9cyxJbCkTJqPSh8TqddirGuIYRUMIKGBShMH1fuXIBS4shWYryfZdvvPH
dqnaYFawQPHb+QEsd/+hSfmghGJkf4Mrl1lYojkNlv4K1oWDug8injSZb0XmREJFDlLPd2NFTlE5
3et5MCgF+3V4QRmUFWy3yjsUmPaa/nY+UEuWZL44PFP1PoKgy3nzGxAwoOc7evuvEtlUIv5e5zJi
xt5xliOILY2R+QxSAMbC9GlIUQY9alWfy5B++FlcsZsU5HZ3tFv6n4BZdTOQ8S3v/o+TXhrWqaRW
ri+zFMrg2riAqnf/4dZpFpy6qaRAS6xqTU/FpUfZyGLIo5RZ9rPTaqHYhQwsOkGKt2el6L4FKVGr
195Xdo6aFh1vPgFQs37yRASGFqyvxYtx76QighpTXBwSW/hrRNpdD7l6QRWPd1eJBF3gVYy8Y7Ha
sH9Z2DLKP9L3F/ELvE9WqEgXN4GNALvbxQzheRi/94MHqIPdfKQXapu73Wyyk0fiYVoOSt3yGQ/w
hHiTu6eG1T7E3t9Uoyztk7G+/hwutk/BpG1MSQN2ZlyE+4HK81fUsX4O4vfCEdBlP7lKGzNrSJGM
g+ZAnD72UrFPfUA8Zk51j9F875oenoV+LWDgH7S36LAGO6zfhqyvrSDVJdnXd9QSD/cbLOTOHbqT
m6mNxE8oSviWbGkaen3qz2JQcXbWlSqTX3R/eikBHg/dQS4P43slzJuFkrcX/29J31N2tP7/7nyw
QK7jipWU44zNs863SyBhDD/1pP0X5GT5aUMciHBO0Syjhqq7HP0me/55gcpkUaY4EhKO99DzuD1j
Maxzy9tQeOCQlRIMllfPSjjo0bv7PKCwoDaPpFK67JKQipJXAMu6mSfEqLno/SHEGgLguj2an4cS
CZy7o+C0xUhKZtIBKZ1xTsnnI+x6SiqlIGEtn/aVJRoIh1YvzrdR/wxeoSwXFn0hpJR6ltpxrnbz
BuogTNqRQpJSt6hUV7920DodBVh8hx+sshbmJgGKkuFBYTcePiGqGta0xa6w5F2Pcs7u5DhL0gcC
yPUqjC7+4bCeuRBsFoHw5FwUqxidD7SPc+9iStQIh1zTwrs1AQegf4itQSyssq0NOAmMlAE0AkTb
erHrKCTMUN2B5XC3NFIEXcX5QPL5OYyfYxi0eArJXn3w5wn6WsJfOxzUjXHmq7OE+4oMukDuITEQ
xDKaBSQiSFYgrwk21JA1pKfl+2ANOOTUEb6I63jP/G+47oA8vcjSrC7DmYHSFalcGRaalFaMqHz0
zVaiOSmZr/R0LNtPtszA5jWKA1j1pzq6+0rkeSv63qbvo0LKOapp15MQzBVPgDg8nZwwvsjSACTc
zMlePeVp2n7nsTdRtY0VXRwpYp16SBhAJW0cO3fS2h7pvSkVY9Io7QPrbjGWv87crk4XogBuCLVn
U1UP/FAf3PbVP9AYfE1eTlmnuSNJd1IRPxwHcVe1Dl0ZAcuhJQ6NELsuRUMlchY533wUckNbbhV9
gIffNuNZpCkrKCjDqKNp1EjU6lEvCpgeKiylgQbqmw8h9EvZEmrvw9AnMgkycoz1KTQG3ckTBHzW
Cr5CFtrvWB49bgyHMI7qBCxzluB6Di+xPZ8dHQ9Pxyu8R6G/8WW3Wk5VhpY4eWskp3jgqETXvxFL
BJmhGC5K0bt4z0LrHDheygWgLUlB/8zDsab3y7jPaSbzjNw6VamBn3Faapyb20o6qr5sF0MkYx7o
oCK4NfjMJSR6+0tLWqCov/gkBbhLRt/7VNnZK8+Lq40GaJFGk+/zWWaxR5CGGm72LbBXVsf0C+nU
vOy6VFn+czWpgLlMXOyZNsr9snc+bBsA7GBpQ72SjbW4nFR53Lo1xIssUalFBHC0Bp/dy9MgtXn3
dI1v/wguEdUcg8td5IeuJxPQSwABy/OtYuizwumf2mrw6vN5EvRz+vUKR2m8UMnK1V92j4xbAftx
nhzwKz2rz0kmPoEndWrW8tmo9yDlPwC/pfgJ6rVucgsLOEuByOfH6MvswJHDWBN8UUEiRmIsPFyQ
P7Z5rFqpFPLRgMbpNwJ9oG8kDC5YOSjziIKzuKADEyW/+mT4QARxS6PsvJ/mqSbE5XLZvNaWRn4w
Fsk9RdHQwu4a0/NRDcWgVarLHUOrE55bEbYiZyhsXgunk2+DnL6MbYzC5KtdlWA9HclVi7wcGJYy
EUknul/SxiOil8p59ehWLeDfzmJ+xwZ6IYJBOyweE91cNqloa+/ISNPsQ0H/O1rSs35g4Hb/z/fq
oFwIM+sv20BZHI8P089iaW+5RLAU56z9zCFxws+HWOhOAHYnsfjXg6R0GRjnU6NUF35fxGFdplL/
oeqyowyh/mnwetlrCWPdcR1BOtoeD9AynyXjdr50HSqAw6HuJ2n2YQzvWBq+auuihWtbWQ/9nI5c
05rLWMu+BXcszXvGEZrtLYRLzrEckHrEzxqcyrnZiMhxFvkt7Iht/vDN41fpomFLKdlMoUs47qs7
qTbujEZORLUu6TvRFmxo3BQTlKrDxM3Y3jHIEpVC6KYK6M7EZNPlgd9fHtJfnFkDLuvKS6U53uNo
XjIAhs16wIpW4SdWDfriyhqwPX7LIWkFy1OgCH7V7olrbqesS05aF3ZSRF8UdYojFSolgw65hORr
GkN9V35ZiNutKCNO8jzYhgEm+PmDNyN0pdSpreeA0vTKuG3MvbGTH9Cukau+xTyQoDmYsgs1/Uu4
/nO7zfPp5qPsTdG8PnJ9keQm+ThYAMjKqZIP6FqSK2QlNAt0unMYNgEFAGxMem6YIR5N8NhG3quj
olTrVz8nIg33HwzvETTGkusIr7MmctURAyhtLv7kL+elXHinRXq6EyHB/PwVdgWD4LDK2F/Z4OFK
xmEux3VCEZmWNEZaZmadnsXT7iQzoVzos0tmUqxqY2Kd7sLJlJG+DsnKHmdLnai7fTN82RcW7P/u
BiY5QZWntmfvGt0lpPuqUdFaiIeBOwgDOEcdvlYX8k+q6DLFgnphpQUMuobW6vggjtEq+FElROqD
vKZKiJQrWScVmzGEg4J9WL/trC1TDF9ZlzX1wzXiEZF27/kyWQO5sSYW+Z0lavXEiyM3BSJl5ntQ
bmucqu8B5sEurWPKBgPix8gAwbXZkVuYJxwV6z8LLD/2oN/juOgx3H3wgXJt3P0Zzc1cYVHu7g0o
3JNfqZKPsooxL6liCvXlXYwZmCFPoTAq8LZhzleDVswt4cqttVeeX/8PLlHk5lxttXAXeSpInqV/
dRxpJbULb9ZfoGXwCeie7gvEBHMRwcJVUd5hDsWt78lHj9RAFoWpR2bo0NdTmnrZzMkFyTv/sqIX
sHd7VF6BZZgu/wOjQtTkmzPbmk16ienIdHzKRTRvvkFMW7EnXxkdCjsLrPyZwbMuVk2ApeU7q/dE
EIkR0rTpgzy2b+E/Ky43IkZTkUEP1XYwRRbpdDyn0z5D9M09IYXqH5b2pqS6jUFn3fXHuCQKI0vt
7HXifdXEZB/KdHjAHnisl6sgo4fPex2/N7pvVc4txmlfpCeVBVe4PKClySi7B/ivRWRwE3B/d/j2
zgCBrOO1l6SyaOsE8g7yhOpX1DqUFHhI4rG8m3gy8+BnreOAdsSGXIyF1KCW26x2b0wl2OzmcvyJ
UtKaCTFyzjAJ9gjocSt3ZrtD5QkhZYU9UEdT7+GC7kUGNqO/rYOoPGk+aHPema2T3/mSPWxCV0sq
JPZgnnZeT8yib7VdaRH6LxJ8ZrLn7aXUQy6SK/bUnZJ1cGnwlFl9QOAjb/H/EXJbK2UdN/aZgK+I
bs2rOSJOolGsiscPmWrt1tLWfhIYGu7vfe6Ba1PhLtGhuUdPayYeFPn9nYAwWEUmQZA2kx33/2XI
sHP8icJF/XW00Gmr/pG5rP1GPK43eQaCUuzPM4bcKjrpKZan7gGfPmX7VBEtH6xRIU3RDVE9nEK6
dKFbDREQrcZ2bRbD2f7IprQV9Vyda9N1X+5YG3lZu2YHlgMnbW8wXikuRu5Jt4B/WT8VWu0lk7EW
vE6dO2soblJcKsVeRCwTm5P4vCo2BgDc4xAmi1HWRPLdmRSjQZ+OZTslfaXg5O/i8ItX2Z3KiKnu
kaV7xTQ0U3bNwX2shbTyeupd2h5PyAPIETCI9ItuQRUwdhDKLZK9pEtDbhyHS5MeVQQaIxiE7a2F
edL3z+z7MjzBHPfXxZFvmQdvGd44GSmdQVTN+gWs7JVc7iwomWXfFAkzclsvVRC3FZWVsL7RHZx1
5IwUNfpBgJBg1AVPh84dQPdx6e9Mvi0XwayqmpdTMH2akrKpkHNmD2MdbLmv7W1AkpwmbMKjJBtp
jzPxh6Dg97KqqVFiPFncLekqhqbU/eoho7T+nlbUOogq4TKoEcl8+QuZKUAA8YfQ9q3kRIdZBCS8
27RoNaecIJ3GMbMvux6s8N2NQWsRQ2GTGBTUBCbxLpePEE2VLmoNaaI+d9Nn9cFBmIWAsIH80REk
IzrjmOaz6v1rzVgtMkn0icOU3/zXaiLapK8CRaDW1UcsW7VmkRJxiBmkXgMAucpllkcANYba2q1t
dR9ZqRFMAtntiQTz806ImFa9TOwJKpHhjFFfUH/P9FNwBNOd6oA25XnkG15wkmpborkN3gMagDDj
G8dMgBwq5pGPw4OZnnR4HhRXN4Tj8SbbbXbfr5nYnx0lvi1pkFcb7H23r5IwaDT3xo+hwfPxwusn
NVpjeS2lRTBIcLQdjvxclU3fgMlRY+kE2wBiNLYZJUI1LXQM2mo+wpzxLsrcFHgO8G94yndtVemB
omADegs3Q5iXJjTHWG8oMbwhEJyK/7wqgSS9m0voS3rkkaqFiYMyvoNOBgvEPODjuTU/5MIF/0HM
3zOkk/OyqM/mR9zUJvm+u4X664TvniQ71oTRYImJhRZ7iMjT+M1+hE1ixlfCHudgvt841IqWWSka
ZN6JhTavZuaBLaonTVnkBUsZosuUCvXS9OGCWlO2qSor210B/5hz1axMDRMwB7KcV9nTkWvHl9W8
RFMNNpraNAWs65Wpnra2Xgi/cbV02k6lsM0YPegpSXDYtv5el7VzfVDam2u9LovXvb6wCC5JuILU
BWywrsvIjVkHdVnP+sfxX9kIHIZt8XwJ3PcY0QIgwq+2tdBS8zt9qPMYcZ4RHv9ixVs9Z8EyWCID
ECOWhk5vcKBBrWErs+ZDZQFwaMM5MzjW09h26lnNr11mgxjNa3qUgDekzkjWqjHdFo3SVULfWtqp
S5INQmiAayMo8cmUnLK8s8kOKUAPPJxskh5+YX36kCysO1u31YleLW3XlmuQs9tR6jXFNUNLirvw
TfPdMNHUCNi3zhAeN9oIuiHj85H/sou3evDqfK2vDmb4mGNccogIEF/fIIrjjGS3uVocEa7K5UC5
C6wnW47Fs4fV0994gt0kTYvz50OY80NFCN+09uomZLD684YkE/d3ffqKHJWiSbgZKB97JnMuR8Tx
lsMSK3h5Jpbcfb1+Q+/fKoTcjnB1Q7GmIXNcFPB2jjjPfs+IyVQes0V7yQdo/5ceVr4D+dqiakqf
BFqNKhzP226+e1FswC+Y+gJ7Kgbi/vWzJ/dOf/cNJ4fqxqTn4r28sYO9WbXA5F/Rf9GIytbEwQ6g
kd4DSSp5xYRtxiER5c90mYRkh0GeGYFLYq2H34JFOYEwvPtu5Lds4YMdaNgo6xIIik5kxZc1xVNa
PQxF6rYnLeBnaIjQnRGIdRVa8ewUHSQbnKVnF34AiVWxur0uxik8R4zeaf6dO+GwGE59Ob31YmVD
5i7NGwKS/aHiU9CpYglcoS5ol6q3u+KorHFi8vekAljDadzoPPmYPZfXnnbCYwXa+nIwdEmvK8aL
hCsMbb+TZqjR+5ruoh6ytp9O4fL66Uuwu31PHuI0RMhNf5gJBKzXzFN9fIVr2tfurX2Zi8bh/ucT
v6JYJUaOnJWJ/c5fSJi9pv02BrzqYoFWOEcnv1V8Qdd5hjgbfpPhCIU6IY6BPMLWuciK3+U12rsk
0CuMRtoYHOpPwrbQogmhZ4qcbTxwqWV8HsJlMok/Tz158iwN7V9MZo2e1tBBLkkGD6NGgEF0AdrH
82/oX0L6Vscf1VvIa4T/zSlgxXoYyhqmV96i8UlsMVOrLUHktOyLPSbsoBD4rX3BByW2+4VEPXOW
1ZqNbOdzO6l55Aw4MYWGF8CaL/UTvNFulxY0TBgxs8WOiFz4kwgiithTMXUaXv6rIx/IgVvKsqno
r0dqAfp4fGuVHwN4Y0U17NY0N2Rtjfw3ROYmIZ/8NDCsCGoLRDp/Tn3k1M8UbyN9HDT3f56Owx97
UvlOhMjKKlmvgr4EDCAqCoMgllgotxfzsf6GRnl78a0fO77vjaM3M3WckYVOzg9Fn5lk4vFk3eeN
Tn7cRfBKS+eV2oAuFTvxl94vSX5AzR/u8R1Adg+w4lTcEuOyomZUHcFhmmT8YiUgcmlxpQ/D7d8L
jJfC3NXrWI7YOo+Xf2CM5r9hDyfQ0VZvgYFvucv50OHJ/m3CUmHofxDKTJKt2nuCtKAbQkfLke/S
XcGeGl+PK+inuEHIKpNBEXEqSefWn7XO34F9hArt5hfmbXEOt+z+O/JEqwKwHXNhYCflH0wDkqNc
gXNMIqVPHfgQJFXRIrw696Lk9pXI3gQXIoh6bczYb2VAqqlosP7UcJpMREDQDZMAKjQavRyk3knr
b+8wCEGnSa3uM6KoUV/E+KHO8qv/kHrWhL2jLikOcio8UEshzHEuJ4Jl5T89vGtMkZzeA51nqBOz
nOp/tXjhEYQ2/+JZEGhFiN5PNY2KPF4prQ4wi0ykzdFL4vccPKQJUmJZH24S6UV3b0xrfu599f1x
J/HHT38EJ0hVJuYagntAHGnJGsnZA0XmxKFxMEwk/HwWyiFyn0h+YnSW5EwFhotjCcIwsFxOARqQ
x497oEIO2xw6VjSDHfueE60M1y9Etp8o+hLttdpQA7DdoAXCawkPyDffqwWMIk1ZkngNoopPNni1
dCN3WYITwFTQEoHuLQUXT07NzEKFALcoumHygY1jqWS7b3oguTIAc708tWZYlRsCR5LG0xLJvgfz
mSkHOJmQAE/7uL3NJQ2AOvG3FqJsU/9iQu/zeNegqvXDOCY8FnkogtzTIkUnxUXmS2mXxaCgyBIq
p5JE0n14gWZz3WM0LXLpomvNeLiyNbxS4Jv9dLpXHqTQBLZVANjoiiGCrSgYuuk7IrZ0uvg+WvaU
2DlJ+geNqQKFYkta/w7fycBrXbl0140HGcBbyibty6/KAOe9MxVnCpQrm3lHWRNtF3FJXO7wvsrG
BkLMerMGiyxOt1+OIej4frb/4o6JGawKti+fAoSOTwoa/3V3nU84HKy3HtGBRELRTKbYxvn/FFvd
fhRVOjnwU1JjdO+mR/rduoyefkOGB8tSW+BuVNhPHd58/KtotFbe3qImS1VepuWgHF8aqPxRI8q1
lXitzFkKRMyOGDuEPRaemCjhTnE4IEVU3L5tuaaiv4VjuIxWJKYzIdRytj1g8ez4qCifdPQ+D8zx
q6CdnVvdM/jCK6K57sUy9ABXJJXzHaVr4LNrzmoDw6ttBe9AEjTDiudII1EWTy72hbxunJqP+zXf
VCk44VKYIzFE0Egk4nfC5/Cb+qNmVVsluIPiX0Sn3VR2OnlHaQTgZmB+6bpKQXx3KN57Z5YzluDJ
SZYWb47QcUeFOy6TijLetbmvvo2VFNshN+icGsnA12WkhD92S588GzFMaQFr69FDKsbQwEWl6dgk
1XEpHn9tpWg81QBGYGgjhgznatoB5/BCBXvjvREXpv7mx1YWd1tl7aoFYgTOp2pEn2RKrOsiHQ03
MEKgotcu202dj7AK+f9N3n1nnrYQ1AgnBqLlt6A8ANNdvFAU1Y0QdnFm2No7CDahKpwoQfL5yiXX
zCmZ9ZqguJyv9xAz9ui6zUvG40fraZzskQ+cJAK5yUgFsqYCoQaAJOfgou0iLms4a19+wBl2yH5J
MFxyg+smAAFGvdcx0qXuZVKzLB3vQThZxmyZBoV/dSn913M9BNlRrg+Yjg9OKvFLG60irmhXaa+d
nijtWiZRt4t9rIMv/wR3LAeBfzP0csZW3EU5z7XD85Af2hRcENGROD6amh9EQM7cLzibnXssSsKP
stINHKpbQJRMguXihEmDtkF/qlPCwp9jjEkFa8SMN06JZbCWX2AEqHx/rtpMEkyaFippAyxL32NN
CezphmU4fp7XplNYyed4iv7NHDWXDA3zejE5qd54vgO6nVrmR5eOyi5aSiugeW8WRjkhiHRWxnBP
MdBEBxP8FW4JVguSvW81thJnrm+QNSichcVjT0RcI6hpShtgnH17OIWVzuyGBQWI4vYnsq9d7gsu
lgDu1Hhw0rEbUtkI67zmXKYC+WTm5T41QYYNCHnOFSU76NcDZBNVJyN1K0Hq6Uq4cU/TxrSWebh6
jgdRYJd415023/bsR9rzwo2GT3D1XmVnF5aY90vYWWXitdbaVvjLKd44/LNAjmnTgjPKUG1l/ELM
7xhcj0xNpYUSUS9/HrwBqQsQ5gX0Chd4thpLPnvGvf/J0I1X3yoaJ9A03GxyJCzTxEeVi6p0y9sY
c6nlURJCgbMbeuPRK1Y8p/t54ebwF/oZ53Iv2qsUZXn3JIPjoxD+g8GbDER+0ANAyfger5FNVstv
zsiEDEaA3jN0JK8nXfro5fYurKYUw+OqcdqStHDs5DHipb31/Y1bi9psr89nBflmbOm6my/LTVBZ
QnjmIpOxkMlB1RNwH0oVdp0k/d0OZE1XT2ZDJZWUEucV8cIOfMGG+3BfqWg7jwYpvEbOqqyjdkXy
MIlmeng9XEqxA4IwbRdyKhDF3Yy5Q9JlEmuUzhztXnW8NCdOUenBN3aTpqVQGrUSLSlMH2L2KGyz
PChiebB6JAkQz8mO9kurXB/YQyF4kvUy1g+jPNkAnD/p1nzmTORRNcWYkulqSAx7EP2N4QlGTQiq
/lEdBPgyAc/49asYGj8ns+u2UwO2NwxZNV4NLtqtMFEvUQI+bCpqTDS23b2FQ12IEm9aUdy1HNpN
DVYBWMEB6qM4q5IdoeR3/p2nM0882vsIcU51Ikmj0ERpQ7Y3MszsnoAeXAuwE5zkBVealNAW6lRt
mgabos+rnqtyh2Uf5SzVIedvgC3sapaoj0y5e9545/dDqgPZv4M0xbTLIxpAtUHI4u1mxy+Wo9Yg
Ger7hAoyo0HI2p8K+WJ9fbZL36bNnS7okjL+Hsien8ZmxFVz7s577NMMQoFflcC7QFHtBkn+9Uxl
6vTPsDA91j64bBXAzz0ayZNw++r7IPpWsgWuYED11lp47kSq0mLzsB2F/20pV454jDdTeVxv9nwi
+Kzl/sZMMV93Tx08kmfglcR/fGJ7+PTvWhzi4h5uxBUeyxKCeU0VoLg5U3C6HcSbsZMLdjPBqDnt
jnbSlIytqrcZScBJ34uuIsCEhd/Xw6yIjVgCffNBioXmWJaIkUqMykZBbvDsViR0dOCXIv3cnSIu
IvfKXgsapXYU+wkS+IRJt6NqIvmf3+xzj8ybU5DiYyDuOtWY7jLQmMSaVJu57vnhdYQ9liE/owQS
DkJ15sc5+d0r4Nm7+pmpaOGhpPg3L4LsvI6Ht2YQSNG7akqF0o4LDRT3sWepvPDfVopMx8Ek3l/6
+QtRCBb7rSADQ77IOs/6aBh4gqG/S+sk42EfCODgFoAEtTQX5GtwshfNyPWeEqg+WliAwsuEOGAd
aE4FVNNlgbnFcatf7czhEfnobteREFKKSvS/dUQF30f12uVVWnMvUXgQ4wt4TgP+WBSY5Bnod8x5
0cN3DtR/b6ceXmBGrBP+ahkvXoox+8Ek79dRbWMJBb+JUCn9LEdKsZRZ1Yh17FC7eukm+zKvZzR/
Fh6ASidvo+0c7n8y/OehHyLjXgtAlZuY8ICUq9q0PR2rNLFM3qetxLeRn52qnUhhKpO/FmrrnhDx
0tFEakQ18nDk9ZITu72LC9qVJAvO6XVR5GLXLXOqbzT1WxA2DTaj43MNzNRcL37yZauWmfPKBRpl
IL/W3B4ICiNz/E7cN+z9yi/JJr+H8+OeIBeL2q4X1tqyeWmPj/dEjFDyOoSlCT1Vqvxdj+6baHna
v0R8FCqBjfUFjWZ3MHkXljkm2ULVfvc4zRRSuQ5SphbBOSgB0+x47IXqCAOm/JbXPSQeGdRUjEt2
CgyNePnf8G93jjbxjYkW087VP65FHMfpLyIoEZ4mUWq/nYUouUg66OWJ7GxUN63/5z2PfGuoaAlN
DsH+eh+LC9lpnE0vDJvl0pl0zmmDGstD2kW3Cq5fGvq0TQ1VVGlQJT+pJR2XUG7ZObb8c3uzVULM
R3NMD9LhdRojHNYaKdQwKj1XFnRJ8WoMizq0oI93CcEx+5KP223eE62YonpGDYvtQ7Ru2/zTfsLK
DgVRg5jxOhiDQOCr8DzN8BLJ5lLbtV+J7KT4QK/rnKTBZ1acddAsKH6PE9iQZ6pi5/4ped04nRMe
IvQYHgYhzKkzaasTIahtsS7bMwhbWLXcongiVhZpQPpcQZUj4etzgwm+wslpeTMfY1DQ7MBfszP9
jE8enAXtFpM8CzLV/fDmvEg1Oy5yOPbaM06lpCyDkYOnWfy2PGzQMJckVKSgKkIAXSyRBsth+Zcj
laprEU8pTekFrC7LFp6CSZDlDSey8/OSd10npKyCoDwJ3s75Kk4A0Iy9vYEAYqrFhWawQrQfA1TB
FYczQCvstP3AwSRF0oxV0LJpvTXt7JHh6b2rSD/0auqLxPcxSvJcEBYBxtIK0mz8k8uqQOdvUhD2
wUUrt7+2VtAQyWY/TE5UVzf5zTZLt5V5k2EF4/94rwrvGOLaxz47FDtaiW+y+adTvBKmi9o5VD3y
rJQ3pgQ8VGVrAz85WbTuHPk9wkGcFG/i5OibCLpK4kRY+oczsoa/zOHk43JFW9S5vNu2RqULMYeV
2Kxf1A2ugNhmGtuOtbTMRSC/Ys/iUlEaM0YZUFjZNiEYz7E5QSdgrMXIXvUzcAFmpuYtnVOBFWjg
y6VW0qFy3pNrcQYYk+LYfzRNG5+kabIHjw3hPoxUArfdBi0v4rMgamx+KUk6jNz9u/FEU4Bk4jaw
8O/Fp4rrxt8H0NQKWZFAsRPfCGMcNFYzAOpf/RqHC4IJGKtNWfCQa4+tgscTQWKB915Q2Wb1ek+W
Et+J8Qhlnl/pmz3lyVxJOhytXWDQxgDI6p0/OTbg2/dbKa6MDifTSVhXDjJcXqy5mlfK72ZPW4v2
n1PLWKn64GHI2+y98/8M/hyIDrWPLWTEsPMdjIwMavDSjEAH8mf6d4emoGgkApKNz6oGVlVfaE3P
jpE3BYQzYHN2inSsciojZJ9TPgU9M3YNQIvSQ9aaCy/L0z3AusGSKl9XiAIifY9iGW53510ne+WL
9EILvyMivthEcx53tigvQ22i+2oCBaP/pa2k7v2j1q7/hQbB8WAM8jPlYjNoOLZJ+1i4A/XQd2gT
svKsrq6JwLVDW+11v4QcDQ0DjKqBr0hpCn90mam7Q62SVkIBJOwG8A3oh9zhMAzjIjC4h6VfvQEb
4412pAINJaBfABNlNl+CcQ0dbFcHYzFQJNzwoy83vdheOmkz3zsw0qg3RCJBuZ3ryY6HAIOP0/Xo
Crc/Nf7x/7GLxABWZInWSgZ2jC5TJ5dMOIingwJIw+ZCQQMnrOS2GC82neUJfI4ZfKN2JbkBMqLS
pCRNIFEPhY1lHA0fOUo3thyxbIyFa3h3Qo0z9I0QyYCaeQiaDWVlR6XdexB1DmouTXuS9YLepg4V
OTqFwsHUJV8dtYKl0Q3k9S+lgnCoVnvOyuBYK2pRBTzmtWm5eM1CJm2UThgMf2k8EJmF+nyWFrwo
ao7n6oBrltqsUF1DRQ6QVJCXPBt6PKtCKKrw2ZszuUs6lkN1LWhywSYSHQnd4fOm33CKQIOGslQU
vB7Tox6Hh2ESPoXSAExlaMskxucHsglrvTrdw0YQ/8uU0Sytyhp50OHRTlAaB9tdk2Gdzs7YjT7a
c0pGvM4HLVeFLlZs9RNdEfKB5kPZ8F6Ip2/cOu7u0kMTNqAHXGWIMfhuSYBsLpojrGLgDCBpspzS
5D6iGToMi/qTqQBkORtFBt86d2QlP+Ux6assdCUCYetFrflcyIaPMdxcYOs4//5pGtKDXorh9k2J
dmD9hlnrizWdaJoMkl/JAv8JIFwh+k1qokgCd1IWch5NNhz/+B+LgkvZUg8xmI14KhcOIQ+NyNUN
ydnjj2+rZ9+waUVMZcemCzROzwHjaDnA4mE+XfVX7owkI3HDe66wq0ags3DEJdkjALMHN7+hHncv
suJpWu3hR9IydNz+JSpyw2bXOkzQJXTi68DI7N7E90RpwvyjIWqDrTrcXNB0sChkpKSvjCytONla
QNjzZuSZVEk0bZFEPKVpK17h4kaIQ1gswhoizyVKNP/7orORBU5Xl/lUmlOGa9+69s3UOJwUn+K4
EnEZ9Wf8UtnGVa3ujvSRtMflAsY5FExIeHKGKZitAuoLpMchXqT1U0XzxkRw0MDbHniw0+yAbfbF
X2SptLFmwkg6BmZuUecs+Y6Gpo54rC3uIdn0rksAEkFm95An6aDhlH6YqPbMQmy5AiwJhaBxWGJz
qciGSmuH/wxV9i2a04h4SpWBcI9lRUcBEONt8zW9Uh6ZFalctTYP53YpkPdXcocZvFh1wg8dEqU8
rNtSE1fNZC9fXSVN8YCV56vZ3QYBGShX+HmZUv2hMhV8viE/mkpQ9gNidru2D2PQGu4TAF9sfqdu
7QFvlpFIkOj4EVwWWr0geeSEh7mWi/8wZcGy6GzC05y+uU93+SsP9WUu0T9d/e36BajnY1DmAlCo
znG8GjxCcw6t7kEz8g6HYhP7vEE48gL/D/TWKre5GWeqOF8L27HINg4XkW8AtwZmbSJU12tXIZnI
bZJDFIBOK4Q7CX69ePWIwwW2gICID9miGUPkrmIkl0/2mJW1R1sr4zgfS3JRufyFROwSHYn6BiS0
N7KDRNO3MyLMLSLv1HaIz7vRvp7LdUGgmCDreuQe+ndFQMmQEX/MB1yI3iK1FsUUQSGoiVlIkysJ
s2t94fBcKkEULOvFkCEOehI4UM3zHYXvOrgT3c9HKCQH6lqfaPnreacXe9B4REF2oqnqkXwNcmz3
oxGutFb4Yy7WGDey9YvUThxMw0j2ESflRwoaLoU9y0Re6eIvN44ObMwnQLn15mSTMXwl1aQ3MjPz
zTo2NvPXFTA5ovb9QBLrdCJ0ClG8BV6WyGZf7LyD2ll1S/x4Pi8ND+wiS9aA9xRGAttXbCG+FMnw
yBbr+M1veurI/pXhYIE1qZDi8e0HG1mDrffZgV0zx53wgkh2JQ8Jf/obOB5mWAJt1xlIhitrSrNp
ZD7RqiQFRFBNXnWHevTe17MLrGBwePEsy/J5XoGro9PpPDC/MjbXu9AEnva+zSICbjj7sdhf/EmN
HT4YQgPbKHJNNt1uT5aPJIxJ/iygE0HworDxrBVCiKQBYtjO7r5KIXFQlWA3U/OrEpq+8qcXCgKx
9RsKte3ylA1v6OlgVM1JNeHF5eBCZbiTJpf27If/71jSI9pZJNoQcbMJNAxD9k+WbSnolhKUPlro
BbHPy3epnRrLPC8ZQM3N6xDhx3sgHq9bXZ4qRaIzm7RdOUo6rsBmWtb2MB0LSZU4na5UGfF0OgMs
CDTCwZOw33la2Ll+3rUaOrmjEUdSP3NsL9U6VYNWDN61PRkvGcwLYQ40/RlWvXIjvGaob6AV8rPp
xIHYQbtFgmhDUZe8V7SJoNFC7Kr1FE+HzAwo5yd2B2RuCOKyhNFwgOoMmrT80O2DsFtUKCUVe6e0
MTXcEhka0Lvn9LM39C+hS8qgUo8gfp1mKqw0FwjYGh3Z3zYCD6NW1EbxCiSIFGrro7vA/bYV0WIC
Wb0LD5b758+noK1JtsDMmRwmmy0BffE9byv8upNnqxIdbvHF8zhraiDJUwfuaBGhsJURejJ7aQz4
Xf+xWw8vveU1x3lx2BiPp1/9Ig3A+/eGLH+HWE7kOB3IGZ+whRok0MfHj6bzYzVL3Kyr3X4a5HPD
L346Pa8T9BNkiJgus/Ig9IvlVWn4Yir/7fadxOjk+gzKeGAfC4osv3urUkYcsE8HL9qma+gjmp7F
NUFd9SRWrhmInAzrB906ddhh6cPiTt7SNDOaftZ6jxHPGU6EkJr+RMoTQxwJLVsJ13gEv4V8ifYq
qvk1zOJ1fhpYNP1snOTmLQIsShJnnC1VQYjyNDxqtLVRY3eAr3YNND8QWF3efiE9b3xIPhbcb5Mi
aMgfW6KsCT8uWoZX4RE9qKPIRcPPjuniIFEM9DJQqFero6qqXyIxWkYnMdJTHaDxbEfpPIGUVN4p
3/KkqOyZl0O8l5Z0LhpUKwCEfX9mu91a1fPCwcwRiYpAocwoERmpzKeu0lQiKkbEXPtdO01+ooDQ
12fSDkXNUAFqDhy83kzXPD++nkEsSBHq4kvGgcdcoP2pmSyIt0k76Z56yoJpAFexLZSGFn+9ZJc6
yyhZ/0elxjcGo83wndebIOr88xLROVUYdHnzyRfQa0t8o4w7zlfMNy/OXLrQArSJQK5LH0nvWrq3
2b0zLJDrj3ewOv4g6cs6MTuEtMFG149KCgqd6W2ZUeaDal1SxcXeFin6PuT2xwrvOUSe9Sw/CwXv
acZGLR8WB3v96rJ5RUzlswUEU7p2sTSwbGN9OzryWlrAJSBGBph289oxkUFp09NM/KtnVh80ZidD
feneMPp5nNztJnlLmhNbniLi5krUollmg96dUc8bk3oGLHTWv0893D94Ksn1//bJl0f7ROUzDTZN
fMO21vkzEzQa1cDMtSQxspmdnqC1bU2p9MVeu0XH2KRKdu0hskaP5srbvCJnnhs6dlcC8h+QZ39h
R83UAoEUg/HkOWzI+11ZR5uxaFwn0gvuQXZa5j2SQehXRfB0M3nECJXhjMgLwmQ38palIjn0Bh+W
7W7X7XlLwqGs1pNX2eZvRS+fvtqznZjYkbFhTBcnYpV1g/CYLKvbY8IADSg0g+syNF7DJ070p/5r
34o2TwC9MZDsszAbYWWvSS7dvy88UC92lh8+xwbWHrSe/mgfGvr6H9FFjVL/Gr9YA/O+raOWrhuV
nr3RArEceLhpuJ37k6fWCoBLZJrjTi9i30E/IE1CRVSEen8N5dsx1lk9YbTY4CPr6vgEFC3Wxkwl
3V/9z7967yPyNCxgbnsi9gVCSUcGfpNO9LIXYQrnigrVT5AQHApjoVLrhYvP/3sE+59hkPnIWoEy
cRk64n+qeEDZeQX3Pt/WDTuA5RWDOP/eN2p1SFWNa+rwp4bSLLMjXHFdA+9Is7spQ3OEH9iRZZ8a
q3YUbNNGY0gwiDzkloUz2w48uUFf54UVBRwCCHI7dbhYVlDA+/noP1npmbjoSWhQ9wSzMl6jGXjF
TTkkC2gPt28XrWj3BkUFSeXTbG7NFo/R24Qw0t3nP5K5tOSM0KssjjdL8l3c8YpFu0AcQ1rlSqK3
aQIA8EbXVE//7xqEJQqr+pYw+gboySKLxQXPruqZty7g0Mj9Ago0DxWIbVgCM/YgIefmMbiCZ5bz
h4MRqjNxQR7pAO9hzQ/8hYFHdjh5K8AopcU+uSUxevDxB/yLESm3L8IIGCWYTU6km5XGCczExLc5
0zysT0gGx7k1KL1d6W9A4CJqR99gF/emLp9T+xz+MDiFeI0wkPBTh/2mp6ZvV8AbzBBp/SjQ9V/m
XCwN2pvvFEQ0QHbAbayVtxK9PjWCjtPKOvQSniPza3gvPIyeJQlUC+xEgGJ/2C2xk9c2Z9LHk7ki
uG9ydGWiZ8QLOR7ao7T34DqX07qQCbgf2bmTiQzYOXZQfBtoH7iW9q0bch1iRUIdj+gD8HnTc3c+
HWhZsph6E0JgaVN3uUgvlwg9od2CgwBuOv5hyNtZzBHoijyRk5GwZn2d0f2iVYfgF/XRs/Y4GpCy
g3OPk5JYQCgLWkmIGbg2x2+4SHC9KJfqPBklCdBdhKs2fQSP17F66Q9Xz2NmKrpTzl7eZw56iXKI
v5VPQ1BgGKThIusih2uwMvD/YzPdoOuIcY29F7R4+vD+H0HdQW4AhMlqe3THvJpCiLKl26U+VSts
ikUy+aFAbXKQYsISUtv3PT0f1lY5y1lcWVNzBicYOLIu2DR3jhZqsEnXlzNNJK10Qx7mX1471Hld
9T53MmwvLIP/LtsBDtvBU3YTE1DsSPISkXTBRwxXBiScZVjLSbmfW9UDfnCmV9p3mY0+ITSAr+9i
sssygag0KNSJCsA2yUWwBsOqvuZMI6BkdVp+D30N08FkHSFcCfwerd2G8zbI+7K+bGLXUEnG1fZx
Z2QW7ttBUq/x4ZiczqPg8vW0o1CwZd0pordnlKu/XNYIsusXub805s/9gBUmRcM0rbGjcK2AVs5T
1a/5lPihP5rYQyx7DsTq7b0L2U2XE5gAkg54hy7uEbqTyo7U/8qVb6QBUiZK+sNxsKikcFYZuDup
VG9kuew6JKf1oIN/zrMKbleeGNP5xAdRhf4XpJ5fnWscglUk80LnAliC1yj1BgBgbK5c+GUxD9CE
t/bRwRk1s146yuaY1xfJVWv5yI42wSckuFSlwr71/h76bVa+LJouK/8+ELi7VBVDSQWx+UvzA5WR
1YO1EroQ1OUmC5/xRzCZSzFHh6sDf1jOwgFHEC/bYdpH9qpaIcrZAgzm5NKhJ/9jbYamU4tDJIgl
KE7/swL4OlyUNNM8kp9vUhL+RCf+gSfDoDrNtq4dMAR1L4CAhJNvCqZqlmFLbuovOGOZTyZABcW9
+M1Hy4KuWUEjQNzxm94wnCtdXkgWcabQiUV2PwaYQeBV+d8Zwr7IeSr+vqcjmyGPNVJ6lcpr+GsF
F9uh0PlAeK9WPkEVcpijyCsikdh1Zu8UuzJhkkfSjhlVOG5RZw3suY+EWC/oVoZJTsjvoVqZppiV
pidNtUY2JHXU5FpF2HpLrAamDNpH43PoOy6mwbWITt4fM7SCfOTndDMjfQjApkTo4m5fgRIps7fD
+c/2q9Sa0oZEclBziyMjfZWES2ge8Cxff+x94kkn4hjjx7PPr62RTh+nj20GlNWSZew7Xe5YcaPq
zhiCV3Tyw/G1UQQbg6/v6xdDzx5VlvXNgZnlXWoCwLL6ZMV9v872xbbS6dnN7cNTb+2Gb0tasJYK
m2VXqsZ5z6ytNh4Zk91dggqwRvDR2Ji+L+ZgvhUdW76qLF079UrmrVVSj6Yh0Y6GZTmusngnHVCm
o3Qmd2FJrQ+fIABPCIbEsr7mFu1A9gIVdPVH66BwPjVhyz17qe+4nCCNFKT0ddULbI2/Z0YnkKQo
rmFIWj/XyElWokd6mCNusDs45N+wp1P9mg80RHJUPg0lGYXFsManG9G9R8FYwfz8UEAYJ5ut7kkQ
rcwoQXHrQFwtnT/K8cU5NuO9xKD2yM9v6UiDgb8mwJIYgrJhNGMkJ7QmJXv6rP3tYBcy99tJieAc
gskmhbseKxybCaDudv5jWvYNk5lmQ0g8NdfjOV48hp04HdL467Xc+aER9KwqTziOUbnnnkm0ZMED
2qbGbn/giSp4spVK23pQEtRNXIB1Th32wN30/I5V0uui5gbwNq2PyAF1wa7OhEAC/UGc5/H5FmI/
yUsh9NUau9WckmlvxHZxOgmvqLwHpH1gJ38Qub4Bjl5l75Y7P732I+9bDFr50TpKVXdV7Eh1xoGF
HPhz3stjto9aNhJCymifV3PC3XAZB4hsepjCIvBKob/0tM0eZL1rnyLI0pzMHEG7Pkjgmos/ohGW
W/fUyJKjgf4YvWESKA6gMCpuELDKwOmp0209GUnqfucn4eMXDh7DfxUimco7OEgyJnB5zDYQQQSN
i3YvfYzIbejZflkxHReMzXV4uHioiZ1sLA3N/8cd4jLwopjN86axIjxq4bXvVs3K1auMuKdTtP8R
ytnAebmhAyq7MJinUHEYonPaWGgEaUC+omIBoKtf9dny1ve2Ffx3nKsDDs/KzslaJsVNBd+/cHxc
+XSEE/yIFA8PiIsEKVhzrxnijZT2QH6L30LyqpY/CWFLoiu8F/vf5M618jh5lMYaoL6z9C+JO7yd
yNOEOKnpO7j9TICDuOIkh0mOSfregqlcamrbT+Yd06TkxWNyFH/6LT+o9Z/ckUyUOJQ7yqdNnaJa
6E0P+JKQQGeEvCPq+ZHIVP9apnk8B6Q83/BYp7prMgR6Y0munnLMU77rCnEzUKW0OOQKt1XPUpoF
kTbBZV9nce/TBiGPbLTf9ddCWC5tNXWEkM8mJmnVKqsK//5r5twBHGu1ZCcAuLTUcQsaT4xapVrR
aow8VXdLx+/uL2qB5ON2Kh5wBZAXD7+s8OjredJq8+DqJsaaTdEK7n7nBagDyLn3AtpRSUcXSG+i
bkiu0n98z1EkXV8g5K5ELOzD3zy8sqwx+JLbv93zRlAtNGUEMyECio2BmLr+RlE9++bGsHTQ4obG
byts5zSmbTxWoReW5PiZVatY3hzN9GN0QqfnzTKnMcotXtxjJn3/IM3DbfdGU7CM9RTH5QZ3/6Ii
06blMPmIjNTpfc18iO3fLPDwd75RurJJdxRGQbmVaWU3LRB3NLodNNu/8Qbmz+geYxi/i32GryzU
pHrlR93+fGn97y6EAK5sa6y1vmINBN6k3Fflkt6gncUw4eAsbmp10/fFcbFCS4EIyW2eO+DrTQXV
dI5J1qtTF6wNL/9ae5PpSqBkefhwVYsFeFBM2vs6QJlZjoESly9IzVfWK7ykJYT8A+6VoOcqmdim
oF8MHRCd/Qj5MC6cnG8IuRSIPnNYE9p5OJc4vArnisYPRz35ZNLi2r+0aEFn9Wo6VZq3YqqGan8x
HZgi0N8qtMhYMhoy0qpSAvr1DnjDiEcfXd04PLVfk17SdZFAAtUB2y77p9f/ZUBLlAxK1zutcQVJ
gQE9j5CYWcw+SHY5q01ALmesAkwizkdtkSx0DJ3wpIGUxXnf4wm2UnKbcWsK3DhuwsdT91kjpZOx
klx5lW+ckpYrOescLQPP0GtcfPpK9nH4W3GICRZ0gKoTraEg5PrOt7v0pSsSA8z99kooLmDTcta7
qU1pU+EpoXlDEULAfzdfunulBzrogOKO6sCHDzUU2RXlG7WYFztYgVSRVxMviT0MvBlbKbI89Yt4
s1W35D1EVdqqbUEt8VwuULJbpO719TasI+OrxqeVzOrbMP1oJNUQblKokCbzEAjr5agkN9PobvZG
LW33Tb8SmqBc/2zFpFlinvV5iGph8qPEQKJ8YpIB3ewqCT7WBLBWOlQBjWMtgVRsbCk9R0NJzXPs
6UgqlxHAFJztjUu73OG9lvXahQATEDaxDlb50z114BwD2jzNCLbkj7ShwIeTdIKrQGwiIu0zJ/Yw
snlz8YnpWoR98Lj5OPlZecwygSGeOaDfhm4Vthi6TotSDYP7Ghb9tkAVPVQsCY0ZLy2gatgNILzO
z+LTeT3Wh6Mamh93H0fDbFO7x8AWrOZ8rI7Vc1YSA8iVFccRVb8AgHJvJjjp5boIV1oZuzfsxjl7
C65xPeAfZkRDDyWgEGHsh8PmSXi1jjWC5m7i33VWJQIWbH5HRPOoWffog9B86GOa9JBMK01y5LR2
dwSKcrBhfZb/q9KZI5+PE0fFCzbJDZk+Nio/ElWagD9OWDzvhwsQDYhbTXEXrBTOS/QBkjVMRngc
I7lX7cdD66K7/iGbiWJDksqN8MDdSmMxSQAGlBZKzsUKtInSTJDxGEQSveynAIKg4/L2Jt+oGVXC
NGhK6dIyBC15gnPUEu1BUXjq+y27rpaEZnaH2fw676/F7l00vGC3YsJfD0F4ZzEULqsVHwv6UGcJ
rWnJfOdTm2vC/0IxaKbKpXwYegMbKAfG63fVsPuqfxo6uLE6BJ354hfmrPBeJg4gyK/P/slBdjnc
3HxLXMcYpDojNIoSekExQD3PzkiGAkm5my0QZxbonDE8n778GY03csuDgoRSLqWmAvpOTeHNTJrs
g1N+uIrjJRMqzK14o7usVOrYtp7pGh+ET/ga8UIUZQCJ6szU21DV7B6MJuHxHp/h2bAdcC33ssJ2
myQXNx/L5UH/iFelC1w4s/dfqvZH6pOJ7+fHICC3bflxRzALw1XabTi3xQJshwvLqA3Ad8zxULo1
Sq7+ZVPKxHCHOtjHordqr4P2azZqOoxce31HqzcAerF3I9k4p3PBOI0lvtbWRhNAe69ICmRg/GPU
J2kjI57a2l6pRjlaSEEGO7bDfimgPUh2UtaCX6X5JB6uD4YMeun4LKOoafvo4ZI6sVxOu7urfoI8
ME3t7xrqsOEHZsR3bMAR+E1Xrc1ccqdxsrXGD6VnyVQCOnLt96GiOAWxoGWClAHwvnYcDhRjzCWI
QeW41uq0W7BixJY6Vb6Tyy/eAgUaEJmX6/LqL7biax7JAShrM9YWFHkpzp8vEIG8TJGbWs56maEh
4QSx0YQmBGjKtzlkuFIp5hgL8Nna1JDPCUt2Dd7c68JDUXpiU98hDIQ/d85rFE1VlXtGvKlaSuBs
EJ1KhtPy2DdS23cJJBczCIuf8oZ1m04GuGQz09R49jBcW4NJOoFuVfQIsjqO7xCdQqYKC9K8JH2O
1E62pjj4/IARHJqgU/wV4rDqUzreJ2nAGhR+lyiu/0SUIbaIGm5IFUg5PLaHMOp6amB2rqeawxdh
Heh5sIpVN+OttLK2bH9P7Q1VsUQX+1NV6QuHv0PkCXG5um0zHDKMZN2Gx0Tqrsvx6BfLeJTntJb7
FfSm4k3aYrqn3/+1eNaXuUS6UfBxEA9q7JTMmFdlf4hPHvkduALqRJAmDUZajUO5VMHz8gw+762m
Yclp8usQyM2B60YSfUN4hhjfLRdGbMsDx4Z5RytIXEBxw24++yCwBrYKBOeru32fMzSrVKhyQ+2y
/P+DbLP8qaXUZJS1ucXnY3vtZ6ihxd6NNv6IPVWk0xL9BIGF5CsF/Lggj76tdwoPBObVGntoRryF
Mg/2BIZoJP+pvhGcGYgIA7/TOBP8DEg3a+Z361x8PDcrlh7Hb2SCCAdjBZInSyIYEioQoEpCKP5F
z2iMecAqwzH9mOUl/16DNWxDl9KMWjt2LssNmgsr7egdsgMfbOuQUDouDRhh3Hxk3RRZ60mQniwd
Keu/UuG+LV8ZWn8U/Dkn3TI2BzvLiyIIDl2TI4Ojs9VPG0UMxEwo5tZDyWchEEfrWeiKGPW9gtn8
p1zjakjbdy+IA+cQcGb9BU2L8RJdOnV13B+sf8A8bwG5WRExmHrpmIhq5rKOzxaD473bB/jOb1+L
evf44g2WXroShq3bJI0+4CmNErapkQw9dffYvU9+cDpXeHDHND86+JAmMFZNndX7hZQgQJe5GeUg
95CymrptX+QtyIYx7zqU13GLHC7vMkGFGYlrJfmGVgBzDUXrk1BIIeM8LFNv53TzDi2oXt0lMDOp
phza4fHdRY7H0Qb89bOni1U/BijrziT8/hIxlsr7GtCuGMY98PpcGlKbuM1cu/HCY3qgVdBJAQOI
cq9KF57TWhDJUVxCZvuybLt31KCnEpZGIYL0CR4v60GSudWNH+eY0bvJFJ59lmFL3ByoyQHOdTye
LuwpkOrrF3qxcCdeDrZqrjoeDXIAU/PWWu8bw5+I8Q4KkKcpG0B9V4ieP2h11FsI/j04KpCJoVth
g0f/IksxzGT13KsCAOlmfPcV97h732453O37C1Y/im5+UrP0phBZ5i0PiBHriPfud0Cv3d1oJHRY
s9Zn3Hk7gIRgQ2o4gs12rdJ/JYFOu2Vo5fmq7lJ5khxj0vOBgfuYt7zQfa5AsQlcfcmUlBXhD4+6
m8++HtXKckA1W9A+E0OHUvf9kRCov88rqmWs1C43s1E4Tp9tLklNDoGwzgCm6uBhMAGFp/LQ2K+k
HreIcZ7zQt8lXGg3nn0wu2mUgf1e4Zn2JcUup0NvZPXi1E0sBK8iKclhWZBaH7x3DyUkOmzp5HXM
RSVQc7brnN9ogZMomDndgBharFF0ZkOxFBjJZQHXGv6IiaAfk04iANUnKVT0m5p2h/2k1AF7arCm
nm8xjkvrYGugp/1Qpkjqo5FDVdX0QOKz9uMh5LPJ4BVwCdoIydgVtnba9kkIpetcA3FuanLy6qyV
sH+bkUsXgQ4KR9ya62/jt6E97pB2CuuT2AuuSkKY1YmbpKvVRKh/RfCoLsLe6oi1mkmOjHeCO8xh
qPWTFcerfzG8fFXdA0xf+eKXD5ISuZoLuAo+yHJ3yBh0pJa94FwPHjVnFCuDl7EfaQOTT13b6t+E
56LRo71wXnjA9yXEicffJ9dm/31If66FFYUXIXIAnhD9tp+Ogab3jQBk74PVEoSbBwNw/3buBswC
N4CtH/heRfoAJ5u6TXqVF2CJ7mh8oUvBS4ZA6nkEj0DS3PX6hiNfuqASuPfRRoO/65EZsWT1fSrm
ddlASexPgB0ZKpQ8OxKMJuWWpKql50UYkwknLsT4yWBS+qLBhouvccXA87Nu6LHqZ4OJys2mAoZt
cqPtrTILmj/36O3wk8RQivC7rP9es+wgSbi/0twFjLSVat2fpPSnqMK1rzpRY8PknBrRtCNHLFwS
NvOAx4vHpNByC9+gVkdwA7OJNmZUg1/3byNyb+PPE86XGTvmm2KOMEzr5HGQmOcujST4p2Xin3Ur
7OZfXocdhkHWanZKZUHuUxChmW2ajQFQq/+c8SASgU8Tgbj5TNX2W2Uj/K4c8tQ+3t5JQoFDUjOv
m5geqtsrJGFmoCXT8BmDC7MiAqqUaNstM1xPPH5MWUg7cfyPdCwwMwmILcLN/qdoB86s1yW9TQDo
sa1ycDp5bL2IEV8bABtQzjLZXVX62nShCbOCP4VzHRtLd2VGkMtkbZWXLABWpPhDkiTU2wpWsmip
bnpCbsCPIPxem17G8tbfokcnua9qOw4dyYapB7CtxqRrJJmzrK/TLG6/E3KTZSy/nohSxaUpSmVp
QlF7N9gUzoTB+r15RcsHrrJa5hwsm2XoNphEgLgdybyleNWEQ6sLhnGotFqN11w7rExc4Ffknfe1
ugOhG1SStWn7q1VSWNZdgkCtn4jLiCOjomRLAAwzK6qbQe88VWS9/JQBYVwuNmwZUMuvRtwt8pMP
BT1hv3kug1HZhOhZwHI1dy51V6Zgn+YH27+x0CdHBz7Uxbh/uDHwvc4TZ8OuqDNPcE2ZRYLSj0oG
45b5tOoCCxYi//vW1YSqezd5Hwr4PnkPg4C117Fmac1IxIBKGvBKS9l6h8qrYET955N+1t5gtBIr
AlKJnC7B4RVJANK6qw+evd2UszLES+h7dN8+CyZbYC5gybKmDzckTQttN+2thK5IrFOrjD9CiVs7
pZmGxcqwqcEHbkhaKKvrRS/Tqg0gUOJMVLs/AXTcfoi0ljFQH2dwLgiQNQC/o8KFTCHAfNRXhlEm
spRPKGI39CqLgbYLNs5G6TB9aGM1p2sNC3mqTJT2MmtwzRWuW5/4uoVn57btVftt7UiML91BvuJR
LZPRXKcCW7KRusdCEczFWGlmWpXXeEmOi/IlMjVHyJlq9sqv0dstRnjJMzMUNGIoWiysxp5eJPEp
n/leuiaEzjV91oAMf8YMBfScUaC3sMUc8RwvyaHGamAmUmLBuPLJU4bBieRZBPt2I8G7aoQJkBEJ
9zoRAIZM8Tvu9Jlr0+itPYG1bnybHUowe0x5zicVT/5KeHYEzvaAS6rFR2OYF/XwpdjrIw3gWy9h
VCXWHZi2X4nXM321hk08dSuTZNk8Iae3EOmqctYnv1KG/1QcnSGVW3P8RR1Csg/Wfo5OC59SSF9z
hACX0DpqFblPYiUbCnKcQg1S7Nst2eUbOiigOZgQEooP9VZ5p882BKNuzoZ8lBSHgTlj9FwIaIaI
2VDOtpJiFS3NffvlAZAeqMu4SJyidt8gpnf017WwcU73rvu0STJXsPK9H06iBSE5TKs8+UYzOsFb
zENVzrTYbJFG5rumCDzVTWXGiDnqsSZSQ7VW9d9rWh5rV7ce0zVu0CvFPCRnzbn8Txrxo/Ogno3r
I1TzQudgLRF4AN+iDhYUDafFyZpxKBDGmS519D6dC1j5yH1e7wdEYjW4gQP/7RzQruoO3sNNlzcE
xudFLAaIoh9ExB3sdX4kUNGUK8Wmk3jz3Fq5SOZyQp2Svuc0MhZljPCnGhG1jcag0lyHZxXR0WmC
VEb7D/t4CpwhpQNLU8TelIdlqF18AIKUAJGQcxcDfFhMlJXjaBsNKxJYYstDQyKnim8UBl4MtLkr
+v3IFTVE9uEnxkBee2a/ioKirps9s8U2jhQ+3cwGjE4zZewAuyIJQ996A6k2dkEoIScuApqf6WOg
02zs4CsPpPdwXHooKammJ3zu4S73VVKJh1IukBp9+GfWVBVpH/9yj96C9xOGvJZxLF/LfAMQGbnA
5Ui+oi7mEEfFSa24FVS4wiifRmZPVgMaJhG92MbaRl6TG0/0Us4RU0J2mpvm7f7o2KBgC96jZ17l
OoMeKUkX4+BGhggQPf+HhGig5wcYrJ9Ua6/fWacpVAGpBX1bCjNvVZuhzy7zp7et01JwQ3wjwgDZ
VPZldW0IYf0L2K6NfFGJyBKrJ2MpAzdsaEio1p/b3M42lT3KT+zinn2SCC9cw4c4az3iIdjjerik
IqfhKVRQiq2knRWCZujpDeI8dPY1oZ941uBkQUd0Wg4vsx+3RigH3SHuROrdZALANQA797h4oF/v
PUhCYernprcq8K0ccgmIbAlKgOKbyGd4v5TAJH0kzAVZ1YXlAzCGTdpgh5SUy0ohLGYSaM8cLr0Q
54lP1O1rRDVcVNhzXS+d4ulIEcetzBZ/OXIpkJYCPlxuRuchpZAW/Abt3spcLJPPSpF3nEYzfEM0
5rNBvFqxUBkR00ndy2zDOAebIFUn9NvYjRqZINMQOkHBPStYfnIGQqhTFt4rC9yRuG0OLGSaMdH2
QUtfj0AX20MSu2aeNHw5GZ70SNaAQvtYJE0Ek2jv/mo/VNgl3vaMWH6fog4z+CB4bCZQdkZ6z9y8
HiIk+AYCP9VRGHAVl/Pl8ypq0k2IKxtGAjNtd0VLeKlh5qyNXjG9CMDK/rI37ljfBzJbMSG6eYx/
iqLDl5sm1zEmq8NLtEjm8XnBsXMLrdz9pTGiSZxoXbF9om6ojk/eSH29Wy3DCX6MTw9Ue2ZVKSkC
RxkLuI/C17GR5+Srr28NsgWn/EcROtJDkOgJzJUeqBV4LYOMpdNazRPq49KlHn3Gl9LCkKxwmWi4
fHtJuAlQM25y10IOGPPwxjjTsR4evn5E6m+Pysh1wjhQWkv3r3wZ6D2dSD940r8KUPOhLp8PYhUF
FFLazx9J4OEYd4K59rhdt/sCzc1RYQOroRafEyo7z/JYJJIyIuUY8gDtV4kBaDVHsACwHSQ9OPxQ
IMbkCRwq+Ssbioiqa8ORhHB7X3xZBb6/F8wYkGPZEGH3BfPisc46/SS8qZVeNAlTwYZ0qLWe4j7P
CVptG1N6yJxC7O/YfECWcgNfJQaq9TMflN65qPuDhnmbhsrPhpzTBlF+5qjqIeirhqngjr5jQbI+
+BMLVbHJMdyryttZcb2VGbVZt6bUSJgQRA74oyaAMbiYgXnnWzm3TTnblE9JbRk5GHCeJ5Aqea8G
1ZI1cOZR/CG40pYAEvMLZJcQxp0BaAaXE9Is2NHT0bnio6syy01CoA8VPhx71SuUVEHuySsJGjQJ
sXUSWBWvqAO+8Nn+Jv5TId9xIV3jh2IsdVENrClgowIm0/4iWDSc9aKY1NTjROWUvwYqUP9SBksc
bU0Ja+vayRtkCBnV2Wtc1FUlr3qNd36BPKTQKRE+65cM8UuVagxOVga9fo028m0y19TSO0jSCF98
iGGz3y8WX3d1hcvOj2VAsLuDyNSSm0tFkzYbhw80xL5zwAaVJHo9M2H4gukRZ8ILVnwS+31+VIlr
lBE+PphleBIfnpiMOg8MYjdydJ5gHLlwZ45ns8zyfh34LHXrJVLTbvIsLIhByK8vqxpDiMS9RSgt
aNq9o1+qBfV89qpJFitHsdG5TIXdHhbcEzZcrcKCuMMrTYm5K5YuoDh0UzggrJSpXuQNrDq5/Xpo
EU8uoCSh9dve73vtZkBZsb70PjoAsNd/0wY1TIBgcK1eN8lBqcbr82aXGm4V6Cylnr5Pw6v15Wi4
a2QJcKVM5qOy8XtkHm2dnGzt7T9z5qCrOyxdDz1mJj5FViMB4EWwpCakXHuCMl3L4uhGWpaqECe2
+UbjsO58fV5BnLX8STQddUy6IOaM4LoJTQxqICtJm1hzP8LK9++GTFFSx0eDKpWtMjyY8A82LZ1q
5YfESTCEfcKEgQUJJHViWwjB6g+F0V/QnpJmTy2yAeGmVmfn5KCrLSalakpOsr9oiiYcOicuZ4Mx
rWqsu5UNI2JssOxMQiDOd5m3G3gAenOuJIp4Ykim7QJJLs3JTN62/cLmikjV8XJ4KQIxdrLqxsO4
LAXZzDi5txDnx8IlWN0EWfpekb5byh1pQWtHhENwvdkK9p7bmoL2Y0eReMNExAmReziwt4Xq5Snd
pNAxjH4xHj5WRKwG3wfYAPnT1p11G5KibT7v2c3eSPiQ09366PB/u41LwgT85kRC9EQwUXkpJD9l
E6dDFtM4Hb64TG2YwbpzNXmPW89jsg+liL8/nevlVo2CJohj+RG1FVll910GquNnDaAVZVzCArLU
Q5EuJbHNIbP0gfDQWkM1n+X8neeipLtOBZsRyuwzx1rzuGi4eSxhbGIsphGDiXIFyKNhZLMHxqaH
RJ1lg2rClbA+yGQGlm8ubujfRJ54oNmW2LIU2nzatW0924asvoKCK/whwrYJM4k4gyU9vra1eKoE
CwApamPdty0aWjWvq3h2C23+eI+DQOi0H3jaW0Dh3nW7jwESdtIzQEx24b8dXOqa7OhTO9opOkeu
llX5DrGgcrQWMfUxw7aNQ3W4Xb3rKZcB4QfXrCwo1RDnaL/J8l3D3dFF/Fyxm2qSe860oTPgMhvj
KU0u74MgZXsZ79eWbIOMcc579dqvpuqLyLUvPIPBNIK0LVpvDb0RVq0Q30z+g5RFyvS3nc2dHyQN
mh6mQGOL8WbQntqBN8ZNc6Q7gIuaUyuHHAHFK5rX5zhOahYKhLDOA5dkm30hpE5HaCjDzkwammIS
ECHDOESTIzUO3gVjiCbVeMSY/vCNWNqRuDWXX8IHS+F8PTv7EZvAXtmrHfInwW+nmLI4bPNQLdbB
aypZ1omV7PitQBq3LXgBHxSaygW97vQVdRmXHrc7FuiofvnFYQoQLKYoNAGeGVMog8BUIp1Al/Bx
K28382DSGiqGoXhrtuJDw84W7qoOmlSB7+ykJivAjFb7M8fApUZl5dAiToJQ7WgnMnGzxv0IxxnV
l/EhKOkS/K7eF1a8TD/orFFuKFGa3cTvqQdsiM8qvQIUACqnRwaJmH3H06RLbfj0RRACHAqWhXa/
djlLewmYFoRdQcD1nT0hiG531P5rJDYcjYtYERqXAnUpA2MNeoLIww336Gk2wDcj97FSwEk5R2fB
UfX0q4AlWnFgWBjOAFGDxjyp20MwdkswGCibuolgsB+MK/jLMKNukitUyiGeUsLQFV8xyzCJfgb5
2XCdvQBzDOmjLOuAnnDqe3mbImcGiOoWLvRet94QIPzzkGq8PGghdV3xt/zhCly3jedJKLSP0cc6
F+NLfRzFCnlrBx95+ahFZdOWvD3IgyWvBaBYDu2QR5tVPQ2danC2m31fLNRJAdmEqzJKkWgFH+H5
HwjJCGZfCGpGOdvyLWpZLV47zJD1C9BE01Hyh9GVWoWhpF3vzR7BxgNk8kackrJ3yXsxnB9qlMKp
m3MQbAFxshm/JC303MRLCY68zYl2Pku3xM43dy9DvT9n+RhCpvcbgGJ0oaMkOceKx8fStVOncs01
h1bwrDKrrNn73lxaQKAaR0oLBpGSHoY8eKdg8hZqzR560gYw51F0MKcc2xLVAAqPA4cywvO7jERS
w/2ljJeNbpD0VWpd5e7MTMv/dy5ZWOhN3ohnCl2T3UbdvlqdnM4JONoINlptrvPGv93FHFVlCFT1
8dpUKQ1tx0j4JETwugsw/G7P0QwQHJchdLpWEwiWqFPYRQDggj6Sf/yLnv9EKtbg1tpLC4ovStEJ
drbFbTa5q/ERIx7dzi3qGIuGHsabIvvba7fKLgbX7cVuNtaoifuCNo5Ytf1WghfbHdjPm8r7eZpR
ozajJck39AhtDjWtEputJkYNcMUm2lSszokje1mlkWL930jYS8kOXL8PIIgy121dMGglx4eNEm0S
QfJYRfW/3c3Osg77eJPzZe2Q2WzD4WfYvoM+b9GztBAU5PFSNlyrDbDh2VCwanR2TpmE7wR+y3p7
dG6fA1bXXtKOwpxCwajNN3nkyTj1EU+TMPnWuZHyIxiBnsab1UHY/Of1T4tRrL4NXfBLygUK6uNa
iWAZGuoZhEXhqfSG/T5azFc4nJ7hvM5Oewr90UqFn+U0vjIBjRBNHB4+lkCNT5svNuvXwGWLd9bT
C9a1FbcX8AT/+i3htvcHfdTz/WQ8s0kTwvPOyl7EYiga+wENUqarrJBkfwZI2eddbh7B903X0wDD
KEiSJ6kphTseaEMEyslHr7WWUdvLrSs8zsgRhhHo82GNMh9rVpZdt0vNTDdFr5h+D/gFvNmQYROz
9w/LeskXQmzGbKXj1hHIsaU6Xj4Ar1pkvx8yHtzlgEJeYi2QbmM9iCGpDb/+Da53IjiDhUjvZB/D
JYrAnm1m0lmZ38LfLTrv4yYwkCHwmtqzvt0skUahDvmC8cqaapTenOykHvZGG/aYANVs0BOgpbHb
UVY5rdyisVPO+E7yNEzCrlf2MzIXVaA4ePKALog33ViPPTv8pdalVHxi1smINoew+kWHKymKvlf2
A1s+e0T1+WLK5PmDHZFp/39M0ZVDGYziHyj/DLwQz846fXjhfPL0hc8TW9y+TXxd9yPfN2pgAwD6
nQ0c7L+F5E7yXoy3LFM5oQrK7ql1kbMwWLrh2aengUhij12OAJO49wdu2sAlaK9+fWGKCW433abn
3ZtxVVoYjiO+PWdCo0VU7rQI9NlFZUADxypAWcCzuCETazoeUH55h2XxCVuuuFkgBx/WESN0ebGg
LlcmTKwIy6GNsHwPTWP7uMZ1EM4Jmh7KW7hZJPY9tbWcsoylAsmB4JN2+zxOpKmHSb+2km3fElDV
Xj13IJ48PukLW/WTk1MeBpadfn2kOaPvNI+sNVOm5L5FZ+lcIUGaGFSYZw+uKFlsktsjKXhI84X5
oVdQKFNC9WoafMgZ3stw+ZpILawbcUBPnGu1dudQuL45phsK/QazhNDz2eT0wxadxtSHlWTQC6pF
R8XYoiOGyp/VlZkTaNoFpvJoZ6hbHHORTHEn5ZZNaSVS2wSH3swT+AKSsLaPzPtGx7Cbng7tZB3h
NxceAQCyNmKBaYtWBBHocF8sASbNCouH8jWRVnjlLu5q8LWEvKtzxutYL/2pTXOext5EtXs9ij9Q
nNtZaRR/jbXSY5Oqdn4SX/xMZMtK4G4X5QzXL4rAQR17Moy/hta/ZUj0nxFmPipmG0n38IxP8wZt
H+TUy2yhXX1KQPJWG4Ia9IAiJ1QWfmf6di93wLn3DaoHc6JzRBa+f6QiuUS/17QB9C92nErNjkkq
T2D0cE4B2HRT6TTMv/9bwp1l/ItNbMb2CWhF6a2cAvDoqMIgvrQYuaj/ZD7BYmnS3ipQLMgFCr3c
n/g/j3Mx6tHCfkr3+VrhI2TLMoJAJFVRq7/bKcRRr5s+UaUlp6nhxHtgfI0FExKQGmxOqLSuiY6f
XS7fHlFeYd25mEVxoACIooEd8BMnSSmibDt32fvhb2SwVdDjZtKd8/qLEjdzOck+4P8Hj69XCGZj
WnM/bCdL4ok0iGTTdNWW8T8cjvz4lNBO7Qkfjgbimtg1DQOOgv9EIM5JzMDBqZU9spniiJiv4uX4
vsZ9dDQIY5ZhYOLl2kJkgqZE+TwwawqH2T/El2izpDqWDU2tHjjOM1QI50Ola8g2tgM0dothzn9i
+6cneYmP7DunzdkQg9ZZTT2OOrAXzknipj2boJx19dL5WoHoOfiXVevGvzkou1QldD1WYYI6uZ/S
LsXbDJmqKN/kogVvvxZNVkLYqJpQ/0LNIYe46AGH2yOFTXK4hQiuiZygX+qce+dJ5rFW58xGcUsr
ZokTkCLyqUaiA28K8cBEi0JFE3owxTG0ePtGlhNkrXPHAEGECpTRCuaNIfcG3ZBap/zynvTB4pY2
xTci6bcFNNmi2EYkkSvu3g19/1KgjRyFCDEGs1CioGgdM+Yo6Iis6MlXVBb0ecl8AaCBZjWxIeKi
Vky1IwWzVlBZlEUhtL+m6WbFi2qw3QHYekc3u9ZbbE8lSZ0fwPa1dpPXpyWvf2TBdNIzsVTQMOm2
M3mwHMNIAHk/ixnZ7v7pAccqewUzqv0BIo2ki6oEZ7t7zecJ6u/MIv1N0SKtufCoAXyloZ9w8a8p
5ZpC3WQadKlRY0Vr3R4jR7x2ph8MFxSqpouFv+TACcHoczB4KXkU1Q+qQIFLvl7rybUKBSlatke1
SV9yos2zKIhJXFZpk2iYyf8FbuTem77Hd9rjd7V5xN4kUIpsIOi1IHLmpWuWRW0ZbkTyKGZYv3kR
jXWDm0ey5eyjwUauw1RDMnuB7jzlQ+4Q2JlVFV6PdNW6lCKEI8JSLOdrVHbICJ9QKj43Pg4qTmgU
F7duu8WFEOMcyV2j6xDn+w3wSI7TfpxzOTX2FPhWz61EZAOIzVbqTKHfspBtXcoO6Df/ntc26SHH
lZr/lD1KM1HISFVyVepw1nFvY4xsW+kfX6wMInSRZ2AjdetSuAsNyoCyb0RlcjmThLaKMqHwhlVy
eQNE4AwgXy+hT2ZfvghcmguWGCZjDtfamMzC9J+RNMYk2zaLu9Eh9DAjW55xhSngHl9p4OIqKyoP
aqDJmELJC1fvP9mLr3z3anHnQGt3vOvcJKF5urV2sMt3cSm6nbjReAvkRQvKSWl5/3cxEtXR4fQZ
38VkIqyNrtxUhE4N8iZva6M0Hwa887BSPeblXk4wJGMh1/HYtMEh0lqyOqXNzEpULVAmGqhfmHRO
RonRLlFzAl9qG6uFloWh/oRQvZ9T/j7+MlFu0DFw0HVile44E7tvhsbf1uVYns64cBkHTpS3nd5H
HlNP708Yd/B46IJQ43RVEEt/jaJFq6tvsJEa4VjJektJuqfGLJTdPLZQIl7MvJu6WHDO6srXmPIh
qBd4S1RNAvlY4imaEIHCh9PKxt6ySGhFkoknR/y4HYNeNPSTGBui/p/0bljdau4s5+M0OQn5EA1+
rKlF2tIsronnZGizIRW03jnzZslHSSY8253+qqnZGP3HJRrpf15qtQ3f8gzYYxnTpgMY3gPa07Ca
sFtFzDDQdM37S5mbRqks2cF1+u1ZV6CdSiOfN4fp0lPgXh41Nq5JzeioxZuaquUoRnbea+bGaHbi
y95gdQgvkaL/yPgGR+SzbojJcpjMLik3PrFzOf4wxUT/hlJwl8xK3JOoQOkvN6e2ohsEaZMmoSng
/WU428vOx5pnouNcnt3Vraa9BgwrI00yj02qRaMIvZVsfjCf3f5UIfLxW33niUP907GGggNyQwI+
067bEaddouJdX2nYI21TGJwXqU1KAtlbk5F+bZMkHbyBfL57LE+ijqQXKLkHUQc0zKxJv61hF964
7JAGeffBxdYRTzGwBGKMHzejSeYBPakwaOirqAQCs759gKdP+bWajyMdX+OEYyEfhYl2UNsW1zNW
vjyD5JtQySmXnU3m2WU2IOMTZxNCq+sceBfSz1yFaNkRVwz+zIxeDzR4YEwS3i4OD+dmNgdAToSR
J6g+EEbuLvHxeQuHNrJg0XG2Ls4BDQRiR1uMdUI/0l3L18hbm8XAXjG2eGZgNM4bmwOaZ5EcnSKj
EZe5WJjtFDLWgQda7FSufIfgKdHkqidWubG1QdjfeZd/NMA8HYeRVfq9dI4OAlnfj5C8/tARJlqj
ZlUT6JNtM2viB7pLxlji4Tkh1xUvKzrGI4CoWkbmOw26vL1Ucs1+G+1TTqOnO8GQDlYXHcpFCy5f
ZINEbz9zbcD23Xb9xi9KxkpDlsZYWOIbfFogFfkf2/vXsOG3Zy/UONI6SrhblG1J6y4O/Y9Y32P8
G9JF4nENh7EiofcOU6cjdISQSNrxDSAY09wt/NQ4XjKJSmmnwoatt2STFObLJylWWF9oRWS1CpzS
CpynO4M4xCLJEEC2FxULYDrSnQ1kz9ztqlRWEB++bjBFP1MoD6RZNkcm+/PM7TqWGUxtzAidQBDk
TtuqlQzJO1P/yttCJRcDX1AFnsDf3CHUUKvlHYgGoXyRwNYyYbFaCbs6upfN2Q2pisKIgBMS4E48
ITK4fM5MFdNs4WygHZMsUowrCws/49cxJg2Q5E3itlWy/evzZ8/L6xZW2/9Nw1fZnEm9hwqi4I2j
+bGHCyEo8kKjUKWMZiTdv+R+4Y8Pd/Ut4wYpkhThZGG5dOzh/Bl0TKbM2EP07OC9ebUwxfutMbIJ
6NqghA3+vN5v7iA8EoC28K38KTGDr0NNnUfMEk4jp35S3FAdD6jqrWfRlSgAtPbPYnTLneV5gr5R
MysnmK/cCTcZ49lMdoOYQSH0NEZp8P8wIImkYtaLEdvQHra79Ouq5wYVc1Vlsvpoo6wDMTw7yalv
L0kE6Xayq/xYOlBBPfthXRq22w9PciGrLLuZAw5QltAm78bbZRVL5D/CavtxxF/642h8exdezzY2
ygdL1+Xvx/Wro+vfX+jU6fe8UJOB6uE+OBr7SW+oYDcX9arsX29ZO0dJuO6S7aF/IhcfSY1S/MRL
mAjbCuRzHHqSxWuk7Sozhelyqo09rxa+wmFi+L5cx5Gx2oXBRWBrsJSi3YQffQJvyW1lG1qoUjXI
BERTw6GiM9ieG98+XPuN2eLG+yh7DN8FeHmfuGJxHqZtzMPLoxmcd5OxFLqZHPSe27ocDyWYX055
oJzojlDSoqUQjK50PxhqeFyD1PMmZLLr4X4zFrSaOusMv2LNZluP0ZFiTek96fRWnqzvyVwC3VWi
jfbu2Rv0viDUWt8rZSLzWHcIzasS7aNfuaA0lOUkMIiVldpnHQMxT30I809GkU5f29tM7xx+uFbG
4/fTggsjSOs73cs08Qa78uWyol08JUDec2jIlD2zwQM+Uk3gUEdQ1iefGrVVlwzHki9Nc49NrX6e
iJCPAPF0DUjzbyDzPIeQw8tUEBZRAGBm6vPXOOIkKgZjCG96d5a9saMrxJS2P5RkJY1CEptsc8zQ
7aTaWZLZXualULIrBhxKgCgYS/XFPWcI/+HQWA6IO+QbR8B/xy1y2cV5CubiwL3fXUxO5UcRsRD+
f9GTt4m19TmKvqQBAQrzd2xqyXleDRRg/gqa8Y0Wb8LTin0EtwE60TNZ6x0Ujyg+2FdeGQESHCTV
oIL6pMIu1OTZJTgQ4Mx/ojiLS6shzqq/BFH6wVV+aYoReTx3P0e3xnONaQDxQzq+oGXrye+ytK47
4KhAAEO3vqu6LWrttZsMCnbJYh+zNDKJch5rdf4+++HuwxQsbRovcsnDIGT1jDoPZcilGB519QC6
tHT7C4f6cojOWjwReGQjrdTBxd/AFYwpFWNCVrkVwqBQ3184XMMhjsd3PqQtofx+KTnqMSi/17K8
3oS+6FA/ogGZkP4q3DXOmf+sYSAdU6X1hm4AHLDdmIqHHDIiEsTItjspMPjOamagnYURlVSIzAns
KlKLkOIeA6zG8mvBhWeGY4zAyFZGM087va5OX7OsR6mQoUmGSicKYZKgDAwjjO/Um3zm9ZPCJ+Yp
GP9QWOIlhRXTG6wx4UM+KfNtmuagrsBFVBY+NjEAasTGyb+/CyV4+3U8eoslliNsA+egJWYQh0CW
ILn+XdW6HC/SxaSBKxN2T8SoXWewI7kPxpAcpRqlYUGNwlh6vhETeVS1PgWJlADbQMOJ3kFoKlDf
bh9iGb4Vvpt5qAH83nSRfPbLi/YrjmHBeutYieqT+ze4nN5/xzpT/0pzi+BdC49gLwjEeLVRGXsa
0Zz8kuMapZm32QYWFu7uEbt+Cmq3ElQw0iO8FtODRihBrXJ7ddtCBRwYBDtJZe/AZUDPEVGSPo3I
ns1e7WFmw5tTRneWja4njHO6MURdex0SAXOOu+Ow4EZPXhVrgK+v63M/BbAWgkTTLNNYBjrEbWLN
K99y18jxEJOSQS6dTRPV3SXUWCCDsQSlVSn9hm27YyT/dMYI+3e+fPmo6vnp7C4VmJu7UDXEx5NQ
/QQ5bBmHRPKedeTwN8CwXR0SvY01b6vpp9yrbvJIkc+P/3YCGN7iG5Rnk2F27cuX3WykIuKPplc5
qe3V0VhhQp6JgYll3Z8DA7csNrTJ6M6C+JV/6o7M0JrJfJpoUHcEF5TnhzDcZ7O2a0Er7LYz5NJj
pysg2En54x/CZBvyI9765gU5XTWkJE+rFERvbfPKdF8F9f4JJq0460+4gYcxtc6QtLLSDEh476N3
+jBnWIzqx/IOFQ0e4lGRG9/W6mt+HEP7VLOpuV4zDHZbHgnsbs382nlccorlHPRXYXAYXokTPGeT
JVStOzhM6ypwsYVXTYdfah+wtJuktB4KI9DZrrJu1m7iLChwu/iLl5Od7Ie29z7SUECD7R139kXX
GCyuW5/pZpJzbgs8dolwfPrjeHeOOpEOEUEv5nVUUlq5A56S0ncRbzA6J4SrpBJOCVRXcJFNokBH
Kr/4dw+M8V8OpTdXFzpeE/RvpYoH9OYOTNFLlKWUcmdld4h7JkKq/z1zeHCtdwX56hWhd0KVFvFU
vVZdKVzRljVHVdHcBN2di/iFj5r+6FgKkF7zECwaHvt9OzicfbDPtfBM7ZPMVGPsRdI1zdW+NvJ/
k6GwU++p0tmyOQPanXpoGc8FfCKFAlg50in84kkGs3WVU//rxOcgaWVxkFbIQDlIXWroxXfFkDeR
RUlzOPTa3iaBiDZeBgN1J73tOFU2Cr7/tVt3x9hksNnTndbdzuQOSm36ojW2WHg78zYsE32WKTNb
7fZdMEoIH4oc05b7d0+GrpiB3pjCARUtAlYgYcRqyowa1R7R6gIbrEDlCnYmflbBdv5Yri+GYYHe
kWTIFtBiuJAtvhONtHG26BdvYcDQaIWF61iiI7oYLU/Rts6HJQMItZt/DIV+LHWuCwvNvmn4ke2h
cVxCCkBb7n4BDXr5DMudjad3+GNXW2O7+kYS15J0B8WGJ0RJE7+sLwKdDKg9ZIeoYyyM2vJ3JFXg
h90SO/lQn1kd7+A/4K22CjaUaT9++ZgAsqKiTwPb4ZBb6Fsi1XF0i51w4Wl1sBKmtKjcxYs5tMMS
izbcCf5COTocfm5YRwXvQtqCcv5Fe8Tpd3vZDdlIML+OTCw7kwkEYL+/eyMCK/q/NCBNE82VwyPN
tUKY5j0eqENjALU4+pIfKFa9/QDDtgoDmMfCHHLklHESoP5LYKKxsi0sH03vvc3uCY+Au+zCUpD5
PD8/9iknyC0/KIlt7/MMjNWPaLZFe7JEkIjOH7oLGZW0iYJJObGsQ3OmtAAMUKUZAn8pGXrzIacF
hHEOvEuzufr7uajgAY36diphjwJ+yW21rLJUYoZqS5Ywew+Fx09Ik9OL4Ee8ziGSRVlkFsYxrWoT
uSxEXdbACIUIzjFH9GVuRACP+CzPLQWTu1Xj5l4j1BAAbjrl2hd/0DZsgb+OvaBJpHNgOgrahFFd
CgfGDJfAo1E3TRVNrzc8MbykugW9EQ6FCStd8TY6CzL8BSvWGaZSRH6NFdRY1SieQdLjOSLSsKjv
+FuMybMJXX3TCJGPonTe6zlovymnhSPv7edghskO0n8ujK2SzYrj851y+kzTu4AaOP8eFrNaDmU9
1RLyI72C/1W77uy6zgeOG8oj5u++fajVUCW37EwlOazxUQiemBUNRLANP6j0dTLs1qP8o43NwnUa
wbM3uC3GxKzgBo/PfQZG+/0B/SMxLYbv00oE1pDWWORndWFfZlvwD4yadQQ24Br4FjVWQx0/q7ZQ
NFmYfG8Fnkf6SGRWYvPAIX9Y/ou8lJGBK5b9a4hhztH3JIbJiJ2J26nXLUBdVD82J96oWZ7Qqn5y
aDxpY1k8erAXW7eyJj206dPwRWlw9lSjtCnYSOnITR8RBokzEthCAR3w1GWwPDfwYg3CyrAHR8WL
pfuipGfuxdTo9v6SSLx7cZhiOP7IdnpCQ2y0UVfsOZTFbQ4LTSkanrYG43GMZTiMUKVIam7RQyIj
IGrji5glUbh++otlXQ42itn8E3tijGpNi6kTtiiZvP6IOs780uwayUjqzLTiL4htJ8wyWBS+w74o
IBf/+1UYquHwd6VGVjbxZOti/kQKmWdRS+RvVPg5kesMgC2dDeasGgRI6etdiioTsIiXk+zhnCaT
g3sMP4t33lPVbaYcAD0zCyF0x45gH0yhp+tDdLMzKUxNNP0wHFpNZgsZOORfOHevw37ybBSqkIYE
8knrlpL2Er7nWz78gXQbhLrhS7m0cOy7S2RZflsmSsGXCKxvhh6+DPXyKfzOwJZeRHsfHBANuZbB
Kt6PYVFv8ewlEWnbSlQI3v9ldjTgsSNmirksSUVKaDdR+aTU9vYGK3yP8MSboULlMoL8rhrfJQFT
fOSL0Sc29MG543De0sxuFDbozN3tZpAGaE6XqQfyIMHkEO54+ewfg7QMpNjEVkwlZG9/kniYW5tO
aYo8BiydQKPJvyP7QXb66FA83Q7lelAZakPGrZPehHDWPOGDUuHpSanEKDMb74LNHgcWrFsC9Y0w
ffHTBG0rmPoTqrUbSQi7bhZwTicT2PfQ1hcx4vHwZH53RdcatUtjriXqOcV68PdvIkBixYuW3nJP
0bx4k4y4totahTh5DmXDDS+KTy27UAysfIe61rkMs9HAUh37WJp+BhwG7Q78kgI0MYrdasIT9mFA
PnD8X136nglwcXsQZCi4ONMaacy9eFAavL+xbRN57w4K3/LuSpDzZ183JEVByzs4RfFJAknZbYX8
FxH0R5YDJmwrfH3ZsTflt9bDT3VTXQO48B6+kavlofQd7gnOi8G1FmtCwyRCpUtDZWcCevTaiM4u
R7lmJn41LNbAAzRHTsZUd8vL7PnBC2Ef1xaDNMTjQ6ZjfgXVkPahb5ib/H9dOr4VtFFGtbQyYt57
5Q6CqZdJYWYCMAHDn1HjxWWd25dyhIIusD+tDX5XVdADzYnxrsc35KB9UbGkyNDy9HgAIswmjWqB
Ux4NrLigo5t1N3x9+RL+5TZrVuBlKu20zXrtojovGGcaJq7E4hXV85aW6PmtHyiZB9S4/6cJ1ESD
Whz30tIl+gqiGCCjMrdUyCje0DOH6Ferh5iRJGxMRozQZr8hc3gmEFXbUmARclWo6xCBALCFCju3
8zgqGWZC+6+x1LFvs8+Cmwn3t3JlSIkbGEocoHl9ZEwMQcQZtZr4jCTRh0RS0S22ZZPFxcBYBEoS
FuOjocVeM9d1FzS0/2ZHToOu9gTAsYL1ootpEqoh5Lou7AbkY64JK+TL7nHd/4PlzfOCGzUl79k5
UA8Px5nnXblAQRzHbziz1CEiEYN8FmE7EnVqEh7ppofyZyEQ4jmCj0ZhbbWFjojHoT7RA2oWPJRY
bM2W60NDAEYu+tMdw33cl54Rj1EB82Vqv8on+o3hGJOpLVvud4oZAgrugncVE8mVqfQ5AGPRkOPu
qzCE6cQdTd6AGktyCKEjCqEBmkmfmfYp0ZxkoZ143uhpTQL+Qvzow/4xPaFPNb0kaT//W+sGELBd
eJD4eNxFzJZ0GGmgskh0Z0AvC52QIrDIjPXZjJpaeL36G0+TVkpQoqFkWnjIwYfCUywVMMKGRe4Z
kMAbn8dwwtUmHwFM7WrX78tc7se2BuR04SjA3XmLdeP6Ld5R9weDtv0X2e6Ky03iwxyBFqITFwmW
aQhl2DCGVUU4zf4GZd5/Kwb8gQUI7+VnSNUiFHIXFtYbdBQTjH6lBX0YpP6PqVWqOE7MgCDiYdf4
R2IIT10ega9qrcLc+ERq2jfEe+JS4HwO3jO/O51j943pDOD4jTBjQCzykvJ+YmWgbakTi0PZewBF
avd5/7KllyTYHoNdBEl9+Y9CO4aAOpCEgUSq5WbmZimK8ENh73Dhg7EpjbbYxwX9eTZ8gUimOJEz
rMbmq4cj5Em2NTDUMFJ5EziNnDXHV3Bi5D0aEkeCse9z8XNkgLCvpmc6cejC0tkAjpMqOze86z1W
XaMVHRD7G9lDB8NjczMmMnIDQaCt4qj1xujBjD4ENZgCpklkFwVzwYE4GIIUqe3H+u8WLPtpIeCV
L0eXLF4S9dx01A1m9bpm0ZS7rxIIF3dDf5LRfkFbBW1hJFsw35HuDDndiZa3H9RbST99gHusEh8D
AQLk6uTPVARX//VUr+6RGB+yF8JHpV3J/d4cxDv/Wgz3O1vyjTZVc/XU/KzyaO1r7gi46eMrtrpN
5jmCZv+Qg2pFa8fuQSdLuWbkXEFjU65gbSZNZQjmmcHB6sciqLM0yz3DAYzqR5i6eNAa9cUjhqsM
Hu6MZ12el023CgDVGQqCUKRj7UZXtL5t5BL5NaxyQUWIz6KWspsrKr1psq5WC1kgdeSw47BXRtTW
mM8oXZkimDB3QrXayzAS8OIZqBO3xo9/tpCpimUf4waP4FeH/GaEpbgqZyfmdrXfguEdJwOQw3tt
CUESY5fkb1KG8pm8LYNvyWBD4Q6G1K0kEVcc+H3Rx3OxEErStxN4PCJ6k1ZsH9clRexqTpfVjYKz
xcmLg03Qr/Je/J0yOEWdMayUUadplwDg9MDYjDoUN0+pIP8rfjUTii7B+66J6RX1mAlYeMIsqsZC
RvRwniXqJ1rM3/ISFbXmJsCBOfq7AuhPmmSdmodXW42+ap62uerVGxGQQJAvqjr2AMufJ9yhthIn
q66oWHlMH5Kaw/eICK7TaxoCA3WbkVrJ9J9pJ0ieuvxeFBlP8ebiu6zsdbf0f42G+DSPCFqQBL5o
0foIqC6Gjkih6tPBNoh1NszfLp1WAVf9Vdpb2NHDMLAWXnsr1jFkslNhO/F0M/izQCTJdOi5xgjw
Clb5vnRdTD0bLxRUcnZsktaF5qoWqijTqkY8olSsSKH9yUXDvT7AMhED6v1gKdZghzPo31eW9e6u
qbGkeNnupdfL/n5So6CKdbj4J9IM1wQb2r2b/Ao6A7d7ihRu73E0cu/y5fq8pUj77cH1w96HN/qw
fZn4lBBTozmQnct1ozAz5SWvnAlTVorlfRwOVizujpH2MDfpWTml5wCbTkAF2L4Ncg+C4n9rVNQy
g/pcO5T3i0RhSnv2h87BAUA9Mn0R/f0bq5kfdrDYK9hix0ZNPVmrgc3nZVn9UR1kJsIAfvMaHB6G
Fsb0h8GNQA92qkHv6sKgEObzvXENCEKIM5uGcEyyuWzhsRI6z/AkVsOSz9B/FRWLEkvESdbVcNdk
kCEnrk/9ipbRuVbIEup18KtWikWEiLzaeGBBWaL24p9PNxo/8t+hsahcQQ/5OqhMPG1nJRXa6CRk
VRWp0EuLkZTCX4gKde3qIehTbZ8nEZHX87WxUM7ylYuz51MCDDhFtWpw+wG7n1IHvKHk/SGJJc/0
q6hcuVXGel9J31BKnw9Gn9kQfo48XMORXSV8OF5hIlzphSwEnizKjAUIUDnYoJxpvOMl6hfCR7v4
UlhKY+V6cFUtDPdI9d9GVYJhm/T1xVHBBmQgnSmSo879p1aMaoeq5OsSwOJDzl4m2/toVyue0ye9
jWzUbqTrTiRA4u7D+8WKHpanVzMFj6Yj0qOSwNK8hF6Pk80mbmdbs69bp6TyFkGPVzmPr2tvuWm4
QCLXqi5Vy+p77u43fZPIXjIJo/lyVIyCO+NfKTJ6nktl8dcrZg018c9uWUstO3gvRabTmz0prSVL
gnC/3vLE7Wf1iEU9PXdbjqV+XApPRvkbOc8qd92MxyYykkS7ecwmeb/uRl6PmP8xsPPgvE9ddzSS
z/vzP5L9rE0bqf8qfPYsSJE0oDYs2vOJJ6mgFoYka6dMOqsUX+VZpT/BIc5DCJgsYbeezS10p90F
8qADrxqCDPBFWB6TSd2xyoa4KLx+O8TrBQQzya9xhtDNkhM76BePkpC6hw4B5k4mv/O+Etr/ap5c
wTTe3DfUjgkKwJNcZ9mr0Qs4TRTepZZSaxCTGjr4T7YaUKd27169eKcGhBVvGH1RstrOI7WmL5YK
5WBIat+rrdEQbFbxgoIoPBFiWGOmqe7A9KkjVmaMDj/C3lCaNKIhy6iEiwA4Vg4vNPWkUf/bf+VV
EXxTjq7HjxRcdrpcBMpw+HNtx9e3vhjiSgwXUgCR/sK23WysM41RPDBCWGhTs3Xtd9eW8dJen8sn
3MGhop5f062cr1tJER0aYpjaogsQ7W9d45bhL4uoq+AkZA9TYFAM4wt5DoKGPwNDOTiaCI+CF6Rq
+srZ007xRRvPW6Pfb+AehMmJs5a49ZzCfsPXWRKg4MM6uVX1Lfk5imiDQ85uGlr40kWxyEDxLJov
HISLvoPfj2hrBnP5Ol3BPM2Oir6GAcjMZSZIw3BIPZ5sIFxlsLf4wCQjIbVB4WNCAd/kF4RJ2SVx
Xfr891mZMDJxmlVhB4R/wDiyGy3KVIQmCUig3kHag36ctVQ7LmQLvlng2Hw+ZLRx6R2url4Ly/Sp
dqjDgw67Vh5lBDar8VbC8oY/Joyxf9+WD2e2L9quSAUjjDXT33NdQyw3nGEF/g3odyvJ1SXnUEkp
vgxhRJ7dFEcSuhiR6JBv9UDNgVS1k35SZAeW6fg+GgggVlOjooWQh4tRBn185XuS9COHkwzS5Psy
ifA2T9KH5sOCyLJzS/4LN0IqieAYy3bxLy1U8qu2sLfm0F9vToKZVfGFGqdISZ0+N0LtvTBSNj0p
slQh93icxx0x6ivT7KmjHuZdnBL9OGi5S+XtG0knPdxnij2gMzuhk2/QHuas5LY51+mia1fD2EnT
ig5OJKCFUDtDp81WA1hDe29CES055sma0D8F/uR6iNPmBPuKuLmRrSRLJHpUw34b5Tl21T+GP/K8
7djbhZlL2yZ2WsPl/rRD0iZAvkDq3PJJT1qRPEaUIdLam8LROkID7Ysyu4R0oXpkaxBNH9qdrsfc
LigBOn5B2CjmT/f5i8YkXUTV+S0myW4fikEOoEcPP8Mqr9euSszsw5x84O8RUHBSTcWV87W6BHyc
IWdGcKk7ekkmjqk967wEJ5s6ZGbspfCTD6xyxUlQXy8Z2yQv11t6k0LE6eB8iZ6/P53bCdgGYycZ
a20/FQXWZ2Q1NHE+uy4j3WXv08CC82K1qM8wcyF2O9jnUjPF7K8Z4phMJm8/pgU+M+e2oi/W6Qc+
8ZWdPI9gOdSwn3yD0tKjQh4FPf+VvDEji4X6wERTC17Q0hRuraUcLAXA1SGelaVypygxB1ioiT6q
Bd+6JPqMJChUGhZIxKLULvy+wtvsCN0t1dSLeRSBjtNEhd0cgWnTCk9VcSScex2bfXGnet66E+RR
HEyk/ZOdJrKjx+7vDMoHNbv0+ZH9shjU6MOsP2JFeMJBCONk8RmYEurqVhUIwTAWXZcEL26WBnN3
pKb15kqdRn1sAs6ThBJ+jzmItY24IMFEW3hyYCDzNiHY816hsrS9CmZhn/t/C3Z+kKysnkTem/Iq
ZFrfly294IKKL2wO7dEktLQkPt0MeP+VlKwGRE3MuulnBsvmybW9NpM0DOQRMpNp8ryYmMnjL+aC
9jnHJZ3GYAhETWXkvTAZ+TpABwBZpt1LSqqe/LKIabkBpENkAtxxrxP2RodV3O36itri5eaxG+Fs
tKGBioMgLGfGAL8KIFqFz4ar/Z3VHkYagllInv7DgKW//aw2PFCdazPGALYurHDGj8OFXvPrx60J
XlDJovgjZHkdUakY6Oad2easrQBdZSkVzHtM4hBufIQ6pDkb22PcHzt4f4On4viXuxG16aR50F0F
Tjxpa19vmnl3Tt4j34L///oPlX5X0/35I4djd2JRkYTgecrId3N+8bFtIexqlW34s4b9leXbkRfR
IotsrtaWoioQ1SEhxwtLE9sG2iA2Ub0nafIOsFJy2UdPlpQ6wc85o72VgTCAl4hRuXdZ6J3s+LHW
cMZ/PwzJiRsM1wX6BgnokeXVLXTiGDo4BNirfg1ZoTPqold91zuEcTDtqdLltSIgnnmsgXfo6Qii
DlSDb7qkrbIJIGKOuPsKSCcZPTzJoHjQckvZNW1k1PYNgKXxjpDAmSjdK/ZWLdD/BYSH5NGyqnFD
umTr3fOn/D+jNqNs9emWa015itqfQ9k9nHtOm9Vn34ifk2DXwVCZ5Z+nv3gjgn4z85uu2d6Wbyoy
WyA6MkIY+msVPjEZBzwEeGstW2ECK6W8Fgsx0siaRdpX8yCiIgWI9oyShmYzm894FJl237G/rMgl
bq9FuH+nTCRwGPTlEtLMhZNGP18pzajZuKoJc56StmiDt0M6aIG8ypIqnSia0sVLa0CAIxtmxuqp
8Ko6ccDeZlD9+w6imN4cah3B21NMXjlv/6ySi2KadoPf5DrhXItr+ND6fv48umIHTpcDtqJUwEAd
9B98XONQA1P0PEqbLtXUjsdwMDKh5wWSFx4I8ID/EQy7506FYwFCS5TaczDSD76DlFuHwe+x6xRQ
gP+1CccYSiBU1vkH+1sjPmrtJkJ8Nr+Il6J/UIzBh64Km5LLLTCJ2W65CtOLIZgfj7tZfF9GhVWw
Y0q1KQgBsP5dfliKMEirU46BK2eRlwh32qtqvY+gMwp8eJgJOVwfoFWvrmjd9Q+RGmeyjhgDjsXo
GhrrPcBQiSbCwX0fJuBZNGiBiRU0DBlKcnhdUgMrDIT/jD5weVu1jN6hfwdE+xDVGzBT5/fYyKCZ
PinOtQ/9xp/4SZgmnxo7bnIhV9f2Qlwa+AkTTvEJ/3M6XvEPHpWsA6K0jDy/B9eS57KGSvvk0neH
cmRkwN8Yq30pTTWmF0BL0+6BX4dOUqBWhsW9rvOdhArYU9z94G9n8DCPLs7q/5cgNS0eZxXLFKkv
E41BCk+HzljFdJWMDfR8/zDbMHZ5oIRubgmsTpQ1lxZRB3bmCnIHCREM/XbJb/qPkXDuLzcHRMR1
NSu9SJ432GriNCtdAhU1Sp+bKPRQxln+ipMKDXAHs9cRCFL0it9aBb1RvQjoj8tQZ5zizoBu4Esg
wEZs9/T2h0WDw/yz0AJV0bxpbe7mGzkApmxrSh307/wJATx8H5D3EMJSqbH5/0EjSGkI3unPsHPf
REksC/1ziG9SC9B+jQ5diJQcdstLIeHlz0U/OLIban+4YW8GDoiYf2uDKFJgjainuMfo+dL+bCVQ
uCQgJ/DF2TG183bdDIc+HjArZFh0THJnq10l3Fr2LEIigj2nmtNrW7ExR7Pf6odOEBqiudKaLX6r
CKPgxkCIvEFdP7HM450rwrJeSlT1B7C/kJGAJzb3B+uacJGqRQTdUL1Qc27ZjGpySeQrVdovCaty
dE8TGBRIuz8+TDc0phmRgt4ahgJr+X5YZX+92fKIJp6dZURszSjINlkSS7Nz09dWgxdOdXd0g6pr
VKfDvPUi0kq99zSIxQzOwnFap9sd6Dh2ct6l56N/xRvibdMbhp5wEnepzXeKp4lXBkKlli34snsR
Sn0c1xF9MrMjoezqVMX2ieQDhuNc2K+K+7rNf+UAPzOTmR7nMEisbP1liQ2G+LWk0erpTzp7hhjG
wk4Ke1XP42GOOdGhlzEzlvg/A7zmDqqrdyEafyzqDPiqoqZfsAcN16j9k8Zl26g1ePHToJQvnKJy
sPJMaBhOXKDu1AUbkX2jFO6nBfDfshGP1LoRYu847rMvjt5WkChJoEllk2rSYo7inweU28sDbCsv
H47C1n4VfHD4DjUFzQFntWjLc+F+1x9CttX9H5HoePAG2xH7KtZTAgnU+HpPmC4zNWSBVeeK5utt
bSD0lcOB3QYBaVt5cB/ocDfiao8c3OtdUtjceqMtM10bo7uZYJY0sD7+cVL0PSbJkHMMNV2m5NBi
d82rPrZauRKY1z60lNcqMNfgxw+Qp5yYn78oMWJV0Fmfq7QQGer7MElmlK/AV+VbLBOK0INxjtZR
K+MlUnwta37SV3obFz0xyDZQXBlDl+eRK7eRrXwwKfNcKFRlWhN/Y1bDdgypW3rJ+IhDJ1vhm2Tm
V4xL/KI09VV1mH3Zn7idl6zbCaDaSkunVuEwicZTTPLywG6mMkBST11qw83OO2Ihm0f9sQMD4zld
WaJA7bWZd2Pv22dUioaEa/EDa3Cji8sbY+yZ3ALQgAudElV2SsWa6ygXc4AgyOoLjqHyy5LRQE0c
gb1aHt1IX5Y35xCtQUeoxXZPJ1nAuLF6uSaMYKVqSw6CeuZm85897PMxFA3gPOnqp2bXnjzKEEmQ
m6hHNMoa4A5EwW9uk0UMwYyK3KnVGgmx6I7QC7jmkmoC71pECY0cpqyWVT+IuDwzhlzTWaRbTWmz
tNcbm2gkaOlklAaNXR0p8X4o9VXA3Ob6KtXQvGwX7gCgRLsKNZjAngYO2Bi1YorrS9sO25BOGXrw
j6kTrd5cl/xxhI4WLhT3rl49lCkjMG6lumUO50UUGvIzPobVnv53voUV5uAkLrPcfNxJ9yC8MMaZ
CNu6Z1ryemOkacorzJ1XXi7T6oCJuovbL9uxexmKSIh7JLrfZK6XxO8m64Zxoa1rN0yY2nr83ooP
4MqmW6lJa6VaFXU6BXxcMbrsoHsv3lGibbExr/rjmWaP/0Eg6HQ22zLUGr/LjqkKwB33dDzsJM+m
HoMz0wEli83bC7IHx0i3r17MajoomymyssKu9UAoY2ZjsM6wcDHcpbH1jBljxDyX9FD1otQGxWnS
cWySMU+TDr5B2+ghUlDbyP6ckN9VXYX5Fgj4Ana9yuG8RDUbS3+/YKK29Rx+HUgXWlij+fXMxqes
chRWY37mCRW5bHTFspwgy/j+cQJ7lQgPmN2Rm9QUXAL4Bs2JaGMlRHyKv//FuhP9MeR875dG0rEw
7ttloT5sEW2uHs3cvMk7IxzMaSBEDP3Jfcmaeu82YlSFQ/D1bXy1lCEPeBrOxtrmQY2f/iAZs2dh
bpm8Kd4h04DXLJUMMCsBoZr16w2m3VUdmg8m2BQKyouzjUWbL41nQiKtWOmMjenmTbhJZaBXiQXv
HHJzS5I9pslSzpvPDhIIFDm29UQ205HdObtk6Amn5YWb6jdYuecCuVwI8Rvj8nEqWDUiVmOYLWNX
ZPwvDYrEAMv7GJ/wgyXbL59O52DDEBELuh5j4an3lAhlGWcLpjirq/tKlcxu4R/OEHYhUbcP678R
WTBFLZyL0mzuwXR9j9xRDFpXc1vxLo6q4nWkaTJ5l2nqfdg8/SGUZ1JWDPq4+Vpow9WbSrz9DuYb
XXoBhH4WZtVQcKHQwuBPBxXcoMVczFh3WyBAmp95KJXCThrfuIdMYMz9pxHQhYOHIocbwR+HKwp0
zUy3hVh4xGPhglYheQPyzpyGnzfgDyyZRC5Ru3f2bCw6/jjIYMkevKSLGyiHR4VvcRC27SPj8WWq
pzyOdB1AsnVqFRs8Xb7WUKtiGVj8eJukRrEhQc/wGXM4Ki1QpV8SzDiOtlcCcko1je+jCp70cDbE
AIC6bEhjXj9GDy1AI2Q6lUGQbb/E4GgGrx7R6ho9x7nSzMnWGHdso8Y6JgmueGLEamq8DPrymFpd
erAfcLZg5P4g5GYYVzLax6szeRHV+ZPVg1D17bXdRb7uO68top48yejI03PBgcEA30b5sPy7ZDho
WBXUYyXdSJZLJGRv+TkU61BhIDAQJe6VPFRg9vMzxNJGIdZDq9eNF1Vc6iyKSgUr+biz2eBlULHn
BdAyL3jcz/lPQDOyMwvKMvxy3hKhjDaHD41C5TqdDIzX/g58Qip6g899uMrFtdG1Z9C+rQpafalZ
R/a5JWIBqTrMxXivX0S2+2ZqN1NXBx31EWmqWaTyXoooCv5MdTYngWSenmgJ+DZ6JRMOYkV3aLxi
3yTPQugdB/XAGnqLYAqRMS+/SJQHV/3fVus60YovHM28IWcZ3QfzWjBPF3m3F+zs/Qq4ZVpQy51q
OuYA0UEZbIKKr45jpg2EKZemMpWl/ETt5kdJL7PDQkEwXvf2wijrvOcjVjTTJzjMccrBZ1v1uLl5
O3hhHrQJKrt8OSLTckFJN8lidWisWArL7S/8Ln7d5kGdNE8Atqd0LGnlngrnTGppTnq215Rv4xpP
uNAH5qms+x/DNz959whNy64PWBM3UCLczMukXWCBu/O+Wr1gZr2RlhnWIMT7wgWHX3aI5bJtGSZl
RMG6fRu8VFJUf6m7IF4HvjNde8bIa0E2Ub0VQkDLUcTEIvCULOGIA/3tNLbXVH3MFiRFJb0n49oa
cqet6YTRRcyRR8ZEl9sGIhH+ABrkc38Vg/k8yIc03DvOvuXMD7DegbpjmIObbFAJ1ixCd2sEg8y8
+A2jl1Y9nZWtLjPZfD+RiSszI+VdqXAuJRsizJA02teJuQQWOZhTbtXzIaTSde5P9xcZP+GCPPm1
5fjtWBmIMqlWu0wEFVYquEvcbMKfJCnp+QPc0D8ePkMN5NfnADNFvWZkjTk4prpBDwRS3AMZ9San
1IAQ9eukbyg2LDdutigMZW70Opi7ENP5R1UqZwL0RofoUthmLj8un0/hShnqo7clJxzA5N9UTZog
KMMddWClwmevMZLQwPWwlM6zzcB8kCM6Ns+j8HgIf0QOkMaQHMbBn7IBAnStI6W2YRuDcD2MRm6N
CBTzo3PqoNdwvaEQef8FByeq9XowMA0NTsX0dar95awmW4tkmDBjsTBcDYwAqrlyOYz5v/oBimzj
RPELvbwibEf3nzfnyf/DP5C7dDhQwHY5TV1zQ5PLO4GopVj0DcHas4wUrm8MLbQdScSgalT6oTQH
AVKmSaqTtqo9muNjDd8+/NUkwr7Y9A7iseg2D2PAIbfMmz9EDmfN+RQdWg44/rraD6lqX4Djz8aJ
GMmqE0eTtQ4F33SzZ73fzVmd3zxPLddR5h7PjOEFAItynDOOoQoqhecYGxpQgE19HyUhiPRHcx1L
uE8vldIMm/Yqhl8bOe2OGcgfDZhAWZXp03OXaOsmg79VLVGVWrBNlLjlIYERL/XO1Xmt+rS5dCB4
t9iKhZXoSW+eLuJXs3du3qTjHbRKnm8dr2jF4uwWleaBzhNfOKN0kSYEZnRQR/LwOHZmtkc9Ut7A
JUstTaIckkHSYD/etarOF+9SoAn+EF1bRDO+vwSUZetpQqYDLIcKOgiua5Y2IRu2+Fj6dVxl1LEO
EJrRs7FG5nmwyJiVPOk6rOfW29iFCWkM1OI0Bafbb8nAkQCMeZ1zc9J1ofPQL68R23QikNfphS/t
O2HfFbtapOqsAehEEmNuH9a3+ELaEonjv2E4KZdtRjaHZYpzhkapY8xP/OGzJPKY0FAWege1UJaM
zteuN6lALKJp04RKRBmKhmWwbvp/GxDy0IPV9Ae359az0oiu+7oA9hBxAWjqPXZOkzJ7p85lOkjn
fuUpJRgoqSsMIF1UrbOos3vXl5gM3gEZqfJCP8QJJOi24qc8RrFvYewSDz+b/99vBbdWdAnmFbra
a21cOZiOeVxhCfafViuohWeKzODQ2ok9A4sX8WPyGrHX8+MF9/8Pq/wxqhFz/txMTd+ALgfSwihJ
pSvy6wXlGQIyxB0DLyTQHlGpEaZYNGDTie56L5w+/9nHqh0/AeMSm8ZKw1PaG9GRLKbp4JS5nmOf
/wsl1mWYVzlnPwDjaDiP44myQWgU1i8Y8CRgWZkp0Gsw3JPmTv+GDWp1zl6cooIm0fou+5lQxhHs
ldNGdG2hJna7Fto3lJUACJOC7rN6dEbCgyVyYw4xivrsHFv3BLDZxp8gr7kVM4OlJ/XpkSH3hZJV
4t3LFGc7cZ1wMaPqLIQJ8aRKgtpx7hYrbfJmBD/v4HkC+dzhRzssGHOGA/5cbsdqQVRJq8QMn+mp
pNfmucBYooICxrRSwg6X2MkPOja7m7oFeChM/OVwWE3H/NdPD70idubH+HVD7+UCOzQRDD4l73WX
u2ZFROkywTy/NUwjrNN6/fb14/LKfEqtnddi7Js2moVIdUGS4bnYuuOFQxIeVO2vUBi3cgYD5LxU
CXjq3WF3ZEgkkD5H5Gfse0nLE2Hc23ws6bp2S9G33hJ5ZtxF+IQh9cqyTMIPeTha/Yjk8ueheIPa
s8FeH4CuQCo3+xK/BCz9Ix0Edmdu9v5zTKzrbgnLqjBeuLkIelVEvvKgVemurYyIA5p4Qf1dVZ3F
KqrRV3PsaixyoPXEPB1Xrz0d0h1yKnfeI0i07bhUy9QjY/KjopXcnhfke4vF+BUom4X5iOdJRNmt
ORPCgLqTbecLafLAFzjcNM4v1HblP3xhQqfauhmrgLovV5BSW7JknQIH7uobq+L/Y1QOYDwllNIz
0cV+ZLhedSKiduhUzDhH5hUKoanyrrWN0W1Y0sAUxlukIs1vLNWChQ1vRQe3kK9BDp0azJCMjX/G
oNiA/0yeB4RcQnEdL0zUsvon1C2cbKooNXU/SKcWv4nBleljRYSxLWjX8N/sBgd8J4jc1o/mOe4C
cP9JVQX/7dfKzGHnaa0729sDXP8pR6KP2GqjDY+eiNSY6smLvMHfoPldam0MdVbxOXdZamaIHk2D
kxHfyjqwO14xK2T2qnriicZpqAY0Oh8TrGQ6wNq/GyWfYa7haU+gqz4PgXKzL80gpyW+0+h+F8iA
H4nWH9oD+osiScGHSRF7PrCjOK+pYSaR6nOE2CSiciuKu90unmDHG7L3FDuYwwJnPOI4xb/knyCY
fCNrcs+sVznaUPy5QWwiA5ssbk4nYYG47gNj2bO/NLAhHvxQnB+o6jDYp5dS+tCqNVkq52+pJp9I
Ebxe8LmjpiaMjqZtO5EaI+GBafulojRCWHjfg8sJuqvslDstO2S/wWUO2+iCNLGk3tenTLZU2vr1
vOFpWw39SKYiD4MOP8sXirUpxCsxDpfhqMCJxl41RDjaAnAzkAHl3unNCWz2Dj15rMGnR4sF/eyk
Pyo6l+ntBOYpqSNs+uUGW21r8VCXpkTqVKVToCCpku/lZ0VYvEaMb514JKhulCmMs56wHLYHJVBj
cX/g0hWvwYKxOtb8YOaIB7z7OMQteH+FbOkNGAdf9MhZcVDs4Vo9Mtp3HiEzcMDTdOJGf+2zazMU
Jyithmnv4zrv76FEDiIO1SHRESrYAsri9ClH8bC/Vz9skOcqE95c2WZ6q1cBzz999eEhaTxOujWB
YU+i+gBjDNkyIhGeD3lsPQPBtIIxf/AWUMdjN6PTJ85rPpgwQ0SFWktXKEOMADm7xpNKr0zjemZk
FsVS1wFSpAewKd0p/VoDrcJ2RD8VjvMGKGanQrhlVbdjq7CmZuWqr7r0BJmjukhK8EfYgyPTBva1
bwRg6P+glY6S6JIbHJqfMj1c9VzR3LGzn/nh49uqGSSUUfIzY0w0mUj2g35ZTCBguT479oeMpwjp
cIqPvVRdp75umkSO0fG1GSJUsxbciEGLOygk6zW+TXxnIz3cpPZPeoGQKV3X7hw8JATebSH4Xrxe
j5affBWZ+yeXGj279+zyxBWbB+b6vQeXB/wNECJkECuasISsbK5cAxtStPX3FcOunebeW/qfzVij
/GXc0yPifnkp7g+oAW8fFg0KYpGokdAjJUHOlbiBLb7IGOezqXNvAnts9DIGPcSw+aorT69KRQGC
D6I5rJjCbeIUzelNTHlO5ro1hPqC7XtAUobJgzglz7n7shPA1G4el+l9FbqQ1VGGF50nrxvrAHmT
H7bzpqfhnDOj5j4x5hhEpDCN8hyBuCiJN9kJoBOqZghAMRL55qeFPYcmTG+3+4Mn6ybfKmHhHvvP
NeOUDZyOXKfKTtbILrOKWVOKHgc6KiUpd8CcUalZGtHZxcU0k3a+zlOzwz+kIMN4df8dxfmORNzq
wwEhq//b7E/cHIeAAORRaqIfmqXi36r0PyRWpA0pm9ID9Ii9M+F9vD6h1z8BPCREg0fhm+1w4U3H
OYnsLLOZIx7PSK9p7TBicipBstnT4sqTmMQVXTIYPgL3zKVerGKsd5w2puZhW5vX/d25py6ADJS8
3ON2+eDptx4y/dkb1MMMtwexVTgDtuapt00zkTfHEkKU0hZHT0grAYDeKvu7fz8b8303TJgWP+9b
IrBBbALQbrv8ZeZnTKWlAzBDp+vFKMoU0fd15s8GEkStNgFMZwHRM9Skk0A3l5tch0HNmOaCeTKp
ig47thn59sL7f423LHVwlexVUWSli8lCAghN69uBGfB3pbIRTbq5ncXL8g9D38IQT5idG8QxLysT
n7S8HLNBFUBhl1wNwesx6AMYS4QHyVgbECsYvkE4B/mkYThN0gNUBskN57hAd779m3ZsjiPeqOXL
Fm/QkdQ7sJbmfgM4PfIuSvrhw4p96NXn1QVWHO+ChPhci81vpN5ryNmoSvfbbgYJ/Txfso+SFLy3
/kfAOlUJpx15lzqbMIoDO/LtkaDQU80bTtN42MTJ2JrpKOC3Eko/PlHCSdQoMLg/q8UF7wwkgcU3
6fplksqhGY5CCDdvs5gqv8GBKbMGFCWJe91JCSeFvr8dn7hSmQyrVvd7BDNMnOEKLyjSANzo9A0z
DDvk6EQ6i8o71orlHsdq7Z3mliXZPSa28MHARV4pQIFJz1ZznAjianaR1Xy+lbTDBi4OOTQsTbQz
9G1VXDgSF7skVXj1mj1wO5EsLyChCkIy8u6XzWcYIIqUTiZm5dvQMxZaabHRG2Y8YJ9OlvU/iexQ
ONvK0AOCH65DhE9MnKJID5yd8TrAi6TStNfKVBvfzuvwKRQSa+wWyyJ/xCwPmI6qqxEQp/j8b7Gb
dOiZC9vIpbvjwHm3Tm/1E15MYrJXoeS8SrPa7hop2N0CVJ/A0iEmIaJMGNsYXwZAeSELT/zw7dVd
IGSzLvfYTZYCskfiQpko1b6eVFLAZCc7gJoNZhx508B/Jfman2oZejo0Rv8GsCv2v6ANaS+oQ/OU
8yHAqi4GiIi3u1hbzcCV4QXpPIJHU/cfOAXjEzDAYNaa3wvBT7V4B0SyEi3qEKVk4zF2+ZluNmN5
4TaoGqyKzfUgnmOgMdMxF4Cgojl0wfPEkMTsai/7Zxwrj2WmuwCy1nrTDRY0hI9vYtkuhHYwqbMt
tzaT7yGsulvUlXtaakemOJ5gV5dRgmoVjAJCoEkDfJM5XH0ScnPZZDuIYshAT29qFKjptDvZl3HI
BTFlK6L++v2HgVoMGY/padq0NrDUrO9oIWXFtn5Tl7jKovjCTMFPRzzHyCZFTXDy5fImbSjyNQ3x
oqkJmUyECKymO8Txq18sB1Z38jr7hs93oX4WKjm2Z4CwLQbIXwP6uFKeqeYz0reOXRw+kXp87coc
5A7+sp7AfgHQVR/mAUSrEkXA40r5v4EYNHN2cQLs9ZEqD+WaNYesBcX85fhUb+FYEab1ENiI/TLW
hzwJcR0rkA33IJKoV9qT/31It6l2ZaHTkhPXyA2YZR6QC0jBG8jXRBfvw6v2TlQkcu6emVkPLvEG
Gqus7YrPSb9n/SOnXB9YsE18aUChAl9Bbcef5i6kZ5gizaUaa8MlHRWI/4KrSQLug4RGnmIMqPNL
LNZRd9I4CrzikoIyYzYKn8nc9+RaKOOzWECtijKlE9lpN0XobjfDhfPeVZPgPy9rEodhhuSnwU9f
ArgWhAMHS66SGuoWGsuyurZs32I6qfSNWiQ46v0D+sj5ycSWxhi/gveAkT1lvSW352XQa0BTxr9P
G/asxQiExyZdJtbJZvsbE/+A0HfZnSpHOMtqanxz2xFjv3nMk4ToLj5vmzxzw6VyRkuUZt9MjMEz
Y3OQmwzwIF7yE5rZGfZnVutpIEQS1QfDvPphiLQvYfYGRDcVzwzdMbNN1D/sSEQnV/64JHCwgMGY
yngINXo2kdvXd8nASFynSwMFpIlsGnw1GlUrmva4AyxNXDVRQHyycbTfm8QsOfTalGdq+98gKb/m
Ayq39sELVaSQWgFAmF52etCg8NivL1tW5moxXzY9GjZnODmmvFQWQccYsRBDJyxMCupg5Jl2VMD3
oACcxA/33z17VwoziKWc92ELfGC1JGKOjMTAD7Q6ETo1zbmbi9A9wrmSqJly3EFS10T5KDTmhi/C
xcuWGj5g3fOKpe8eVmvaIMR5ewW+UB8AcI53ampr/o8y2Zah7L4CXvpm/LQzMSPm/0y5J582/R4f
n6Pek7+bMYOwbKS1PBPgynMaJCKipaBPJIDZ8at136AhHzss0umDffB7hCvUwJRdGIFxYSzTh4pN
WcNe/SBM5n/VdICD/KTthmzI+DeM8ySX0Q4/SnhoP+UhovYfDA4pgvmyyNDjYjf7eON+KVVAxEJq
QSBHLRh0EfB4CA+bsQxtpNtjgTPYvU0QP7Xmw2cQqnOiJelkEjCSUugVmSWCvYGw5vHqh2SeXYXj
XKHtHQBCA3G0FXuuV7aJWB6tSwJOkeTCiv5TCj5tnEy16N4CCcGQWURl2LDRwP5b8+N3XLkeuuJ0
dkm8MAIGdbRit7Uce2Wgp+asGR7FCFzDKlgGPF9LyIv3ZrFNlKhN+lzqB7zKe1auabiWMb8q0GOy
xVodm+HhoAlakBwz9TPccmKqf1IDs6uWeDKXLNjzHDUNwHUVSjdJBx+U6Kctf89rZGXkXQrw0luP
HGPSMRZWrSGPqkD2gIU5McBWXY6i17/blU8ukzDMsLZB1WhoY7vc6v0imc96A02RiMehOp/gE51Z
NAGSytj/F8zy6bKYeZuQ1bbhRhN5Oxw4+9GFrWTf1W6o5x7TGSd7Rkmk8ZoMooecjDwyJOqFIfRJ
ID0CH08OV309vGk/UlSKaE85TO3aDabLy+4N1Q0XofN7uHkQAQSBZYFvPiiTjHI+GV0wgoIbsYuD
6KsLaFmzC4l8BpJsREWAVTquuCAYJ8q9wR3mu73Cb+bumHWOJWgKkiFPO18MvFFXuFUhh+pVv4KG
Kw76kDSgztnJ0ReAqhjtFkSVnEX+eNcrrCp9AqmOaPgrSiki7IkdneVgA5SQ0aDNYMAShbAwlsqU
itr7UKP30OdoM/ChPPSticsoSj6akkiVe0xbrJozziyQBrMkIHssGjp1W8ILlMcADGIoFxUZNKFZ
gdeAIBmheJCv6WUiAhuVXWUa91IvXz/0KvIXF4c/6xHJrrCAwkL2jn7YJ+qt4FWgNo3jVtuxP/Jq
Ejqp1wPKZnncXmeiljqF743y0QcF1MYcrFh8rU5y+cWYEgYxUaaKCXesfOYZWHDeveM6zHkNRjwD
BRqDXQueClSi0zPenorGoOPvV9lDVCJ/HEsm+xizUOKzLnaD5cPV8Ch+k+mLH/IXBym4jb76s8bN
BN3ytZhcpXCX+Jewvg1FO67ozk7pVvTUgWjsSSV3Ro6yXCE0A9KfI3VUaDSr0/umdg2+DNEmesDJ
A4lup0PLr15ZHMfghgoAAAx72KNQXFSyUMfxXzLMvshkZfmz02HBvFZ/QSMeyMsCeSqMv2mMWEzW
3KtAmf5ZKVrqZJIsvT5rGZhZ6ZTrPdMrxjr4Boa7nUZYr3gGQLXKh/yP7F1PXki3d8fqMuyF0ZsL
yh0yoGSw4diMX9/Bq9LqXIBK98AgxwftnkLWX71QL4KmaojR2MX3ZxnG8/1OHiWKpiUZlMTkR4OJ
q7iMOPHLg93KP9B5FwQFbwy9/ijrim6cLS+3IBlSLIbexe2RWNTXecltYb6SuNIjyK2gtqddTEEk
+ef5A8GEo+M+otvou3p3sgciua0B4ue90l7sr3TOvS7XBtjiJDFvhoDpKSPc5gxl6753iq5k4FZQ
OrJZbFzZhboEdOGMotzBDUw1DuZhJXv8EcAI1TBfNosEUhCaSwr5ds4jlq3l4StXWcYMUNpUPljC
tJf6c3FMz0cO40CknkvU9zrb6AB9ZmTgh/GKX5XBFwM+Ow+SqbQBiBGMqK441Cx5OGxnX5Kb413n
4uVKExa2ICd0HogaP7hiqbUR6f//YqE/jFuvRuqN6fnxzdYUgtwfGl0JTndHoBYARhBJOdrpVKIl
V+x9pnf6IiwC+2EqjeDep2StgIYRIORLCnU3GO/tKkie3Nf8E+itIVI1/+T2cZQnrExQOqSDHQVC
u5TPcjzup94rFwysFR+lU4/heooMJvo5RQNa09VRbrmFT5B066KTIHW7A+RWHfbln/3eQdnCQo8c
mJ+Rj8blwe0EEc/+t1Z05C3Fi9zmGMm9NcAGe/nlqBhqArFwYVROznFFl1kGexJj1yw1oeJpiBSS
+mFFedQe6jtlBkiAa3rIfmmoZSJJzr0zKe59g1T0NX0xxK2wGUh+ptj/ThVmGeckzhMxz+FIQmcy
cJk6iiDJSWvn3V/7UTccBKkwBr+AmV0Qv+j+vweqkRAgyahFPG1mjtOqvBwIcW18+xgGtzSLWjEs
RiQWIfU2Lptu+Hgc1U2xfCNLa55NKryKsvLt7qvDJ43C85ndRrTls8dlZXSwkBGv4EdiUfGMzxBm
bqnJQjrlkb6QDq9dsTXFmCKpgn/oasjvj80UyJWRdrLofE4lJq8pwKxiKU8jv+XUEwggA6FIrOWv
yJH3ckMd1LI5vG7Jf+77pkKRRNlOxe+SgxiT6IaWm3Jw08MQ4bbsjC2erzDdBLz7/4/+qzIDKVfj
0thELjXeKWSZBF7NXN70E6KMx2mqLt+66IYiD8kVfc9322wPoTi1TQtUD/mQK1bmcO2PAnKjoDQU
B6IRVPnkWCfeyCh2s/ntPZkBdbVJTxykhZgGLC092xDMWD4EA4oYEv4wcdsaJzNBdSnAxG25oIV6
TvSsg6QslC6cKd4LPMRmFLxj2D/yVjRzIsVyD2fYj7mIfI4063347+vzfJhaB63okRLy9XUDcym5
rauPc57TnyW8RVIK0RslBca85RTHrnkJldX/pAY4mNo+GCjeD27gO7CuNmiD/1pFWTtzYlOreOpW
0IOJBzyb2Fehsh29dMZMUNuZj5D4hteiLEfAUt9QvkEW+dci6MWGfA93EroB6MbgpYiqU18mxFGO
PAtjhmZhuNNKX6kVvHE3yNBo7PgoMjAgsmYDNt5DAh3ZfzSURYRukf4W2+0Bw06LcsgFunUFvZun
Q++WDtyLypgcyJlep3r/QCR3u+knTmTayIF8dKl/WCWuxhAQoFColwHT19pAOBI27v8Y3taBLWq1
bJ6kWZu4nrH3rCgy4yIHS88kvkmRqQ8Ks3Y8u6d8lwFEt0IlupTkRgqeX6uc27hk8Phh/UjuDH8H
b5wew/gWEdApAT2n4cYPcjnhScgidRErU0aoTs2L3tBGlYngYxZLHIfEBE4IYH5oxdV5zqVusbRr
1b82QIDu1oRkN2YEPQ1KnnEatZpPpSrfbqoYu8tVpkscTMeFI+hwye8DCJZZTT9LNpM5I81bU5KD
XvyyeO9J1NxFHWnnxCU6+x1cJlL1TXazMx9piLdH34M4OZ6a0DKnsBzFR1Bo/Vjd/W2dcWproSeW
/XUSWq8D8SGsiSzeJOHAjnc5xnLNl34ZwgVkmFV83pwIyK4Mt05l/LPR7SRqzyD2FoaxdRcH2ibk
c6hjShI82IRaoTdkjeOgSYOkJuL3xfsgg1ICfdEob6xAHhLpCSZbGUDsKaZ6BCwj35+3sP5vx1XO
GnJH5aTTlSqrUUIQPUxQlzGHCBllZGGNqN4bCeAzlUHAQMPNzAmq8yXkMYUG4vet+1TwIOys/wvS
/1rggblS4hM/Og2L5rOOgFD9YBcYWD0zH5SzBoOEhuLT6G6jmA0vSvseIhyo/SrdxWSYKURZEDNa
FALFTeOoE2SiNx3RDljR602L7d8gxZtYJyn/dj28hfLta/IDR+yFe63uJ1qQWmCGGVmbYFlsP4Fj
8D77N8sZRLFSuzXl8dUvNSH9rt3DvKGxrGJL5lvugdHerlvvBlBTGXJv1Hy7K6olJUad3SCTXBnc
1wVWBU9tsqhLfSnCcHjPTnSXGrkzKj6ykgFbaZ/WJz7b53GQ7q9QVXUMxBZR7t32xYiWOm1UnjFI
a6Lu0cD52+NtTMChu37ePvAIrAqalIkxVA30euWgm+nEZRjLBXJ08gHGrDcI9DRxclANak1nea+M
lAOfBQvapV7PJ19y7GakmfujhGsj+cT8CB7WHqWuDqP03gIxU2s/0KUu2Cd1QYXHhgjP82hbdUCZ
k261VrkhvJ0F0mcRvTphmR+NPvA/Cc3W6PzBUD6ycla8XJN6ikTtCyKR8DDw1qZfAW1OrWoucNZU
CwpEgOBB/AxBS7d+TbzuvDRb4gs7IeWEiqV5w8sXGollnxwGK3KGs0DuHfkYOs7TIQPA0oOEABeT
r7rjZyniP5qi+WmZxkxwtO8OE45QP8OXkyNvPjpMtKmfoT6mZlDrVV/GTz7M6yAk4jECueZBBiaF
RiFZPLpGAqhZPwtHVWGcqO5yyVDF9h++Xp8bR6G9xLMgjQw9jjI8UUPMOeRyKg2PsemugsJaImj4
GwNnsiHydThl8psvOpPNYep1lOdrYAt6id9X2NcqvtWeRgCa1Kvu+MFk9pDDvziwG04O3Yr0Y8Fm
H8iwFNSnt/gMpfi2TYGtD5w3TEQd+0T2MdQ6pSPcGoSRetKwOnagyxpXYp5bQF3If8nLK5XPni42
PY9lyftALirRAgP2r+McQZJOBD957iwuxAxN1Edwv3ZKIp3MBdymmeQ7WPv0GDP/WgnynUCaa0yb
m+JRYFtG0ypmMx7BlbiTRjeSsPtJTOaHm8P/+zM3Q+gjEHoaExirzMfUMeXccO5GgtESif5a45h6
a/o3AeCJd1o67r3G9eyxRVhqq6jAvBBxqE+CKpow1U4hls/jqMG7+RQyBPEgrW2+7U9fUBnuOsgt
Dzlp6ofwRQ90iLenB4qaH7IHSkO63ZdPEca4Bay2lAMcXJJYnr9Q4LDLQ3BKPdS2ccY6cORqpAr6
8W3+YoT7rKohIZNKn4bd6K/NPu4UvMnMVchP0wg/9huAg4b2SrPCHgbYRMIVlv+L8/dq+olYjEuS
Cei9FSSaFmYbqfnCw9iRZTwT2jsivFa4tb562m8RCyv/ML+1s1hIgzJHZmns2uUeDBbD0skrgXtg
KGoudVplH1btbsROyfjMpCc6poW370GRjzVcMevEZRgZFdwhfff/oREtXSuEW60cDWVUdLIN71uf
xnDuGuG8NJokt9z22es7wtuuGUt1mb2Ea83F55zqBai74VMEWbON8VZn7SFtZ2BFN6m+ambnaYyV
AS+jaY/+qg0mFslTfZ1Qyzul+SwEGGgKOu+KCk7B8BedUH6SNhp96mqtLiA88gYIJnO9r+8dnwDb
7ZaEhfv6pj370J/nbzsBhCZg8KQAQUXg+95xWS8H1xN2MX1Kpv+mw7C7kvSDWwyeS0+cwskRYEJ7
lUSqLDiJAJlskQheljeNINbYIbBppE3a0/ARrnkIGQQIss+vzWLcXypIkYRrQ18q8ktBRbS9ULQ4
V6aFrYIbOI2kjMRvDq8qXo3+ztpbgoIBWuHGodFbWs7xSXoBm9UM0WQHe79faoKA/T85gwwB5tCW
4LIUW/7CQXI0JyIQRBtQgIFm2mLu5hAkI2ahfLdKiR2WgpbPk0QUXYY2XRCobzEcATchIXJCCzkU
wt2IylYdoFdj63TucdakiXrSgAC2Ssf8qLxgtFEUhZNrgsOclbAvfDXClfrp4kyOr2tphDf6w/F3
6ZCc/ueA5Pg9z9Jhm6eKr/lxCsga+xGePUvmRK23tqKOSZNCigOPdcSzgo6cnyU7ZtfbZPFp/qPr
PM25iUl3MDuZUbIe7T7mRrXE0qT4ILRNygJ6FSZ9tw4DX8KArTIgvAIbVq36Iz82MOuhy7htv/1Z
y4Uiz8pXopnin/INTju80kxWhThxBOljcLSSFX+u5ai4MeCQoWEUF6KgNu72oOVNn8W4hhKxTBw6
UM/GSsRgjvV62VzdPabcM9UJWJZm1V+0jew2YGYVnOZ4KDtRWvV0oXlex40L/7nC3m/30wYpAKfv
OiNImcgKRNoM7sHGrL+dAryuTdn99M9lWOKW26gYP/dml772WOzOj2UvdJQZwguZeIkbeNG8Kyrl
2fJAo0SKQTxv/rQiNC3o5tZvkHMYD7AoJ1wkmZGXgyo288/A4RmkUsq3Y7WEV3vUmxsHuNCMS2gC
HOOy5XCkfb+Zhawi7CKTkCOMln0bf4F5r1BKxCHZ6VBUk73MLbkH3Hmrtn43NQmMjVD+Xq87dhut
5VCxDkWWoKeZ3rCNlnX3WzZhUli1zUJOwhEvQbODOwjNVnwJCeNu5VUrpIUKQrRGDIZNexVxp3Wc
8/LnOBZyncmziTq4vsb8VJwbJzEwggHNHtyZ+RyvTAO9vZhuza5faRgcomhwg0pEnJVkDAnPmHFI
YraCxHv+wWds+Au5CSA7M83CTbFNdwVLzaMN/VndE2Tu62t2fzYeU6yLykjTc5tHS8sD4N9V/m6C
n1b5UZ6VPwMXeCJpg58KaeY7PxCJft0FGC/BLTJKynIOAidgT/FTZNPM+7VWXsKOnzhQy7KHw27G
ZWzmKns+6lDfa4DvbUu7Z548OEL1k3As6/Oc+ekKl57dfhSrd1dbyTIPPxhJlk6CmrItd9rp2EA1
hVW9VI2T0pWPSR7FTDBDZejlZ46re8Fw+YtgmM7V2UxM08VSUE0j04BzegjW7lvEc4n+vLjDUpXW
ER2LEfcuIfcwx8976sqhCip+uaSyJTo7GrkBsluDkRJXnj+Bik5+T/s9QQ+zUSzExix35jlkvvcB
IUqiGpynHi3+M7sFW6eaRmoe1fUYDLjAUEpbsjMS8gQucdqaak3SC8mnc/XrUEt/oXkYbcoBMbu1
1jOvzcAC4JrH83Ty7aRrP7shp5woWa1Bg6eFs1ugOZ1eEJdTyIc2e8l+Xsu5KHkZtqQ4ZFMlKYD/
kfu8d0PwHyhRoMD6k4F0+KEJREWkk843IDY3lbG3wkQVGRgOAoZIf9I6G57HfYzCsIU9XYtUiwWa
GFOwaa+gh7XVEjqiDeXXEl97ASUPYISzq/WTXY+PqBvM+atjx/vV3+jrzclH7oa2AZmoP4x6G4RJ
BlDEphQUQ4U+2iIuMMNzgFv2c8JKccwxXhvu1UQf+SrwA4MoLqMokXgfBeY3TGWidfu7n0B4nD6F
iZUnHvTSZ7CXoA+bZmVUmOzkdPUWEtLJDILUSso3MZB+L83hlN0HlrPdfFoRqxsqfltOcQrpqbTb
IaHLJX7ntirZQqCMDg7PqUk98Bvh1VosYSUTq3y9EKyRHET+IiNlHRoZuDMvVibUvmf+nqUHoHVw
UbkWyuKkVLPcmhSnLoXWPsrXROFQ8h8LHoBx041tY9Yg7+7beEE31viUq2yuH0o3eyoprZwy25N7
Poomg8EBfGbl57cj8FvXZossicC7/gElCAeIVIO91P0HrlHU2sLOoLqFV0xg+vxe0tfb840YL2Gy
bb9gDLsRRnh7I6w4s47Q4seux+k6fpl+k4ewYD4lYrJYsYXk/5SeniItzfkDA442IoNFlpyYpIoR
GQ+XyeOI8dFufD90ZVAFIXV0zWffid6rKOzJv38RXbK0YmVvHY8TUHQdwrzuyHRCJqrUC14h6oaR
JTIWdww9QYSUgQNoA6mi/w0PwRfNEJrxF5M1IDhSVcoQZSEZg7rB334Q+lpnIOPcZf8B/TWweDBz
VvHgyhX6Oo++dXZTFcRNKWAtdfgGdJ07CVrvvmrm2vpvzLrJ97e9RtnpW8cYY7FLh0mhLJt8akIl
am632hObbc7nCbi3qxDmb/fl1jsMDfPf9YVGZtzFx31YHndWguKXYTPvGO6El8b8/WA9h0gdm7nu
ITXxIogas+2tPUjaGiVAJh4PYJyW+P5b7tWOlCcS34JwGLftGrBFVmiDGeOzzIN0MeHajRZY5YJ5
JNvZOyMtiPU6tS23o8YDdBbUsHoVHAchoto1FzekrswVP2g/zXRJYLpHIwfc5cudjN1AhwnvZukq
mPn4vmHgXBIwPZ2MW+QPfR4ghdruQLYEorcf4E07/FLzHBB5tjYiFXhy0/6DlwpyrpJk5ce6GnvR
aL62gM7oJ1TKhTCAuYJtR6/uqQtSf68KCU4G2Hyey/cXDdUSRYz/U6dsrHtDUSuq/sIOqRJ6StnO
2I+KxSHDtRMRzdSL7jTro2KzWB5w4VK8h4A9JScMDwcR5RngRosf5pHVutwVnd5sg2PLpLmxeYs7
sgeLbQ2qggICNLfkSX4bohv/r6QcdX3i0DjQcS7Z6jS0VJzdpcHvU+/pV4SmpbhULZSkKMtYpMsH
5xT1iCQ9ZR5kA0elBGb4tTgwhPAC/evYeKiDO23a+WXdbGkyRK0PVZbYjs53BYozFtq7OKkBdaxH
XFl6Pt/MnPFh3orZ2NC0TZslnXyvOYpB/3UFLe5l29Ye7kkAVNgMPgKI4GZYTsX/8GTvRssV5Nr1
GrEXvtqF32JnafQcES4PQE5RxQsIi8MIDn2ojizrE9tAgQf9FVqBfzJLom+3WHUhGykFB7RUYlXo
sH1F9e8uf/CMtzpPpRpWv//jm0jb21VpEFb/izbg+elVp7i0DChD+H3Ny/qCvddjWfMV7NHWxQHg
JiZdgXV+NLuqavYrbcsC7tK4aghsLohM33lUo7XlrRfEJ3FCL1rVzyyn1heuvxNbokiE9BxDUxbd
O1JJvnpQIphiqfgvQsfcnWg9DuehQIkQTO2w876ChP7QhJ/eJhDR0/URjAHV6djf3XNtyxEEYBme
3lUqMVwhIktQ1SGgwj1O+w8cnxIrN35n4JRniUo10GXEiFFt/PJgDP8U0Rm9zUtrks/MSE1bPynG
YO51sj7XvPVgDoFX1EtMMfrpsX+vdJgBQIoWwFAAVAhTfd2en/YB2xuAJbuykS8PuFKziCQOjpdw
m4FPYnIpwSosTAHB8e+NIjzzkrkWuacqBlF+HTeF2p7c9eyPb/JxiljL9Ps2tiGkzbzJxFwPNYha
9FKx3cuVMvofyTrXGKiApfobRdrbbodRqlpJw8az3FGgohchPT4GUG47E1Z2oOtK7sMSiqsnUBjZ
gk1g+dIADZwt747nDTFb2XYw3OKi3LhJ1ZZfEZLHBnUO3LbTQgsec6WSFAsdP+ryajjo/C9rLD9t
64RyDTtDdhmTeajEOvTacF0Jq1lr4DYZ1wX+GF1zvW9QCNtDdeolQEZfv0kYrnQq8GpdFcqcRTmP
EM3seMxHl/6BR7BbRKuVD8JT4xS8R62cZQPm0xQHuU21x4UHFB/V+XSOpxjIBmGgZx9M9FCPN0md
lEIDy6fNxyYxGrckXjpvg/j5MAqjF6CY1luxQ2lSfpetVbais4Zc785bPsyn3+mQsZvAq+5+dJHf
7/m6hsSakbfRQqNObHbvTBX8MOljvLAaFrkLB43/VFOJW7Q6jLq/coSSxbBVp+RdrCV/mUAyV6De
6o0mofIMXYSSCTsZeMF2HexdIAOdvpmUvYIivFvZeYQ2GO9nrhIumdwL+riUg9JRgxZO5SGZdSRW
30NKusrHu8mPA7HMSQyXC7o7boYc0Jr5foWb+H8afEPmmPjKoXd9GLLbtDH2Fi/OZw37DDCSE7Fi
thCoq4h26gTwPWL27r3Nwr8hgY30PrQnvRQpanTD50ICgKHL+8A1mxOd4coB9dGlxEI5FK2IBeEg
TsH8Rg9QDq1mTtutXGZMv56ZoG6onAMqGg+/GW9fPJoNUCka/rDJf6DX4S4GzQCA5jsBTwZ3s/rb
18aNcYew8SOM8dKglcAebQ4RZI/E8Y3zRU74tnWPlSPLX1NotscRzPIJa9CtkKa/fEpNBF8Ytdco
ZyNJ07ngOdSWWcXYlDDXCCVSmqTpyiB/osCNeZ2P+xegMfLOVgvq8FYucMjkkBDuwYgANd9jPVjg
lYekF3Q+hlmq/dZIg/nN3PQL9RGW+1YYA6Ty5fFVhrON8apdezsZUgNqVp3dPL2pu3SgqKVAa1yO
9M305sQp8DO06R7qyzU36KeOmHs5Acu9I2KVs6jbmogGOLTWS2RVpyXuUgNShfIo+eQXEaYzwxOR
929MHWmpx0fvl+GYYYe252WMOZFWAMqoSFGEhd8aHPsyS+GoMDlZr/EpL6aV+aOVwDm2O/v2azLg
TzuHG8aEuFc4Eqq3TlgEdt2UsvyGkYOJMqDGPJVx4WFf1+hejijeeSt4a/ji8G7qkKzdDSmQ+cRI
r1q/kAm7oolZXDdtKgcDF0NBpF9uSnaI1aipzUdqiHTqATytJOSU4vX2ktRoH6Q0TOHt6akgXiE0
q9Cv+wFEAQPY5429piWt52up72VOQ0UjlzuBMIvuZmRVvZhEGyYTOKoB+XZMxhb1TvaXyVh6lOB7
t1LEgeZ94YL8WGYOrfZXi7lHx4I3U1g6BkNz4hQzX5Q97cuj06fnZoDO1ygUR0m032mds8pJZJUt
io1nFgDJnZS+/WBHFNfq8jMbVriXbdS2ieYS7CfH4ZZAkNQ5TIFYrJdeztyPWoPhIXHzPnyMsaA8
Zi7XKJr+ANdVKCZcy7fZQunFUi/Skk0+HsJXVt/L58FJ+AXxi69zD4JREh+EQGY835+DOfxG5HQl
SkBTEfzc+fpmL0+HMhDIy//Fhp/v3C5vpBP5ABNy6zP0i8nQfV83WvDrqZKvKONjP5Z6lIaGEbir
ENhOZ4frhsxM/lpcVPz3zaN/kCbkDOuJjHioboRUVDEuhOQynG07MWB+6SQ2jEMbs7d3VrePAiFz
u0hl/d/Ya2MFNvh7GTuHihi+eU+woozfyoOusCryC2wxtWVg3sa6HknDYY/Witooii1PU88audxI
+k0ln21ihdKkZllwpGDScUqLwFMEWIS3hf+A/Yx3EZhZ3d4APof1NTmwpBvjXmIkR1vdYm07OeLo
MhoI0ljexns0vOzoscuU4QzXkWO+qibLuk3CAgYQAKzMOye06bp/sm8kvNjbadRT+136HyRV4vlT
bOIxyAgDIDQ2Fws6WBYDChdx12byMSs2qLyigM6U4VSE/BhhxFAUcXRedYQatNCBx7WRsdqa/WyM
ZJMfdjJCUG0B9ELI7H9Kb1WrI8NPnFnDx9AaDO9yHZp0qtI6ub3/gStXdTlpoxuqATZrOerq3GZu
Lnb6OO0PjPVFmxA9ePKSqWtjwaXLi/KmpHGe8wWtvEqjyCs6J/3hJnk08fPlN4L2mHh2wFKfvG9H
TFp7QFrFVHoiTXezReDIBvTyob7coUaFIyqwRNw37ZkKRVt2820jsPbNtFBDEOe0NUUCIsYAschV
pizJGPWR8+KzZ6b57XFRhm5h7Jqqvj+/xnPpvlEWe/ng0t8nTAbCNYWQHmo1swQ+KeQkun5josPW
+b+rBTtkr0XZ0mbmLr4VIUt0vn6bshgQWdfH8aybGHF1SOuJl5F3xX6V7TPo/nAbeQrGMOeJGl3Y
qm1q1lwizxJxm7ldjWjQ3wFF9s01fV7ptMaetIIl3SREOIwSK513byNne+dyGng/xwx2cHw4xDXN
nzFq7+MlkVNpZoaNUTkSmjPx2BERJNaVwvMLt1t/MO1tRhR1dlA05OOfZCTi1OUHnz8/rZg4ICYH
O9DLGq225dS7nOGcHUS9oxXpd4bmkSVXuD+zUz3EUlVaw/axTxmn7f7HQPl+fz7W8jairUl1ebU0
98Q3wyJqx1Hp8ra99Ilqp2k3xkHRqoo+THZSmGtRqBXTHB1JdqEoqVDRiDcdFG41ZsiwyjRmdi5Q
bmpAZATZWTahbGndw8TYTxFpNNmcOCqNKDEw4UtsH2+vLD6PJBzLOR4qILvZSZxzzCHU03fyy1d1
oAjKCmLvn7KhTAb3T2Cc1DpLC1aaEkEXxLqds0/ZNCUFRDWosij5xQg8UAV6u0um6LBpxCpn6DyE
docNjWCzzbruqy2NBa4W1Ev5WqfUlcPXMjsMyUGRF/S0oy5EAkyctuU24E9VCgMf4PBaXcAdKC2r
xob19ccLR3sNMOPXmRPFmKuqMKM29AoD+kLrWDcD4cgxMrWPP0IvIQAZlEv0o3wuFxqCZ7a+jT0V
YDo4fQ8uJUDsyxabFRNTo0X4Nt1jgs3n3dMTphTpq7aLdP5Yc3ehPV+jP4NMIIB6iGqG4XrAjqO9
fB/Zycj134pZa6rTQtG5sYhieLMsG+z/heITa3djZz5goRmK1TnDy6cpL25bMfcgi06NTymUMqU9
yqe1E9l0b8BRqWPs5LvdbQHShCl6V+UoffF4LdKr0USt32lSs4tAZ5847wMzTkwQ4lmAiYp1/TaW
CheW/6FdUldkyJtAoCdGDmJCQIr4p2RHVv9JefGBpcJ1iXV09R2yH5obzl0hvYQ1I3N0GDKKFAX/
+FQdtRy/9wnpVr/XmpwgdODzD8n993phaURJLBHA9XtnaPY7RP0WmYmi55BXjHOjI/jg02FYBptj
8nLH3K/ILev/PL8zGjNWesaO2o9kZvgMS9gE+PNzX1xVJyINYwaQOCPKP2DC+mHHV/2mnZ0k9efK
2K3Hdjdfx2WArzNHWH4ThPVWk9sQi+ePV8mGIH1lP7AZn96fyeKf1ZvdPhZY+6C03TEvC2wrJw6d
1N0aItwMbFxM0mYxuNg1bDI4cPBzl8Kd4d0dGJ+VxhLWQDW1+3RjBItAOi9gcUNZdB8Ri2uFW8Of
lvsdVcZFZ6Oh67Pyaqd2luEGZ2c9NzjnPQB7YwQvr0QiqwwHlfx1PS2ZUqX2MKuKhNvia0vcqoTO
VS3g+oclx8LUVWW8da8VH1u9LkDvg9wsjbDwDyuHb0JBKUKcqgmFl7B0ne0yNbTev8Hq0qOOS4C/
iRY4jqEMfM7/xSVxmaiFgJ40ja7XTd5kYxUOMtXDr3OBeaFO+447NuJrPJyQLCat7+Jsu2fwempp
g8DXhKO0ZFq1cGmf7Jzkqrw+rSBMcW7lxLQrNzYvb4oHqxMYX4ZJ0xp39OliDboQ70dD4vSGDm7A
iNWPQ+oo5gkO1tnw5c9BVPB6xgTVe0OT4b5NsZFHbytoHocneleLu+6KG2VR+lCCwEs7CIrKxwF1
L7F0336uDqE6MnSIH58kZhra9o0c+GfIW3xwV9PdTxrVZ9r/3s5RoxxnuFCdv7mIja3VQ/UtjZwE
tgE7bHniijMqznr1fjE70z/ti7RHFE2mfGoe4IkY8N6qQicvRPK45BM9iLNJnfzebyFtGSDtRD9z
pSM8xLze7M5FZVcQtwmkzNGuULtKqxEi6rS0ieV7g0wSiwv5neqRmaJElQKL7CZrALg+ZUY0AbM5
yBHkL4UJ9oB0JVTwuMtCYPH1NpaOpZ6ouPBhHb525nBbX9HGkHlYqlKzpbCCTgOy5Zdzi2LQXKGn
69CSEBPXvzTVElbIX56PXfJ0DJSFjuTw7E2kVXn2El/aXfwXsU+fT3Hco9D9RNnKQkW/G82+Zy7Z
Eph+Ajxd90VS5EA2rRjF+Zc3OItwAsXxXnexLE3CTI3PvMjQOKBnIolcoc6EyjNc25OxEQn9qakc
65Yh6tgT2t/PmCG/pG1w4Y/SrSgrq6VhSgz9CR45wMKiWKd4rUOJl80Ip7ry/hJglByNQZV2ktb3
cKoz+UTYCAHE3fo3EH0FKUB0x9bZkQ3DBBNSzTBy2wWIgh0zNsmAXdMoGAKrmcU+IR9h28vtOluI
kSIvIXGsQZRQ60E8QYKiaQxBZRup/bkWNhlOB1o+JhjiQxJSAFpE0eccDq5YbX62QUo0IhFN3O68
MYTrBw3xq2fCx6gUZK3Doi8TIuOmkW8TUGSFIO/8Vmi8A4cCxAlHl5Oqw8EewkDBjUxA111j0Ncp
J6VZ0A7zR4y5Hr7ux7RWdUBuMLHcXBq7mg02nz4IucMg2HSBM74qzAhO5U1BX2nRpNtb9ePwsk2V
N0lpiYa2KVq4aLtiGP/8VaKTvrFC2+wku0q6f7043MGaxYsLNh8EP7wKsJY3Wr9PGOVBq9yaTKhm
To9DMPt5XAyh99kAQIXusAf1AeOQ4+06f5kN12gxmGQeOnjbMR04kLp8RfOFXJ7vvb2sgOr/j8y1
5L/jR4T+fAK9z0UASkpoIGS2pFTc6cNI8sZJGzofGfDcbKfMMlhqEsrYwuKSYYC3JsdPqtBl5a9V
vVPq5d3DtxgmgZsjc3w/NqgbtHXxRnkHC1c0sJS7q7ENP6mskhJx8/xMFyP7Cq2sH2n2BxtMhWZ4
WpXO+x6IhPCWo1g5XlceRR3fcxLm7HIbGWQ8oVoYx4dxMq7NycOrsHXSN5EQZsupX5vHzIgPQSqd
GoJfFODQyS+YKW72vFufVuvtErSShl2LnWnLyqyHIHt007VtRSqzdvWikwCBiq6rhaNSvlSi2RFn
Cg2m24IX57Xr2+LxSXxycY4qO6uDIbfh21HxS+Eo3909h11F9fsC7p6hXw4MNFUxRATRTQS/C7A+
cR5PHooZoOk/SZc/6mWljGCA0NEkdu0VUz0HChG+riSMyaXrU1/QyLXFLzrP2yDNMVBYuG4vCJuf
M+rq0h/L+RZV0icINS+YgMUp8oUhaoYAye8M13Jw3NQTYGUG2d/94Im9LEdZ9B/VyPT7v8Fr4759
Kv7HhIfba0YdhjT6HjS1Uygp1DqChO5TtndALv5AO3qB7RzQrB9/Uaihb9DJfxJsEUSWoBO4Ehnn
X9Qo7xBHCdmSuUVHM6wc6khmsw9/t6OI5Tr+s7zhT3fanKeM33rL8AMSi6mSguprwqDn/MlJ6WrD
ruPb5f8wjlWwMsMhtJpxQOSjwclWUJdoOkjQjQghA0tTNxzDQvj27k8Bs/JcCCoOcCw2t559D7t9
jn0/GQX8IS7vdKu+sA825WkMfpKReeN6nVg95/eGYmGEIlVAHPClPx17rGwsbY4KDbvC/QlMNhAd
G7hBh6NDrzpl22DkcJzI1z66dgXTy/QvunUua7VbYnzPdLBpV1wKqa7UdWc9kE1RqGz4v2gI9DiP
T7SLQiX+MAhsyRtTRZe/gJA4dnb0XRB+VKm4qjZxYVqBiLiYPs4Lw7QcDKoqdV+nWeS2fAwgJd0l
orYe66vRFVgOc2kq5tMJxN9R+FrApwaZZb8XL2ErlyoKH7k4nn1prYTAnQKa258yAGECHsNCQB9+
XY4xjK5xshjwCbACmgFpV26Ek9tKAb03weqOYXiwH9rVJSx39WdPqnqYaUqDTYDjFyhriiWupk66
3r7OqchNtf+ntwfHYzRaBtHi85DCZIj9Ei8vjsoXOBZ9lfLYR5+gBylakLTSPxCb9d3J94h1msgA
46TWtakFXRBs/QEUF6Zpv/2Q7/SgCiFo84lHjRqRgjonS9wK2AS79lPqZ9nK9uqAkvoste9mrKZg
JDuGkP1knK5xghvqUttaCrxd8ME172ljW1LZMT6/wXdcs+K0nc+EKceM7yg7FGoc69gBOiofXIsT
meA2uN//YRgiPWZtLARZQ9yDN39gjdc8+vvYk6AbDmr4bzoRrP6CcyK6v0WpVWOKUKnWeQB7e/QX
jVQpIfpzu8/Wkd0gcGIRlN2z+8UoGIgfyf13eb7D2SfkRc34vOBaoc8E+sTrDcPyh653xtrGf4pa
qPy67r7V2ferpG7+2LSgoz0+mFLUoQXVu6koDPguan8TAJM6nnQLVBVGG0hZdo4kplZOaB8wYip/
UQGwh5aKc9Jb0rbiBd3RzSCZSSkSCd7szkBRw1etpH4XIgvQgmZdU8ybwfIeED1oaFScBBqQI2Vc
Tl/DNOTmoHr5HXNfc4Diaf26clvQGAIOnhZcR5+7G9dZBay8nKB2dEtGe8SlNQNJsup//j094mUo
2mKn4mhFpA/jjdnJnql5W8Bz/rix4hibya5NBsXYrZ6OIaZRdyq8NhMtK4pTc7Lpbd1nc81meo3G
MY6zm9z2ySEeyy0blUlj1FyM6psF98Ns5yFvsWt+iVdN/l9bke6ZsEeNgJy16WSXsRSi/+DdhvB+
TlWa63BhMEyJQ8QPii3J4AA6bqfgK4ZpOvnCqPFb3VKHbg2A+un9LNrTXUtf+nE5gkel9bkvOlET
G2l9m6qKCRVLvMNqww+D6B7IZoh9vIF1yB0STPH3wrcXbBNqr4GByW7TL2U+7CH0WWZMAm3Enptx
AXBSodfmUNF3Fvock9xpCMxb7ozx7S9WAPJ3mu96tvM2ztGY4sIe3tSrF3Detkt5M2FX9f4U/68V
mE2QsS5WBzuNWkUOErhdScIIVK0YEt9LTh0rG4/fQQb4kRgV97lYeyeIrk9fjfFS4umi5h9Cy0Jm
KZ3I6FLQzGtWzZrEoYpzWAmI5bdJpX2xQbXewKNfGGZSyzMZ8x9WQmXr1SZgLfoxnqeaZoZJjvuC
dXrBcShSmJu4FDO884Z33De0ZTEvC+LKYwDwrX9p9BN+l4illiUSAgxZkVEp9TUXKP/y2WkWm5Cl
XvxwZYkP6aujsyUYQi7MXUCxBLOif5BpoNAJB0G80i4FRBrOpy81h4j0Vx7DLP74q3hYeoucvJbv
mcC5RorP1WVXLIqLQ03KE6G4KmMX6xoUwF4iJJj2BWyS7DhvzvQVdLI7u1yuzA9teA6C91eXdxYI
8Q2AdoyZuZHk6zjwKEnLSmEZXu5SdEsrcERMXl++kTKKT0sQwI5UELCkTC87UiNYFbHAyPgXXXT0
hX0xoL30Zc36QhzUfg1BrDvMKEO5bjuRLhaD+XpyCTWH/HcXqxP0+ksf3FKZlpQugk/SZvy06hNE
9pSwPKtr8ECqQ9QyWxy+YV7ADY6XiUoqzLUi5kn+kgEeer4jsg4OqjUhE+8R6DR2piVC6BU42jmh
bqJ6/Gda5aiIuihU0e963Rk6L9l5yb3dAdicjdwEtVMRieuvjnR+blVmrDrlYsizgwrCa5uEeewt
hzMRcKSX178cciYGTAbciv9020kRzjiPgfGVMcN2TgazpJY81qRCa76rPlWPYwFhBumXrNWUshn1
WXDVFfBqxXQV1R5ElmppVGUluGEnlcpwOKw/RtU0GUvMwMXNgbqDgj9ahZoohOPbPgxLEGrDLPvF
bEmCtDJ4jJ0nkJcpIeLX0jWfiBhbLmqd881GyuF7rKG9rEFwB9SZo2NePHs+nCVIxNPj7SbQFMtZ
nUtEodG9IG/3tG+skLgBtK08WwNMeBPpZm/UfZ4NdaGefV8P74TJMhrK9SUdpMWaeSM8ImZcHldH
wSRhoAf6g5nZ+/ly/kvgBgFAOtRlEdB2r3TIOGepwHMicpQaxX5gnpOBI8HXR20e+AK1+CdX5+2e
IVcDsF09W+CGxKryQG/Xz1wjoIDp7cgQ5YwdynCxGjbfuGfzBQgQjoq7Of+LvDM5dl566sHqW2vv
+IPyQQ5xcaaFPWyLoBt+1TpZ2GlwQW+RL7biGDsDD8NuC1az2qr/iolZMv0hUUTU6n/9ro93rGlX
TmffW7DXHpSbQ+VPqlVWp6Ja4ytyEGpnBNjnoMVxwNarHMqlUva0yMR4PGWz+NFKYki7oV+gQOCj
tbuQ05tgcn4qF5MQa4yA3yPpr9rGvpD0JWYqG/Sj7w0q/mx6SdoESiASJ4B4RX3d4xS+XqZut4VZ
w/u7rR8ULGltaR4xcZLz8XHjqzkosLU+6SJA4QvKSCOV5jdxbVL5nQUssOOpvA3rP1mITJrvdriY
ZXTYeNiGYDeB1JAITjqRgqKU4+faGLiGfqPtZgQih7XLwoXDqwqO2j0TKvDHfFNz0mdiTzPLHRMB
CHrhBsqEaagDBaVuyXabOQmPWhtlg3NIXmPc8hDhX6Ag1BjIxBBdnZ6u5+zkCyhy6yrkDYu1rCby
9rAOi0EzvgtyPgkx55tU9ifcTJi+yLca2tyDUiiyJ61OTg45WPw2EkW8L46G/by+j9Icy+TLnWuq
CVYE613Jh8AewCXP2JRnevRy9qJQbJxQs+QWNCV9K4GR/FYgr6ygoyYoopbuEqQbMhwC+FtzM5Ap
EHCZHGRCM8wevfizJe49b7gnEbWFt3P2PSHKZU6LmFFrxKkg5AEUd4LEbkpnXmBetvxDUIt4hZj2
Zdfq5yA9tsJ97pWajtJO6iae3THEAJXuwMZSwlHUA1iEDBcZE8qKfM5QklkzDJSE/tdodmh2xXRS
zxphTwQ1SEnl6745LbBetBZKGb95tq+aYBvMcCQq9N/cSaCRd2ymyevSUvgdYLo8QlySeGUcgWqr
J4cJnCe2BRf9IDc38y/e9VL6zq2lV2XZ8a180FYtJwbTwRJEQgAlvwqF7+5B3uZn/yzCXVUPrbPX
MeL5xFWRgebzIXYjJ/tDSE0MF8DDIKY00ZSxvtR+7kgZkqFnGSwlJL9yFzwKXRnf9Qah9ufgRuWe
JHPm/caHvejkNh5tOIVsQZsc94VI1jAIfgft2/cnYERqFP6G0KBzyDIpT4cqVrHszoUdbqDWZ5nC
BlVC22hHHJ9f90ZnL+MxRAp2tUpBSbIJlHHiVAmft2gnNHVvVwq4Gdt4US85qf7Q65TtBKhOK8jS
TkHxqI7gX5kzIrehEEbuzkMYwaK38RrArpCWOICMJ3nDadRSF+N53iTwBfBtFp4QukzMnwUNmtVH
D5ScyFmMmVXeDv66QxgjwPvPDuzpxp9zNHFVsrv//xB1RhWIGQeQl1ucGyDLqpFAnqd/OzD3IUVT
KvAACk1dIaWP2fOoZSA7PIOYoCTImi6PPgdlnYOwWmZK/TNyMfFPCYMbCF5uMTe5KhxB5ZXHJwaP
90ClXiZC2B7X556EImqV1E+RjMvOebaw7DUAnp8t4fNvF01XiIRE6SbdyzWaYXTuKaKcdjwxG6kZ
wOnqJO64zy/u20lFlfud04HYDW5kv/SER3H/DFlaEWyuZOlJoZWGtx3jPl8qcnnComTEZnnJ2k+I
w+wpCLyHCRqkS7i3giagzisaGXqaZ9fIKlRWUUIfIsg2bsXvBYkRHSIdOcH0RgIpd2R7shQ3Frf8
+YYZY9shTT2h9W7Z+fE3rTHdiciHQ/c8DAqst06z1En8NCF3W3WLCPAEV8eScItsK/vJX/CuIcMB
paO5yIVqLeNuwAEhLR56i0VNPS+FCynuobEC8jPV5F9nuv0fIsl2g2Un7uKFq1OA5TadWUdzXAtp
+/B3u858GezN3dcwFUePgRtrIikPLS3SIJAGHeEGVCxpy5Pw1+rNFoOcnNkb70Q0vSZkhRNnYP5C
PerGSGEqhO8ztjej61TIXz/AgsLkIQmDsA0Q0kD1eszwm8s/DwqmPo+AdOE9EhmmLYkIH8CKO0/T
1LoOel81rbPqRoQ+9pr6BlQx0wHUccFdLLoYcJ5laaslr1N21OKjwzJAk7lmwSzoDDeExxZVHv4e
L6pS3VWrBS8jq/bsJ/oRg/dUDIS63OnbYtwZdBexZsqIM+qYbhIFe70lV0SUZQL8F5RY0HClcfCc
ElDrBZtbxFlOmsFOXTUs5Y7J0r3c9WaaD3sw/zMinJ0pyG0OcQplEuZoMjCo4eTfZcTlorTOPuKP
PAm5WZPSM5oznJt4icx/3Hu6bNIsAPHgCuJmL4MvCXl/yEMOfaloo87dQpvqYmPg4L7inzjpdn2k
TWgvrDilYte/cuNsTNJsReKsmwuu2HKx/YofJBVhrKwA9yMcxQ1A4srAKgXmSh6q4lYxZzjrkJx6
GJ8HinDoUNPDnQwMKOOGjtFveTMPkvMx5Q5h47TzKyP+GNeIwd5VZnEVa9ARH78VLEVu2f9IM6ic
tDT/mip1JMgZKE7unuS7oGTDmZjCvErj6czwRqBgaIURayvR9hjO4esVRHm3hvikJLqfYKlB3duV
LesgEP2+MbPRD/R+T9nm5uxQLVlwXSZLnwlqtHjfn0jOBHIHDBz0kXulIPR9V9lgRXYrIyqmJTpA
iLmxHsfdQqlqb4zmbiSgm51UKzSP5KJiSHahzIShk1X0kvYf6JsFHCzAuqN4z5XLXAGNMU6+o61O
wJrOqKhce4PrCavi0ascX9Lsl2AsWSFDvlfC1Zu7cU3O48x6EQ5yNA+dQvkuhCigmTdEvaH8mV0y
8clkwKCqB/tQxwMs67ma7oqeWw5rwPOS0tPDM5UVImP2jMzjVOJXuUl1Efh7iVEPdU9VY4e6SsLp
252FaSM5ii8L5SuWIT9odhR8DJElgYoCCDcAmn/PTWvHC4Jdas6QMOUI22OxvFMXn/Na6D99KJ0n
yBovc+pnwNl1TSyrxJeTMlxI2BmWQbkcQHD9CCM4yuKxYyesM7b1Bx0vbMOuV3HYV8Owf8mJaVf8
prWyw6FwVUJqZVwewKUTOt2ESx8YNvQJhwA+I8bjzH/e7n+wiaJsX8yZc1FZdjp7lx6kAYxHM/Cm
WAngHFYeflcJVaqWSvmlM88iN4/o3HyNTri+/lhzDMAj62gLULDotBrJJgjym/WSteThq8Rd7REV
B9CYZXPqY8MqwaB6LFv6BiLGZoP3Az/lz0xtFXdW3sy1SLhED9b/CB+vW+drorTErLngJxVI9VFj
PygiHPCLuVOI2+ZfPnIS1Q5xOY3Yg7QKr1OkpdL6kJyE5uAgeDntqNbNKqL31lxHL/lp3vhKVjXi
qjjX6o04qUOl331Rf3FC8e7vNF4Y3ZCSPpQD4w4qXak9+ZGBxMXvnHXc0qBpL0l2jOuWjjniktAJ
uVtmwDCJX5eRnDV28FMycJR/fOkFBj1Ma8CPLbg50M/uJu4jjmCX+Sg3W9l2vPZuJXUgXrxZn8I6
JcGvMsjZcfXTYvytkN9o4cx3luylKt2VX5csJlbe2VTRjVnEP8k+lbXKpwAHdPl64rWu6atIds1n
7427tURZuDrHwSfpE5PY1ZZkbLDnlHxg1wLJCFToKyeMXF+0DPEMowaRFCPDGHOS4Qx4QQAoxU/7
zwzHfW6B7KcWx97YmPEKQg/S8wDO5lSkX5NQosPe1NR0MJ/qvqdbOylLxoba/Oq17ZKl9IiVj0HJ
+NGV1crOSc/Lp8Y9eyk56SMXbtAEqEs1QcRjQAaUGKeNw0RHBAJ0UYB60B/IZXghxu43VR/oLWIC
j3yu/a1hsSKPfH2NV9wbsREUEyCy5K/G69H6OR0OGWOrR6+KicXDnflQ7/GMFkavtfTIRUeZilAC
C3tz0RlRWLV0bsgUgy9XJMTbaqNOdn9eE3u36rF1FG83/3GCdsl9yAgzCp2b9uzLrSW+/qPIAaon
tiqu+4fQ9eEF6xXjnDV/gVuuAFbpx3hYpF3uIIDWBkkt3/IBC5362Ut8DFtAwDkLCy084KbWzQ+2
ahkYShiZ7Y9/93cbG3Zfola93lM0LdGcqcmSKSaMPoFALX1J5LoiKVGAngyJg+GvumDAy4NU8wIH
uYiAxy4Sk7fjtkGOCJYiwVTIPMxSxBsLFKehaWzbwe0r25RBymw8Rnx9jQ1ablGOjD9cpSqOm+nE
3sdaouEVjk1cOT43pmHGaCyQYlaUr1NK07rLdJ6j7iPi0oHWxJHiBDMtfFGpU/IZlCzR4seDSSlR
RDHDSNbGxngJyUjVv6SXppLqY+hxeOL7oq82NSMk0dwF93hXXbmgvOALaQSw9uiTEX7JmK5Yp8We
w6zBKXG3EZ1fxKgteBS6ChTeIQ8kWNv95xvENNOOnvpUytOOcoX2Ntf91pU42KZGzCAlzTCZiJfv
1ArlhWw2IWwpA8ZYCrv+Lw3Tk7c6qwQwZRgEyxp9LDy3QOVZv2u77mnfglyL3LzcY0jxhP/VrRKi
9sr/1G7RYVr55iGWVNnqE4eoX605icxny9f040iv2tRDrlYEw/qwjVmgRPvsxb8mM36L7ZhFil7j
juZ/lmvV39WoH9r9gTKZPJYU0Uz5ecVkTnVNfNAtxr+3KOAAu2JfrURZX7jq8keenvT8opG4Ia6H
uqvp5XmoAgthLKM5zNurAzn1y1lLsb+pQp0/kYQ/AZTQZSsz8tuofkQL6i62IafK9PfRD/dGJVwd
Qb6tjkrJchoI2rZ1/g3OaMFhud6gJkETOSQGJswAiddw+avit1cM/Ll1Nnxlyg1CHq2S+9oquGYR
ADpvBorMbLbHyaPXqaOUvoEXl+eenLstY/8g7WUJ95KYGqHYNbrWspmmYlmmO3dT6puaEvyLKdll
O6GT9tYMjpq6JyjQb3TvqVDpC0Y3x9yLrDKRtfT8v1ukzOUd3VLxSbxFSsIhIlLtexsRytrNUlA0
4C6lajGP75A58hgJxW1i5uxfmNcmdB764lXB1jgR4LFSRbGr3rhMJjL/jKPfk+QvuWkn7Y8BU5kp
UNxD+IIowdC5g1CPOpu64wAk9NuEdkBw8PAZKAwmGgqrDf3sBsC/jahGifx0PbXjRj6WWafSFqBd
r5vgzjaQ9cx7/Afn8qXEpQd9ktOL7hP0bepvmVjVEa7gdTD5ykNVIwx9+9YWCewWxv3P+dxRhafw
TaORtjZNrGQ2AszHE6PhmlkgUnLj6x26jkgjyPBhJ4Wl98dYWhKGgTN+9Jq87oGEw+Xl+z/Oa1Ct
ErCppZczvCSQWI8XBxi9PvPYwTRee0wn648HEqu9BokvFl3V5cG1reDSgdkw2d9auFfxHnY18Bl9
uV07WIYBBfZ77FJisOAYVLzrr/0GZNxDsEwpjZCsAMtN7AVH3b6IEQVDse9woFdU2AxAtQ3Onqw0
Ec7UewFBdQ+dSy0+d98ZyzDcIUYYJOcWDckFBH3qBdkG4FD7wbv5/BSbQkp2byqFqJR0GFXZadvz
v7OqJOOwfVJKF+uN2vNTJM3yJ8r0wREqwKUXvyBWMAHS6IqbTbtBdD/mBBcUyqmAqS+J0Izp64uQ
ARl9ofdgHPxt27lTSfey9V64CFKKKksgEPXdlTw/jFe1hBCBnRcvgl3Hq7Vk7YsKHUcPt2+hufIb
Dukdu75tZvx/M98w/bTA2f5QUdM1I6fmYYuuBxY1GsnxTkeV7mv1gqjZDizUEebgMXc9XuYrHyZE
3NxTzRrs/vK4b9xtI3uOJ6CsSNcY9dbrkKof1+wu2/uvvDgxKfFRnOG+JHx++q30pYM55CtSZ/Gn
HCPrVQJjtSdVQrvBxDNVhVbl0JDAvFwBZdzyvzdkhKJYGQ5aRr9yk2fzH4Rwb7FX3V6Vcu9ilImc
HPBkpru8uhOUch7NOPwV/ege+6TlcOApru9wXMrWg+uXC4wrrg7RXlxnbhq769bDCgS9e+LqZRQY
SJtYJdCWMdT+0ILZmfPSGLf1Fkv6ICWD3ckpKIPNw7MIACMBBYvkOspUBfdObm/oBMVSHzPksvuC
goWlVahsTOmDDkz0D50KmmOxppeP5sg0873JVL7A9E6pfXgUbNh6pMyGsmWCYYPO640iD0v9+xV7
0MW/C2BHdrSXO1p62L0kVaO9PfxrlDjHKWT5P00eOnyvN2bNYm8m3hzocplINCAhqTAercGIOnfG
E/MfFAHaIoMSst+AQdB6hiTFM4mLILwh/j5p/lxWqh2gFfpo1Xto56koJk4R/B+kco3+jpgTbi/O
/Dk20oOQi57drwWQqtDJI8GwWYHI1Ak5CStsJt1LztDP41u/hCubMGSN4xJIb+R+cLzlwgbanZ2n
tUrUfOOc++CPruGthOfrMAFsyRspCbLd4nz/sCjTWaTHA/MpUenLPuAOqU1KcoVZ+sJlL4MoAbo3
wFumsqcSdr6PEnyqB4Lx1n1mkYFGjY9dXRBlvJiAXv+BTv8WuXwjNlAp+Rz5ljDQGAgMRIiPe5NM
SuxeWDiJGoWjSnaU4IHq3PmHIsHaBml6Z+CTAiPFMN+p27aMAQl8uelZieJdcetK/4T5lDEtycHO
QgVX20mk4Q3ZQ2dNceAlS6uV3p2UVfKvrG8kJt7zN2z79k172cudJkZUIICrbg1aSp7+fwjRbS3c
62ALjLAJhA5AoVPWPLbqMHnQKJoBnBzMoPhMyRKhDOuevqbkEnGOFzDSv94DXH9PH94lSIC5qXVm
FbY/6dyK5eArsf4Nomscpj4GFex9L+/rPpmzCTxZX8OtVQ6/vr2YqRDT5nFBuKp7Th8S/oMDcUzt
q72iUS0L1SvQt/jzPYzWoAM36+G18TEOxDrnzF4UI46Im99cPfWRhtRk3WbLZXmzXQhUc6z+CSqz
ifZOzrHoMHNKHryptW7inJ8xdVWSBZJGIRghToJNMlQduyPUbf6V7pHJYwZocqKP8waLgBVu9buF
fhBfxgpJnBWMJ6iEENm3LyKDSAu3NwyG2VwGKef+kpccQ+47l0U3Dk3wWcNDta0wKTlfU51uJnRZ
V2Npo6jjDyHhYhqxH6PQvtZoUiQwV1isU5bZqAEopCIrcQYL3ZNSIg3c0b/llJDZK8yP+wxD1i9h
ZRM3M5pufSwnpxMdbsWskFpApsfXaPQSS+myM9wmoMC0IrNrhT9Fh3kAGHH1aNfmledGAaNR51CF
6WcyI2px7iMAxonM66ifw+C++7h9CbgWtBfaRm+ygdAHa0h2PxE1AWLWUyem/1SAuw58R8eQiqWF
Esfhy1+++xU+QwJS4/pzFWsCYBSdXmdBrnxtds+eJ5V8+Qzb6zofTO0IMJY8UqfZkw9Vrwnlqq07
pTo0KQTG/gSPgas8yN+Q/DrAhNQYQZzi83Fk6aYDcTkMhesNqC37doEZt21lc1Y6Pr/8dN4Yktwh
y9wvogYu51LXTrdkeSH5TOyRRMZ2GiDpGGfHnLedJ7nYU31pUKeyIrxzaVxvCzQ8K4nSQCWo7F+K
jkNhR7U7iaBjFakfWAz3CeVGL8Uuc57A4XEhz1BOkDbqm2mH5yybkJ/xgQUbYeiVn2/YQLLJibL7
RoG8tm5Qbl4wTRyBEakPq5KfiZ8D7dwrkDgUGj/imt2NyanWLxbNSGhFbRecuv6kgnDtowjBEbMD
9oxSeCgBhP1PBsJIxqzMFb2N/cpKfevUIsR3pxqkWAgfgYTtVSeauN7/QgW2yLSHdzNAztEECSWW
ce8jt8FlOmoDnbZLQbRuANXBFNJlj8Z3g77lMU0UYvT6L7eBWQvidUBpWK+NPoEn/Dv5LmT4uH+b
9EshsnKyPXIL30fsk1Tx7ZJRkPmVqdlT9thoieF/AmLHayDEpLZ44bHJpM6CD/uwhq4lNhAakEgN
zFyRua6Obz9QJHwrbXBB1WF0UESqu4Zm+NvRU8vje1fRaRPT0VYFQdh07Ii8SXCsPFpe4okcHADS
vVzQnElz5zx1w2zmZlOXipVpR7tCWBJH+P4kfP9T7AuhkoGRc/Up0gkx9js4SFHA033Ex/cryIAA
9X+oLPSUdT4SyEYK4eu/uExW/FGEZD3asmFEg27r6zH9P+0ptaqI9X5KrxmAX9p5bZl7+3aYbrV8
J086JRYp4PlhyMhOpDVkdCjOf3sER/ldmR438aXkto3LnFkjsRMQFtBAc+ywTH40RTWhghRUDGqQ
IoI6J7Reb0TFaETMdKmwHWpwd+wwzWgB6hM1Z/fDVVd1ddlJH3uGupS1zXlFFw6JL5/2cGF6IqfU
4ojyECcoRaX/ySzIlLD1U0pD+5iPfjN/sjEmn/L8ZM3nA8PWS8gs9+gSEZNWZBrOj4bJuz5AOv39
UWFKBQmkAZeWrgUxOgkxS0KRDQTFTauG4wLtI4Q87GrJjosvVHyteKzH4oXBOPxJ4K123oEltp78
ouSQpWzUuobD/wWXG/zKTBqv+7Yk/XtEeH7FK/PhVoyUFR/Hkk/j2XGCddTe8UD6sV5RVwCtlX4U
cWG06HIuvcn+QmGeGwa0aZMbnwRrW1M43CE5T68Jf8ybnH0mpM2lE1izpwYvbb7gplZomvzW8Vrh
NSRRKM1M2v9nQeSVXJ6VsV3ODXmoHTr+w/6E5/LNioJTLYtuDDX4bofiBS1gwliJQyGZ25rW6x2T
3+DdXnA6azzOmVLmTNGaAYZEb1D9gZG1KglWX7G0HkeEWJti7r8mEcYGl7wo3C7RnAviWklI6PEp
IjLNBKx/OGjJQZLkXt0zxtnaj8oa4du0QW+WiEe5dgmbHVCe34HvtTPaVF3hegdri0DH8MYUettU
F6WDziPog3DxJlhE77K3gNwcKqP7sFVZFNxFcwu8gOQhjktBc5Kb/zi4P8YFWyYj/Y6dYcIaL8uV
IU65lz6gt669myOhK0TY6dyp30FI2tET0oQzezddR+xZvhKrOTSnUuBEkYAENKYiHOWqRJmGHPlZ
DFQK6oBF7v5VH84A9BEF3voMZ7jysESAW/EGAWmH888l/xFOchUYmyNf2A+Q7ggBr3GrnqdD4XZ9
IHGYnT/sDh12kPIy+/+Q69K0zRBiHUzjS7UQ5xUMbOeBT6kd6sHxhluLZZzw/XE/SzDymFWW5I9G
Ye7k6bkG7HY2Zqm9v6CSj307GDNcnHObXt3mYljG+7RkE9hfy9lJHkaFpxLmDyKBkUy8VcrDtlb9
nQdOpf/o95A9E9pqY+89UPtC4lSzXh/yXxsEy3mttJ91EemBduX0jCHEMUoWF715Tomn1hVzJ1FN
yJcBtSJXo2/K1sds8MAWdIaqG1qKZhbZ69wQlk7gWB1dqXdA5GIDETmqDnzgKwoN+nyV0Y29igS9
oKqGSAEn11VcsSNi+NbiHBQecNK+Fa8Tbmtao5sZx1RNDAoUjPtL3ewRU2PBnQkpU2r20ffpTz/M
1ISY7nYdsWQi1AbDYI5TGDI1v2PfQ7qdHlbOkoIiASJ8rnk5PVzd6+DFe4qxFuscqd8KQDWKCjXB
QB2PqhPNKSTyuWEkHRakum8i0haIRBLif6xCmfHmwWeO6d9mipLuU9vwu3Awq5DL1qHDT6hFtUkm
P2+18UZLQt7fFId5RL23p09LDI3Z3PFoDCzB+pqAp8PNSti7sThYmqoCx1KQ9aMrJSMZ4PTMisqi
BTSs04FkcdXxaIacZlDpuzPHeR/XypMXAvAeNFRIGhikQxnfG0QZRY13FDtaNgAZHghCKHUSWWnE
ZiPGfVvGsNJ7ekLUzogy25spaZglArbTKQjLii215ChmoccDPozJzMHvgm97AmOjkbjPu8x4oVrA
GslW5rrEBgO39yFQ6XIlqlmCrdECmgIc3f6POLYqhD2lHRLvqFDxWcBWjnhmgZdl90pBEoeNqMXH
LmAEPkjMq697xOpLTInxBNQAgfEfWooQShrMywiGhuGjXjEiIrGBWTkpHrWgoUDomhm57JHxZUX+
J37LDilOB4rivVJbmfrrAnngte5/X8w3bFC6Bge1bkUIZUpNV4Nu/vGwkvM+GEfuALPQOR5O5oCk
Oa36vxu2iZ28Ag38+AhfSOLNWmCBYKW1JN7qOzOYCE+GmeJbxJc78Z0U/VHGWsXmLG2oB/npW+35
krQrEm9EzHBEvBQLlzaOEz+cTb2vr/T5Xo2T4a/mpv9/Th2ZHwBUiojXzzGfn8mM25s9yHIky60j
KiLiUcuw0kOCL5N8pUGjJRoz/KPROMqzSmFJiaLKELR7Tneh17a9aCYc3+KTS1GEKiG3jyCbbh7o
icpGrHbVze+fOLC7j3Xvo47YrCNkltCHWTeVea6Ab8pMJ2znX+ggWqzlL47/fjNKlhbNmmvaN/Ul
sJAKKZc6znP3p3aiGdHHLdQh6gWb88Tbambs3DjlIoE0mZ/lWuhcyrBMJmOs6UtG68KEz/VXuU3L
gJaTsRC5EVMafD/OpvtKkq7A1Mg91rPkJ+vdPZmdehR/fxIVAd/VBLfJZUz2vddi8Ev2/A1TAIi9
LyIEfwS/2SPiHgsyMBz4FM0m1Vharhm7rT4ue5YA7F3+XsmOYABVp0SHi6xZqNYsh3mod9IR+RlP
GGTxRNtMzUj6nM3ZBEe8LWoE/zpyUttEwJLnqObmB0OXLjxqzzoXReCgUTg/w5oGF/zvfVjWGYe3
a2PmXJ7EZ4sx/41xv/YvBsDi9nWvwnTnPBX+q0BSFf9mXweYqAjbgsHLIBZz/RWpT3tsE57foSmD
GijCayCZkku3WEJXyFHcIbo1GC3SWxK0LuL7etCagjUUCZB+hNOZsH5ewpkCgYKQ6ELd8EhdP4X2
bR071yUbvGIpWZAxanDZWOJaLyuSC0xzDBtkngh+qOoDugj1P0xEC5v4aQHvpH9VHVcWmmx1J9hU
P+LTXayOP6NALaIbb1r5Wgj5LFTgt1+tqp83uwUElbaQ3aKElm2nUE4Jc0ZzQoKpo4Kvs8QShSN8
QX3NtLTjrlRkqLh30ppbr6KqQ9inz1aQkPgh5tdgdNN6kGO/5KA9rfbUJxnv0cZz/eiT2uVabnY8
TaV6Zv7jlxN4wP2H07oaIw6D/kvGkjYG7kdEwz7f1+P2uKpAmz3QnfJAPIItuG2tMBByaqT+w7HS
4m8Y+xr56DJN58DBe0W9Khbaf8bYyyELhK7XwAKxbcy9Va6iZm5Bn5kgl1zgz2rmzN4UwFGWZxx3
r67td0fK1TLTRJcNWyjfbBDLzgm/lGKr9aJqwkGkL81FqiyIX1+BXMDpQ+QPq6BLiALfOBhlSPqB
1O1L5us/oj1Jk9c7Ck/XjuLtoF+hPp21y9PDn7VB8f+Vlaasvox3d2hjKabQpOI+11NeVxLc0pgh
dgaHHYJFlk+ZndNukgEngqAGSSMGAZAnLesnG9Tr2wJ+ob4cgIklSaYqBD66Vdy6Wl63QNGuC+Uz
lm1aOXx7Cf0zFNvlVqUNNpyTEPKh828levW1uFTNGDn6Z3SnYOYK6smUU8wrtR6g7mh8YwRFzZfC
xlASkHoj1iWIn/ItPrORerf6n8ddQDTX8iGiFMZDAuJNN72BellbTgSKBjHz0CIYfSEHFO8tJgL4
hXdJpCQV0XtVBjtebluHW6wvY6VS+sAjEm9fbtmxIhUhiEAScVKmmZF/BRosI/seBA+zDJK1AxyF
MgFzf5pwhAiS6P1PDS8bbbp2lo4m7u6Fo4zqzod6QOwI8vsBueIw9DisJNgIlSTk1FqJ54FCWaFi
9fNUUOdNC/kQdPb09sglL/Pv6D6u4Vn7/378G4RHMOYpl1zL0GeNj/15T6s71iK8hvO63rbEom44
TznXW3LilWR3DBkEnW/6Mj7+LY/gOEIq2/Ov+61BClADWwNduRNdnoogezEBCsab1TYJsnPmsJhD
qYte2ZKXbcXYwZZ8dfT4SFwJPqyaNrVBrQ7Lg72Cy/obIsO0iLjlsufbtSyqADZis3BCVONGNO6l
P8CNytdxNVYVqcfHbhTlUUn02j60Oh1TbDzZ28sWId7XPQBcDA+6BYfsQCk10XJ1WKvHvT6E3jBq
8uf4ed2okUFEiLEz5MovKPTli0jv17yiPH266SvYuFYCbqeVj46OTUHMIQuud1Sa8nn6IQVC5U1Z
1wgviLPEsDy5DMiZFdrIYS7PJ6feeErp8k2a5VDObxslt7hAA8gNsw==
`protect end_protected
|
gpl-3.0
|
51de2df39cbf27414ce5fd7180c46e09
| 0.952847 | 1.840204 | false | false | false | false |
nickg/nvc
|
test/eopt/arrayref4.vhd
| 1 | 584 |
entity arrayref4 is
end entity;
architecture test of arrayref4 is
signal sticky : bit;
signal shiftedFracY_d1 : bit_vector(49 downto 0);
begin
update: sticky <= '0' when (shiftedFracY_d1(23 downto 0)=(23 downto 0 => '0')) else '1';
stim: process is
begin
wait for 1 ns;
assert sticky = '1';
shiftedFracY_d1(19 downto 0) <= X"00000";
wait for 1 ns;
assert sticky = '1';
shiftedFracY_d1(24 downto 20) <= "00000";
wait for 1 ns;
assert sticky = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
9448ee655a13280299e4218f2b4e6f56
| 0.585616 | 3.672956 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd
| 4 | 2,127 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2297.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p33n01i02297ent IS
END c07s02b06x00p33n01i02297ent;
ARCHITECTURE c07s02b06x00p33n01i02297arch OF c07s02b06x00p33n01i02297ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 min / 60) = 1 sec);
assert ((1 sec / 1000) = 1 ms);
assert ((1 ms / 1000) = 1 us);
wait for 5 us;
assert NOT( ((1 min / 60) = 1 sec) and
((1 sec / 1000) = 1 ms) and
((1 ms / 1000) = 1 us) )
report "***PASSED TEST: c07s02b06x00p33n01i02297"
severity NOTE;
assert ( ((1 min / 60) = 1 sec) and
((1 sec / 1000) = 1 ms) and
((1 ms / 1000) = 1 us) )
report "***FAILED TEST: c07s02b06x00p33n01i02297 - Division of an user-defined physical type by an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p33n01i02297arch;
|
gpl-2.0
|
3538bb469c0fcfe78b1afd6dc87a0114
| 0.615421 | 3.598985 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd
| 4 | 1,540 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
-- code from book:
type natural_ptr is access natural;
variable count : natural_ptr;
-- end of code from book
begin
-- code from book:
count := new natural;
count.all := 10;
if count.all = 0 then
-- . . .
-- not in book
report "count.all = 0";
-- end not in book
end if;
-- end of code from book
if count.all /= 0 then
report "count.all /= 0";
end if;
-- code from book:
count := new natural'(10);
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
68a37ac62def56e208e51ce3df925576
| 0.633766 | 4.196185 | false | false | false | false |
nickg/nvc
|
test/regress/const8.vhd
| 1 | 448 |
entity const8 is
end entity;
architecture test of const8 is
begin
p1: process is
variable s : string(1 to 12);
begin
s := (1 to 11 => "some string", others => NUL);
wait for 1 ns;
assert s = "some string" & NUL;
s := ("foo", "bar", "baz", others => NUL);
wait for 1 ns;
report s;
assert s = "foobarbaz" & NUL & NUL & NUL;
wait;
end process;
end architecture;
|
gpl-3.0
|
abee941a4c59ef85d26911b3f077bdb3
| 0.524554 | 3.642276 | false | false | false | false |
hubertokf/VHDL-Fast-Adders
|
CLAH/CLA4bits/8bits/CLAH8bits/CLA4bits.vhd
| 2 | 967 |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLA4bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
END CLA4bits;
ARCHITECTURE strc_cla4bits of CLA4bits is
SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- soma dos valores e propagação do carry --
Sum<=val1 xor val2;
Prop<=val1 or val2;
Gen<=val1 and val2;
PROCESS (Gen,Prop,Carry)
BEGIN
Carry(1) <= Gen(0) OR (Prop(0) AND CarryIn);
inst: FOR i IN 1 TO 2 LOOP
Carry(i+1) <= Gen(i) OR (Prop(i) AND Carry(i));
END LOOP;
END PROCESS;
SomaResult(0) <= Sum(0) XOR CarryIn;
SomaResult(3 DOWNTO 1) <= Sum(3 DOWNTO 1) XOR Carry(3 DOWNTO 1);
P <= Prop(3) AND Prop(2) AND Prop(1) AND Prop(0);
G <= Gen(3) OR (Prop(3) AND Gen(2)) OR (Prop(3) AND Prop(2) AND Gen(1)) OR (Prop(3) AND Prop(2) AND Prop(1) AND Gen(0));
END strc_cla4bits;
|
mit
|
0fe79b8eaeb6e6ba709060cbc29d74a2
| 0.63909 | 2.671271 | false | false | false | false |
nickg/nvc
|
test/regress/driver6.vhd
| 1 | 1,220 |
entity driver6 is
end entity;
architecture test of driver6 is
type int_vec is array (natural range <>) of integer;
function resolved (v : int_vec) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
subtype rint is resolved integer;
signal x : rint := 0;
type rint_vec is array (natural range <>) of rint;
signal y : rint_vec(1 to 2) := (0, 0);
begin
p1: process is
begin
x <= 1;
wait for 1 ns;
assert x = 3;
assert x'driving;
assert x'driving_value = 1;
wait;
end process;
p2: process is
begin
x <= 2;
wait for 1 ns;
assert x'driving;
assert x'driving_value = 2;
wait;
end process;
p3: process is
begin
y <= (1, 2);
wait for 1 ns;
assert y = (6, 2);
assert y'driving;
assert y'driving_value = (1, 2);
wait;
end process;
p4: process is
begin
y(1) <= 5;
wait for 1 ns;
assert not y'driving;
wait;
end process;
end architecture;
|
gpl-3.0
|
d2cb75e9123558fae3728f08cb4e12bb
| 0.522131 | 3.8125 | false | false | false | false |
nickg/nvc
|
test/regress/issue352.vhd
| 1 | 1,177 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_unsigned.all;
entity issue352 is
end entity;
architecture arch of issue352 is
signal FixRealKCM_F400_uid2_Rtemp : std_logic_vector(4 downto 0) := "11111";
signal R :std_logic_vector(5 downto 0);
function check_dims(x : unsigned) return unsigned is
alias ax : unsigned(1 to x'length) is x;
variable s : string(1 to x'length);
begin
assert x'low >= unsigned'low;
assert x'high <= unsigned'high;
for i in 1 to x'length loop
s(i) := std_logic'image(ax(i))(2);
end loop;
report s;
return x;
end function;
begin
-- R <= "000000" - (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0));
R <= std_logic_vector(unsigned'(unsigned'("00000") - check_dims(unsigned (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0)))));
process is
begin
wait for 1 ns;
assert R = "000001";
assert FixRealKCM_F400_uid2_Rtemp'last_event = time'high;
wait;
end process;
end architecture;
|
gpl-3.0
|
79fe732785463245a0e20538a0b6c1be
| 0.630416 | 3.189702 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/lpm_add_sub_oe0.vhd
| 1 | 4,984 |
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub_oe0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub_oe0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_add_sub_oe0;
ARCHITECTURE SYN OF lpm_add_sub_oe0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_representation => "SIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 32
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_oe0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_oe0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_oe0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
91e0a8c9023733ace18fdca5cea10417
| 0.64386 | 3.529745 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/lpm_dff_db0.vhd
| 1 | 4,247 |
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff_db0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff_db0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_dff_db0;
ARCHITECTURE SYN OF lpm_dff_db0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(8 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 9
)
PORT MAP (
sclr => sclr,
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL data[8..0]
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL q[8..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 9 0 data 0 0 9 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_db0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_db0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_db0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_db0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_db0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
d352d1ca98925cef6e58d0d003a59fce
| 0.618554 | 3.504125 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/blk_mem_gen_v8_2/simulation/blk_mem_gen_v8_2.vhd
| 9 | 213,662 |
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: BLK_MEM_GEN_v8_2.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_2 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_2;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_2 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_v8_2_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_2_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF BLK_MEM_GEN_v8_2_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (BLK_MEM_GEN_v8_2_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_v8_2_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_2_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF BLK_MEM_GEN_v8_2_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY BLK_MEM_GEN_v8_2_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_2";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_2_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF BLK_MEM_GEN_v8_2_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT BLK_MEM_GEN_v8_2_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_2_output_stage;
COMPONENT BLK_MEM_GEN_v8_2_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_2_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : BLK_MEM_GEN_v8_2_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : BLK_MEM_GEN_v8_2_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: BLK_MEM_GEN_v8_2_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_2 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_2";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_2;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF BLK_MEM_GEN_v8_2 IS
COMPONENT BLK_MEM_GEN_v8_2_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_2";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_2_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_2 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_2;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: BLK_MEM_GEN_v8_2_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY)))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => rsta_in,
ENA => ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB,
ENB => ENB,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: BLK_MEM_GEN_v8_2_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => rsta_in,
ENA => ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB,
ENB => ENB,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_2
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: BLK_MEM_GEN_v8_2_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
|
mit
|
e0983a4c6a50390b99efda35ec31d1e2
| 0.510643 | 3.541613 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/var01/tb_var04.vhdl
| 1 | 746 |
entity tb_var04 is
end tb_var04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var04 is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (15 downto 0);
signal res : std_logic_vector (15 downto 0);
begin
dut: entity work.var04
port map (
mask => mask,
val => val,
res => res);
process
begin
mask <= "11";
val <= x"aa_bb";
wait for 1 ns;
assert res = x"aa_bb" severity failure;
mask <= "00";
val <= x"12_34";
wait for 1 ns;
assert res = x"00_00" severity failure;
mask <= "10";
val <= x"12_34";
wait for 1 ns;
assert res = x"12_00" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
033dce6ac0ff66dee944d33e8001199d
| 0.592493 | 3.147679 | false | false | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_inst.vhd
| 1 | 472 |
component pr_region_default_reset_in is
port (
clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_reset : out std_logic -- reset
);
end component pr_region_default_reset_in;
u0 : component pr_region_default_reset_in
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_reset => CONNECTED_TO_in_reset, -- in_reset.reset
out_reset => CONNECTED_TO_out_reset -- out_reset.reset
);
|
mit
|
63573220b205e9fc7fadbda4de112df1
| 0.582627 | 2.878049 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/var01/tb_var01b.vhdl
| 1 | 996 |
entity tb_var01b is
end tb_var01b;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var01b is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (3 downto 0);
signal res : std_logic_vector (3 downto 0);
begin
dut: entity work.var01b
port map (
clk => clk,
mask => mask,
val => val,
res => res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
mask <= "11";
val <= b"00_01";
pulse;
assert res = b"00_01" report "res=" & to_bstring (res) severity failure;
mask <= "10";
val <= b"11_00";
pulse;
assert res = b"11_01" severity failure;
mask <= "00";
val <= b"00_00";
pulse;
assert res = b"11_01" severity failure;
mask <= "01";
val <= b"00_10";
pulse;
assert res = b"11_10" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
ac43f08714b3e3b6a0aa417d16faff38
| 0.563253 | 3.182109 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/HEX_DISP.vhd
| 1 | 1,746 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
--USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.STD_LOGIC_UNSIGNED.all;
-- Hexadecimal to 7 Segment Decoder for LED Display
-- 1) when free held low, displays latched data
-- 2) when free held high, constantly displays input (free-run)
-- 3) data is latched on rising edge of CS
ENTITY HEX_DISP IS
PORT( hex_val : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cs : IN STD_LOGIC;
free : IN STD_LOGIC;
resetn : IN STD_LOGIC;
segments : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END HEX_DISP;
ARCHITECTURE a OF HEX_DISP IS
SIGNAL latched_hex : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL hex_d : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (resetn, cs)
BEGIN
IF (resetn = '0') THEN
latched_hex <= "0000";
ELSIF ( RISING_EDGE(cs) ) THEN
latched_hex <= hex_val;
END IF;
END PROCESS;
WITH free SELECT
hex_d <= latched_hex WHEN '0',
hex_val WHEN '1';
WITH hex_d SELECT
segments <= "1000000" WHEN "0000",
"1111001" WHEN "0001",
"0100100" WHEN "0010",
"0110000" WHEN "0011",
"0011001" WHEN "0100",
"0010010" WHEN "0101",
"0000010" WHEN "0110",
"1111000" WHEN "0111",
"0000000" WHEN "1000",
"0010000" WHEN "1001",
"0001000" WHEN "1010",
"0000011" WHEN "1011",
"1000110" WHEN "1100",
"0100001" WHEN "1101",
"0000110" WHEN "1110",
"0001110" WHEN "1111",
"0111111" WHEN OTHERS;
END a;
|
mit
|
d594bd4731aa85802ba4a28a2c529c5f
| 0.512027 | 3.845815 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1004/test.vhdl
| 1 | 1,042 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity test is
generic(
MEMORY_SIZE : natural := 4096;
RAM_INIT_FILE : string := "firmware.hex"
);
end entity test;
architecture behaviour of test is
type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
impure function init_ram(name : STRING) return ram_t is
file ram_file : text open read_mode is name;
variable ram_line : line;
variable temp_word : std_logic_vector(63 downto 0);
variable temp_ram : ram_t := (others => (others => '0'));
begin
for i in 0 to (MEMORY_SIZE/8)-1 loop
exit when endfile(ram_file);
readline(ram_file, ram_line);
report "read: " & ram_line.all;
hread(ram_line, temp_word);
temp_ram(i) := temp_word;
end loop;
return temp_ram;
end function;
signal memory : ram_t := init_ram(RAM_INIT_FILE);
begin
end architecture behaviour;
|
gpl-2.0
|
d77c4f4d82623ea668d9965a711b0a68
| 0.597889 | 3.52027 | false | true | false | false |
tgingold/ghdl
|
libraries/openieee/v93/std_logic_1164-body.vhdl
| 2 | 21,289 |
-- This -*- vhdl -*- file was generated from std_logic_1164-body.proto
-- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
-- This is a template file. To avoid errors and duplication, the python
-- script build.py generate most of the bodies.
package body std_logic_1164 is
type table_1d is array (std_ulogic) of std_ulogic;
type table_2d is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX0X0000X", -- 0
"UXX11111X", -- 1
"UX01ZWLHX", -- Z
"UX01WWWWX", -- W
"UX01LWLWX", -- L
"UX01HWWHX", -- H
"UXXXXXXXX" -- -
);
function resolved (s : std_ulogic_vector) return std_ulogic
is
variable res : std_ulogic := 'Z';
begin
for I in s'range loop
res := resolution (res, s (I));
end loop;
return res;
end resolved;
constant and_table : table_2d :=
-- UX01ZWLH-
("UU0UUU0UU", -- U
"UX0XXX0XX", -- X
"000000000", -- 0
"UX01XX01X", -- 1
"UX0XXX0XX", -- Z
"UX0XXX0XX", -- W
"000000000", -- L
"UX01XX01X", -- H
"UX0XXX0XX" -- -
);
constant nand_table : table_2d :=
-- UX01ZWLH-
("UU1UUU1UU", -- U
"UX1XXX1XX", -- X
"111111111", -- 0
"UX10XX10X", -- 1
"UX1XXX1XX", -- Z
"UX1XXX1XX", -- W
"111111111", -- L
"UX10XX10X", -- H
"UX1XXX1XX" -- -
);
constant or_table : table_2d :=
-- UX01ZWLH-
("UUU1UUU1U", -- U
"UXX1XXX1X", -- X
"UX01XX01X", -- 0
"111111111", -- 1
"UXX1XXX1X", -- Z
"UXX1XXX1X", -- W
"UX01XX01X", -- L
"111111111", -- H
"UXX1XXX1X" -- -
);
constant nor_table : table_2d :=
-- UX01ZWLH-
("UUU0UUU0U", -- U
"UXX0XXX0X", -- X
"UX10XX10X", -- 0
"000000000", -- 1
"UXX0XXX0X", -- Z
"UXX0XXX0X", -- W
"UX10XX10X", -- L
"000000000", -- H
"UXX0XXX0X" -- -
);
constant xor_table : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX01XX01X", -- 0
"UX10XX10X", -- 1
"UXXXXXXXX", -- Z
"UXXXXXXXX", -- W
"UX01XX01X", -- L
"UX10XX10X", -- H
"UXXXXXXXX" -- -
);
constant xnor_table : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX10XX10X", -- 0
"UX01XX01X", -- 1
"UXXXXXXXX", -- Z
"UXXXXXXXX", -- W
"UX10XX10X", -- L
"UX01XX01X", -- H
"UXXXXXXXX" -- -
);
constant not_table : table_1d :=
-- UX01ZWLH-
"UX10XX10X";
function "and" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return and_table (l, r);
end "and";
function "nand" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return nand_table (l, r);
end "nand";
function "or" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return or_table (l, r);
end "or";
function "nor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return nor_table (l, r);
end "nor";
function "xor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return xor_table (l, r);
end "xor";
function "xnor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return xnor_table (l, r);
end "xnor";
function "not" (l : std_ulogic) return UX01 is
begin
return not_table (l);
end "not";
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := and_table (la (I), ra (I));
end loop;
end if;
return res;
end "and";
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nand_table (la (I), ra (I));
end loop;
end if;
return res;
end "nand";
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := or_table (la (I), ra (I));
end loop;
end if;
return res;
end "or";
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nor_table (la (I), ra (I));
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xor";
function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xnor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xnor";
function "not" (l : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not_table (la (I));
end loop;
return res;
end "not";
function "and" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := and_table (la (I), ra (I));
end loop;
end if;
return res;
end "and";
function "nand" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nand_table (la (I), ra (I));
end loop;
end if;
return res;
end "nand";
function "or" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := or_table (la (I), ra (I));
end loop;
end if;
return res;
end "or";
function "nor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nor_table (la (I), ra (I));
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xor";
function "xnor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xnor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xnor";
function "not" (l : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not_table (la (I));
end loop;
return res;
end "not";
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit is
begin
case s is
when '0' | 'L' =>
return '0';
when '1' | 'H' =>
return '1';
when others =>
return xmap;
end case;
end to_bit;
type bit_to_std_table is array (bit) of std_ulogic;
constant bit_to_std : bit_to_std_table := "01";
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector
is
subtype res_range is natural range s'length - 1 downto 0;
alias as : std_ulogic_vector (res_range) is s;
variable res : bit_vector (res_range);
variable b : bit;
begin
for I in res_range loop
-- Inline for efficiency.
case as (I) is
when '0' | 'L' =>
b := '0';
when '1' | 'H' =>
b := '1';
when others =>
b := xmap;
end case;
res (I) := b;
end loop;
return res;
end to_bitvector;
function to_bitvector (s : std_logic_vector; xmap : bit := '0')
return bit_vector
is
subtype res_range is natural range s'length - 1 downto 0;
alias as : std_logic_vector (res_range) is s;
variable res : bit_vector (res_range);
variable b : bit;
begin
for I in res_range loop
-- Inline for efficiency.
case as (I) is
when '0' | 'L' =>
b := '0';
when '1' | 'H' =>
b := '1';
when others =>
b := xmap;
end case;
res (I) := b;
end loop;
return res;
end to_bitvector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector is
subtype res_range is natural range b'length - 1 downto 0;
alias ab : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for I in res_range loop
res (I) := bit_to_std (ab (I));
end loop;
return res;
end to_stdulogicvector;
function to_stdlogicvector (b : bit_vector) return std_logic_vector is
subtype res_range is natural range b'length - 1 downto 0;
alias ab : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for I in res_range loop
res (I) := bit_to_std (ab (I));
end loop;
return res;
end to_stdlogicvector;
function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (s'length - 1 downto 0);
begin
return res_type (s);
end to_stdulogicvector;
function to_stdlogicvector (s : std_ulogic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (s'length - 1 downto 0);
begin
return res_type (s);
end to_stdlogicvector;
function to_stdulogic (b : bit) return std_ulogic is
begin
return bit_to_std (b);
end to_stdulogic;
-- Normalization.
type table_std_x01 is array (std_ulogic) of X01;
constant std_to_x01 : table_std_x01 := ('U' | 'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
type table_bit_x01 is array (bit) of X01;
constant bit_to_x01 : table_bit_x01 := ('0' => '0',
'1' => '1');
type table_std_x01z is array (std_ulogic) of X01Z;
constant std_to_x01z : table_std_x01z := ('U' | 'X' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1',
'Z' => 'Z');
type table_std_ux01 is array (std_ulogic) of UX01;
constant std_to_ux01 : table_std_ux01 := ('U' => 'U',
'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01 (sa (i));
end loop;
return res;
end to_X01;
function to_X01 (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01 (sa (i));
end loop;
return res;
end to_X01;
function to_X01 (s : std_ulogic) return X01 is
begin
return std_to_x01 (s);
end to_X01;
function to_X01 (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01;
function to_X01 (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01;
function to_X01 (b : bit) return X01 is
begin
return bit_to_x01 (b);
end to_X01;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01z (sa (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01z (sa (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (s : std_ulogic) return X01Z is
begin
return std_to_x01z (s);
end to_X01Z;
function to_X01Z (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (b : bit) return X01Z is
begin
return bit_to_x01 (b);
end to_X01Z;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_ux01 (sa (i));
end loop;
return res;
end to_UX01;
function to_UX01 (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_ux01 (sa (i));
end loop;
return res;
end to_UX01;
function to_UX01 (s : std_ulogic) return UX01 is
begin
return std_to_ux01 (s);
end to_UX01;
function to_UX01 (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_UX01;
function to_UX01 (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_UX01;
function to_UX01 (b : bit) return UX01 is
begin
return bit_to_x01 (b);
end to_UX01;
function rising_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '0'
and to_x01 (s) = '1';
end rising_edge;
function falling_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '1'
and to_x01 (s) = '0';
end falling_edge;
type std_x_array is array (std_ulogic) of boolean;
constant std_x : std_x_array := ('U' | 'X' | 'Z' | 'W' | '-' => true,
'0' | '1' | 'L' | 'H' => false);
function is_X (s : std_ulogic_vector) return boolean is
begin
for i in s'range loop
if std_x (s (i)) then
return true;
end if;
end loop;
return false;
end is_X;
function is_X (s : std_logic_vector) return boolean is
begin
for i in s'range loop
if std_x (s (i)) then
return true;
end if;
end loop;
return false;
end is_X;
function is_X (s : std_ulogic) return boolean is
begin
return std_x (s);
end is_X;
end std_logic_1164;
|
gpl-2.0
|
8d48b4cd01963fee82c54779a08f7736
| 0.574851 | 3.245274 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/arr01/arr05.vhdl
| 1 | 957 |
library ieee;
use ieee.std_logic_1164.all;
entity arr05 is
port (clk : in std_logic;
val : std_logic_vector(7 downto 0);
res : out std_logic_vector(7 downto 0);
par : out std_logic);
end arr05;
architecture behav of arr05 is
type pipe_el is record
val : std_logic_vector(7 downto 0);
odd : std_logic;
end record;
type pipe_arr is array (0 to 4) of pipe_el;
type pipe_type is record
p : pipe_arr;
end record;
signal mem : pipe_type;
signal n_mem : pipe_type;
signal tick : std_logic := '0';
begin
process(clk)
begin
if rising_edge (clk) then
mem <= n_mem;
tick <= not tick;
end if;
end process;
process(mem, val, tick)
begin
for i in 1 to pipe_arr'high loop
n_mem.p (i) <= mem.p (i - 1);
end loop;
n_mem.p (0).val <= val;
n_mem.p (0).odd <= tick;
end process;
res <= mem.p (pipe_arr'high).val;
par <= mem.p (pipe_arr'high).odd;
end behav;
|
gpl-2.0
|
5529bfd6e9c236a328b20ebaab2632c3
| 0.595611 | 2.962848 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd
| 4 | 2,447 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_16 is
end entity inline_16;
----------------------------------------------------------------
architecture test of inline_16 is
-- code from book:
type time_stamp is record
seconds : integer range 0 to 59;
minutes : integer range 0 to 59;
hours : integer range 0 to 23;
end record time_stamp;
-- end of code from book
begin
process_4_a : process is
-- code from book:
variable sample_time, current_time : time_stamp;
--
constant midday : time_stamp := (0, 0, 12);
-- end of code from book
constant clock : integer := 79;
variable sample_hour : integer;
begin
current_time := (30, 15, 2);
-- code from book:
sample_time := current_time;
sample_hour := sample_time.hours;
current_time.seconds := clock mod 60;
-- end of code from book
wait;
end process process_4_a;
process_4_b : process is
type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
type reg_number is range 0 to 31;
type instruction is record
opcode : opcodes;
source_reg1, source_reg2, dest_reg : reg_number;
displacement : integer;
end record instruction;
-- code from book:
constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
--
constant nop_instr : instruction :=
( opcode => addu,
source_reg1 | source_reg2 | dest_reg => 0,
displacement => 0 );
variable latest_event : time_stamp := (others => 0); -- initially midnight
-- end of code from book
begin
wait;
end process process_4_b;
end architecture test;
|
gpl-2.0
|
de52fd6f813c038413765362b8ef0a02
| 0.634246 | 4.031301 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3022.vhd
| 4 | 2,135 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3022.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c11s03b00x00p04n02i03022pkg is
type T is (one,two,three,four);
subtype SIN is INTEGER;
end c11s03b00x00p04n02i03022pkg;
use work.c11s03b00x00p04n02i03022pkg.all;
ENTITY c11s03b00x00p04n02i03022ent IS
END c11s03b00x00p04n02i03022ent;
ARCHITECTURE c11s03b00x00p04n02i03022arch OF c11s03b00x00p04n02i03022ent IS
signal S1 : T; -- type T should be visible
signal S2 : SIN; -- subtype SIN should be visible
signal S3 : REAL;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= one; --literal "one" should be visible
S2 <= 1234;
wait for 5 ns;
assert NOT( S1 = one and S2 = 1234 )
report "***PASSED TEST: c11s03b00x00p04n02i03022"
severity NOTE;
assert ( S1 = one and S2 = 1234 )
report "***FAILED TEST: c11s03b00x00p04n02i03022 - A use clause should make certain declarations directly visible within the design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s03b00x00p04n02i03022arch;
|
gpl-2.0
|
5d89044cd88764cc5a8f7b1cb968181e
| 0.679157 | 3.528926 | false | true | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_inst.vhd
| 1 | 4,666 |
component pr_region_default_mm_bridge_1 is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_logic := 'X'; -- clk
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
m0_write : out std_logic; -- write
m0_read : out std_logic; -- read
m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
reset : in std_logic := 'X'; -- reset
s0_waitrequest : out std_logic; -- waitrequest
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
s0_readdatavalid : out std_logic; -- readdatavalid
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
s0_write : in std_logic := 'X'; -- write
s0_read : in std_logic := 'X'; -- read
s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
s0_debugaccess : in std_logic := 'X' -- debugaccess
);
end component pr_region_default_mm_bridge_1;
u0 : component pr_region_default_mm_bridge_1
generic map (
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE
)
port map (
clk => CONNECTED_TO_clk, -- clk.clk
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
m0_address => CONNECTED_TO_m0_address, -- .address
m0_write => CONNECTED_TO_m0_write, -- .write
m0_read => CONNECTED_TO_m0_read, -- .read
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess
reset => CONNECTED_TO_reset, -- reset.reset
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
s0_address => CONNECTED_TO_s0_address, -- .address
s0_write => CONNECTED_TO_s0_write, -- .write
s0_read => CONNECTED_TO_s0_read, -- .read
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess
);
|
mit
|
bc0f22b26aaee7deb3504641b38f84e2
| 0.494213 | 3.781199 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd
| 4 | 4,534 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_10 is
end entity fg_18_10;
architecture test of fg_18_10 is
signal temperature, setting : integer;
signal enable, heater_fail : bit;
begin
-- code from book
stimulus_interpreter : process is
use std.textio.all;
file control : text open read_mode is "control";
variable command : line;
variable read_ok : boolean;
variable next_time : time;
variable whitespace : character;
variable signal_id : string(1 to 4);
variable temp_value, set_value : integer;
variable on_value, fail_value : bit;
begin
command_loop : while not endfile(control) loop
readline ( control, command );
-- read next stimulus time, and suspend until then
read ( command, next_time, read_ok );
if not read_ok then
report "error reading time from line: " & command.all
severity warning;
next command_loop;
end if;
wait for next_time - now;
-- skip whitespace
while command'length > 0
and ( command(command'left) = ' ' -- ordinary space
or command(command'left) = ' ' -- non-breaking space
or command(command'left) = HT ) loop
read ( command, whitespace );
end loop;
-- read signal identifier string
read ( command, signal_id, read_ok );
if not read_ok then
report "error reading signal id from line: " & command.all
severity warning;
next command_loop;
end if;
-- dispatch based on signal id
case signal_id is
when "temp" =>
read ( command, temp_value, read_ok );
if not read_ok then
report "error reading temperature value from line: "
& command.all
severity warning;
next command_loop;
end if;
temperature <= temp_value;
when "set " =>
-- . . . -- similar to "temp"
-- not in book
read ( command, set_value, read_ok );
if not read_ok then
report "error reading setting value from line: "
& command.all
severity warning;
next command_loop;
end if;
setting <= set_value;
-- end not in book
when "on " =>
read ( command, on_value, read_ok );
if not read_ok then
report "error reading on value from line: "
& command.all
severity warning;
next command_loop;
end if;
enable <= on_value;
when "fail" =>
-- . . . -- similar to "on "
-- not in book
read ( command, fail_value, read_ok );
if not read_ok then
report "error reading fail value from line: "
& command.all
severity warning;
next command_loop;
end if;
heater_fail <= fail_value;
-- end not in book
when others =>
report "invalid signal id in line: " & signal_id
severity warning;
next command_loop;
end case;
end loop command_loop;
wait;
end process stimulus_interpreter;
-- end code from book
end architecture test;
|
gpl-2.0
|
245636b4f16bca52a56360d1c6ee1861
| 0.53176 | 4.640737 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug079/repro2.vhdl
| 1 | 410 |
entity repro2 is
end repro2;
architecture behav of repro2 is
begin
process
type my_rec is record
inc : natural;
b : bit;
end record;
constant bv : bit_vector := x"45";
procedure proc (v : my_rec; bv : bit) is
begin
assert v.b = bv;
end;
begin
proc (v => (inc => 3,
b => bv(3)),
bv => '0');
wait;
end process;
end behav;
|
gpl-2.0
|
cbe4e27925a81d1837e63b11c37edb92
| 0.514634 | 3.445378 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1253/repro2.vhdl
| 1 | 487 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity repro1 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end repro1;
architecture archi of repro1 is
signal tmp: signed(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= 1 + tmp;
end if;
end process;
Q <= std_logic_vector(tmp);
end archi;
|
gpl-2.0
|
d27ca38beccf79f88f2b21390cf8ce3c
| 0.572895 | 3.225166 | false | false | false | false |
nickg/nvc
|
test/regress/record24.vhd
| 1 | 1,462 |
package directmap2_pack is
type rec is record
x : integer;
y : bit;
z : bit_vector(1 to 3);
end record;
end package;
-------------------------------------------------------------------------------
use work.directmap2_pack.all;
entity bot1 is
port ( r : in rec );
end entity;
architecture test of bot1 is
begin
p1: process is
begin
wait for 1 ns;
assert r = ( 5, '1', "101" );
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.directmap2_pack.all;
entity bot2 is
port ( r : in rec );
end entity;
architecture test of bot2 is
begin
p1: process is
begin
wait for 1 ns;
assert r = ( 6, '1', "101" );
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.directmap2_pack.all;
entity record24 is
end entity;
architecture test of record24 is
signal p : bit;
signal q : bit_vector(1 to 3);
signal i : integer;
begin
uut1: entity work.bot1
port map (
r.x => 5,
r.y => p,
r.z => q );
uut2: entity work.bot2
port map (
r.x => i,
r.y => p,
r.z => q );
main: process is
begin
i <= 6;
p <= '1';
q <= "101";
wait;
end process;
end architecture;
|
gpl-3.0
|
c1a789d2388984b8f459f4254bb9d5a6
| 0.433653 | 3.919571 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/memmux01/tb_memmux05.vhdl
| 1 | 1,515 |
entity tb_memmux05 is
end tb_memmux05;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux05 is
signal ad : std_logic;
signal val : std_logic_vector (1 downto 0);
signal dat, res : std_logic_vector (2 downto 0);
begin
dut : entity work.memmux05
port map (
ad => ad,
val => val,
dat => dat,
res => res);
process
begin
dat <= "110";
ad <= '0';
val <= "00";
wait for 1 ns;
assert res = "100" report "1) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "00";
wait for 1 ns;
assert res = "000" report "2) res=" & to_bstring (res) severity failure;
ad <= '0';
val <= "01";
wait for 1 ns;
assert res = "101" report "3) res=" & to_bstring (res) severity failure;
ad <= '0';
val <= "10";
wait for 1 ns;
assert res = "110" report "4) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "10";
wait for 1 ns;
assert res = "100" report "5) res=" & to_bstring (res) severity failure;
dat <= "010";
ad <= '0';
val <= "00";
wait for 1 ns;
assert res = "000" report "6) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "00";
wait for 1 ns;
assert res = "000" report "7) res=" & to_bstring (res) severity failure;
ad <= '1';
val <= "10";
wait for 1 ns;
assert res = "100" report "8) res=" & to_bstring (res) severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
c6ab4013411c2cb1171de34f9b70ac1c
| 0.549835 | 3.169456 | false | false | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/ghrd_10as066n2_fpga_m_inst.vhd
| 1 | 2,099 |
component ghrd_10as066n2_fpga_m is
port (
clk_clk : in std_logic := 'X'; -- clk
clk_reset_reset : in std_logic := 'X'; -- reset
master_address : out std_logic_vector(31 downto 0); -- address
master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
master_read : out std_logic; -- read
master_write : out std_logic; -- write
master_writedata : out std_logic_vector(31 downto 0); -- writedata
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_readdatavalid : in std_logic := 'X'; -- readdatavalid
master_byteenable : out std_logic_vector(3 downto 0); -- byteenable
master_reset_reset : out std_logic -- reset
);
end component ghrd_10as066n2_fpga_m;
u0 : component ghrd_10as066n2_fpga_m
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clk_reset_reset => CONNECTED_TO_clk_reset_reset, -- clk_reset.reset
master_address => CONNECTED_TO_master_address, -- master.address
master_readdata => CONNECTED_TO_master_readdata, -- .readdata
master_read => CONNECTED_TO_master_read, -- .read
master_write => CONNECTED_TO_master_write, -- .write
master_writedata => CONNECTED_TO_master_writedata, -- .writedata
master_waitrequest => CONNECTED_TO_master_waitrequest, -- .waitrequest
master_readdatavalid => CONNECTED_TO_master_readdatavalid, -- .readdatavalid
master_byteenable => CONNECTED_TO_master_byteenable, -- .byteenable
master_reset_reset => CONNECTED_TO_master_reset_reset -- master_reset.reset
);
|
mit
|
45f81360c78587ac73660c0828881396
| 0.49738 | 4.091618 | false | false | false | false |
nickg/nvc
|
test/sem/issue264.vhd
| 3 | 1,045 |
entity mux4to1 is
port (
A,B : in bit;
Y1 : out bit
);
end entity mux4to1;
architecture behv of mux4to1 is
--signal test : bit_vector(1 downto 0);
begin
y1proc : process(A, B)
type foo is (F1, F2);
type foo_vec1 is array (integer range <>) of foo;
type foo_vec2 is array (integer range <>) of foo;
variable x : integer;
variable f : foo;
begin
--test <= A & B;
case (A&B) is -- Error
--case test is
when others => Y1 <= '0';
end case;
case (x & x) is -- Error
when others => null;
end case;
case (f & f) is -- Error
when others => null;
end case;
end process;
process is
type int_vec is array (integer range <>) of integer;
variable x : integer;
begin
case (x & x) is -- Error
when others => null;
end case;
end process;
end architecture;
|
gpl-3.0
|
74b03a7d6b2c57185c996e8652ca3445
| 0.472727 | 3.943396 | false | true | false | false |
makestuff/comm-fpga
|
ss/vhdl/sync-send/sync_send.vhdl
| 1 | 2,787 |
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_send is
port(
clk_in : in std_logic;
-- Serial I/O
serClkRE_in : in std_logic;
serData_out : out std_logic;
-- Parallel in
sendData_in : in std_logic_vector(7 downto 0);
sendValid_in : in std_logic;
sendReady_out : out std_logic
);
end entity;
architecture rtl of sync_send is
type StateType is (
S_IDLE,
S_WAIT,
S_SEND_BITS
);
signal state : StateType := S_IDLE;
signal state_next : StateType;
signal sendCount : unsigned(3 downto 0) := (others => '0');
signal sendCount_next : unsigned(3 downto 0);
signal sendData : std_logic_vector(8 downto 0) := (others => '0');
signal sendData_next : std_logic_vector(8 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
state <= state_next;
sendCount <= sendCount_next;
sendData <= sendData_next;
end if;
end process;
-- Next state logic
process(
state, serClkRE_in, sendData_in, sendValid_in, sendCount, sendData)
begin
state_next <= state;
sendCount_next <= sendCount;
sendData_next <= sendData;
sendReady_out <= '0';
serData_out <= '1';
case state is
-- Sending bits
when S_SEND_BITS =>
serData_out <= sendData(0);
if ( serClkRE_in = '1' ) then
sendData_next <= "1" & sendData(8 downto 1);
sendCount_next <= sendCount - 1;
if ( sendCount = 1 ) then
state_next <= S_IDLE;
end if;
end if;
-- Got a byte to send, waiting for rising_edge(serClk)
when S_WAIT =>
if ( serClkRE_in = '1' ) then
state_next <= S_SEND_BITS;
end if;
-- S_IDLE and others
when others =>
sendReady_out <= '1';
if ( sendValid_in = '1' ) then
-- There's a byte ready to be sent
sendCount_next <= x"9";
sendData_next <= sendData_in & "0";
if ( serClkRE_in = '1' ) then
state_next <= S_SEND_BITS;
else
state_next <= S_WAIT;
end if;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
88d73ae9b2e4d63625aeca4d1ed94c9c
| 0.640115 | 3.210829 | false | false | false | false |
nickg/nvc
|
lib/std/textio-body.vhd
| 1 | 27,185 |
-------------------------------------------------------------------------------
-- Copyright (C) 2012-2021 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library nvc;
use nvc.polyfill.all;
package body textio is
function get_slice (str : in string; ifrom, ito : positive) return string is
alias astr : string(1 to str'length) is str;
begin
return astr(ifrom to ito);
end function;
function get_char (str : in string; nth : in positive) return character is
alias astr : string(1 to str'length) is str;
begin
return astr(nth);
end function;
procedure grow (l : inout line;
extra : in natural;
old_size : out natural ) is
variable tmp : line;
begin
if l = null then
l := new string(1 to extra);
old_size := 0;
elsif extra > 0 then
old_size := l'length;
tmp := new string(1 to l'length + extra);
tmp(1 to l'length) := l.all;
deallocate(l);
l := tmp;
end if;
end procedure;
procedure shrink (l : inout line; size : in natural) is
variable tmp : line;
begin
assert l /= null;
if size < l'length then
tmp := new string(1 to size);
tmp.all := l.all(1 to size);
deallocate(l);
l := tmp;
end if;
end procedure;
procedure consume (l : inout line; nchars : in natural) is
variable tmp : line;
begin
if nchars = 0 then
return;
end if;
assert l /= null;
if nchars = l'length then
tmp := new string'("");
else
assert nchars <= l'length;
tmp := new string(1 to l'length - nchars);
tmp.all := get_slice(l.all, 1 + nchars, l'length);
end if;
deallocate(l);
l := tmp;
end procedure;
function is_whitespace (x : character) return boolean is
begin
return x = ' ' or x = CR or x = LF or x = HT
or x = character'val(160); -- NBSP
end function;
procedure skip_whitespace (l : inout line) is
variable skip : natural := 0;
begin
if l /= null then
while skip < l'length and is_whitespace(get_char(l.all, skip + 1)) loop
skip := skip + 1;
end loop;
consume(l, skip);
end if;
end procedure;
function tolower (x : character) return character is
constant offset : natural := character'pos('a') - character'pos('A');
begin
if x >= 'A' and x <= 'Z' then
return character'val(character'pos(x) + offset);
else
return x;
end if;
end function;
function strcasecmp (x, y : string) return boolean is
begin
if x'length /= y'length then
return false;
else
for i in 1 to x'length loop
if tolower(x(i)) /= tolower(y(i)) then
return false;
end if;
end loop;
end if;
return true;
end function;
procedure read (l : inout line;
value : out bit;
good : out boolean ) is
begin
good := false;
skip_whitespace(l);
if l /= null and l.all'length > 0 then
case get_char(l.all, 1) is
when '0' =>
value := '0';
good := true;
consume(l, 1);
when '1' =>
value := '1';
good := true;
consume(l, 1);
when others =>
null;
end case;
end if;
end procedure;
procedure read (l : inout line;
value : out bit )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit read failed";
end procedure;
procedure read (l : inout line;
value : out bit_vector;
good : out boolean ) is
variable consumed : natural := 0;
variable char : character;
begin
good := true;
outer: for i in value'range loop
loop
if l.all'length <= consumed then
good := false;
exit outer;
end if;
char := get_char(l.all, consumed + 1);
exit when not is_whitespace(char);
consumed := consumed + 1;
end loop;
if char = '0' then
value(i) := '0';
elsif char = '1' then
value(i) := '1';
else
good := false;
exit;
end if;
consumed := consumed + 1;
end loop;
consume(l, consumed);
end procedure;
procedure read (l : inout line;
value : out bit_vector )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit_vector read failed";
end procedure;
procedure read (l : inout line;
value : out boolean;
good : out boolean ) is
begin
good := false;
skip_whitespace(l);
if l.all'length >= 4 and strcasecmp(get_slice(l.all, 1, 4), "true") then
consume(l, 4);
good := true;
value := true;
elsif l.all'length >= 5 and strcasecmp(get_slice(l.all, 1, 5), "false") then
consume(l, 5);
good := true;
value := false;
end if;
end procedure;
procedure read (l : inout line;
value : out boolean )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "boolean read failed";
end procedure;
procedure read (l : inout line;
value : out character;
good : out boolean ) is
begin
if l /= null and l'length > 0 then
value := get_char(l.all, 1);
consume(l, 1);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out character )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "character read failed";
end procedure;
procedure read (l : inout line;
value : out integer;
good : out boolean ) is
variable pos : integer := 1;
variable digit : integer;
variable result : integer := 0;
variable is_negative : boolean := false;
variable peek : character;
begin
skip_whitespace(l);
if pos <= l.all'length then
case get_char(l.all, pos) is
when '-' =>
pos := pos + 1;
is_negative := true;
when '+' =>
pos := pos + 1;
when others =>
end case;
end if;
while pos <= l.all'length loop
peek := get_char(l.all, pos);
exit when peek < '0' or peek > '9';
digit := character'pos(peek) - character'pos('0');
if is_negative then
digit := -digit;
end if;
result := (result * 10) + digit;
pos := pos + 1;
end loop;
if is_negative and pos = 2 then
-- Single dash without trailing digit is not good
pos := 1;
end if;
good := pos > 1;
value := result;
consume(l, pos - 1);
end procedure;
procedure read (l : inout line;
value : out integer )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "integer read failed";
end procedure;
procedure read (l : inout line;
value : out real;
good : out boolean ) is
variable whole : integer;
variable exponent : integer;
variable result : real;
variable digit : integer;
variable shift : integer := 1;
variable pos : integer := 2;
variable sign : character;
variable rgood : boolean;
variable peek : character;
begin
skip_whitespace(l);
peek := get_char(l.all, 1);
if l.all'length > 0 and (peek = '-' or peek = '+') then
sign := get_char(l.all, 1);
consume(l, 1);
end if;
read(l, whole, rgood);
if not rgood then
good := false;
return;
end if;
result := real(whole);
good := true;
if l.all'length > 0 and get_char(l.all, 1) = '.' then
while pos <= l.all'length loop
peek := get_char(l.all, pos);
exit when peek < '0' or peek > '9';
digit := character'pos(peek) - character'pos('0');
result := result + (real(digit) * (10.0 ** (-shift)));
shift := shift + 1;
pos := pos + 1;
end loop;
good := pos > 2;
consume(l, pos - 1);
end if;
if l.all'length > 0 then
peek := get_char(l.all, 1);
if (peek = 'e' or peek = 'E') then
consume(l, 1);
read(l, exponent, rgood);
if not rgood then
good := false;
return;
end if;
result := result * (10.0 ** exponent);
end if;
end if;
if sign = '-' then
value := -result;
else
value := result;
end if;
end procedure;
procedure read (l : inout line;
value : out real )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "real read failed";
end procedure;
procedure read (l : inout line;
value : out string;
good : out boolean ) is
begin
if l /= null and value'length <= l'length then
value := get_slice(l.all, 1, value'length);
consume(l, value'length);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out string )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "string read failed";
end procedure;
procedure read (l : inout line;
value : out time;
good : out boolean ) is
type unit_spec_t is record
name : string(1 to 3);
length : positive;
unit : time;
end record;
type unit_map_t is array (natural range <>) of unit_spec_t;
constant unit_map : unit_map_t := (
( "fs ", 2, fs ),
( "ps ", 2, ps ),
( "ns ", 2, ns ),
( "us ", 2, us ),
( "ms ", 2, ms ),
( "sec", 3, sec ),
( "min", 3, min ),
( "hr ", 2, hr ) );
variable scale, len : integer;
variable scale_good : boolean;
begin
good := false;
skip_whitespace(l);
read(l, scale, scale_good);
if not scale_good then
return;
end if;
skip_whitespace(l);
for i in unit_map'range loop
len := unit_map(i).length;
if l'length >= len
and strcasecmp(get_slice(l.all, 1, len), unit_map(i).name(1 to len))
then
value := scale * unit_map(i).unit;
consume(l, len);
good := true;
end if;
end loop;
end procedure;
procedure read (l : inout line;
value : out time )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "time read failed";
end procedure;
procedure sread (l : inout line;
value : out string;
strlen : out natural) is
variable pos : integer := 1;
variable peek : character;
alias avalue : string(1 to value'length) is value;
begin
skip_whitespace(l);
while pos <= l'right and pos <= avalue'right loop
peek := get_char(l.all, pos);
exit when is_whitespace(peek);
avalue(pos) := peek;
pos := pos + 1;
end loop;
consume(l, pos - 1);
strlen := pos - 1;
end procedure;
procedure oread (l : inout line;
value : out bit_vector;
good : out boolean) is
variable digits : string(1 to (value'length + 2) / 3);
variable ipos : integer := 1;
variable opos : integer := 1;
variable remainder : integer;
variable char : character;
variable bits : bit_vector(1 to 3);
variable underscore : boolean := false;
alias avalue : bit_vector(1 to value'length) is value;
begin
good := false;
avalue := (others => '0');
skip_whitespace(l);
while ipos <= l'right and opos <= digits'right loop
char := get_char(l.all, ipos);
ipos := ipos + 1;
if char = '_' and underscore then
underscore := false;
next;
elsif char >= '0' and char <= '7' then
digits(opos) := char;
underscore := true;
opos := opos + 1;
else
exit;
end if;
end loop;
consume(l, ipos - 1);
if opos /= digits'right + 1 then
return;
end if;
opos := 1;
remainder := avalue'length rem 3;
for i in digits'range loop
case digits(i) is
when '0' => bits := "000";
when '1' => bits := "001";
when '2' => bits := "010";
when '3' => bits := "011";
when '4' => bits := "100";
when '5' => bits := "101";
when '6' => bits := "110";
when '7' => bits := "111";
when others => assert false;
end case;
if i = digits'left and remainder /= 0 then
-- Partial copy of first digit
avalue(1 to remainder) := bits(4 - remainder to 3);
opos := opos + remainder;
for j in 1 to 3 - remainder loop
if bits(j) /= '0' then
return;
end if;
end loop;
else
avalue(opos to opos + 2) := bits;
opos := opos + 3;
end if;
end loop;
good := true;
end procedure;
procedure oread (l : inout line;
value : out bit_vector) is
variable good : boolean;
begin
oread(l, value, good);
assert good report "oread failed";
end procedure;
procedure hread (l : inout line;
value : out bit_vector;
good : out boolean) is
variable digits : string(1 to (value'length + 3) / 4);
variable ipos : integer := 1;
variable opos : integer := 1;
variable remainder : integer;
variable char : character;
variable bits : bit_vector(1 to 4);
variable underscore : boolean := false;
alias avalue : bit_vector(1 to value'length) is value;
begin
good := false;
avalue := (others => '0');
skip_whitespace(l);
while ipos <= l'right and opos <= digits'right loop
char := get_char(l.all, ipos);
ipos := ipos + 1;
if char = '_' and underscore then
underscore := false;
next;
elsif (char >= '0' and char <= '9')
or (char >= 'a' and char <= 'f')
or (char >= 'A' and char <= 'F')
then
digits(opos) := char;
underscore := true;
opos := opos + 1;
else
exit;
end if;
end loop;
consume(l, ipos - 1);
if opos /= digits'right + 1 then
return;
end if;
opos := 1;
remainder := avalue'length rem 4;
for i in digits'range loop
case digits(i) is
when '0' => bits := "0000";
when '1' => bits := "0001";
when '2' => bits := "0010";
when '3' => bits := "0011";
when '4' => bits := "0100";
when '5' => bits := "0101";
when '6' => bits := "0110";
when '7' => bits := "0111";
when '8' => bits := "1000";
when '9' => bits := "1001";
when 'a' | 'A' => bits := "1010";
when 'b' | 'B' => bits := "1011";
when 'c' | 'C' => bits := "1100";
when 'd' | 'D' => bits := "1101";
when 'e' | 'E' => bits := "1110";
when 'f' | 'F' => bits := "1111";
when others => assert false;
end case;
if i = digits'left and remainder /= 0 then
-- Partial copy of first digit
avalue(1 to remainder) := bits(5 - remainder to 4);
opos := opos + remainder;
for j in 1 to 4 - remainder loop
if bits(j) /= '0' then
return;
end if;
end loop;
else
avalue(opos to opos + 3) := bits;
opos := opos + 4;
end if;
end loop;
good := true;
end procedure;
procedure hread (l : inout line;
value : out bit_vector) is
variable good : boolean;
begin
hread(l, value, good);
assert good report "hread failed";
end procedure;
constant LINE_BUFFER_SIZE : positive := 128;
procedure readline (file f: text; l: inout line) is
variable tmp : line;
variable ch : string(1 to 1);
variable used : natural;
variable got : integer;
begin
if l /= null then
deallocate(l);
end if;
tmp := new string(1 to LINE_BUFFER_SIZE);
loop
exit when endfile(f);
read(f, ch, got);
exit when got /= 1;
next when ch(1) = CR;
if ch(1) = LF then
exit;
else
if used = tmp'length then
grow(tmp, LINE_BUFFER_SIZE, used);
end if;
used := used + 1;
tmp(used) := ch(1);
end if;
end loop;
shrink(tmp, used);
l := tmp;
end procedure;
procedure writeline (file f : text; l : inout line) is
begin
if l /= null then
write(f, l.all);
deallocate(l);
end if;
write(f, (1 => LF)); -- Prepend CR on Windows?
l := new string'("");
end procedure;
procedure tee (file f : text; l : inout line) is
begin
if l /= null then
write(f, l.all);
write(output, l.all);
deallocate(l);
end if;
write(f, (1 => LF)); -- Prepend CR on Windows?
write(output, (1 => LF));
l := new string'("");
end procedure;
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 )
is
variable orig : natural;
variable width : natural;
begin
width := maximum(value'length, field);
grow(l, width, orig);
if justified = left then
l(orig + 1 to orig + value'length) := value;
for i in orig + value'length + 1 to orig + width loop
l(i) := ' ';
end loop;
else
for i in orig + 1 to orig + width - value'length loop
l(i) := ' ';
end loop;
l(orig + 1 + width - value'length to orig + width) := value;
end if;
end procedure;
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, string'(1 => value), justified, field);
end procedure;
function bit_to_char (b : bit) return character is
type table_t is array (bit) of character;
constant table : table_t := ( '0' => '0',
'1' => '1' );
begin
return table(b);
end function;
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, bit_to_char(value), justified, field);
end procedure;
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 )
is
variable s : string(1 to value'length);
alias v : bit_vector(1 to value'length) is value;
begin
for i in s'range loop
s(i) := bit_to_char(v(i));
end loop;
write(l, s, justified, field);
end procedure;
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, boolean'image(value), justified, field);
end procedure;
function unit_string (unit : time) return string is
begin
-- Standard requires unit in lower case
if unit = fs then
return " fs";
elsif unit = ps then
return " ps";
elsif unit = ns then
return " ns";
elsif unit = us then
return " us";
elsif unit = ms then
return " ms";
elsif unit = sec then
return " sec";
elsif unit = min then
return " min";
elsif unit = hr then
return " hr";
else
report "invalid unit " & time'image(unit);
end if;
end function;
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns )
is
variable value_time: time := abs(value);
variable digit_time: time := unit;
variable str : string (1 to 22);
variable pos : natural := str'left;
variable digit : integer;
begin
if value < 0 ns then
str(pos) := '-';
pos := pos + 1;
end if;
while value_time / 10 >= digit_time loop
digit_time := digit_time * 10;
end loop;
while (pos <= str'right) loop
digit := value_time / digit_time;
value_time := value_time - digit * digit_time;
str(pos) := character'val(digit + character'pos ('0'));
pos := pos + 1;
exit when value_time = 0 fs and digit_time <= unit;
if digit_time = unit and pos <= str'right then
str(pos) := '.';
pos := pos + 1;
end if;
exit when (digit_time / 10) * 10 /= digit_time;
digit_time := digit_time / 10;
end loop;
write(l, str(1 to pos-1) & unit_string(unit), justified, field);
end procedure;
procedure write (l : inout line;
value : in real;
justified : in side := right;
field : in width := 0;
digits : in natural := 0 ) is
begin
if digits = 0 then
write(l, to_string(value, "%e"), justified, field);
else
write(l, to_string(value, "%." & integer'image(digits) & "f"),
justified, field);
end if;
end procedure;
procedure write (l : inout line;
value : in real;
format : in string ) is
begin
write(l, to_string(value, format));
end procedure;
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, integer'image(value), justified, field);
end procedure;
procedure owrite (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0) is
begin
write(l, to_ostring(value), justified, field);
end procedure;
procedure hwrite (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0) is
begin
write(l, to_hstring(value), justified, field);
end procedure;
function justify (value : string;
justified : side := right;
field : width := 0) return string
is
variable width : natural := maximum(value'length, field);
variable result : string(1 to width) := (others => ' ');
begin
if justified = left then
result(1 to value'length) := value;
else
result(1 + width - value'length to width) := value;
end if;
return result;
end function;
end package body;
|
gpl-3.0
|
d7c3d0312d5a2dcae552d978c6df9820
| 0.449439 | 4.425362 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc477.vhd
| 4 | 3,190 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc477.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00477ent IS
END c03s02b01x01p19n01i00477ent;
ARCHITECTURE c03s02b01x01p19n01i00477arch OF c03s02b01x01p19n01i00477ent IS
function resolution3(i:in bit_vector) return bit is
variable temp : bit := '1';
begin
return temp;
end resolution3;
subtype bit_state is resolution3 bit;
constant C66 : bit_state := '1';
function complex_scalar(s : bit_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return bit_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : bit_state;
signal S2 : bit_state;
signal S3 : bit_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00477"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00477 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00477arch;
|
gpl-2.0
|
fd25717e8084bdd4caaf74a5a4c8e940
| 0.651724 | 3.633257 | false | true | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/lpm_shiftreg_db0.vhd
| 1 | 4,514 |
-- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_shiftreg
-- ============================================================
-- File Name: lpm_shiftreg_db0.vhd
-- Megafunction Name(s):
-- lpm_shiftreg
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_shiftreg_db0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
load : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC
);
END lpm_shiftreg_db0;
ARCHITECTURE SYN OF lpm_shiftreg_db0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
load : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
shiftout : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
shiftout <= sub_wire0;
lpm_shiftreg_component : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 32
)
PORT MAP (
load => load,
clock => clock,
data => data,
shiftout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "1"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "0"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
98be14ca611a44cfc6914146cf66bee4
| 0.636686 | 3.675896 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/project.srcs/sources_1/ip/doHistStretch_ap_fdiv_14_no_dsp_32/synth/doHistStretch_ap_fdiv_14_no_dsp_32.vhd
| 1 | 12,802 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fdiv_14_no_dsp_32;
ARCHITECTURE doHistStretch_ap_fdiv_14_no_dsp_32_arch OF doHistStretch_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_fdiv_14_no_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_fdiv_14_no_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0," &
"C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_T" &
"HROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fdiv_14_no_dsp_32_arch;
|
gpl-3.0
|
1932e34a3d8dd0da57c2be7ef3625ee8
| 0.651851 | 3.023618 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dispin01/tb_rec04.vhdl
| 1 | 687 |
entity tb_rec04 is
end tb_rec04;
library ieee;
use ieee.std_logic_1164.all;
use work.rec04_pkg.all;
architecture behav of tb_rec04 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec04
port map (inp => inp, o => r);
process
begin
inp.a <= "0000";
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= "0010";
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= "1101";
inp.b <= '0';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= "1101";
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
e630ee3cda4be4e254fd853b81f70f95
| 0.56623 | 2.974026 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/psl01/assume2.vhdl
| 1 | 527 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assume2 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assume2;
architecture behav of assume2 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
--psl default clock is (clk'event and clk = '1');
--psl assume always val < 50;
end behav;
|
gpl-2.0
|
5ede6838ee641a8d4320ebba8dedd45c
| 0.620493 | 3.174699 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug017/case4.vhdl
| 2 | 760 |
entity case4 is
end;
architecture behav of case4 is
subtype bv4 is bit_vector (1 to 4);
type vec2 is array (natural range <>) of bv4;
constant vects : vec2 := (x"0", x"3", x"9", x"4", x"a");
procedure print (msg : string; t : time) is
begin
report msg;
wait for t;
end print;
begin
process
begin
for i in vects'range loop
case bv4'(vects (i)) is
when "0100" =>
print ("value is 4", 4 ns);
print ("yes, really 4", 4 ns);
when "0011" =>
print ("value is 3", 3 ns);
when "0101" =>
print ("value is 5", 5 ns);
when others =>
print ("unknown value", 0 ns);
end case;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
gpl-2.0
|
75ac6cf4b633c114f0b1e04e8135634a
| 0.535526 | 3.408072 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_noqueue.vhd
| 7 | 30,472 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
gpl-3.0
|
882fa404e6886b2d99840430b4373aab
| 0.402698 | 4.906134 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd
| 4 | 1,617 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
entity reg is
port ( d : in bit_vector; q : out bit_vector; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity reg;
-- end code from book
architecture test of reg is
begin
q <= d;
end architecture test;
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
-- code from book
signal small_data : bit_vector(0 to 7);
signal large_data : bit_vector(0 to 15);
-- . . .
-- end code from book
begin
-- code from book
problem_reg : entity work.reg
port map ( d => small_data, q => large_data, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- end code from book
end architecture test;
|
gpl-2.0
|
0b62072a026afaaafd78abf5047042c9
| 0.640074 | 3.905797 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd
| 4 | 2,240 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2123.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02123ent IS
END c07s02b04x00p20n01i02123ent;
ARCHITECTURE c07s02b04x00p20n01i02123arch OF c07s02b04x00p20n01i02123ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_4 is severity_level_v (1 to 4);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING : PROCESS
variable result : severity_level_4;
variable l_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
variable r_operand : severity_level_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
report "***PASSED TEST: c07s02b04x00p20n01i02123"
severity NOTE;
assert ((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
report "***FAILED TEST: c07s02b04x00p20n01i02123 - Concatenation of null and SEVERITY_LEVEL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02123arch;
|
gpl-2.0
|
b21598212ee1f4907872e81a18dfcc8c
| 0.667857 | 3.684211 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/w_split1.vhd
| 2 | 1,359 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split1 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split1;
architecture augh of w_split1 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
gpl-2.0
|
d7f30161a3ea8c0c0c68d5cb5e68ee9a
| 0.66961 | 2.843096 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/var01/tb_var06.vhdl
| 1 | 746 |
entity tb_var06 is
end tb_var06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var06 is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (15 downto 0);
signal res : std_logic_vector (15 downto 0);
begin
dut: entity work.var06
port map (
mask => mask,
val => val,
res => res);
process
begin
mask <= "11";
val <= x"aa_bb";
wait for 1 ns;
assert res = x"aa_bb" severity failure;
mask <= "00";
val <= x"12_34";
wait for 1 ns;
assert res = x"00_00" severity failure;
mask <= "10";
val <= x"12_34";
wait for 1 ns;
assert res = x"12_00" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
b000f81c675eba4a1ee04bf86b83d10f
| 0.592493 | 3.147679 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/AESL_axi_s_outStream.vhd
| 1 | 86,425 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_axi_s_outStream is
generic (
constant TV_OUT_outStream_TDATA : STRING (1 to 68) := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_data_V.dat";
constant LENGTH_outStream_V_data_V : INTEGER := 262144;
constant TV_OUT_outStream_TKEEP : STRING (1 to 68) := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_keep_V.dat";
constant LENGTH_outStream_V_keep_V : INTEGER := 262144;
constant TV_OUT_outStream_TSTRB : STRING (1 to 68) := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_strb_V.dat";
constant LENGTH_outStream_V_strb_V : INTEGER := 262144;
constant TV_OUT_outStream_TUSER : STRING (1 to 68) := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_user_V.dat";
constant LENGTH_outStream_V_user_V : INTEGER := 262144;
constant TV_OUT_outStream_TLAST : STRING (1 to 68) := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_last_V.dat";
constant LENGTH_outStream_V_last_V : INTEGER := 262144;
constant TV_OUT_outStream_TID : STRING (1 to 66) := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_id_V.dat";
constant LENGTH_outStream_V_id_V : INTEGER := 262144;
constant TV_OUT_outStream_TDEST : STRING (1 to 68) := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_dest_V.dat";
constant LENGTH_outStream_V_dest_V : INTEGER := 262144;
constant INTERFACE_TYPE : STRING (1 to 5) := "axi_s";
constant AUTOTB_TRANSACTION_NUM : INTEGER := 1
);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_outStream_TDATA : IN STD_LOGIC_VECTOR (8 - 1 downto 0);
outStream_TDATA_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_outStream_TKEEP : IN STD_LOGIC_VECTOR (1 - 1 downto 0);
outStream_TKEEP_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_outStream_TSTRB : IN STD_LOGIC_VECTOR (1 - 1 downto 0);
outStream_TSTRB_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_outStream_TUSER : IN STD_LOGIC_VECTOR (2 - 1 downto 0);
outStream_TUSER_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_outStream_TLAST : IN STD_LOGIC_VECTOR (1 - 1 downto 0);
outStream_TLAST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_outStream_TID : IN STD_LOGIC_VECTOR (5 - 1 downto 0);
outStream_TID_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_outStream_TDEST : IN STD_LOGIC_VECTOR (6 - 1 downto 0);
outStream_TDEST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_outStream_TVALID : IN STD_LOGIC;
TRAN_outStream_TREADY : OUT STD_LOGIC;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_axi_s_outStream;
architecture behav of AESL_axi_s_outStream is
------------------------Local signal-------------------
signal reg_outStream_TREADY : STD_LOGIC;
signal outStream_TDATA_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TDATA_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TDATA_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal outStream_TDATA_empty_n : STD_LOGIC;
signal outStream_TDATA_full_n : STD_LOGIC;
type outStream_TDATA_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(8 - 1 downto 0);
signal outStream_TDATA_mem : outStream_TDATA_arr2D := (others => (others => '0'));
signal outStream_TDATA_ingress_status : INTEGER;
signal outStream_TDATA_ingress_status_bit : STD_LOGIC;
signal outStream_TDATA_out_i : INTEGER;
signal outStream_TDATA_out_end : STD_LOGIC;
signal outStream_TDATA_out_end_reg : STD_LOGIC;
signal outStream_TDATA_out_size : INTEGER;
signal outStream_TDATA_out_size_reg : INTEGER;
signal outStream_TDATA_out_step : INTEGER;
signal outStream_TDATA_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TDATA_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TKEEP_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TKEEP_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TKEEP_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal outStream_TKEEP_empty_n : STD_LOGIC;
signal outStream_TKEEP_full_n : STD_LOGIC;
type outStream_TKEEP_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal outStream_TKEEP_mem : outStream_TKEEP_arr2D := (others => (others => '0'));
signal outStream_TKEEP_ingress_status : INTEGER;
signal outStream_TKEEP_ingress_status_bit : STD_LOGIC;
signal outStream_TKEEP_out_i : INTEGER;
signal outStream_TKEEP_out_end : STD_LOGIC;
signal outStream_TKEEP_out_end_reg : STD_LOGIC;
signal outStream_TKEEP_out_size : INTEGER;
signal outStream_TKEEP_out_size_reg : INTEGER;
signal outStream_TKEEP_out_step : INTEGER;
signal outStream_TKEEP_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TKEEP_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TSTRB_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TSTRB_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TSTRB_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal outStream_TSTRB_empty_n : STD_LOGIC;
signal outStream_TSTRB_full_n : STD_LOGIC;
type outStream_TSTRB_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal outStream_TSTRB_mem : outStream_TSTRB_arr2D := (others => (others => '0'));
signal outStream_TSTRB_ingress_status : INTEGER;
signal outStream_TSTRB_ingress_status_bit : STD_LOGIC;
signal outStream_TSTRB_out_i : INTEGER;
signal outStream_TSTRB_out_end : STD_LOGIC;
signal outStream_TSTRB_out_end_reg : STD_LOGIC;
signal outStream_TSTRB_out_size : INTEGER;
signal outStream_TSTRB_out_size_reg : INTEGER;
signal outStream_TSTRB_out_step : INTEGER;
signal outStream_TSTRB_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TSTRB_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TUSER_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TUSER_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TUSER_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal outStream_TUSER_empty_n : STD_LOGIC;
signal outStream_TUSER_full_n : STD_LOGIC;
type outStream_TUSER_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(2 - 1 downto 0);
signal outStream_TUSER_mem : outStream_TUSER_arr2D := (others => (others => '0'));
signal outStream_TUSER_ingress_status : INTEGER;
signal outStream_TUSER_ingress_status_bit : STD_LOGIC;
signal outStream_TUSER_out_i : INTEGER;
signal outStream_TUSER_out_end : STD_LOGIC;
signal outStream_TUSER_out_end_reg : STD_LOGIC;
signal outStream_TUSER_out_size : INTEGER;
signal outStream_TUSER_out_size_reg : INTEGER;
signal outStream_TUSER_out_step : INTEGER;
signal outStream_TUSER_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TUSER_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TLAST_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TLAST_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TLAST_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal outStream_TLAST_empty_n : STD_LOGIC;
signal outStream_TLAST_full_n : STD_LOGIC;
type outStream_TLAST_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal outStream_TLAST_mem : outStream_TLAST_arr2D := (others => (others => '0'));
signal outStream_TLAST_ingress_status : INTEGER;
signal outStream_TLAST_ingress_status_bit : STD_LOGIC;
signal outStream_TLAST_out_i : INTEGER;
signal outStream_TLAST_out_end : STD_LOGIC;
signal outStream_TLAST_out_end_reg : STD_LOGIC;
signal outStream_TLAST_out_size : INTEGER;
signal outStream_TLAST_out_size_reg : INTEGER;
signal outStream_TLAST_out_step : INTEGER;
signal outStream_TLAST_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TLAST_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TID_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TID_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TID_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal outStream_TID_empty_n : STD_LOGIC;
signal outStream_TID_full_n : STD_LOGIC;
type outStream_TID_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(5 - 1 downto 0);
signal outStream_TID_mem : outStream_TID_arr2D := (others => (others => '0'));
signal outStream_TID_ingress_status : INTEGER;
signal outStream_TID_ingress_status_bit : STD_LOGIC;
signal outStream_TID_out_i : INTEGER;
signal outStream_TID_out_end : STD_LOGIC;
signal outStream_TID_out_end_reg : STD_LOGIC;
signal outStream_TID_out_size : INTEGER;
signal outStream_TID_out_size_reg : INTEGER;
signal outStream_TID_out_step : INTEGER;
signal outStream_TID_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TID_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TDEST_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TDEST_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal outStream_TDEST_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal outStream_TDEST_empty_n : STD_LOGIC;
signal outStream_TDEST_full_n : STD_LOGIC;
type outStream_TDEST_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(6 - 1 downto 0);
signal outStream_TDEST_mem : outStream_TDEST_arr2D := (others => (others => '0'));
signal outStream_TDEST_ingress_status : INTEGER;
signal outStream_TDEST_ingress_status_bit : STD_LOGIC;
signal outStream_TDEST_out_i : INTEGER;
signal outStream_TDEST_out_end : STD_LOGIC;
signal outStream_TDEST_out_end_reg : STD_LOGIC;
signal outStream_TDEST_out_size : INTEGER;
signal outStream_TDEST_out_size_reg : INTEGER;
signal outStream_TDEST_out_step : INTEGER;
signal outStream_TDEST_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal outStream_TDEST_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal reset_reg : STD_LOGIC;
function esl_icmp_eq(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if v1 = v2 then
res := "1";
else
res := "0";
end if;
return res;
end function;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_icmp_ult(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if unsigned(v1) < unsigned(v2) then
res := "1";
else
res := "0";
end if;
return res;
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if (RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if (i = 1) then
if ((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
begin
TRAN_outStream_TREADY_proc : process( outStream_TDATA_full_n, outStream_TKEEP_full_n, outStream_TSTRB_full_n, outStream_TUSER_full_n, outStream_TLAST_full_n, outStream_TID_full_n, outStream_TDEST_full_n, reset)
begin
if reset = '0' then
TRAN_outStream_TREADY <= '0';
reg_outStream_TREADY <= '0';
else
TRAN_outStream_TREADY <= '1' and outStream_TDATA_full_n and outStream_TKEEP_full_n and outStream_TSTRB_full_n and outStream_TUSER_full_n and outStream_TLAST_full_n and outStream_TID_full_n and outStream_TDEST_full_n and '1';
reg_outStream_TREADY <= '1' and outStream_TDATA_full_n and outStream_TKEEP_full_n and outStream_TSTRB_full_n and outStream_TUSER_full_n and outStream_TLAST_full_n and outStream_TID_full_n and outStream_TDEST_full_n and '1';
end if;
end process;
------------------------Write-only axi_s-------------------
--------------------Assignment for output axi_s port--------------
------------------------------------ outStream_TDATA ------------------------------
outStream_TDATA_full_n_proc : process(outStream_TDATA_mInPtr, outStream_TDATA_mOutPtr, outStream_TDATA_mFlag_hint)
begin
if (esl_icmp_eq(outStream_TDATA_mInPtr, outStream_TDATA_mOutPtr) = "1" and (outStream_TDATA_mFlag_hint = '1')) then
outStream_TDATA_full_n <= '0';
else
outStream_TDATA_full_n <= '1';
end if;
end process;
outStream_TDATA_out_end <= '1' when (outStream_TDATA_out_size /= 0) and ((outStream_TDATA_out_i = (outStream_TDATA_out_size - 1)) and (TRAN_outStream_TVALID = '1')) else '0';
outStream_TDATA_trans_num_sig <= (outStream_TDATA_trans_num_reg + outStream_TDATA_out_step) when ((outStream_TDATA_out_end = '1') and (outStream_TDATA_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) or ((outStream_TDATA_trans_num_reg + outStream_TDATA_out_step = AUTOTB_TRANSACTION_NUM) and (outStream_TDATA_out_size = 0)) else outStream_TDATA_trans_num_reg;
outStream_TDATA_trans_num <= (others => '0') when (reset = '0') else (outStream_TDATA_trans_num_reg + outStream_TDATA_out_step - 1) when ((outStream_TDATA_out_end = '0') and (outStream_TDATA_out_end_reg = '0') and (outStream_TDATA_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) else outStream_TDATA_trans_num_sig;
proc_gen_outStream_TDATA_out_i : process(reset, clk)
begin
if(reset = '0') then
outStream_TDATA_out_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_outStream_TVALID = '1' and outStream_TDATA_out_i < outStream_TDATA_out_size - 1) then
outStream_TDATA_out_i <= outStream_TDATA_out_i + 1;
elsif(outStream_TDATA_out_end = '1') then
outStream_TDATA_out_i <= 0;
end if;
end if;
end process;
proc_gen_outStream_TDATA_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
outStream_TDATA_trans_num_reg <= X"00000000";
elsif(clk'event and clk = '1') then
outStream_TDATA_trans_num_reg <= outStream_TDATA_trans_num_sig;
end if;
end process;
proc_gen_outStream_TDATA_out_end_reg: process(reset, clk)
begin
if(reset = '0') then
outStream_TDATA_out_end_reg <= '0';
elsif(clk'event and clk = '1') then
outStream_TDATA_out_end_reg <= outStream_TDATA_out_end;
end if;
end process;
proc_gen_outStream_TDATA_out_size: process
file fp : TEXT;
variable i : INTEGER;
variable size : INTEGER;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 200);
variable transaction_idx : INTEGER;
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_out_outStream_V_data_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_out_outStream_V_data_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until clk'event and clk = '1';
wait until reset = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 1;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
while((size = 0) and (token(1 to 14) /= "[[[/runtime]]]")) loop
i := i + 1;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
outStream_TDATA_out_size <= size;
outStream_TDATA_out_step <= i;
if(token(1 to 14) /= "[[[/runtime]]]") then
wait until clk'event and clk = '0';
while (outStream_TDATA_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
end if;
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
file_close (fp);
wait;
end process;
outStream_TDATA_out_mem_proc : process(outStream_TDATA_mInPtr, clk)
begin
if (CONV_INTEGER(outStream_TDATA_mInPtr) = 0) then
outStream_TDATA_mem(0) <= TRAN_outStream_TDATA ;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TDATA_mInPtr) < 262144) then
outStream_TDATA_mem(CONV_INTEGER(outStream_TDATA_mInPtr)) <= TRAN_outStream_TDATA ;
end if;
end if;
end if;
end process;
outStream_TDATA_mInPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (reset = '0' OR outStream_TDATA_out_end_reg = '1') then
outStream_TDATA_mInPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TDATA_mInPtr) < 262144) then
outStream_TDATA_mInPtr <= esl_add(outStream_TDATA_mInPtr, "1");
end if;
end if;
end if;
end process;
outStream_TDATA_out_size_reg_proc : process(reset, clk)
begin
if (reset = '0') then
outStream_TDATA_out_size_reg <= 0;
elsif (clk'event and clk = '1') then
outStream_TDATA_out_size_reg <= outStream_TDATA_out_size;
end if;
end process;
outStream_TDATA_write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
begin
transaction_idx := 0;
outStream_TDATA_mOutPtr <= std_logic_vector(to_unsigned(262145, outStream_TDATA_mOutPtr'length));
outStream_TDATA_mFlag_hint <= '1';
wait until reset = '1';
while (true) loop
wait until clk'event and clk = '1';
i := outStream_TDATA_out_step;
if ((i + transaction_idx) < AUTOTB_TRANSACTION_NUM + 1) then
while ((i /= 0) and ((i /= 1) or (i = 1 and outStream_TDATA_out_size = 0))) loop
file_open(fstatus, fp, TV_OUT_outStream_TDATA, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TDATA & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
i := i - 1;
end loop;
end if;
wait until clk'event and clk = '0';
while (outStream_TDATA_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
file_open(fstatus, fp, TV_OUT_outStream_TDATA, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TDATA & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
if (outStream_TDATA_out_size_reg /= 0) then
for i in 0 to outStream_TDATA_out_size_reg - 1 loop
write(token_line, "0x" & esl_conv_string_hex(outStream_TDATA_mem(i)));
writeline(fp, token_line);
end loop;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
------------------------------------ outStream_TKEEP ------------------------------
outStream_TKEEP_full_n_proc : process(outStream_TKEEP_mInPtr, outStream_TKEEP_mOutPtr, outStream_TKEEP_mFlag_hint)
begin
if (esl_icmp_eq(outStream_TKEEP_mInPtr, outStream_TKEEP_mOutPtr) = "1" and (outStream_TKEEP_mFlag_hint = '1')) then
outStream_TKEEP_full_n <= '0';
else
outStream_TKEEP_full_n <= '1';
end if;
end process;
outStream_TKEEP_out_end <= '1' when (outStream_TKEEP_out_size /= 0) and ((outStream_TKEEP_out_i = (outStream_TKEEP_out_size - 1)) and (TRAN_outStream_TVALID = '1')) else '0';
outStream_TKEEP_trans_num_sig <= (outStream_TKEEP_trans_num_reg + outStream_TKEEP_out_step) when ((outStream_TKEEP_out_end = '1') and (outStream_TKEEP_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) or ((outStream_TKEEP_trans_num_reg + outStream_TKEEP_out_step = AUTOTB_TRANSACTION_NUM) and (outStream_TKEEP_out_size = 0)) else outStream_TKEEP_trans_num_reg;
outStream_TKEEP_trans_num <= (others => '0') when (reset = '0') else (outStream_TKEEP_trans_num_reg + outStream_TKEEP_out_step - 1) when ((outStream_TKEEP_out_end = '0') and (outStream_TKEEP_out_end_reg = '0') and (outStream_TKEEP_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) else outStream_TKEEP_trans_num_sig;
proc_gen_outStream_TKEEP_out_i : process(reset, clk)
begin
if(reset = '0') then
outStream_TKEEP_out_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_outStream_TVALID = '1' and outStream_TKEEP_out_i < outStream_TKEEP_out_size - 1) then
outStream_TKEEP_out_i <= outStream_TKEEP_out_i + 1;
elsif(outStream_TKEEP_out_end = '1') then
outStream_TKEEP_out_i <= 0;
end if;
end if;
end process;
proc_gen_outStream_TKEEP_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
outStream_TKEEP_trans_num_reg <= X"00000000";
elsif(clk'event and clk = '1') then
outStream_TKEEP_trans_num_reg <= outStream_TKEEP_trans_num_sig;
end if;
end process;
proc_gen_outStream_TKEEP_out_end_reg: process(reset, clk)
begin
if(reset = '0') then
outStream_TKEEP_out_end_reg <= '0';
elsif(clk'event and clk = '1') then
outStream_TKEEP_out_end_reg <= outStream_TKEEP_out_end;
end if;
end process;
proc_gen_outStream_TKEEP_out_size: process
file fp : TEXT;
variable i : INTEGER;
variable size : INTEGER;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 200);
variable transaction_idx : INTEGER;
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_out_outStream_V_keep_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_out_outStream_V_keep_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until clk'event and clk = '1';
wait until reset = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 1;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
while((size = 0) and (token(1 to 14) /= "[[[/runtime]]]")) loop
i := i + 1;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
outStream_TKEEP_out_size <= size;
outStream_TKEEP_out_step <= i;
if(token(1 to 14) /= "[[[/runtime]]]") then
wait until clk'event and clk = '0';
while (outStream_TKEEP_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
end if;
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
file_close (fp);
wait;
end process;
outStream_TKEEP_out_mem_proc : process(outStream_TKEEP_mInPtr, clk)
begin
if (CONV_INTEGER(outStream_TKEEP_mInPtr) = 0) then
outStream_TKEEP_mem(0) <= TRAN_outStream_TKEEP ;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TKEEP_mInPtr) < 262144) then
outStream_TKEEP_mem(CONV_INTEGER(outStream_TKEEP_mInPtr)) <= TRAN_outStream_TKEEP ;
end if;
end if;
end if;
end process;
outStream_TKEEP_mInPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (reset = '0' OR outStream_TKEEP_out_end_reg = '1') then
outStream_TKEEP_mInPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TKEEP_mInPtr) < 262144) then
outStream_TKEEP_mInPtr <= esl_add(outStream_TKEEP_mInPtr, "1");
end if;
end if;
end if;
end process;
outStream_TKEEP_out_size_reg_proc : process(reset, clk)
begin
if (reset = '0') then
outStream_TKEEP_out_size_reg <= 0;
elsif (clk'event and clk = '1') then
outStream_TKEEP_out_size_reg <= outStream_TKEEP_out_size;
end if;
end process;
outStream_TKEEP_write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
begin
transaction_idx := 0;
outStream_TKEEP_mOutPtr <= std_logic_vector(to_unsigned(262145, outStream_TKEEP_mOutPtr'length));
outStream_TKEEP_mFlag_hint <= '1';
wait until reset = '1';
while (true) loop
wait until clk'event and clk = '1';
i := outStream_TKEEP_out_step;
if ((i + transaction_idx) < AUTOTB_TRANSACTION_NUM + 1) then
while ((i /= 0) and ((i /= 1) or (i = 1 and outStream_TKEEP_out_size = 0))) loop
file_open(fstatus, fp, TV_OUT_outStream_TKEEP, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TKEEP & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
i := i - 1;
end loop;
end if;
wait until clk'event and clk = '0';
while (outStream_TKEEP_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
file_open(fstatus, fp, TV_OUT_outStream_TKEEP, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TKEEP & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
if (outStream_TKEEP_out_size_reg /= 0) then
for i in 0 to outStream_TKEEP_out_size_reg - 1 loop
write(token_line, "0x" & esl_conv_string_hex(outStream_TKEEP_mem(i)));
writeline(fp, token_line);
end loop;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
------------------------------------ outStream_TSTRB ------------------------------
outStream_TSTRB_full_n_proc : process(outStream_TSTRB_mInPtr, outStream_TSTRB_mOutPtr, outStream_TSTRB_mFlag_hint)
begin
if (esl_icmp_eq(outStream_TSTRB_mInPtr, outStream_TSTRB_mOutPtr) = "1" and (outStream_TSTRB_mFlag_hint = '1')) then
outStream_TSTRB_full_n <= '0';
else
outStream_TSTRB_full_n <= '1';
end if;
end process;
outStream_TSTRB_out_end <= '1' when (outStream_TSTRB_out_size /= 0) and ((outStream_TSTRB_out_i = (outStream_TSTRB_out_size - 1)) and (TRAN_outStream_TVALID = '1')) else '0';
outStream_TSTRB_trans_num_sig <= (outStream_TSTRB_trans_num_reg + outStream_TSTRB_out_step) when ((outStream_TSTRB_out_end = '1') and (outStream_TSTRB_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) or ((outStream_TSTRB_trans_num_reg + outStream_TSTRB_out_step = AUTOTB_TRANSACTION_NUM) and (outStream_TSTRB_out_size = 0)) else outStream_TSTRB_trans_num_reg;
outStream_TSTRB_trans_num <= (others => '0') when (reset = '0') else (outStream_TSTRB_trans_num_reg + outStream_TSTRB_out_step - 1) when ((outStream_TSTRB_out_end = '0') and (outStream_TSTRB_out_end_reg = '0') and (outStream_TSTRB_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) else outStream_TSTRB_trans_num_sig;
proc_gen_outStream_TSTRB_out_i : process(reset, clk)
begin
if(reset = '0') then
outStream_TSTRB_out_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_outStream_TVALID = '1' and outStream_TSTRB_out_i < outStream_TSTRB_out_size - 1) then
outStream_TSTRB_out_i <= outStream_TSTRB_out_i + 1;
elsif(outStream_TSTRB_out_end = '1') then
outStream_TSTRB_out_i <= 0;
end if;
end if;
end process;
proc_gen_outStream_TSTRB_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
outStream_TSTRB_trans_num_reg <= X"00000000";
elsif(clk'event and clk = '1') then
outStream_TSTRB_trans_num_reg <= outStream_TSTRB_trans_num_sig;
end if;
end process;
proc_gen_outStream_TSTRB_out_end_reg: process(reset, clk)
begin
if(reset = '0') then
outStream_TSTRB_out_end_reg <= '0';
elsif(clk'event and clk = '1') then
outStream_TSTRB_out_end_reg <= outStream_TSTRB_out_end;
end if;
end process;
proc_gen_outStream_TSTRB_out_size: process
file fp : TEXT;
variable i : INTEGER;
variable size : INTEGER;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 200);
variable transaction_idx : INTEGER;
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_out_outStream_V_strb_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_out_outStream_V_strb_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until clk'event and clk = '1';
wait until reset = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 1;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
while((size = 0) and (token(1 to 14) /= "[[[/runtime]]]")) loop
i := i + 1;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
outStream_TSTRB_out_size <= size;
outStream_TSTRB_out_step <= i;
if(token(1 to 14) /= "[[[/runtime]]]") then
wait until clk'event and clk = '0';
while (outStream_TSTRB_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
end if;
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
file_close (fp);
wait;
end process;
outStream_TSTRB_out_mem_proc : process(outStream_TSTRB_mInPtr, clk)
begin
if (CONV_INTEGER(outStream_TSTRB_mInPtr) = 0) then
outStream_TSTRB_mem(0) <= TRAN_outStream_TSTRB ;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TSTRB_mInPtr) < 262144) then
outStream_TSTRB_mem(CONV_INTEGER(outStream_TSTRB_mInPtr)) <= TRAN_outStream_TSTRB ;
end if;
end if;
end if;
end process;
outStream_TSTRB_mInPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (reset = '0' OR outStream_TSTRB_out_end_reg = '1') then
outStream_TSTRB_mInPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TSTRB_mInPtr) < 262144) then
outStream_TSTRB_mInPtr <= esl_add(outStream_TSTRB_mInPtr, "1");
end if;
end if;
end if;
end process;
outStream_TSTRB_out_size_reg_proc : process(reset, clk)
begin
if (reset = '0') then
outStream_TSTRB_out_size_reg <= 0;
elsif (clk'event and clk = '1') then
outStream_TSTRB_out_size_reg <= outStream_TSTRB_out_size;
end if;
end process;
outStream_TSTRB_write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
begin
transaction_idx := 0;
outStream_TSTRB_mOutPtr <= std_logic_vector(to_unsigned(262145, outStream_TSTRB_mOutPtr'length));
outStream_TSTRB_mFlag_hint <= '1';
wait until reset = '1';
while (true) loop
wait until clk'event and clk = '1';
i := outStream_TSTRB_out_step;
if ((i + transaction_idx) < AUTOTB_TRANSACTION_NUM + 1) then
while ((i /= 0) and ((i /= 1) or (i = 1 and outStream_TSTRB_out_size = 0))) loop
file_open(fstatus, fp, TV_OUT_outStream_TSTRB, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TSTRB & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
i := i - 1;
end loop;
end if;
wait until clk'event and clk = '0';
while (outStream_TSTRB_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
file_open(fstatus, fp, TV_OUT_outStream_TSTRB, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TSTRB & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
if (outStream_TSTRB_out_size_reg /= 0) then
for i in 0 to outStream_TSTRB_out_size_reg - 1 loop
write(token_line, "0x" & esl_conv_string_hex(outStream_TSTRB_mem(i)));
writeline(fp, token_line);
end loop;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
------------------------------------ outStream_TUSER ------------------------------
outStream_TUSER_full_n_proc : process(outStream_TUSER_mInPtr, outStream_TUSER_mOutPtr, outStream_TUSER_mFlag_hint)
begin
if (esl_icmp_eq(outStream_TUSER_mInPtr, outStream_TUSER_mOutPtr) = "1" and (outStream_TUSER_mFlag_hint = '1')) then
outStream_TUSER_full_n <= '0';
else
outStream_TUSER_full_n <= '1';
end if;
end process;
outStream_TUSER_out_end <= '1' when (outStream_TUSER_out_size /= 0) and ((outStream_TUSER_out_i = (outStream_TUSER_out_size - 1)) and (TRAN_outStream_TVALID = '1')) else '0';
outStream_TUSER_trans_num_sig <= (outStream_TUSER_trans_num_reg + outStream_TUSER_out_step) when ((outStream_TUSER_out_end = '1') and (outStream_TUSER_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) or ((outStream_TUSER_trans_num_reg + outStream_TUSER_out_step = AUTOTB_TRANSACTION_NUM) and (outStream_TUSER_out_size = 0)) else outStream_TUSER_trans_num_reg;
outStream_TUSER_trans_num <= (others => '0') when (reset = '0') else (outStream_TUSER_trans_num_reg + outStream_TUSER_out_step - 1) when ((outStream_TUSER_out_end = '0') and (outStream_TUSER_out_end_reg = '0') and (outStream_TUSER_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) else outStream_TUSER_trans_num_sig;
proc_gen_outStream_TUSER_out_i : process(reset, clk)
begin
if(reset = '0') then
outStream_TUSER_out_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_outStream_TVALID = '1' and outStream_TUSER_out_i < outStream_TUSER_out_size - 1) then
outStream_TUSER_out_i <= outStream_TUSER_out_i + 1;
elsif(outStream_TUSER_out_end = '1') then
outStream_TUSER_out_i <= 0;
end if;
end if;
end process;
proc_gen_outStream_TUSER_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
outStream_TUSER_trans_num_reg <= X"00000000";
elsif(clk'event and clk = '1') then
outStream_TUSER_trans_num_reg <= outStream_TUSER_trans_num_sig;
end if;
end process;
proc_gen_outStream_TUSER_out_end_reg: process(reset, clk)
begin
if(reset = '0') then
outStream_TUSER_out_end_reg <= '0';
elsif(clk'event and clk = '1') then
outStream_TUSER_out_end_reg <= outStream_TUSER_out_end;
end if;
end process;
proc_gen_outStream_TUSER_out_size: process
file fp : TEXT;
variable i : INTEGER;
variable size : INTEGER;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 200);
variable transaction_idx : INTEGER;
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_out_outStream_V_user_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_out_outStream_V_user_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until clk'event and clk = '1';
wait until reset = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 1;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
while((size = 0) and (token(1 to 14) /= "[[[/runtime]]]")) loop
i := i + 1;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
outStream_TUSER_out_size <= size;
outStream_TUSER_out_step <= i;
if(token(1 to 14) /= "[[[/runtime]]]") then
wait until clk'event and clk = '0';
while (outStream_TUSER_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
end if;
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
file_close (fp);
wait;
end process;
outStream_TUSER_out_mem_proc : process(outStream_TUSER_mInPtr, clk)
begin
if (CONV_INTEGER(outStream_TUSER_mInPtr) = 0) then
outStream_TUSER_mem(0) <= TRAN_outStream_TUSER ;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TUSER_mInPtr) < 262144) then
outStream_TUSER_mem(CONV_INTEGER(outStream_TUSER_mInPtr)) <= TRAN_outStream_TUSER ;
end if;
end if;
end if;
end process;
outStream_TUSER_mInPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (reset = '0' OR outStream_TUSER_out_end_reg = '1') then
outStream_TUSER_mInPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TUSER_mInPtr) < 262144) then
outStream_TUSER_mInPtr <= esl_add(outStream_TUSER_mInPtr, "1");
end if;
end if;
end if;
end process;
outStream_TUSER_out_size_reg_proc : process(reset, clk)
begin
if (reset = '0') then
outStream_TUSER_out_size_reg <= 0;
elsif (clk'event and clk = '1') then
outStream_TUSER_out_size_reg <= outStream_TUSER_out_size;
end if;
end process;
outStream_TUSER_write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
begin
transaction_idx := 0;
outStream_TUSER_mOutPtr <= std_logic_vector(to_unsigned(262145, outStream_TUSER_mOutPtr'length));
outStream_TUSER_mFlag_hint <= '1';
wait until reset = '1';
while (true) loop
wait until clk'event and clk = '1';
i := outStream_TUSER_out_step;
if ((i + transaction_idx) < AUTOTB_TRANSACTION_NUM + 1) then
while ((i /= 0) and ((i /= 1) or (i = 1 and outStream_TUSER_out_size = 0))) loop
file_open(fstatus, fp, TV_OUT_outStream_TUSER, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TUSER & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
i := i - 1;
end loop;
end if;
wait until clk'event and clk = '0';
while (outStream_TUSER_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
file_open(fstatus, fp, TV_OUT_outStream_TUSER, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TUSER & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
if (outStream_TUSER_out_size_reg /= 0) then
for i in 0 to outStream_TUSER_out_size_reg - 1 loop
write(token_line, "0x" & esl_conv_string_hex(outStream_TUSER_mem(i)));
writeline(fp, token_line);
end loop;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
------------------------------------ outStream_TLAST ------------------------------
outStream_TLAST_full_n_proc : process(outStream_TLAST_mInPtr, outStream_TLAST_mOutPtr, outStream_TLAST_mFlag_hint)
begin
if (esl_icmp_eq(outStream_TLAST_mInPtr, outStream_TLAST_mOutPtr) = "1" and (outStream_TLAST_mFlag_hint = '1')) then
outStream_TLAST_full_n <= '0';
else
outStream_TLAST_full_n <= '1';
end if;
end process;
outStream_TLAST_out_end <= '1' when (outStream_TLAST_out_size /= 0) and ((outStream_TLAST_out_i = (outStream_TLAST_out_size - 1)) and (TRAN_outStream_TVALID = '1')) else '0';
outStream_TLAST_trans_num_sig <= (outStream_TLAST_trans_num_reg + outStream_TLAST_out_step) when ((outStream_TLAST_out_end = '1') and (outStream_TLAST_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) or ((outStream_TLAST_trans_num_reg + outStream_TLAST_out_step = AUTOTB_TRANSACTION_NUM) and (outStream_TLAST_out_size = 0)) else outStream_TLAST_trans_num_reg;
outStream_TLAST_trans_num <= (others => '0') when (reset = '0') else (outStream_TLAST_trans_num_reg + outStream_TLAST_out_step - 1) when ((outStream_TLAST_out_end = '0') and (outStream_TLAST_out_end_reg = '0') and (outStream_TLAST_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) else outStream_TLAST_trans_num_sig;
proc_gen_outStream_TLAST_out_i : process(reset, clk)
begin
if(reset = '0') then
outStream_TLAST_out_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_outStream_TVALID = '1' and outStream_TLAST_out_i < outStream_TLAST_out_size - 1) then
outStream_TLAST_out_i <= outStream_TLAST_out_i + 1;
elsif(outStream_TLAST_out_end = '1') then
outStream_TLAST_out_i <= 0;
end if;
end if;
end process;
proc_gen_outStream_TLAST_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
outStream_TLAST_trans_num_reg <= X"00000000";
elsif(clk'event and clk = '1') then
outStream_TLAST_trans_num_reg <= outStream_TLAST_trans_num_sig;
end if;
end process;
proc_gen_outStream_TLAST_out_end_reg: process(reset, clk)
begin
if(reset = '0') then
outStream_TLAST_out_end_reg <= '0';
elsif(clk'event and clk = '1') then
outStream_TLAST_out_end_reg <= outStream_TLAST_out_end;
end if;
end process;
proc_gen_outStream_TLAST_out_size: process
file fp : TEXT;
variable i : INTEGER;
variable size : INTEGER;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 200);
variable transaction_idx : INTEGER;
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_out_outStream_V_last_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_out_outStream_V_last_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until clk'event and clk = '1';
wait until reset = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 1;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
while((size = 0) and (token(1 to 14) /= "[[[/runtime]]]")) loop
i := i + 1;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
outStream_TLAST_out_size <= size;
outStream_TLAST_out_step <= i;
if(token(1 to 14) /= "[[[/runtime]]]") then
wait until clk'event and clk = '0';
while (outStream_TLAST_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
end if;
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
file_close (fp);
wait;
end process;
outStream_TLAST_out_mem_proc : process(outStream_TLAST_mInPtr, clk)
begin
if (CONV_INTEGER(outStream_TLAST_mInPtr) = 0) then
outStream_TLAST_mem(0) <= TRAN_outStream_TLAST ;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TLAST_mInPtr) < 262144) then
outStream_TLAST_mem(CONV_INTEGER(outStream_TLAST_mInPtr)) <= TRAN_outStream_TLAST ;
end if;
end if;
end if;
end process;
outStream_TLAST_mInPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (reset = '0' OR outStream_TLAST_out_end_reg = '1') then
outStream_TLAST_mInPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TLAST_mInPtr) < 262144) then
outStream_TLAST_mInPtr <= esl_add(outStream_TLAST_mInPtr, "1");
end if;
end if;
end if;
end process;
outStream_TLAST_out_size_reg_proc : process(reset, clk)
begin
if (reset = '0') then
outStream_TLAST_out_size_reg <= 0;
elsif (clk'event and clk = '1') then
outStream_TLAST_out_size_reg <= outStream_TLAST_out_size;
end if;
end process;
outStream_TLAST_write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
begin
transaction_idx := 0;
outStream_TLAST_mOutPtr <= std_logic_vector(to_unsigned(262145, outStream_TLAST_mOutPtr'length));
outStream_TLAST_mFlag_hint <= '1';
wait until reset = '1';
while (true) loop
wait until clk'event and clk = '1';
i := outStream_TLAST_out_step;
if ((i + transaction_idx) < AUTOTB_TRANSACTION_NUM + 1) then
while ((i /= 0) and ((i /= 1) or (i = 1 and outStream_TLAST_out_size = 0))) loop
file_open(fstatus, fp, TV_OUT_outStream_TLAST, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TLAST & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
i := i - 1;
end loop;
end if;
wait until clk'event and clk = '0';
while (outStream_TLAST_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
file_open(fstatus, fp, TV_OUT_outStream_TLAST, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TLAST & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
if (outStream_TLAST_out_size_reg /= 0) then
for i in 0 to outStream_TLAST_out_size_reg - 1 loop
write(token_line, "0x" & esl_conv_string_hex(outStream_TLAST_mem(i)));
writeline(fp, token_line);
end loop;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
------------------------------------ outStream_TID ------------------------------
outStream_TID_full_n_proc : process(outStream_TID_mInPtr, outStream_TID_mOutPtr, outStream_TID_mFlag_hint)
begin
if (esl_icmp_eq(outStream_TID_mInPtr, outStream_TID_mOutPtr) = "1" and (outStream_TID_mFlag_hint = '1')) then
outStream_TID_full_n <= '0';
else
outStream_TID_full_n <= '1';
end if;
end process;
outStream_TID_out_end <= '1' when (outStream_TID_out_size /= 0) and ((outStream_TID_out_i = (outStream_TID_out_size - 1)) and (TRAN_outStream_TVALID = '1')) else '0';
outStream_TID_trans_num_sig <= (outStream_TID_trans_num_reg + outStream_TID_out_step) when ((outStream_TID_out_end = '1') and (outStream_TID_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) or ((outStream_TID_trans_num_reg + outStream_TID_out_step = AUTOTB_TRANSACTION_NUM) and (outStream_TID_out_size = 0)) else outStream_TID_trans_num_reg;
outStream_TID_trans_num <= (others => '0') when (reset = '0') else (outStream_TID_trans_num_reg + outStream_TID_out_step - 1) when ((outStream_TID_out_end = '0') and (outStream_TID_out_end_reg = '0') and (outStream_TID_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) else outStream_TID_trans_num_sig;
proc_gen_outStream_TID_out_i : process(reset, clk)
begin
if(reset = '0') then
outStream_TID_out_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_outStream_TVALID = '1' and outStream_TID_out_i < outStream_TID_out_size - 1) then
outStream_TID_out_i <= outStream_TID_out_i + 1;
elsif(outStream_TID_out_end = '1') then
outStream_TID_out_i <= 0;
end if;
end if;
end process;
proc_gen_outStream_TID_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
outStream_TID_trans_num_reg <= X"00000000";
elsif(clk'event and clk = '1') then
outStream_TID_trans_num_reg <= outStream_TID_trans_num_sig;
end if;
end process;
proc_gen_outStream_TID_out_end_reg: process(reset, clk)
begin
if(reset = '0') then
outStream_TID_out_end_reg <= '0';
elsif(clk'event and clk = '1') then
outStream_TID_out_end_reg <= outStream_TID_out_end;
end if;
end process;
proc_gen_outStream_TID_out_size: process
file fp : TEXT;
variable i : INTEGER;
variable size : INTEGER;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 200);
variable transaction_idx : INTEGER;
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_out_outStream_V_id_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_out_outStream_V_id_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until clk'event and clk = '1';
wait until reset = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 1;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
while((size = 0) and (token(1 to 14) /= "[[[/runtime]]]")) loop
i := i + 1;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
outStream_TID_out_size <= size;
outStream_TID_out_step <= i;
if(token(1 to 14) /= "[[[/runtime]]]") then
wait until clk'event and clk = '0';
while (outStream_TID_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
end if;
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
file_close (fp);
wait;
end process;
outStream_TID_out_mem_proc : process(outStream_TID_mInPtr, clk)
begin
if (CONV_INTEGER(outStream_TID_mInPtr) = 0) then
outStream_TID_mem(0) <= TRAN_outStream_TID ;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TID_mInPtr) < 262144) then
outStream_TID_mem(CONV_INTEGER(outStream_TID_mInPtr)) <= TRAN_outStream_TID ;
end if;
end if;
end if;
end process;
outStream_TID_mInPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (reset = '0' OR outStream_TID_out_end_reg = '1') then
outStream_TID_mInPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TID_mInPtr) < 262144) then
outStream_TID_mInPtr <= esl_add(outStream_TID_mInPtr, "1");
end if;
end if;
end if;
end process;
outStream_TID_out_size_reg_proc : process(reset, clk)
begin
if (reset = '0') then
outStream_TID_out_size_reg <= 0;
elsif (clk'event and clk = '1') then
outStream_TID_out_size_reg <= outStream_TID_out_size;
end if;
end process;
outStream_TID_write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
begin
transaction_idx := 0;
outStream_TID_mOutPtr <= std_logic_vector(to_unsigned(262145, outStream_TID_mOutPtr'length));
outStream_TID_mFlag_hint <= '1';
wait until reset = '1';
while (true) loop
wait until clk'event and clk = '1';
i := outStream_TID_out_step;
if ((i + transaction_idx) < AUTOTB_TRANSACTION_NUM + 1) then
while ((i /= 0) and ((i /= 1) or (i = 1 and outStream_TID_out_size = 0))) loop
file_open(fstatus, fp, TV_OUT_outStream_TID, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TID & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
i := i - 1;
end loop;
end if;
wait until clk'event and clk = '0';
while (outStream_TID_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
file_open(fstatus, fp, TV_OUT_outStream_TID, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TID & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
if (outStream_TID_out_size_reg /= 0) then
for i in 0 to outStream_TID_out_size_reg - 1 loop
write(token_line, "0x" & esl_conv_string_hex(outStream_TID_mem(i)));
writeline(fp, token_line);
end loop;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
------------------------------------ outStream_TDEST ------------------------------
outStream_TDEST_full_n_proc : process(outStream_TDEST_mInPtr, outStream_TDEST_mOutPtr, outStream_TDEST_mFlag_hint)
begin
if (esl_icmp_eq(outStream_TDEST_mInPtr, outStream_TDEST_mOutPtr) = "1" and (outStream_TDEST_mFlag_hint = '1')) then
outStream_TDEST_full_n <= '0';
else
outStream_TDEST_full_n <= '1';
end if;
end process;
outStream_TDEST_out_end <= '1' when (outStream_TDEST_out_size /= 0) and ((outStream_TDEST_out_i = (outStream_TDEST_out_size - 1)) and (TRAN_outStream_TVALID = '1')) else '0';
outStream_TDEST_trans_num_sig <= (outStream_TDEST_trans_num_reg + outStream_TDEST_out_step) when ((outStream_TDEST_out_end = '1') and (outStream_TDEST_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) or ((outStream_TDEST_trans_num_reg + outStream_TDEST_out_step = AUTOTB_TRANSACTION_NUM) and (outStream_TDEST_out_size = 0)) else outStream_TDEST_trans_num_reg;
outStream_TDEST_trans_num <= (others => '0') when (reset = '0') else (outStream_TDEST_trans_num_reg + outStream_TDEST_out_step - 1) when ((outStream_TDEST_out_end = '0') and (outStream_TDEST_out_end_reg = '0') and (outStream_TDEST_trans_num_reg /= AUTOTB_TRANSACTION_NUM)) else outStream_TDEST_trans_num_sig;
proc_gen_outStream_TDEST_out_i : process(reset, clk)
begin
if(reset = '0') then
outStream_TDEST_out_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_outStream_TVALID = '1' and outStream_TDEST_out_i < outStream_TDEST_out_size - 1) then
outStream_TDEST_out_i <= outStream_TDEST_out_i + 1;
elsif(outStream_TDEST_out_end = '1') then
outStream_TDEST_out_i <= 0;
end if;
end if;
end process;
proc_gen_outStream_TDEST_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
outStream_TDEST_trans_num_reg <= X"00000000";
elsif(clk'event and clk = '1') then
outStream_TDEST_trans_num_reg <= outStream_TDEST_trans_num_sig;
end if;
end process;
proc_gen_outStream_TDEST_out_end_reg: process(reset, clk)
begin
if(reset = '0') then
outStream_TDEST_out_end_reg <= '0';
elsif(clk'event and clk = '1') then
outStream_TDEST_out_end_reg <= outStream_TDEST_out_end;
end if;
end process;
proc_gen_outStream_TDEST_out_size: process
file fp : TEXT;
variable i : INTEGER;
variable size : INTEGER;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 200);
variable transaction_idx : INTEGER;
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_out_outStream_V_dest_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_out_outStream_V_dest_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until clk'event and clk = '1';
wait until reset = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 1;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
while((size = 0) and (token(1 to 14) /= "[[[/runtime]]]")) loop
i := i + 1;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
size := esl_str_dec2int(token);
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
outStream_TDEST_out_size <= size;
outStream_TDEST_out_step <= i;
if(token(1 to 14) /= "[[[/runtime]]]") then
wait until clk'event and clk = '0';
while (outStream_TDEST_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
end if;
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
file_close (fp);
wait;
end process;
outStream_TDEST_out_mem_proc : process(outStream_TDEST_mInPtr, clk)
begin
if (CONV_INTEGER(outStream_TDEST_mInPtr) = 0) then
outStream_TDEST_mem(0) <= TRAN_outStream_TDEST ;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TDEST_mInPtr) < 262144) then
outStream_TDEST_mem(CONV_INTEGER(outStream_TDEST_mInPtr)) <= TRAN_outStream_TDEST ;
end if;
end if;
end if;
end process;
outStream_TDEST_mInPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (reset = '0' OR outStream_TDEST_out_end_reg = '1') then
outStream_TDEST_mInPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (TRAN_outStream_TVALID = '1' and reg_outStream_TREADY = '1' ) then
if (CONV_INTEGER(outStream_TDEST_mInPtr) < 262144) then
outStream_TDEST_mInPtr <= esl_add(outStream_TDEST_mInPtr, "1");
end if;
end if;
end if;
end process;
outStream_TDEST_out_size_reg_proc : process(reset, clk)
begin
if (reset = '0') then
outStream_TDEST_out_size_reg <= 0;
elsif (clk'event and clk = '1') then
outStream_TDEST_out_size_reg <= outStream_TDEST_out_size;
end if;
end process;
outStream_TDEST_write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
begin
transaction_idx := 0;
outStream_TDEST_mOutPtr <= std_logic_vector(to_unsigned(262145, outStream_TDEST_mOutPtr'length));
outStream_TDEST_mFlag_hint <= '1';
wait until reset = '1';
while (true) loop
wait until clk'event and clk = '1';
i := outStream_TDEST_out_step;
if ((i + transaction_idx) < AUTOTB_TRANSACTION_NUM + 1) then
while ((i /= 0) and ((i /= 1) or (i = 1 and outStream_TDEST_out_size = 0))) loop
file_open(fstatus, fp, TV_OUT_outStream_TDEST, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TDEST & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
i := i - 1;
end loop;
end if;
wait until clk'event and clk = '0';
while (outStream_TDEST_out_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
file_open(fstatus, fp, TV_OUT_outStream_TDEST, APPEND_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_outStream_TDEST & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
if (outStream_TDEST_out_size_reg /= 0) then
for i in 0 to outStream_TDEST_out_size_reg - 1 loop
write(token_line, "0x" & esl_conv_string_hex(outStream_TDEST_mem(i)));
writeline(fp, token_line);
end loop;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
|
gpl-3.0
|
3583310ddb9ca9a61a4861ad384b1e12
| 0.555036 | 3.657117 | false | false | false | false |
makestuff/comm-fpga
|
ss/vhdl/sync-recv/sync_recv.vhdl
| 1 | 2,582 |
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_recv is
port(
clk_in : in std_logic;
-- Serial in
serClkFE_in : in std_logic; -- serClk falling edge
serData_in : in std_logic;
-- Parallel out
recvData_out : out std_logic_vector(7 downto 0);
recvValid_out : out std_logic
);
end entity;
architecture rtl of sync_recv is
type StateType is (
S_IDLE,
S_RECV_BITS
);
signal state : StateType := S_IDLE;
signal state_next : StateType;
signal recvCount : unsigned(2 downto 0) := (others => '0');
signal recvCount_next : unsigned(2 downto 0);
signal recvData : std_logic_vector(6 downto 0) := (others => '0');
signal recvData_next : std_logic_vector(6 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
state <= state_next;
recvCount <= recvCount_next;
recvData <= recvData_next;
end if;
end process;
-- Next state logic
process(
state, serClkFE_in, serData_in, recvCount, recvData)
begin
state_next <= state;
recvCount_next <= recvCount;
recvData_next <= recvData;
recvData_out <= (others => 'X');
recvValid_out <= '0';
case state is
-- Receiving bits
when S_RECV_BITS =>
if ( serClkFE_in = '1' ) then
recvData_next <= serData_in & recvData(6 downto 1);
recvCount_next <= recvCount - 1;
if ( recvCount = 0 ) then
recvData_out <= serData_in & recvData;
recvValid_out <= '1';
state_next <= S_IDLE;
end if;
end if;
-- S_IDLE and others
when others =>
if ( serClkFE_in = '1' ) then
if ( serData_in = '0' ) then
-- This is a start bit; next bit will be data bit zero
recvCount_next <= "111";
state_next <= S_RECV_BITS;
end if;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
4c7481e87dd6ff00bf50dddc8ef60576
| 0.648335 | 3.27665 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/syn/vhdl/doHistStretch_CTRL_BUS_s_axi.vhd
| 5 | 13,493 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHistStretch_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
xMin :out STD_LOGIC_VECTOR(7 downto 0);
xMax :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity doHistStretch_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of xMin
-- bit 7~0 - xMin[7:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of xMax
-- bit 7~0 - xMax[7:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHistStretch_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_XMIN_DATA_0 : INTEGER := 16#10#;
constant ADDR_XMIN_CTRL : INTEGER := 16#14#;
constant ADDR_XMAX_DATA_0 : INTEGER := 16#18#;
constant ADDR_XMAX_CTRL : INTEGER := 16#1c#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_xMin : UNSIGNED(7 downto 0);
signal int_xMax : UNSIGNED(7 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_XMIN_DATA_0 =>
rdata_data <= RESIZE(int_xMin(7 downto 0), 32);
when ADDR_XMAX_DATA_0 =>
rdata_data <= RESIZE(int_xMax(7 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
xMin <= STD_LOGIC_VECTOR(int_xMin);
xMax <= STD_LOGIC_VECTOR(int_xMax);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_XMIN_DATA_0) then
int_xMin(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_xMin(7 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_XMAX_DATA_0) then
int_xMax(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_xMax(7 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
gpl-3.0
|
1b7a42a3b269a69c7eca366cad966511
| 0.451493 | 3.82238 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/iassoc01/tb_iassoc03.vhdl
| 1 | 472 |
entity tb_iassoc03 is
end tb_iassoc03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc03 is
signal a : natural;
signal b : natural;
signal res : natural;
begin
dut: entity work.iassoc03
port map (a, b, res);
process
begin
a <= 1;
b <= 5;
wait for 1 ns;
assert res = 6 severity failure;
a <= 197;
b <= 203;
wait for 1 ns;
assert res = 400 severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
b85c72f9b5177ae823d8312efcd88350
| 0.625 | 3.323944 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_03.vhd
| 4 | 2,469 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book (in text)
entity random_source is
generic ( min, max : natural;
seed : natural;
interval : delay_length );
port ( number : out natural );
end entity random_source;
-- end code from book
architecture fudged of random_source is
begin
process is
variable next_number : natural := seed;
begin
if next_number > max then
next_number := min;
end if;
number <= next_number;
next_number := next_number + 1;
wait for interval;
end process;
end architecture fudged;
entity test_bench is
end entity test_bench;
-- code from book
architecture random_test of test_bench is
subtype bv11 is bit_vector(10 downto 0);
function natural_to_bv11 ( n : natural ) return bv11 is
variable result : bv11 := (others => '0');
variable remaining_digits : natural := n;
begin
for index in result'reverse_range loop
result(index) := bit'val(remaining_digits mod 2);
remaining_digits := remaining_digits / 2;
exit when remaining_digits = 0;
end loop;
return result;
end function natural_to_bv11;
signal stimulus_vector : bv11;
-- . . .
begin
stimulus_generator : entity work.random_source
generic map ( min => 0, max => 2**10 - 1, seed => 0,
interval => 100 ns )
port map ( natural_to_bv11(number) => stimulus_vector );
-- . . .
end architecture random_test;
-- end code from book
|
gpl-2.0
|
2c01fa04b776d91aaa6c95f62d4cfec0
| 0.629 | 3.963082 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/dff03/tb_dff01.vhdl
| 1 | 894 |
entity tb_dff01 is
end tb_dff01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff01 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff01
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
67091c661ae516628ae7ad77c5b60f78
| 0.532438 | 3.204301 | false | false | false | false |
nickg/nvc
|
test/parse/bitstring.vhd
| 1 | 676 |
PACKAGE bitstring IS
CONSTANT x : bit_vector := X"1234";
CONSTANT y : bit_vector := O"1234";
CONSTANT z : bit_vector := X"ab";
CONSTANT b : bit_vector := B"101";
CONSTANT c : bit_vector := x"f";
CONSTANT d : bit_vector := X"a_b";
CONSTANT e : bit_vector := B"1111_1111_1111";
CONSTANT f : bit_vector := X"FFF";
CONSTANT g : bit_vector := O"777";
CONSTANT h : bit_vector := X"777";
CONSTANT i : bit_vector := B%1111_1111_1111%;
CONSTANT j : bit_vector := X%FFF%;
CONSTANT k : bit_vector := O%777%;
CONSTANT l : bit_vector := X%777%;
END PACKAGE;
PACKAGE bitstring_error IS
CONSTANT e1 : bit_vector := O"9"; -- Error
END PACKAGE;
|
gpl-3.0
|
8562db71157c847b55c30a0a7b0cb700
| 0.607988 | 3.115207 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dff03/tb_dff04.vhdl
| 1 | 1,062 |
entity tb_dff04 is
end tb_dff04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff04 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff04
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
en2 <= '0';
din <= '1';
pulse;
assert dout = '0' severity failure;
en2 <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
60f8a34c59fa0806d2f5014b76b49bd8
| 0.521657 | 3.208459 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/slice01/tb_slice01.vhdl
| 1 | 731 |
entity tb_slice01 is
end tb_slice01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_slice01 is
signal rst : std_logic;
signal clk : std_logic;
signal di : std_logic;
signal do : std_logic_vector (3 downto 0);
begin
dut: entity work.slice01
generic map (w => 4)
port map (rst, clk, di, do);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
constant b0 : std_logic_vector (3 downto 0) := "1101";
begin
rst <= '1';
pulse;
rst <= '0';
for i in b0'reverse_range loop
di <= b0 (i);
pulse;
end loop;
assert do = b0 severity error;
wait;
end process;
end behav;
|
gpl-2.0
|
f52f07a3a11d2ab9c33acbbe08da4548
| 0.588235 | 3.220264 | false | false | false | false |
nickg/nvc
|
test/misc/bufr_test.vhd
| 5 | 969 |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufr_test is
end entity;
architecture test of bufr_test is
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "7SERIES");
port ( O : out STD_LOGIC;
CE : in STD_LOGIC;
CLR : in STD_LOGIC;
I : in STD_LOGIC);
end component;
attribute BOX_TYPE of BUFR : component is "PRIMITIVE";
signal amu_adc_dco_i : std_logic;
signal amu_adc_dco : std_logic;
begin
BUF_DATA_CLK : BUFR
generic map ( BUFR_DIVIDE => "BYPASS",
SIM_DEVICE => "7SERIES")
port map ( O => amu_adc_dco,
CE => '1',
CLR => '0',
I => amu_adc_dco_i);
end architecture;
|
gpl-3.0
|
061166141e9f11432ba1506eeeb8638e
| 0.464396 | 3.971311 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/lib01/tb_and3.vhdl
| 1 | 657 |
library ieee;
use ieee.std_logic_1164.all;
entity tb_and3 is
end tb_and3;
architecture behav of tb_and3 is
signal i0, i1, i2 : std_logic;
signal o : std_logic;
begin
dut : entity work.and3
port map (i0 => i0, i1 => i1, i2 => i2, o => o);
process
constant v0 : std_logic_vector := b"1011";
constant v1 : std_logic_vector := b"1111";
constant v2 : std_logic_vector := b"1101";
constant ov : std_logic_vector := b"1001";
begin
for i in ov'range loop
i0 <= v0 (i);
i1 <= v1 (i);
i2 <= v2 (i);
wait for 1 ns;
assert o = ov(i) severity failure;
end loop;
wait;
end process;
end behav;
|
gpl-2.0
|
f0d9444bef69a3ddb9feecb47a87fcbe
| 0.585997 | 2.844156 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/SCOMP.vhd
| 1 | 20,769 |
LIBRARY IEEE;
LIBRARY ALTERA_MF;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ALTERA_MF.ALTERA_MF_COMPONENTS.ALL;
USE LPM.LPM_COMPONENTS.ALL;
use ieee.numeric_std.all;
ENTITY SCOMP IS
PORT(
CLOCK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
PCINT : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
IO_WRITE : OUT STD_LOGIC;
IO_CYCLE : OUT STD_LOGIC;
IO_ADDR : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
IO_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END SCOMP;
ARCHITECTURE a OF SCOMP IS
TYPE STATE_TYPE IS (
RESET_PC,
FETCH,
DECODE,
EX_LOAD,
EX_STORE,
EX_STORE2,
EX_ADD,
EX_SUB,
EX_JUMP,
EX_JNEG,
EX_JPOS,
EX_JZERO,
EX_AND,
EX_OR,
EX_XOR,
EX_SHIFT,
EX_ADDI,
EX_ILOAD,
EX_ISTORE,
EX_CALL,
EX_RETURN,
EX_IN,
EX_OUT,
EX_OUT2,
EX_LOADI,
EX_RETI,
EX_MOVR,
EX_ADDR,
EX_SUBR,
EX_ANDR,
EX_ORR,
EX_CMP,
EX_STORER,
EX_STORER2,
EX_LOADR,
EX_LOADR2
);
TYPE STACK_TYPE IS ARRAY (0 TO 9) OF STD_LOGIC_VECTOR(10 DOWNTO 0);
type HSREGISTER_FILE is array (0 to 31) of std_logic_vector(15 downto 0);
SIGNAL regFile : HSREGISTER_FILE;
SIGNAL STATE : STATE_TYPE;
SIGNAL PC_STACK : STACK_TYPE;
SIGNAL IO_IN : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL AC : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL AC_SAVED : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL AC_SHIFTED : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL IR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL MDR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL PC : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL PC_SAVED : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL MEM_ADDR : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL MW : STD_LOGIC;
SIGNAL IO_WRITE_INT : STD_LOGIC;
SIGNAL GIE : STD_LOGIC;
SIGNAL IIE : STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL INT_REQ : STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL INT_REQ_SYNC : STD_LOGIC_VECTOR( 3 DOWNTO 0); -- registered version of INT_REQ
SIGNAL INT_ACK : STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL IN_HOLD : STD_LOGIC;
BEGIN
-- Use altsyncram component for unified program and data memory
MEMORY : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
width_a => 16,
widthad_a => 11,
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_reg_a => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
outdata_aclr_a => "NONE",
init_file => "misctest.mif",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram"
)
PORT MAP (
wren_a => MW,
clock0 => NOT(CLOCK),
address_a => MEM_ADDR,
data_a => AC,
q_a => MDR
);
-- Use LPM function to shift AC using the SHIFT instruction
SHIFTER: LPM_CLSHIFT
GENERIC MAP (
lpm_width => 16,
lpm_widthdist => 4,
lpm_shifttype => "ARITHMETIC"
)
PORT MAP (
data => AC,
distance => IR(3 DOWNTO 0),
direction => IR(4),
result => AC_SHIFTED
);
-- Use LPM function to drive I/O bus
IO_BUS: LPM_BUSTRI
GENERIC MAP (
lpm_width => 16
)
PORT MAP (
data => AC,
enabledt => IO_WRITE_INT,
tridata => IO_DATA
);
IO_ADDR <= IR(7 DOWNTO 0);
WITH STATE SELECT MEM_ADDR <=
PC WHEN FETCH,
IR(10 DOWNTO 0) WHEN OTHERS;
WITH STATE SELECT IO_CYCLE <=
'1' WHEN EX_IN,
'1' WHEN EX_OUT2,
'0' WHEN OTHERS;
IO_WRITE <= IO_WRITE_INT;
PROCESS (CLOCK, RESETN)
variable regFileDest : integer range 0 to 31;
variable regFileSource : integer range 0 to 31;
BEGIN
IF (RESETN = '0') THEN -- Active low, asynchronous reset
STATE <= RESET_PC;
ELSIF (RISING_EDGE(CLOCK)) THEN
CASE STATE IS
WHEN RESET_PC =>
MW <= '0'; -- Clear memory write flag
PC <= "00000000000"; -- Reset PC to the beginning of memory, address 0x000
AC <= x"0000"; -- Clear AC register
IO_WRITE_INT <= '0';
GIE <= '1'; -- Enable interrupts
IIE <= "0000"; -- Mask all interrupts
STATE <= FETCH;
IN_HOLD <= '0';
INT_REQ_SYNC <= "0000";
WHEN FETCH =>
MW <= '0'; -- Clear memory write flag
IR <= MDR; -- Latch instruction into the IR
IO_WRITE_INT <= '0'; -- Lower IO_WRITE after an OUT
-- Interrupt Control
IF (GIE = '1') AND -- If Global Interrupt Enable set and...
(INT_REQ_SYNC /= "0000") THEN -- ...an interrupt is pending
IF INT_REQ_SYNC(0) = '1' THEN -- Got interrupt on PCINT0
INT_ACK <= "0001"; -- Acknowledge the interrupt
PC <= "00000000001"; -- Redirect execution
ELSIF INT_REQ_SYNC(1) = '1' THEN
INT_ACK <= "0010"; -- repeat for other pins
PC <= "00000000010";
ELSIF INT_REQ_SYNC(2) = '1' THEN
INT_ACK <= "0100";
PC <= "00000000011";
ELSIF INT_REQ_SYNC(3) = '1' THEN
INT_ACK <= "1000";
PC <= "00000000100";
END IF;
GIE <= '0'; -- Disable interrupts while in ISR
AC_SAVED <= AC; -- Save AC
PC_SAVED <= PC; -- Save PC
STATE <= FETCH; -- Repeat FETCH with new PC
ELSE -- either no interrupt or interrupts disabled
PC <= PC + 1; -- Increment PC to next instruction address
STATE <= DECODE;
INT_ACK <= "0000"; -- Clear any interrupt acknowledge
END IF;
WHEN DECODE =>
-- Write to the register variables.
regFileDest := ieee.numeric_std.to_integer(ieee.numeric_std.unsigned(IR(9 downto 5)));
regFileSource := ieee.numeric_std.to_integer(ieee.numeric_std.unsigned(IR(4 downto 0)));
CASE IR(15 downto 11) IS
WHEN "00000" => STATE <= FETCH;
WHEN "00001" => STATE <= EX_LOAD;
WHEN "00010" => STATE <= EX_STORE;
WHEN "00011" => STATE <= EX_ADD;
WHEN "00100" => STATE <= EX_SUB;
WHEN "00101" => STATE <= EX_JUMP;
WHEN "00110" => STATE <= EX_JNEG;
WHEN "00111" => STATE <= EX_JPOS;
WHEN "01000" => STATE <= EX_JZERO;
WHEN "01001" => STATE <= EX_AND;
WHEN "01010" => STATE <= EX_OR;
WHEN "01011" => STATE <= EX_XOR;
WHEN "01100" => STATE <= EX_SHIFT;
WHEN "01101" => STATE <= EX_ADDI;
WHEN "01110" => STATE <= EX_ILOAD;
WHEN "01111" => STATE <= EX_ISTORE;
WHEN "10000" => STATE <= EX_CALL;
WHEN "10001" => STATE <= EX_RETURN;
WHEN "10010" => STATE <= EX_IN;
WHEN "10011" => -- OUT
STATE <= EX_OUT;
IO_WRITE_INT <= '1'; -- raise IO_WRITE
WHEN "10100" => -- CLI
IIE <= IIE AND NOT(IR(3 DOWNTO 0)); -- disable indicated interrupts
STATE <= FETCH;
WHEN "10101" => -- SEI
IIE <= IIE OR IR(3 DOWNTO 0); -- enable indicated interrupts
STATE <= FETCH;
WHEN "10110" => STATE <= EX_RETI;
WHEN "10111" => STATE <= EX_LOADI;
--
-- Register-to-Register Operations
--
-- Harrison
WHEN "11000" => STATE <= EX_MOVR;
WHEN "11001" => STATE <= EX_ADDR;
WHEN "11010" => STATE <= EX_SUBR;
WHEN "11011" => STATE <= EX_ANDR;
WHEN "11100" => STATE <= EX_ORR;
WHEN "11101" => STATE <= EX_CMP;
WHEN "11110" => STATE <= EX_STORER;
WHEN "11111" => STATE <= EX_LOADR;
WHEN OTHERS => STATE <= FETCH; -- Invalid opcodes default to NOP
END CASE;
--
-- Fetch States
--
--
WHEN EX_LOAD =>
AC <= MDR; -- Latch data from MDR (memory contents) to AC
STATE <= FETCH;
WHEN EX_STORE =>
MW <= '1'; -- Raise MW to write AC to MEM
STATE <= EX_STORE2;
WHEN EX_STORE2 =>
MW <= '0'; -- Drop MW to end write cycle
STATE <= FETCH;
WHEN EX_ADD =>
AC <= AC + MDR;
STATE <= FETCH;
WHEN EX_SUB =>
AC <= AC - MDR;
STATE <= FETCH;
WHEN EX_JUMP =>
PC <= IR(10 DOWNTO 0);
STATE <= FETCH;
WHEN EX_JNEG =>
IF (AC(15) = '1') THEN
PC <= IR(10 DOWNTO 0);
END IF;
STATE <= FETCH;
WHEN EX_JPOS =>
IF ((AC(15) = '0') AND (AC /= x"0000")) THEN
PC <= IR(10 DOWNTO 0);
END IF;
STATE <= FETCH;
WHEN EX_JZERO =>
IF (AC = x"0000") THEN
PC <= IR(10 DOWNTO 0);
END IF;
STATE <= FETCH;
WHEN EX_AND =>
AC <= AC AND MDR;
STATE <= FETCH;
WHEN EX_OR =>
AC <= AC OR MDR;
STATE <= FETCH;
WHEN EX_XOR =>
AC <= AC XOR MDR;
STATE <= FETCH;
WHEN EX_SHIFT =>
AC <= AC_SHIFTED;
STATE <= FETCH;
WHEN EX_ADDI =>
AC <= AC + (IR(10) & IR(10) & IR(10) &
IR(10) & IR(10) & IR(10 DOWNTO 0));
STATE <= FETCH;
WHEN EX_ILOAD =>
IR(10 DOWNTO 0) <= MDR(10 DOWNTO 0);
STATE <= EX_LOAD;
WHEN EX_ISTORE =>
IR(10 DOWNTO 0) <= MDR(10 DOWNTO 0);
STATE <= EX_STORE;
WHEN EX_CALL =>
FOR i IN 0 TO 8 LOOP
PC_STACK(i + 1) <= PC_STACK(i);
END LOOP;
PC_STACK(0) <= PC;
PC <= IR(10 DOWNTO 0);
STATE <= FETCH;
WHEN EX_RETURN =>
FOR i IN 0 TO 8 LOOP
PC_STACK(i) <= PC_STACK(i + 1);
END LOOP;
PC <= PC_STACK(0);
STATE <= FETCH;
WHEN EX_IN =>
IF IN_HOLD = '0' THEN
AC <= IO_DATA;
IN_HOLD <= '1';
ELSE
STATE <= FETCH;
IN_HOLD <= '0';
END IF;
WHEN EX_OUT =>
STATE <= EX_OUT2;
WHEN EX_OUT2 =>
STATE <= FETCH;
WHEN EX_LOADI =>
AC <= (IR(10) & IR(10) & IR(10) &
IR(10) & IR(10) & IR(10 DOWNTO 0));
STATE <= FETCH;
WHEN EX_RETI =>
GIE <= '1'; -- re-enable interrupts
PC <= PC_SAVED; -- restore saved registers
AC <= AC_SAVED;
STATE <= FETCH;
--
-- Register-to-Register Operations
--
WHEN EX_MOVR =>
if( regFileDest = 0 ) then
-- If regFileSource is 0, then we dont want to overwrite AC with register_file(0)
-- We just skip.
if( regFileSource /= 0 ) then
AC <= regFile(regFileSource);
end if;
else
if( regFileSource = 0) then
regFile(regFileDest) <= AC;
else
regFile(regFileDest) <= regFile(regFileSource);
end if;
end if;
STATE <= FETCH;
WHEN EX_ADDR =>
if( regFileDest = 0 ) then
if(regFileSource = 0) then
-- Effectively doing AC*2.
AC <= AC + AC;
else
AC <= AC + regFile(regFileSource);
end if;
else
if(regFileSource = 0) then
AC <= regFile(regFileDest) + AC;
else
AC <= regFile(regFileDest) + regFile(regFileSource);
end if;
end if;
STATE <= FETCH;
--
-- SUBR
--
-- Subtract two registers together.
--
-- Format: subr <regA>, <regB>
--
-- AC = <regA> - <regB>
--
-- NOTE: The following pseudo-instructions could be implemented in the assembler:
--
-- 1) subr <regA>, <regB>, <regC> becomes
--
-- subr <regB>, <regC>
-- movr <regA>, AC
--
--
--
WHEN EX_SUBR =>
if( regFileDest = 0 ) then
if(regFileSource = 0) then
-- Anything minus itself is just zero.
AC <= x"0000";
else
AC <= AC - regFile(regFileSource);
end if;
else
if(regFileSource = 0) then
AC <= regFile(regFileDest) - AC;
else
AC <= regFile(regFileDest) - regFile(regFileSource);
end if;
end if;
STATE <= FETCH;
--
-- ANDR
--
-- Logical AND two registers together.
--
-- Format: ANDR <regA>, <regB>
--
-- AC = <regA> & <regB>
--
-- NOTE: The following pseudo-instructions could be implemented in the assembler:
--
-- 1) andr <regA>, <regB>, <regC> becomes
--
-- andr <regB>, <regC>
-- movr <regA>, AC
--
--
--
WHEN EX_ANDR =>
if( regFileDest = 0 ) then
if(regFileSource /= 0) then
AC <= AC and regFile(regFileSource);
end if;
-- AC <= AC and AC is just AC... IE do nothing.
else
if(regFileSource /= 0) then
AC <= regFile(regFileDest) and regFile(regFileSource);
else
AC <= regFile(regFileDest) and AC;
end if;
end if;
STATE <= FETCH;
--
-- ORR
--
-- Logical OR two registers together.
--
-- Format: ORR <regA>, <regB>
--
-- AC = <regA> | <regB>
--
-- NOTE: The following pseudo-instructions could be implemented in the assembler:
--
-- 1) orr <regA>, <regB>, <regC> becomes
--
-- orr <regB>, <regC>
-- movr <regA>, AC
--
--
--
WHEN EX_ORR =>
if( regFileDest = 0 ) then
if( regFileSource /= 0) then
AC <= AC or regFile(regFileSource);
end if;
-- AC <= AC or AC is just AC.
else
if( regFileSource = 0) then
AC <= regFile(regFileDest) or AC;
else
AC <= regFile(regFileDest) or regFile(regFileSource);
end if;
end if;
STATE <= FETCH;
--
-- CMP
--
-- Compare two registers together.
--
-- Format: CMP <regA>, <regB>
--
-- AC = -1 when <regA> is less than <regB>
-- AC = 0 when <regA> equals <regB>
-- AC = 1 when <regA> is greater than <regB>
--
-- Then the programmer uses jneg, jzero, jpos to jump accordingly.
--
-- NOTE: The following pseudo-instructions could be implemented in the assembler:
--
-- 1) gt <regA>, <regB>, <labelToJumpToIfTrue> becomes
--
-- cmp <regA>, <regB>
-- jpos <labelToJumpToIfTrue>
--
-- 2) lt <regA>, <regB>, <labelToJumpToIfTrue> becomes
--
-- cmp <regA>, <regB>
-- jneg <labelToJumpToIfTrue>
--
-- 3) eq <regA>, <regB>, <labelToJumpToIfTrue> becomes
--
-- cmp <regA>, <regB>
-- jzero <labelToJumpToIfTrue>
--
-- 4) lte <regA>, <regB>, <labelToJumpToIfTrue> becomes
--
-- cmp <regA>, <regB>
-- jneg <labelToJumpToIfTrue>
-- jzero <labelToJumpToIfTrue>
--
-- 5) gte <regA>, <regB>, <labelToJumpToIfTrue> becomes
--
-- cmp <regA>, <regB>
-- jzero <labelToJumpToIfTrue>
-- jpos <labelToJumpToIfTrue>
--
--
--
--
WHEN EX_CMP =>
if( regFileDest = 0 ) then
-- If we are comparing the AC to the AC then of course it is equal.
if(regFileSource = 0) then
AC <= x"0000";
else
-- If the AC and the source register are equal then we set the AC = 0.
if(AC = regFile(regFileSource)) then
AC <= "0000000000000000";
-- If the AC is less than the register source, then we set AC = -1.
elsif(ieee.numeric_std.signed(AC) < ieee.numeric_std.signed(regFile(regFileSource))) then
AC <= "1111111111111111";
-- If the AC is greater than the register source, then we set AC = 1.
else
AC <= "0000000000000001";
end if;
end if;
else
if(regFileSource = 0) then
if(regFile(regFileDest) = AC) then
AC <= "0000000000000000";
elsif(ieee.numeric_std.signed(regFile(regFileDest)) < ieee.numeric_std.signed(AC)) then
AC <= "1111111111111111";
else
AC <= "0000000000000001";
end if;
else
if(regFile(regFileDest) = regFile(regFileSource)) then
AC <= "0000000000000000";
elsif(ieee.numeric_std.signed(regFile(regFileDest)) < ieee.numeric_std.signed(regFile(regFileSource))) then
AC <= "1111111111111111";
else
AC <= "0000000000000001";
end if;
end if;
end if;
STATE <= FETCH;
--
-- STORER
--
-- Store data to an address in the supplied register.
-- Oh yeah, you MUST BE CAREFUL when using this...
--
-- On the other hand, you can now write self modifying
-- code, just in case you want to have some fun...
--
--
-- Format: STORER <register>
--
-- Memory[register] := AC
--
--
--
WHEN EX_STORER =>
-- Modify the instruction register to our new
-- address which is stored in the register that is
-- provided as part of the instruction.
if(regFileDest = 0) then
IR(10 downto 0) <= AC(10 downto 0);
else
IR(10 downto 0) <= regFile(regFileDest)(10 downto 0);
end if;
-- Now we write the MW signal high.
-- On the next clock, MEM_ADDR will be loaded with our
-- new "modified" IR values :)
MW <= '1';
STATE <= EX_STORER2;
WHEN EX_STORER2 =>
MW <= '0';
STATE <= FETCH;
--
-- LOADR
--
-- Load data stored in memory at the address specified by in
-- in the register to the AC.
--
-- NOTE: Be careful!! There is no telling what will happen
-- if you specify an address that is out of bounds!!
--
-- Have fun!
--
-- Format: LOADR <register>
--
-- AC := Memory[register]
--
--
WHEN EX_LOADR =>
-- Modify the IR(10 downto 0) value to the value stored in
-- the register.
if(regFileDest = 0) then
IR(10 downto 0) <= AC(10 downto 0);
else
IR(10 downto 0) <= regFile(regFileDest)(10 downto 0);
end if;
STATE <= EX_LOADR2;
WHEN EX_LOADR2 =>
-- At this point, the memory has been read, and the value
-- returned to the MDR. We can now grab that data like normal.
AC <= MDR;
STATE <= FETCH;
-- Just for reference.
--WHEN EX_STORE =>
-- MW <= '1'; -- Raise MW to write AC to MEM
-- STATE <= EX_STORE2;
-- WHEN EX_STORE2 =>
-- MW <= '0'; -- Drop MW to end write cycle
-- STATE <= FETCH;
-- Dont need this...
WHEN EX_GT =>
STATE <= FETCH;
WHEN OTHERS =>
STATE <= FETCH; -- If an invalid state is reached, return to FETCH
END CASE;
INT_REQ_SYNC <= INT_REQ; -- register interrupt requests to SCOMP's clock.
END IF;
END PROCESS;
-- This process monitors the external interrupt pins, setting
-- some flags if a rising edge is detected, and clearing flags
-- once the interrupt is acknowledged.
PROCESS(RESETN, PCINT, INT_ACK, IIE)
BEGIN
IF (RESETN = '0') THEN
INT_REQ <= "0000"; -- clear all interrupts on reset
ELSE
FOR i IN 0 TO 3 LOOP -- for each of the 4 interrupt pins
IF (INT_ACK(i) = '1') OR (IIE(i) = '0') THEN
INT_REQ(i) <= '0'; -- if acknowledged or masked, clear interrupt
ELSIF RISING_EDGE(PCINT(i)) THEN
INT_REQ(i) <= '1'; -- if rising edge on PCINT, request interrupt
END IF;
END LOOP;
END IF;
END PROCESS;
END a;
|
mit
|
f42416eec9750910492d594f8d71a7b5
| 0.486494 | 3.444279 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.