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stringlengths 6
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int64 1
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int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
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float64 1.51
17.5
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bool 1
class | config_or_test
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classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
nickg/nvc
|
lib/std/textio.vhd
| 1 | 4,641 |
-------------------------------------------------------------------------------
-- Copyright (C) 2012-2021 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TEXTIO package as defined by IEEE 1076-1993
-------------------------------------------------------------------------------
package textio is
type line is access string;
type text is file of string;
type side is (RIGHT, LEFT);
subtype width is natural;
file input : text open READ_MODE is "STD_INPUT";
file output : text open WRITE_MODE is "STD_OUTPUT";
procedure readline (file f: text; l: inout line);
procedure read (l : inout line;
value : out bit;
good : out boolean );
procedure read (l : inout line;
value : out bit );
procedure read (l : inout line;
value : out bit_vector;
good : out boolean );
procedure read (l : inout line;
value : out bit_vector );
procedure read (l : inout line;
value : out boolean;
good : out boolean );
procedure read (l : inout line;
value : out boolean );
procedure read (l : inout line;
value : out character;
good : out boolean );
procedure read (l : inout line;
value : out character );
procedure read (l : inout line;
value : out integer;
good : out boolean );
procedure read (l : inout line;
value : out integer );
procedure read (l : inout line;
value : out real;
good : out boolean );
procedure read (l : inout line;
value : out real );
procedure read (l : inout line;
value : out string;
good : out boolean );
procedure read (l : inout line;
value : out string );
procedure read (l : inout line;
value : out time;
good : out boolean );
procedure read (l : inout line;
value : out time );
procedure writeline (file f : text; l : inout line);
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 );
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns );
end package;
|
gpl-3.0
|
64a9a3b7880e20813991885f36832bc0
| 0.437406 | 5.285877 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_cmdsts_if.vhd
| 7 | 13,184 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
-- s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
gpl-3.0
|
c313c91c477f1376bfc3143e6800a42a
| 0.420055 | 4.954528 | false | false | false | false |
nickg/nvc
|
lib/vital/prmtvs_b.vhdl
| 1 | 235,734 |
-------------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : VITAL
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #204 - glitch detection prior to OutputMap
-- ----------------------------------------------------------------------------
-- v95.2 | ddl | 09/14/96 | #223 - single input prmtvs use on-detect
-- | | | instead of glitch-on-event behavior
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL
-- v95.4 | ddl | 01/16/97 | #243 - index constraint error in nbit xor/xnor
-- v99.1 | dbb | 03/31/99 | Updated for VHDL 93
-- ----------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE BODY VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Default values for Primitives
-- ------------------------------------------------------------------------
-- default values for delay parameters
CONSTANT VitalDefDelay01 : VitalDelayType01 := VitalZeroDelay01;
CONSTANT VitalDefDelay01Z : VitalDelayType01Z := VitalZeroDelay01Z;
TYPE VitalTimeArray IS ARRAY (NATURAL RANGE <>) OF TIME;
-- default primitive model operation parameters
-- Glitch detection/reporting
TYPE VitalGlitchModeType IS ( MessagePlusX, MessageOnly, XOnly, NoGlitch);
CONSTANT PrimGlitchMode : VitalGlitchModeType := XOnly;
-- ------------------------------------------------------------------------
-- Local Type and Subtype Declarations
-- ------------------------------------------------------------------------
---------------------------------------------------------------------------
-- enumeration value representing the transition or level of the signal.
-- See function 'GetEdge'
---------------------------------------------------------------------------
TYPE EdgeType IS ( 'U', -- Uninitialized level
'X', -- Unknown level
'0', -- low level
'1', -- high level
'\', -- 1 to 0 falling edge
'/', -- 0 to 1 rising edge
'F', -- * to 0 falling edge
'R', -- * to 1 rising edge
'f', -- rising to X edge
'r', -- falling to X edge
'x', -- Unknown edge (ie U->X)
'V' -- Timing violation edge
);
TYPE EdgeArray IS ARRAY ( NATURAL RANGE <> ) OF EdgeType;
TYPE EdgeX1Table IS ARRAY ( EdgeType ) OF EdgeType;
TYPE EdgeX2Table IS ARRAY ( EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX3Table IS ARRAY ( EdgeType, EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX4Table IS ARRAY (EdgeType,EdgeType,EdgeType,EdgeType) OF EdgeType;
TYPE LogicToEdgeT IS ARRAY(std_ulogic, std_ulogic) OF EdgeType;
TYPE LogicToLevelT IS ARRAY(std_ulogic ) OF EdgeType;
TYPE GlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
CurrentValue : std_ulogic;
END RECORD;
TYPE GlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF GlitchDataType;
-- Enumerated type used in selection of output path delays
TYPE SchedType IS
RECORD
inp0 : TIME; -- time (abs) of output change due to input change to 0
inp1 : TIME; -- time (abs) of output change due to input change to 1
InpX : TIME; -- time (abs) of output change due to input change to X
Glch0 : TIME; -- time (abs) of output glitch due to input change to 0
Glch1 : TIME; -- time (abs) of output glitch due to input change to 0
END RECORD;
TYPE SchedArray IS ARRAY ( NATURAL RANGE <> ) OF SchedType;
CONSTANT DefSchedType : SchedType := (TIME'HIGH, TIME'HIGH, 0 ns,0 ns,0 ns);
CONSTANT DefSchedAnd : SchedType := (TIME'HIGH, 0 ns,0 ns, TIME'HIGH,0 ns);
-- Constrained array declarations (common sizes used by primitives)
SUBTYPE SchedArray2 IS SchedArray(1 DOWNTO 0);
SUBTYPE SchedArray3 IS SchedArray(2 DOWNTO 0);
SUBTYPE SchedArray4 IS SchedArray(3 DOWNTO 0);
SUBTYPE SchedArray8 IS SchedArray(7 DOWNTO 0);
SUBTYPE TimeArray2 IS VitalTimeArray(1 DOWNTO 0);
SUBTYPE TimeArray3 IS VitalTimeArray(2 DOWNTO 0);
SUBTYPE TimeArray4 IS VitalTimeArray(3 DOWNTO 0);
SUBTYPE TimeArray8 IS VitalTimeArray(7 DOWNTO 0);
SUBTYPE GlitchArray2 IS GlitchDataArrayType(1 DOWNTO 0);
SUBTYPE GlitchArray3 IS GlitchDataArrayType(2 DOWNTO 0);
SUBTYPE GlitchArray4 IS GlitchDataArrayType(3 DOWNTO 0);
SUBTYPE GlitchArray8 IS GlitchDataArrayType(7 DOWNTO 0);
SUBTYPE EdgeArray2 IS EdgeArray(1 DOWNTO 0);
SUBTYPE EdgeArray3 IS EdgeArray(2 DOWNTO 0);
SUBTYPE EdgeArray4 IS EdgeArray(3 DOWNTO 0);
SUBTYPE EdgeArray8 IS EdgeArray(7 DOWNTO 0);
CONSTANT DefSchedArray2 : SchedArray2 :=
(OTHERS=> (0 ns, 0 ns, 0 ns, 0 ns, 0 ns));
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT InitialEdge : LogicToLevelT := (
'1'|'H' => 'R',
'0'|'L' => 'F',
OTHERS => 'x'
);
CONSTANT LogicToEdge : LogicToEdgeT := ( -- previous, current
-- old \ new: U X 0 1 Z W L H -
'U' => ( 'U', 'x', 'F', 'R', 'x', 'x', 'F', 'R', 'x' ),
'X' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'0' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'1' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'Z' => ( 'x', 'X', 'F', 'R', 'X', 'x', 'F', 'R', 'x' ),
'W' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'L' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'H' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'-' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' )
);
CONSTANT LogicToLevel : LogicToLevelT := (
'1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X'
);
-- -----------------------------------
-- 3-state logic tables
-- -----------------------------------
CONSTANT BufIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT BufIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
TYPE To_StateCharType IS ARRAY (VitalStateSymbolType) OF CHARACTER;
CONSTANT To_StateChar : To_StateCharType :=
( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v',
'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S' );
TYPE To_TruthCharType IS ARRAY (VitalTruthSymbolType) OF CHARACTER;
CONSTANT To_TruthChar : To_TruthCharType :=
( 'X', '0', '1', '-', 'B', 'Z' );
TYPE TruthTableOutMapType IS ARRAY (VitalTruthSymbolType) OF std_ulogic;
CONSTANT TruthTableOutMap : TruthTableOutMapType :=
-- 'X', '0', '1', '-', 'B', 'Z'
( 'X', '0', '1', 'X', '-', 'Z' );
TYPE StateTableOutMapType IS ARRAY (VitalStateSymbolType) OF std_ulogic;
-- does conversion to X01Z or '-' if invalid
CONSTANT StateTableOutMap : StateTableOutMapType :=
-- '/' '\' 'P' 'N' 'r' 'f' 'p' 'n' 'R' 'F' '^' 'v'
-- 'E' 'A' 'D' '*' 'X' '0' '1' '-' 'B' 'Z' 'S'
( '-','-','-','-','-','-','-','-','-','-','-','-',
'-','-','-','-','X','0','1','X','-','Z','W');
-- ------------------------------------------------------------------------
TYPE ValidTruthTableInputType IS ARRAY (VitalTruthSymbolType) OF BOOLEAN;
-- checks if a symbol IS valid for the stimulus portion of a truth table
CONSTANT ValidTruthTableInput : ValidTruthTableInputType :=
-- 'X' '0' '1' '-' 'B' 'Z'
( TRUE, TRUE, TRUE, TRUE, TRUE, FALSE );
TYPE TruthTableMatchType IS ARRAY (X01, VitalTruthSymbolType) OF BOOLEAN;
-- checks if an input matches th corresponding truth table symbol
-- use: TruthTableMatch(input_converted_to_X01, truth_table_stimulus_symbol)
CONSTANT TruthTableMatch : TruthTableMatchType := (
-- X, 0, 1, - B Z
( TRUE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- X
( FALSE, TRUE, FALSE, TRUE, TRUE, FALSE ), -- 0
( FALSE, FALSE, TRUE, TRUE, TRUE, FALSE ) -- 1
);
-- ------------------------------------------------------------------------
TYPE ValidStateTableInputType IS ARRAY (VitalStateSymbolType) OF BOOLEAN;
CONSTANT ValidStateTableInput : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'p', 'n', 'R', 'F', '^', 'v',
TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'E', 'A', 'D', '*',
TRUE, TRUE, TRUE, TRUE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
TRUE );
CONSTANT ValidStateTableState : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'p', 'n', 'R', 'F', '^', 'v',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'E', 'A', 'D', '*',
FALSE, FALSE, FALSE, FALSE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
FALSE );
TYPE StateTableMatchType IS ARRAY (X01,X01,VitalStateSymbolType) OF BOOLEAN;
-- last value, present value, table symbol
CONSTANT StateTableMatch : StateTableMatchType := (
( -- X (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,TRUE, TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, FALSE,TRUE, FALSE,
TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 0 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,TRUE, FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE ),
(TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 1 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,TRUE ,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE )
)
);
TYPE Logic_UX01Z_Table IS ARRAY (std_ulogic) OF UX01Z;
----------------------------------------------------------
-- table name : cvt_to_x01z
-- parameters : std_ulogic -- some logic value
-- returns : UX01Z -- state value of logic value
-- purpose : to convert state-strength to state only
----------------------------------------------------------
CONSTANT cvt_to_ux01z : Logic_UX01Z_Table :=
('U','X','0','1','Z','X','0','1','X' );
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MINIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return smaller of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 < in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MAXIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return larger of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 > in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-----------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Maximum;
-----------------------------------------------------------------------
IMPURE FUNCTION GlitchMinTime (
CONSTANT Time1, Time2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( Time1 >= NOW ) THEN
IF ( Time2 >= NOW ) THEN
RETURN Minimum ( Time1, Time2);
ELSE
RETURN Time1;
END IF;
ELSE
IF ( Time2 >= NOW ) THEN
RETURN Time2;
ELSE
RETURN 0 ns;
END IF;
END IF;
END;
--------------------------------------------------------------------
-- Error Message Types and Tables
--------------------------------------------------------------------
TYPE VitalErrorType IS (
ErrNegDel,
ErrInpSym,
ErrOutSym,
ErrStaSym,
ErrVctLng,
ErrTabWidSml,
ErrTabWidLrg,
ErrTabResSml,
ErrTabResLrg
);
TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalErrorSeverity : VitalErrorSeverityType := (
ErrNegDel => WARNING,
ErrInpSym => ERROR,
ErrOutSym => ERROR,
ErrStaSym => ERROR,
ErrVctLng => ERROR,
ErrTabWidSml => ERROR,
ErrTabWidLrg => WARNING,
ErrTabResSml => WARNING,
ErrTabResLrg => WARNING
);
CONSTANT MsgNegDel : STRING :=
"Negative delay. New output value not scheduled. Output signal is: ";
CONSTANT MsgInpSym : STRING :=
"Illegal symbol in the input portion of a Truth/State table.";
CONSTANT MsgOutSym : STRING :=
"Illegal symbol in the output portion of a Truth/State table.";
CONSTANT MsgStaSym : STRING :=
"Illegal symbol in the state portion of a State table.";
CONSTANT MsgVctLng : STRING :=
"Vector (array) lengths not equal. ";
CONSTANT MsgTabWidSml : STRING :=
"Width of the Truth/State table is too small.";
CONSTANT MsgTabWidLrg : STRING :=
"Width of Truth/State table is too large. Extra elements are ignored.";
CONSTANT MsgTabResSml : STRING :=
"Result of Truth/State table has too many elements.";
CONSTANT MsgTabResLrg : STRING :=
"Result of Truth/State table has too few elements.";
CONSTANT MsgUnknown : STRING :=
"Unknown error message.";
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
FUNCTION VitalMessage (
CONSTANT ErrorId : IN VitalErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrNegDel => RETURN MsgNegDel;
WHEN ErrInpSym => RETURN MsgInpSym;
WHEN ErrOutSym => RETURN MsgOutSym;
WHEN ErrStaSym => RETURN MsgStaSym;
WHEN ErrVctLng => RETURN MsgVctLng;
WHEN ErrTabWidSml => RETURN MsgTabWidSml;
WHEN ErrTabWidLrg => RETURN MsgTabWidLrg;
WHEN ErrTabResSml => RETURN MsgTabResSml;
WHEN ErrTabResLrg => RETURN MsgTabResLrg;
WHEN OTHERS => RETURN MsgUnknown;
END CASE;
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId)
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
---------------------------------------------------------------------------
PROCEDURE ReportGlitch (
CONSTANT GlitchRoutine : IN STRING;
CONSTANT OutSignalName : IN STRING;
CONSTANT PreemptedTime : IN TIME;
CONSTANT PreemptedValue : IN std_ulogic;
CONSTANT NewTime : IN TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT Index : IN INTEGER := 0;
CONSTANT IsArraySignal : IN BOOLEAN := FALSE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE;
BEGIN
Write (StrPtr1, PreemptedTime );
Write (StrPtr2, NewTime);
Write (StrPtr3, LogicCvtTable(PreemptedValue));
Write (StrPtr4, LogicCvtTable(NewValue));
IF IsArraySignal THEN
Write (StrPtr5, STRING'( "(" ) );
Write (StrPtr5, Index);
Write (StrPtr5, STRING'( ")" ) );
ELSE
Write (StrPtr5, STRING'( " " ) );
END IF;
-- Issue Report only if Preemted value has not been
-- removed from event queue
ASSERT PreemptedTime > NewTime
REPORT GlitchRoutine & ": GLITCH Detected on port " &
OutSignalName & StrPtr5.ALL &
"; Preempted Future Value := " & StrPtr3.ALL &
" @ " & StrPtr1.ALL &
"; Newly Scheduled Value := " & StrPtr4.ALL &
" @ " & StrPtr2.ALL &
";"
SEVERITY MsgSeverity;
DEALLOCATE(StrPtr1);
DEALLOCATE(StrPtr2);
DEALLOCATE(StrPtr3);
DEALLOCATE(StrPtr4);
DEALLOCATE(StrPtr5);
RETURN;
END ReportGlitch;
---------------------------------------------------------------------------
-- Procedure : VitalGlitchOnEvent
-- :
-- Parameters : OutSignal ........ signal being driven
-- : OutSignalName..... name of the driven signal
-- : GlitchData........ internal data required by the procedure
-- : NewValue.......... new value being assigned
-- : NewDelay.......... Delay accompanying the assignment
-- : (Note: for vectors, this is an array)
-- : GlitchMode........ Glitch generation mode
-- : MessagePlusX, MessageOnly,
-- : XOnly, NoGlitch )
-- : GlitchDelay....... if <= 0 ns , then there will be no Glitch
-- : if > NewDelay, then there is no Glitch,
-- : otherwise, this is the time when a FORCED
-- : generation of a glitch will occur.
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataType;
CONSTANT NewValue : IN std_logic;
CONSTANT NewDelay : IN TIME := 0 ns;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN TIME := -1 ns; -- IR#223
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
-- ------------------------------------------------------------------------
VARIABLE NoGlitchDet : BOOLEAN := FALSE;
VARIABLE OldGlitch : BOOLEAN := FALSE;
VARIABLE Dly : TIME := NewDelay;
BEGIN
-- If nothing to schedule, just return
IF NewDelay < 0 ns THEN
IF (NewValue /= GlitchData.SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled
IF GlitchData.SchedTime <= NOW THEN
GlitchData.CurrentValue := GlitchData.SchedValue;
IF (GlitchDelay <= 0 ns) THEN
IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF;
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlitchData.GlitchTime <= NOW THEN
GlitchData.CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlitchData.SchedValue = NewValue) THEN
dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
-- Transaction currently scheduled (no glitch if same value)
ELSIF (GlitchData.SchedValue = NewValue) AND
(GlitchData.SchedTime = GlitchData.GlitchTime) AND
(GlitchDelay <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
GlitchData.SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal <= NewValue AFTER Dly;
ELSIF NoGlitchDet THEN
GlitchData.GlitchTime := NOW+Dly;
OutSignal <= NewValue AFTER Dly;
ELSE -- new glitch
GlitchData.GlitchTime := GlitchMinTime ( GlitchData.GlitchTime,
NOW+GlitchDelay );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlitchData.GlitchTime, GlitchData.SchedValue,
(Dly + NOW), NewValue,
MsgSeverity=>MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW;
OutSignal <= TRANSPORT NewValue AFTER Dly;
ELSE
OutSignal <= NewValue AFTER Dly;
END IF;
END IF;
GlitchData.SchedValue := NewValue;
END IF;
RETURN;
END;
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataArrayType;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT NewDelay : IN VitalTimeArray;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN VitalTimeArray;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
ALIAS GlDataAlias : GlitchDataArrayType(1 TO GlitchData'LENGTH)
IS GlitchData;
ALIAS NewValAlias : std_logic_vector(1 TO NewValue'LENGTH) IS NewValue;
ALIAS GlDelayAlias : VitalTimeArray(1 TO GlitchDelay'LENGTH)
IS GlitchDelay;
ALIAS NewDelAlias : VitalTimeArray(1 TO NewDelay'LENGTH) IS NewDelay;
VARIABLE Index : INTEGER := OutSignal'LEFT;
VARIABLE Direction : INTEGER;
VARIABLE NoGlitchDet : BOOLEAN;
VARIABLE OldGlitch : BOOLEAN;
VARIABLE Dly, GlDly : TIME;
BEGIN
IF (OutSignal'LEFT > OutSignal'RIGHT) THEN
Direction := -1;
ELSE
Direction := 1;
END IF;
IF ( (OutSignal'LENGTH /= GlitchData'LENGTH) OR
(OutSignal'LENGTH /= NewValue'LENGTH) OR
(OutSignal'LENGTH /= NewDelay'LENGTH) OR
(OutSignal'LENGTH /= GlitchDelay'LENGTH) ) THEN
VitalError ( "VitalGlitchOnEvent", ErrVctLng, OutSignalName );
RETURN;
END IF;
-- a call to the scalar function cannot be made since the actual
-- name associated with a signal parameter must be locally static
FOR n IN 1 TO OutSignal'LENGTH LOOP
NoGlitchDet := FALSE;
OldGlitch := FALSE;
Dly := NewDelAlias(n);
-- If nothing to schedule, just skip to next loop iteration
IF NewDelAlias(n) < 0 ns THEN
IF (NewValAlias(n) /= GlDataAlias(n).SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled (i.e. last scheduled
-- transaction already occurred)
IF GlDataAlias(n).SchedTime <= NOW THEN
GlDataAlias(n).CurrentValue := GlDataAlias(n).SchedValue;
IF (GlDelayAlias(n) <= 0 ns) THEN
-- Next iteration if no change in value
IF (NewValAlias(n) = GlDataAlias(n).SchedValue) THEN
Index := Index + Direction;
NEXT;
END IF;
-- since last transaction already occurred there is no glitch
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlDataAlias(n).GlitchTime <= NOW THEN
GlDataAlias(n).CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlDataAlias(n).SchedValue = NewValAlias(n)) THEN
dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- Transaction currently scheduled
ELSIF (GlDataAlias(n).SchedValue = NewValAlias(n)) AND
(GlDataAlias(n).SchedTime = GlDataAlias(n).GlitchTime) AND
(GlDelayAlias(n) <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- update last scheduled transaction
GlDataAlias(n).SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSIF NoGlitchDet THEN
-- if no glitch then update last glitch time
-- and OutSignal(actual_index)
GlDataAlias(n).GlitchTime := NOW+Dly;
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSE -- new glitch
GlDataAlias(n).GlitchTime := GlitchMinTime (
GlDataAlias(n).GlitchTime,
NOW+GlDelayAlias(n) );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlDataAlias(n).GlitchTime,
GlDataAlias(n).SchedValue,
(Dly + NOW), NewValAlias(n),
Index, TRUE, MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
GlDly := GlDataAlias(n).GlitchTime - NOW;
OutSignal(Index) <= 'X' AFTER GlDly;
OutSignal(Index) <= TRANSPORT NewValAlias(n) AFTER Dly;
ELSE
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
END IF;
END IF; -- glitch / no-glitch
GlDataAlias(n).SchedValue := NewValAlias(n);
END IF; -- NewDelAlias(n) < 0 ns
Index := Index + Direction;
END LOOP;
RETURN;
END;
---------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : TruthOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- X01Zout - output converted to X01Z
-- err - true if illegal character is encountered
--
--
-- DESCRIPTION : converts the output of a truth table to a valid
-- std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE TruthOutputX01Z (
CONSTANT TableOut : IN VitalTruthSymbolType;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := TruthTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalTruthTable", ErrOutSym, To_TruthChar(TableOut));
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : StateOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- prev_out - previous output value
-- X01Zout - output cojnverted to X01Z
-- err - true if illegal character is encountered
--
-- DESCRIPTION : converts the output of a state table to a
-- valid std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE StateOutputX01Z (
CONSTANT TableOut : IN VitalStateSymbolType;
CONSTANT PrevOut : IN std_ulogic;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := StateTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalStateTable", ErrOutSym, To_StateChar(TableOut));
ELSIF (TempOut = 'W') THEN
TempOut := To_X01Z(PrevOut);
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME: StateMatch
--
-- PARAMETERS : symbol - symbol from state table
-- in2 - input from VitalStateTble procedure
-- to state table
-- in2LastValue - previous value of input
-- state - false if the symbol is from the input
-- portion of the table,
-- true if the symbol is from the state
-- portion of the table
-- Err - true if symbol is not a valid input symbol
-- ReturnValue - true if match occurred
--
-- DESCRIPTION : This procedure sets ReturnValue to true if in2 matches
-- symbol (from the state table). If symbol is an edge
-- value edge is set to true and in2 and in2LastValue are
-- checked against symbol. Err is set to true if symbol
-- is an invalid value for the input portion of the state
-- table.
--
-- ------------------------------------------------------------------------
PROCEDURE StateMatch (
CONSTANT Symbol : IN VitalStateSymbolType;
CONSTANT in2 : IN std_ulogic;
CONSTANT in2LastValue : IN std_ulogic;
CONSTANT State : IN BOOLEAN;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
IF (State) THEN
IF (NOT ValidStateTableState(Symbol)) THEN
VitalError ( "VitalStateTable", ErrStaSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
Err := FALSE;
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
END IF;
ELSE
IF (NOT ValidStateTableInput(Symbol) ) THEN
VitalError ( "VitalStateTable", ErrInpSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
Err := FALSE;
END IF;
END IF;
END;
-- -----------------------------------------------------------------------
-- FUNCTION NAME: StateTableLookUp
--
-- PARAMETERS : StateTable - state table
-- PresentDataIn - current inputs
-- PreviousDataIn - previous inputs and states
-- NumStates - number of state variables
-- PresentOutputs - current state and current outputs
--
-- DESCRIPTION : This function is used to find the output of the
-- StateTable corresponding to a given set of inputs.
--
-- ------------------------------------------------------------------------
FUNCTION StateTableLookUp (
CONSTANT StateTable : VitalStateTableType;
CONSTANT PresentDataIn : std_logic_vector;
CONSTANT PreviousDataIn : std_logic_vector;
CONSTANT NumStates : NATURAL;
CONSTANT PresentOutputs : std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := PresentDataIn'LENGTH;
CONSTANT NumInputs : INTEGER := InputSize + NumStates - 1;
CONSTANT TableEntries : INTEGER := StateTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := StateTable'LENGTH(2);
CONSTANT OutSize : INTEGER := TableWidth - InputSize - NumStates;
VARIABLE Inputs : std_logic_vector(0 TO NumInputs);
VARIABLE PrevInputs : std_logic_vector(0 TO NumInputs)
:= (OTHERS => 'X');
VARIABLE ReturnValue : std_logic_vector(0 TO (OutSize-1))
:= (OTHERS => 'X');
VARIABLE Temp : std_ulogic;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalStateTableType(0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= StateTable;
BEGIN
Inputs(0 TO InputSize-1) := PresentDataIn;
Inputs(InputSize TO NumInputs) := PresentOutputs(0 TO NumStates - 1);
PrevInputs(0 TO InputSize - 1) := PreviousDataIn(0 TO InputSize - 1);
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the entry
FOR j IN 0 TO InputSize + NumStates LOOP
IF (j = InputSize + NumStates) THEN -- a match occurred
FOR k IN 0 TO Minimum(OutSize, PresentOutputs'LENGTH)-1 LOOP
StateOutputX01Z (
TableAlias(i, TableWidth - k - 1),
PresentOutputs(PresentOutputs'LENGTH - k - 1),
Temp, Err);
ReturnValue(OutSize - k - 1) := Temp;
IF (Err) THEN
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END IF;
END LOOP;
RETURN ReturnValue;
END IF;
StateMatch ( TableAlias(i,j),
Inputs(j), PrevInputs(j),
j >= InputSize, Err, Match);
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END;
--------------------------------------------------------------------
-- to_ux01z
-------------------------------------------------------------------
FUNCTION To_UX01Z ( s : std_ulogic
) RETURN UX01Z IS
BEGIN
RETURN cvt_to_ux01z (s);
END;
---------------------------------------------------------------------------
-- Function : GetEdge
-- Purpose : Converts transitions on a given input signal into a
-- enumeration value representing the transition or level
-- of the signal.
--
-- previous "value" current "value" := "edge"
-- ---------------------------------------------------------
-- '1' | 'H' '1' | 'H' '1' level, no edge
-- '0' | 'L' '1' | 'H' '/' rising edge
-- others '1' | 'H' 'R' rising from X
--
-- '1' | 'H' '0' | 'L' '\' falling egde
-- '0' | 'L' '0' | 'L' '0' level, no edge
-- others '0' | 'L' 'F' falling from X
--
-- 'X' | 'W' | '-' 'X' | 'W' | '-' 'X' unknown (X) level
-- 'Z' 'Z' 'X' unknown (X) level
-- 'U' 'U' 'U' 'U' level
--
-- '1' | 'H' others 'f' falling to X
-- '0' | 'L' others 'r' rising to X
-- 'X' | 'W' | '-' 'U' | 'Z' 'x' unknown (X) edge
-- 'Z' 'X' | 'W' | '-' | 'U' 'x' unknown (X) edge
-- 'U' 'X' | 'W' | '-' | 'Z' 'x' unknown (X) edge
--
---------------------------------------------------------------------------
FUNCTION GetEdge (
SIGNAL s : IN std_logic
) RETURN EdgeType IS
BEGIN
IF (s'EVENT)
THEN RETURN LogicToEdge ( s'LAST_VALUE, s );
ELSE RETURN LogicToLevel ( s );
END IF;
END;
---------------------------------------------------------------------------
PROCEDURE GetEdge (
SIGNAL s : IN std_logic_vector;
VARIABLE LastS : INOUT std_logic_vector;
VARIABLE Edge : OUT EdgeArray ) IS
ALIAS sAlias : std_logic_vector ( 1 TO s'LENGTH ) IS s;
ALIAS LastSAlias : std_logic_vector ( 1 TO LastS'LENGTH ) IS LastS;
ALIAS EdgeAlias : EdgeArray ( 1 TO Edge'LENGTH ) IS Edge;
BEGIN
IF s'LENGTH /= LastS'LENGTH OR
s'LENGTH /= Edge'LENGTH THEN
VitalError ( "GetEdge", ErrVctLng, "s, LastS, Edge" );
END IF;
FOR n IN 1 TO s'LENGTH LOOP
EdgeAlias(n) := LogicToEdge( LastSAlias(n), sAlias(n) );
LastSAlias(n) := sAlias(n);
END LOOP;
END;
---------------------------------------------------------------------------
FUNCTION ToEdge ( Value : IN std_logic
) RETURN EdgeType IS
BEGIN
RETURN LogicToLevel( Value );
END;
-- Note: This function will likely be replaced by S'DRIVING_VALUE in VHDL'92
----------------------------------------------------------------------------
IMPURE FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataType
) RETURN std_logic IS
BEGIN
IF NOW >= GlitchData.SchedTime THEN
RETURN GlitchData.SchedValue;
ELSIF NOW >= GlitchData.GlitchTime THEN
RETURN 'X';
ELSE
RETURN GlitchData.CurrentValue;
END IF;
END;
---------------------------------------------------------------------------
IMPURE FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataArrayType
) RETURN std_logic_vector IS
VARIABLE Result : std_logic_vector(GlitchData'RANGE);
BEGIN
FOR n IN GlitchData'RANGE LOOP
IF NOW >= GlitchData(n).SchedTime THEN
Result(n) := GlitchData(n).SchedValue;
ELSIF NOW >= GlitchData(n).GlitchTime THEN
Result(n) := 'X';
ELSE
Result(n) := GlitchData(n).CurrentValue;
END IF;
END LOOP;
RETURN Result;
END;
---------------------------------------------------------------------------
-- function calculation utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Function : VitalSame
-- Returns : VitalSame compares the state (UX01) of two logic value. A
-- value of 'X' is returned if the values are different. The
-- common value is returned if the values are equal.
-- Purpose : When the result of a logic model may be either of two
-- separate input values (eg. when the select on a MUX is 'X'),
-- VitalSame may be used to determine if the result needs to
-- be 'X'.
-- Arguments : See the declarations below...
---------------------------------------------------------------------------
FUNCTION VitalSame (
CONSTANT a, b : IN std_ulogic
) RETURN std_ulogic IS
BEGIN
IF To_UX01(a) = To_UX01(b)
THEN RETURN To_UX01(a);
ELSE RETURN 'X';
END IF;
END;
---------------------------------------------------------------------------
-- delay selection utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure : BufPath, InvPath
--
-- Purpose : BufPath and InvPath compute output change times, based on
-- a change on an input port. The computed output change times
-- returned in the composite parameter 'schd'.
--
-- BufPath and InpPath are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the input ports of a model are
-- combined by the delay selection functions (VitalAND,
-- VitalOR, ...). The GetSchedDelay procedure converts the
-- combined output changes times to the single delay (delta
-- time) value for scheduling the output change (passed to
-- VitalGlitchOnEvent).
--
-- The values in 'schd' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- The output times are computed from the model INPUT value
-- and not the final value. For this reason, 'BufPath' should
-- be used to compute the output times for a non-inverting
-- delay paths and 'InvPath' should be used to compute the
-- ouput times for inverting delay paths. Delay paths which
-- include both non-inverting and paths require usage of both
-- 'BufPath' and 'InvPath'. (IE this is needed for the
-- select->output path of a MUX -- See the VitalMUX model).
--
--
-- Parameters : schd....... Computed output result times. (INOUT parameter
-- modified only on input edges)
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays from this input
--
---------------------------------------------------------------------------
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr01); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr10); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr01);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr10);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr10); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr01); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr10);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr01);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
---------------------------------------------------------------------------
-- Procedure : BufEnab, InvEnab
--
-- Purpose : BufEnab and InvEnab compute output change times, from a
-- change on an input enable port for a 3-state driver. The
-- computed output change times are returned in the composite
-- parameters 'schd1', 'schd0'.
--
-- BufEnab and InpEnab are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the non-enable input ports of
-- a model (See BufPath, InvPath) are combined using the delay
-- selection functions (VitalAND, VitalOR, ...). The
-- GetSchedDelay procedure combines the output times on the
-- enable path with the output times from the data path(s) and
-- computes the single delay (delta time) value for scheduling
-- the output change (passed to VitalGlitchOnEvent)
--
-- The values in 'schd*' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- 'schd1' contains output times for 1->Z, Z->1 transitions.
-- 'schd0' contains output times for 0->Z, Z->0 transitions.
--
-- 'BufEnab' is used for computing the output times for an
-- high asserted enable (output 'Z' for enable='0').
-- 'InvEnab' is used for computing the output times for an
-- low asserted enable (output 'Z' for enable='1').
--
-- Note: separate 'schd1', 'schd0' parameters are generated
-- so that the combination of the delay paths from
-- multiple enable signals may be combined using the
-- same functions/operators used in combining separate
-- data paths. (See exampe 2 below)
--
--
-- Parameters : schd1...... Computed output result times for 1->Z, Z->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- schd0...... Computed output result times for 0->Z, 0->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays for the enable -> output path.
--
---------------------------------------------------------------------------
PROCEDURE BufEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(trz1);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(trz0);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(tr1z);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(tr0z);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(tr1z);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(tr0z);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(trz1);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(trz0);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
---------------------------------------------------------------------------
-- Procedure : GetSchedDelay
--
-- Purpose : GetSchedDelay computes the final delay (incremental) for
-- for scheduling an output signal. The delay is computed
-- from the absolute output times in the 'NewSched' parameter.
-- (See BufPath, InvPath).
--
-- Computation of the output delay for non-3_state outputs
-- consists of selection the appropriate output time based
-- on the new output value 'NewValue' and subtracting 'NOW'
-- to convert to an incremental delay value.
--
-- The Computation of the output delay for 3_state output
-- also includes combination of the enable path delay with
-- the date path delay.
--
-- Parameters : NewDelay... Returned output delay value.
-- GlchDelay.. Returned output delay for the start of a glitch.
-- NewValue... New output value.
-- CurValue... Current value of the output.
-- NewSched... Composite containing the combined absolute
-- output times from the data inputs.
-- EnSched1... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 1->Z, Z->1)
-- EnSched0... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 0->Z, Z->0)
--
---------------------------------------------------------------------------
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType
) IS
VARIABLE Tim, Glch : TIME;
BEGIN
CASE To_UX01(NewValue) IS
WHEN '0' => Tim := NewSched.inp0;
Glch := NewSched.Glch1;
WHEN '1' => Tim := NewSched.inp1;
Glch := NewSched.Glch0;
WHEN OTHERS => Tim := NewSched.InpX;
Glch := -1 ns;
END CASE;
IF (CurValue /= NewValue)
THEN Glch := -1 ns;
END IF;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT VitalTimeArray;
VARIABLE GlchDelay : OUT VitalTimeArray;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT CurValue : IN std_logic_vector;
CONSTANT NewSched : IN SchedArray
) IS
VARIABLE Tim, Glch : TIME;
ALIAS NewDelayAlias : VitalTimeArray( NewDelay'LENGTH DOWNTO 1)
IS NewDelay;
ALIAS GlchDelayAlias : VitalTimeArray(GlchDelay'LENGTH DOWNTO 1)
IS GlchDelay;
ALIAS NewSchedAlias : SchedArray( NewSched'LENGTH DOWNTO 1)
IS NewSched;
ALIAS NewValueAlias : std_logic_vector ( NewValue'LENGTH DOWNTO 1 )
IS NewValue;
ALIAS CurValueAlias : std_logic_vector ( CurValue'LENGTH DOWNTO 1 )
IS CurValue;
BEGIN
FOR n IN NewDelay'LENGTH DOWNTO 1 LOOP
CASE To_UX01(NewValueAlias(n)) IS
WHEN '0' => Tim := NewSchedAlias(n).inp0;
Glch := NewSchedAlias(n).Glch1;
WHEN '1' => Tim := NewSchedAlias(n).inp1;
Glch := NewSchedAlias(n).Glch0;
WHEN OTHERS => Tim := NewSchedAlias(n).InpX;
Glch := -1 ns;
END CASE;
IF (CurValueAlias(n) /= NewValueAlias(n))
THEN Glch := -1 ns;
END IF;
NewDelayAlias(n) := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelayAlias(n) := Glch;
ELSE GlchDelayAlias(n) := Glch - NOW;
END IF; -- glch < 0 ns
END LOOP;
RETURN;
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType;
CONSTANT EnSched1 : IN SchedType;
CONSTANT EnSched0 : IN SchedType
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE Tim, Glch : TIME;
BEGIN
CASE v2'(To_X01Z(CurValue) & To_X01Z(NewValue)) IS
WHEN "00" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := GlitchMinTime(NewSched.Glch1,EnSched0.Glch0);
WHEN "01" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := EnSched1.Glch0;
WHEN "0Z" => Tim := EnSched0.inp0;
Glch := NewSched.Glch1;
WHEN "0X" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "10" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := EnSched0.Glch0;
WHEN "11" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := GlitchMinTime(NewSched.Glch0,EnSched1.Glch0);
WHEN "1Z" => Tim := EnSched1.inp0;
Glch := NewSched.Glch0;
WHEN "1X" => Tim := Maximum (NewSched.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "Z0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
IF NewSched.Glch0 > NOW
THEN Glch := Maximum(NewSched.Glch1,EnSched1.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "Z1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
IF NewSched.Glch1 > NOW
THEN Glch := Maximum(NewSched.Glch0,EnSched0.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "ZX" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "ZZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "X0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := 0 ns;
WHEN "X1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := 0 ns;
WHEN "XZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN OTHERS => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
END CASE;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
---------------------------------------------------------------------------
-- Operators and Functions for combination (selection) of path delays
-- > These functions support selection of the "appripriate" path delay
-- dependent on the logic function.
-- > These functions only "select" from the possable output times. No
-- calculation (addition) of delays is performed.
-- > See description of 'BufPath', 'InvPath' and 'GetSchedDelay'
-- > See primitive PROCEDURE models for examples.
---------------------------------------------------------------------------
FUNCTION "not" (
CONSTANT a : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := a.inp0 ;
z.inp0 := a.inp1 ;
z.InpX := a.InpX ;
z.Glch1 := a.Glch0;
z.Glch0 := a.Glch1;
RETURN (z);
END;
IMPURE FUNCTION "and" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp1 , b.inp1 );
z.inp0 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch1, b.Glch1 );
z.Glch0 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
IMPURE FUNCTION "or" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp0 , b.inp0 );
z.inp1 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch0, b.Glch0 );
z.Glch1 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
IMPURE FUNCTION "nand" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp1 , b.inp1 );
z.inp1 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch1, b.Glch1 );
z.Glch1 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
IMPURE FUNCTION "nor" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp0 , b.inp0 );
z.inp0 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch0, b.Glch0 );
z.Glch0 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 2-bit Logical gates.
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalXOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) NOR (a NOR b)
z.inp1 := Maximum ( Minimum (ai.inp0 , bi.inp0 ),
Minimum (ab.inp1 , bb.inp1 ) );
z.inp0 := Minimum ( Maximum (ai.inp1 , bi.inp1 ),
Maximum (ab.inp0 , bb.inp0 ) );
z.InpX := Maximum ( Maximum (ai.InpX , bi.InpX ),
Maximum (ab.InpX , bb.InpX ) );
z.Glch1 := Maximum (GlitchMinTime (ai.Glch0, bi.Glch0),
GlitchMinTime (ab.Glch1, bb.Glch1) );
z.Glch0 := GlitchMinTime ( Maximum (ai.Glch1, bi.Glch1),
Maximum (ab.Glch0, bb.Glch0) );
RETURN (z);
END;
IMPURE FUNCTION VitalXNOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) OR (a NOR b)
z.inp0 := Maximum ( Minimum (ab.inp0 , bb.inp0 ),
Minimum (ai.inp1 , bi.inp1 ) );
z.inp1 := Minimum ( Maximum (ab.inp1 , bb.inp1 ),
Maximum (ai.inp0 , bi.inp0 ) );
z.InpX := Maximum ( Maximum (ab.InpX , bb.InpX ),
Maximum (ai.InpX , bi.InpX ) );
z.Glch0 := Maximum (GlitchMinTime (ab.Glch0, bb.Glch0),
GlitchMinTime (ai.Glch1, bi.Glch1) );
z.Glch1 := GlitchMinTime ( Maximum (ab.Glch1, bb.Glch1),
Maximum (ai.Glch0, bi.Glch0) );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 3-bit Logical gates.
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalXOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 (ab,ai, bb,bi),
VitalXOR2 (ai,ab, bi,bb),
cb, ci );
END;
IMPURE FUNCTION VitalXNOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
cb, ci );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 4-bit Logical gates.
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalXOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
IMPURE FUNCTION VitalXNOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for N-bit Logical gates.
-- ------------------------------------------------------------------------
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
IMPURE FUNCTION VitalXOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
IMPURE FUNCTION VitalXNOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXNOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXNOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalMUX2 (
CONSTANT d1, d0 : IN SchedType;
CONSTANT sb, SI : IN SchedType
) RETURN SchedType IS
BEGIN
RETURN (d1 AND sb) OR (d0 AND (NOT SI) );
END;
--
IMPURE FUNCTION VitalMUX4 (
CONSTANT Data : IN SchedArray4;
CONSTANT sb : IN SchedArray2;
CONSTANT SI : IN SchedArray2
) RETURN SchedType IS
BEGIN
RETURN ( sb(1) AND VitalMUX2(Data(3),Data(2), sb(0), SI(0)) )
OR ( (NOT SI(1)) AND VitalMUX2(Data(1),Data(0), sb(0), SI(0)) );
END;
IMPURE FUNCTION VitalMUX8 (
CONSTANT Data : IN SchedArray8;
CONSTANT sb : IN SchedArray3;
CONSTANT SI : IN SchedArray3
) RETURN SchedType IS
BEGIN
RETURN ( ( sb(2)) AND VitalMUX4 (Data(7 DOWNTO 4),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) )
OR ( (NOT SI(2)) AND VitalMUX4 (Data(3 DOWNTO 0),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) );
END;
--
IMPURE FUNCTION VInterMux (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT sMsb : INTEGER := sb'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
BEGIN
IF sb'LENGTH = 1 THEN
RETURN VitalMUX2( Data(2), Data(1), sb(1), SI(1) );
ELSIF sb'LENGTH = 2 THEN
RETURN VitalMUX4( Data, sb, SI );
ELSIF sb'LENGTH = 3 THEN
RETURN VitalMUX8( Data, sb, SI );
ELSIF sb'LENGTH > 3 THEN
RETURN (( sb(sMsb)) AND VInterMux( Data(dMsbLow DOWNTO 1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ))
OR ((NOT SI(sMsb)) AND VInterMux( Data(dMsbHigh DOWNTO dMsbLow+1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ));
ELSE
RETURN (0 ns, 0 ns, 0 ns, 0 ns, 0 ns); -- dselect'LENGTH < 1
END IF;
END;
--
IMPURE FUNCTION VitalMUX (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT msb : INTEGER := 2**sb'LENGTH;
VARIABLE lDat : SchedArray(msb DOWNTO 1);
ALIAS DataAlias : SchedArray ( Data'LENGTH DOWNTO 1 ) IS Data;
ALIAS sbAlias : SchedArray ( sb'LENGTH DOWNTO 1 ) IS sb;
ALIAS siAlias : SchedArray ( SI'LENGTH DOWNTO 1 ) IS SI;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
FOR i IN msb DOWNTO Data'LENGTH+1 LOOP
lDat(i) := DefSchedAnd;
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
RETURN VInterMux( lDat, sbAlias, siAlias );
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalDECODER2 (
CONSTANT DataB : IN SchedType;
CONSTANT DataI : IN SchedType;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray2;
BEGIN
Result(1) := Enable AND ( DataB);
Result(0) := Enable AND (NOT DataI);
RETURN Result;
END;
IMPURE FUNCTION VitalDECODER4 (
CONSTANT DataB : IN SchedArray2;
CONSTANT DataI : IN SchedArray2;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray4;
BEGIN
Result(3) := Enable AND ( DataB(1)) AND ( DataB(0));
Result(2) := Enable AND ( DataB(1)) AND (NOT DataI(0));
Result(1) := Enable AND (NOT DataI(1)) AND ( DataB(0));
Result(0) := Enable AND (NOT DataI(1)) AND (NOT DataI(0));
RETURN Result;
END;
IMPURE FUNCTION VitalDECODER8 (
CONSTANT DataB : IN SchedArray3;
CONSTANT DataI : IN SchedArray3;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray8;
BEGIN
Result(7):= Enable AND ( DataB(2))AND( DataB(1))AND( DataB(0));
Result(6):= Enable AND ( DataB(2))AND( DataB(1))AND(NOT DataI(0));
Result(5):= Enable AND ( DataB(2))AND(NOT DataI(1))AND( DataB(0));
Result(4):= Enable AND ( DataB(2))AND(NOT DataI(1))AND(NOT DataI(0));
Result(3):= Enable AND (NOT DataI(2))AND( DataB(1))AND( DataB(0));
Result(2):= Enable AND (NOT DataI(2))AND( DataB(1))AND(NOT DataI(0));
Result(1):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND( DataB(0));
Result(0):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND(NOT DataI(0));
RETURN Result;
END;
IMPURE FUNCTION VitalDECODER (
CONSTANT DataB : IN SchedArray;
CONSTANT DataI : IN SchedArray;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
CONSTANT DMsb : INTEGER := DataB'LENGTH - 1;
ALIAS DataBAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataB;
ALIAS DataIAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataI;
BEGIN
IF DataB'LENGTH = 1 THEN
RETURN VitalDECODER2 ( DataBAlias( 0 ),
DataIAlias( 0 ), Enable );
ELSIF DataB'LENGTH = 2 THEN
RETURN VitalDECODER4 ( DataBAlias(1 DOWNTO 0),
DataIAlias(1 DOWNTO 0), Enable );
ELSIF DataB'LENGTH = 3 THEN
RETURN VitalDECODER8 ( DataBAlias(2 DOWNTO 0),
DataIAlias(2 DOWNTO 0), Enable );
ELSIF DataB'LENGTH > 3 THEN
RETURN VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataBAlias(DMsb)) )
& VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataIAlias(DMsb)) );
ELSE
RETURN DefSchedArray2;
END IF;
END;
-------------------------------------------------------------------------------
-- PRIMITIVES
-------------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b);
END;
--
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b);
END;
--
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b);
END;
--
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NAND b);
END;
--
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NOR b);
END;
--
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b));
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c);
END;
--
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c);
END;
--
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c);
END;
--
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c));
END;
--
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c));
END;
--
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c));
END;
-- ---------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ---------------------------------------------------------------------------
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c AND d);
END;
--
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c OR d);
END;
--
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c XOR d);
END;
--
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c AND d));
END;
--
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c OR d));
END;
--
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c XOR d));
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01(Data));
END;
--
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf0_Table(Enable,Data));
END;
--
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf1_Table(Enable,Data));
END;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01Z(Data));
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT Data);
END;
--
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf0_Table(Enable,Data));
END;
--
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf1_Table(Enable,Data));
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect) IS
WHEN '0' => Result := To_UX01(Data0);
WHEN '1' => Result := To_UX01(Data1);
WHEN OTHERS => Result := VitalSame( Data1, Data0 );
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Slct : std_logic_vector2;
VARIABLE Result : UX01;
BEGIN
Slct := To_X01(dSelect);
CASE Slct IS
WHEN "00" => Result := To_UX01(Data(0));
WHEN "01" => Result := To_UX01(Data(1));
WHEN "10" => Result := To_UX01(Data(2));
WHEN "11" => Result := To_UX01(Data(3));
WHEN "0X" => Result := VitalSame( Data(1), Data(0) );
WHEN "1X" => Result := VitalSame( Data(2), Data(3) );
WHEN "X0" => Result := VitalSame( Data(2), Data(0) );
WHEN "X1" => Result := VitalSame( Data(3), Data(1) );
WHEN OTHERS => Result := VitalSame( VitalSame(Data(3),Data(2)),
VitalSame(Data(1),Data(0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect(2)) IS
WHEN '0' => Result := VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0));
WHEN '1' => Result := VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0));
WHEN OTHERS => Result := VitalSame( VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0)),
VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector
) RETURN std_ulogic IS
CONSTANT sMsb : INTEGER := dSelect'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE Result : UX01;
BEGIN
IF dSelect'LENGTH = 1 THEN
Result := VitalMUX2( DataAlias(2), DataAlias(1), dSelAlias(1) );
ELSIF dSelect'LENGTH = 2 THEN
Result := VitalMUX4( DataAlias, dSelAlias );
ELSIF dSelect'LENGTH > 2 THEN
CASE To_X01(dSelect(sMsb)) IS
WHEN '0' =>
Result := VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN '1' =>
Result := VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN OTHERS =>
Result := VitalSame(
VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) ),
VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) )
);
END CASE;
ELSE
Result := 'X'; -- dselect'LENGTH < 1
END IF;
RETURN Result;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
CONSTANT msb : INTEGER := 2**dSelect'LENGTH;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE lDat : std_logic_vector(msb DOWNTO 1) := (OTHERS=>'X');
VARIABLE Result : UX01;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
Result := VInterMux( lDat, dSelAlias );
RETURN ResultMap(Result);
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2 IS
VARIABLE Result : std_logic_vector2;
BEGIN
Result(1) := ResultMap(Enable AND ( Data));
Result(0) := ResultMap(Enable AND (NOT Data));
RETURN Result;
END;
--
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4 IS
VARIABLE Result : std_logic_vector4;
BEGIN
Result(3) := ResultMap(Enable AND ( Data(1)) AND ( Data(0)));
Result(2) := ResultMap(Enable AND ( Data(1)) AND (NOT Data(0)));
Result(1) := ResultMap(Enable AND (NOT Data(1)) AND ( Data(0)));
Result(0) := ResultMap(Enable AND (NOT Data(1)) AND (NOT Data(0)));
RETURN Result;
END;
--
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8 IS
VARIABLE Result : std_logic_vector8;
BEGIN
Result(7) := ( Data(2)) AND ( Data(1)) AND ( Data(0));
Result(6) := ( Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(5) := ( Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(4) := ( Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(3) := (NOT Data(2)) AND ( Data(1)) AND ( Data(0));
Result(2) := (NOT Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(1) := (NOT Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(0) := (NOT Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(0) := ResultMap ( Enable AND Result(0) );
Result(1) := ResultMap ( Enable AND Result(1) );
Result(2) := ResultMap ( Enable AND Result(2) );
Result(3) := ResultMap ( Enable AND Result(3) );
Result(4) := ResultMap ( Enable AND Result(4) );
Result(5) := ResultMap ( Enable AND Result(5) );
Result(6) := ResultMap ( Enable AND Result(6) );
Result(7) := ResultMap ( Enable AND Result(7) );
RETURN Result;
END;
--
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector IS
CONSTANT DMsb : INTEGER := Data'LENGTH - 1;
ALIAS DataAlias : std_logic_vector ( DMsb DOWNTO 0 ) IS Data;
BEGIN
IF Data'LENGTH = 1 THEN
RETURN VitalDECODER2 (DataAlias( 0 ), Enable, ResultMap );
ELSIF Data'LENGTH = 2 THEN
RETURN VitalDECODER4 (DataAlias(1 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH = 3 THEN
RETURN VitalDECODER8 (DataAlias(2 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH > 3 THEN
RETURN VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataAlias(DMsb)), ResultMap )
& VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataAlias(DMsb)), ResultMap );
ELSE RETURN "X";
END IF;
END;
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( ADataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( ADataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXOR ( Data );
new_schd := VitalXOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( ADataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( ADataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXNOR ( Data );
new_schd := VitalXNOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b;
new_schd := a_schd AND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b;
new_schd := a_schd OR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NAND b;
new_schd := a_schd NAND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NOR b;
new_schd := a_schd NOR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b;
new_schd := VitalXOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b);
new_schd := VitalXNOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
--
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c;
new_schd := a_schd AND b_schd AND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c;
new_schd := a_schd OR b_schd OR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND c;
new_schd := (a_schd AND b_schd) NAND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR c;
new_schd := (a_schd OR b_schd) NOR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c;
new_schd := VitalXOR3 ( ab_schd,ai_schd,
bb_schd,bi_schd,
cb_schd,ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c);
new_schd := VitalXNOR3 ( ab_schd, ai_schd,
bb_schd, bi_schd,
cb_schd, ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c AND d;
new_schd := a_schd AND b_schd AND c_schd AND d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c OR d;
new_schd := a_schd OR b_schd OR c_schd OR d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND (c AND d);
new_schd := (a_schd AND b_schd) NAND (c_schd AND d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR (c OR d);
new_schd := (a_schd OR b_schd) NOR (c_schd OR d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c XOR d;
new_schd := VitalXOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c XOR d);
new_schd := VitalXNOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(To_UX01(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := To_UX01(a); -- convert to forcing strengths
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr01);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr10);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF1( Data, Enable );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01Z) THEN
LOOP
q <= ResultMap(To_UX01Z(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
CASE v2'(To_X01Z(NewValue) & To_X01Z(a)) IS
WHEN "00" => Dly := tpd_a_q(tr10);
WHEN "01" => Dly := tpd_a_q(tr01);
WHEN "0Z" => Dly := tpd_a_q(tr0z);
WHEN "0X" => Dly := tpd_a_q(tr01);
WHEN "10" => Dly := tpd_a_q(tr10);
WHEN "11" => Dly := tpd_a_q(tr01);
WHEN "1Z" => Dly := tpd_a_q(tr1z);
WHEN "1X" => Dly := tpd_a_q(tr10);
WHEN "Z0" => Dly := tpd_a_q(trz0);
WHEN "Z1" => Dly := tpd_a_q(trz1);
WHEN "ZZ" => Dly := 0 ns;
WHEN "ZX" => Dly := Minimum (tpd_a_q(trz1), tpd_a_q(trz0));
WHEN "X0" => Dly := tpd_a_q(tr10);
WHEN "X1" => Dly := tpd_a_q(tr01);
WHEN "XZ" => Dly := Minimum (tpd_a_q(tr0z), tpd_a_q(tr1z));
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
NewValue := To_UX01Z(a);
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(NOT a);
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT a;
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr10);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr01);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF1( Data, Enable );
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType := DefSchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE d1_Schd, d0_Schd : SchedType;
VARIABLE dSel_bSchd, dSel_iSchd : SchedType;
VARIABLE d1_Edge, d0_Edge, dSel_Edge : EdgeType;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_d1_q = VitalZeroDelay01)
AND (tpd_d0_q = VitalZeroDelay01)
AND (tpd_dsel_q = VitalZeroDelay01) ) THEN
LOOP
q <= VitalMUX2 ( d1, d0, dSel, ResultMap );
WAIT ON d1, d0, dSel;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d1_Schd, InitialEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, InitialEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, InitialEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, InitialEdge(dSel), tpd_dsel_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d1_Schd, GetEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, GetEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, GetEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, GetEdge(dSel), tpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX2 ( d1, d0, dSel );
new_schd := VitalMUX2 ( d1_Schd, d0_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON d1, d0, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray4;
VARIABLE Data_Edge : EdgeArray4;
VARIABLE dSel_Edge : EdgeArray2;
VARIABLE dSel_bSchd : SchedArray2;
VARIABLE dSel_iSchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX4 ( Data, dSel );
new_schd := VitalMUX4 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray8;
VARIABLE Data_Edge : EdgeArray8;
VARIABLE dSel_Edge : EdgeArray3;
VARIABLE dSel_bSchd : SchedArray3;
VARIABLE dSel_iSchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX8 ( Data, dSel );
new_schd := VitalMUX8 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE dSel_Edge : EdgeArray(dSel'RANGE);
VARIABLE dSel_bSchd : SchedArray(dSel'RANGE);
VARIABLE dSel_iSchd : SchedArray(dSel'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX ( Data, dSel );
new_schd := VitalMUX ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- Caution: If 'ResultMap' defines other than strength mapping, the
-- delay selection is not defined.
-- ------------------------------------------------------------------------
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : std_logic_vector2;
VARIABLE Glitch_Data : GlitchArray2;
VARIABLE new_schd : SchedArray2;
VARIABLE Dly, Glch : TimeArray2;
VARIABLE Enable_Schd : SchedType := DefSchedType;
VARIABLE Data_BSchd, Data_ISchd : SchedType;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q = VitalZeroDelay01) AND (tpd_data_q = VitalZeroDelay01) THEN
LOOP
q <= VitalDECODER2(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( Data_BSchd, InitialEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, InitialEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( Data_BSchd, GetEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, GetEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER2 ( Data, Enable, ResultMap );
new_schd := VitalDECODER2 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; -- SN
END;
--
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector4;
VARIABLE Glitch_Data : GlitchArray4;
VARIABLE new_schd : SchedArray4;
VARIABLE Dly, Glch : TimeArray4;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray2;
VARIABLE Data_BSchd, Data_ISchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER4(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER4 ( Data, Enable, ResultMap );
new_schd := VitalDECODER4 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector8;
VARIABLE Glitch_Data : GlitchArray8;
VARIABLE new_schd : SchedArray8;
VARIABLE Dly, Glch : TimeArray8;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray3;
VARIABLE Data_BSchd, Data_ISchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER8 ( Data, Enable, ResultMap );
new_schd := VitalDECODER8 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector(q'RANGE);
VARIABLE Glitch_Data : GlitchDataArrayType(q'RANGE);
VARIABLE new_schd : SchedArray(q'RANGE);
VARIABLE Dly, Glch : VitalTimeArray(q'RANGE);
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_BSchd, Data_ISchd : SchedArray(Data'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER ( Data, Enable, ResultMap );
new_schd := VitalDECODER ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE ReturnValue : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO InputSize - 1)
:= To_X01(DataIn);
VARIABLE Index : INTEGER;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalTruthTableType(0 TO (TruthTable'LENGTH(1)-1),
0 TO (TruthTable'LENGTH(2)-1))
:= TruthTable;
BEGIN
-- search through each row of the truth table
IF OutSize > 0 THEN
ColLoop:
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each input element of the entry
FOR j IN 0 TO InputSize LOOP
IF (j = InputSize) THEN -- This entry matches
-- Return the Result
Index := 0;
FOR k IN TruthTable'LENGTH(2) - 1 DOWNTO InputSize LOOP
TruthOutputX01Z ( TableAlias(i,k),
ReturnValue(Index), Err);
EXIT WHEN Err;
Index := Index + 1;
END LOOP;
IF Err THEN
ReturnValue := (OTHERS => 'X');
END IF;
RETURN ReturnValue;
END IF;
IF NOT ValidTruthTableInput(TableAlias(i,j)) THEN
VitalError ( "VitalTruthTable", ErrInpSym,
To_TruthChar(TableAlias(i,j)) );
EXIT ColLoop;
END IF;
EXIT RowLoop WHEN NOT ( TruthTableMatch( DataInAlias(j),
TableAlias(i, j)));
END LOOP RowLoop;
END LOOP ColLoop;
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
END IF;
RETURN ReturnValue;
END VitalTruthTable;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE TempResult : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
IF (OutSize > 0) THEN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
RETURN (TempResult(0));
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
RETURN 'X';
END IF;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
) IS
CONSTANT ResLeng : INTEGER := Result'LENGTH;
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
CONSTANT FinalResLen : INTEGER := Minimum(ActResLen, ResLeng);
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF (ResLeng > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF (ResLeng < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
TempResult(FinalResLen-1 DOWNTO 0) := TempResult(FinalResLen-1 DOWNTO 0);
Result <= TempResult;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
) IS
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
IF (ActResLen > 0) THEN
Result <= TempResult(0);
END IF;
END VitalTruthTable;
-- ------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1)
:= To_X01(DataIn);
VARIABLE PrevDataAlias : std_logic_vector(0 TO PreviousDataIn'LENGTH-1)
:= To_X01(PreviousDataIn);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1)
:= To_X01(Result);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (PreviousDataIn'LENGTH < DataIn'LENGTH) THEN
VitalError ( "VitalStateTable", ErrVctLng, "PreviousDataIn<DataIn");
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSIF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevDataAlias, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias ( Maximum(0, ResLeng - OutSize) TO ResLeng - 1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result := ResultAlias;
PrevDataAlias(0 TO InputSize - 1) := DataInAlias;
PreviousDataIn := PrevDataAlias;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic; -- states
VARIABLE PreviousDataIn : INOUT std_logic_vector; -- previous inputs and states
CONSTANT StateTable : IN VitalStateTableType; -- User's StateTable data
CONSTANT DataIn : IN std_logic_vector -- Inputs
) IS
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
BEGIN
ResultAlias(0) := Result;
VitalStateTable ( StateTable => StateTable,
DataIn => DataIn,
NumStates => 1,
Result => ResultAlias,
PreviousDataIn => PreviousDataIn
);
Result := ResultAlias(0);
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result <= ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
DataInAlias := To_X01(DataIn);
ResultAlias := To_X01(Result);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias(Maximum(0, ResLeng - OutSize) TO ResLeng-1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result <= ResultAlias;
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := StateTable'LENGTH(2) - InputSize-1;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
Result <= 'X';
ELSE
IF ( 1 > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
ResultAlias(0) := To_X01(Result);
DataInAlias := To_X01(DataIn);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, 1, ResultAlias);
Result <= ExpResult(OutSize-1);
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
-- ------------------------------------------------------------------------
-- std_logic resolution primitive
-- ------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector --IR236 4/2/98
) IS
VARIABLE uData : std_ulogic_vector(Data'RANGE);
BEGIN
FOR i IN Data'RANGE LOOP
uData(i) := Data(i);
END LOOP;
q <= resolved(uData);
END;
END VITAL_Primitives;
|
gpl-3.0
|
304eecb348e727d184f55fed82d05cef
| 0.451462 | 4.994576 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd
| 4 | 2,494 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
|
gpl-2.0
|
6b154774cca3d5788761b0e92a005ef1
| 0.580593 | 3.454294 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_01.vhd
| 4 | 2,307 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
function resolve_bits ( bits : bit_vector ) return bit is
variable result : bit := '0';
begin
for index in bits'range loop
result := result or bits(index);
exit when result = '1';
end loop;
return result;
end function resolve_bits;
signal write_en : resolve_bits bit bus;
-- . . .
-- not in book
constant Tpd : delay_length := 2 ns;
signal clock, hold_req : bit := '0';
-- end not in book
begin
CPU : process is
-- . . .
begin
write_en <= '0' after Tpd;
-- . . .
loop
wait until clock = '1';
if hold_req = '1' then
write_en <= null after Tpd;
wait on clock until clock = '1' and hold_req = '0';
write_en <= '0' after Tpd;
end if;
-- . . .
end loop;
end process CPU;
-- . . .
-- not in book
clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0';
stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns;
process is
begin
write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns;
wait;
end process;
-- end not in book
end architecture top_level;
|
gpl-2.0
|
c03003cdc87bcc1a9d3472b40c86dbc0
| 0.592111 | 3.775777 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue376/util.vhdl
| 1 | 4,635 |
library ieee ;
use ieee.std_logic_1164.all ;
library std;
use std.textio.all;
-- Utility package
package util is
procedure nop( signal clock : in std_logic ; count : in natural ) ;
end package ;
package body util is
procedure nop( signal clock : in std_logic ; count : in natural ) is
begin
for i in 1 to count loop
wait until rising_edge( clock ) ;
end loop ;
end procedure ;
end package body ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity data_saver is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data : std_logic_vector(DATA_WIDTH-1 downto 0);
data_valid : std_logic
);
end entity;
architecture arch of data_saver is
begin
handler : process
FILE fp : text;
variable line_data : line;
begin
--
wait until falling_edge(reset);
file_open(fp, FILENAME, WRITE_MODE);
while (reset = '0') loop
wait until rising_edge(data_valid);
write(line_data, data);
writeline(fp,line_data);
end loop;
file_close(fp);
end process;
end architecture;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity signed_saver is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data : signed(DATA_WIDTH-1 downto 0);
data_valid : std_logic
);
end entity;
architecture arch of signed_saver is
begin
handler : process
FILE fp : text;
variable line_data : line;
begin
--
wait until falling_edge(reset);
file_open(fp, FILENAME, WRITE_MODE);
while (reset = '0') loop
wait until rising_edge(clock);
if data_valid = '1' then
write(line_data, (to_integer(data)));
writeline(fp,line_data);
end if;
end loop;
file_close(fp);
end process;
end architecture;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity data_reader is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data_request : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_valid : out std_logic
);
end entity;
architecture arch of data_reader is
type character_array_t is array (natural range <>) of character;
begin
handler : process
variable line_data : line;
variable tmp : integer;
variable c : character;--_array_t(0 to 3);
type bin_t is file of character ;
file fp : bin_t ;
variable fs : file_open_status ;
begin
--
data <= (others => '0');
data_valid <= '0';
wait until falling_edge(reset);
file_open(fs, fp, FILENAME, READ_MODE);
if( fs /= OPEN_OK ) then
report "File open issues" severity failure ;
end if ;
--readline(fp,line_data);
while (reset = '0') loop
wait until rising_edge(clock);
data_valid <= '0';
if data_request = '1' then
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(7 downto 0) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(15 downto 8) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(23 downto 16) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(31 downto 24) <= std_logic_vector(to_unsigned(tmp,8));
data_valid <= '1';
wait until rising_edge(clock);
data_valid <= '0';
end if;
end loop;
file_close(fp);
end process;
end architecture;
|
gpl-2.0
|
d91f7955063a8c230c09ed042a137c5b
| 0.519094 | 4.019948 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd
| 4 | 1,653 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_23a is
end entity inline_23a;
architecture test of inline_23a is
signal digital_level : integer;
constant num_levels : integer := 63;
constant max_voltage : real := 10.0;
begin
block_1 : block is
quantity analog_voltage : real;
begin
-- code from book
analog_voltage == real(digital_level) / real(num_levels) * max_voltage;
-- end code from book
end block block_1;
block_2 : block is
signal real_digital_level : real;
quantity analog_voltage : real;
begin
-- code from book
real_digital_level <= real(digital_level);
analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage;
-- end code from book
end block block_2;
end architecture test;
|
gpl-2.0
|
1732ea763abdb1e766a5ffb4211842b2
| 0.69389 | 3.954545 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/ticket24/psl.vhdl
| 2 | 684 |
entity psl is
end;
architecture behav of psl is
signal a, b, c : bit;
signal clk : bit;
subtype wf_type is bit_vector (0 to 7);
constant wave_a : wf_type := "10010100";
constant wave_b : wf_type := "01001010";
constant wave_c : wf_type := "00100101";
begin
process
begin
for i in wf_type'range loop
clk <= '0';
wait for 1 ns;
a <= wave_a (i);
b <= wave_b (i);
c <= wave_c (i);
clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;
-- psl default clock is (clk'event and clk = '1');
-- psl a1: assert always a |=> b;
-- psl a2: assert always a -> eventually! c;
-- psl c1: cover {a;b;c};
end behav;
|
gpl-2.0
|
20328369c67cb49fc45b9152df2aff71
| 0.555556 | 3.095023 | false | false | false | false |
lfmunoz/vhdl
|
testbench_template.vhd
| 1 | 11,573 |
-------------------------------------------------------------------------------------
-- FILE NAME : testbench_template.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - testbench_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- This entity is template for writing test benches
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_xcvr is
end tb_xcvr;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_xcvr is
-------------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------------
component generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end component generic_host_emu;
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus016 is array(natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_clkin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_cmd : std_logic;
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal host_data_in : std_logic_vector(63 downto 0);
signal host_data_out : std_logic_vector(63 downto 0);
signal host_val_in : std_logic;
signal host_val_out : std_logic;
signal host_stop_out : std_logic;
signal host_stop_in : std_logic;
--stimulus
signal samples16bit : bus016(3 downto 0) := (others=>(others=>'0'));
signal base_cnt : std_logic_vector(15 downto 0);
signal send_data : std_logic_vector(63 downto 0);
signal sim_count : std_logic_vector(31 downto 0) := (others=>'0');
signal we : std_logic;
signal data_rst : std_logic := '1';
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_100_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_200_MHZ / 2;
clk100 <= not clk100 after CLK_100_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rstn <= '1' after CLK_125_MHZ * 10;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------------------------------
-- Host Interface
-----------------------------------------------------------------------------------
inst0_generic_host: generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'),-- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'),-- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => host_stop_in, -- out std_logic;
in_data_in_dval => host_val_in, -- in std_logic;
in_data_in_data => host_data_in, -- in std_logic_vector(63 downto 0);
out_data_out_stop => host_stop_out,-- in std_logic;
out_data_out_dval => host_val_out, -- out std_logic;
out_data_out_data => host_data_out -- out std_logic_vector(63 downto 0)
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk200, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
sip_capture_x4_0 : entity xil_defaultlib.sip_capture_x4
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"0001FFF",
private_start_addr_gen => x"0000100",
private_stop_addr_gen => x"00001FF"
)
port map (
cmdclk_in_cmdclk => clk_cmd,
cmd_in_cmdin => in_cmd,
cmd_in_cmdin_val => in_cmd_val,
cmd_out_cmdout => out_cmd,
cmd_out_cmdout_val => out_cmd_val,
clk_clkin => clk_clkin,
rst_rstin => rst_rstin,
in0_in_stop => open,
in0_in_dval => valid,
in0_in_data => data,
in1_in_stop => open,
in1_in_dval => valid,
in1_in_data => data,
in2_in_stop => open,
in2_in_dval => valid,
in2_in_data => data,
in3_in_stop => open,
in3_in_dval => valid,
in3_in_data => data,
out0_out_stop => '0',
out0_out_dval => open,
out0_out_data => open,
out1_out_stop => '0',
out1_out_dval => open,
out1_out_data => open,
out2_out_stop => '0',
out2_out_dval => open,
out2_out_data => open,
out3_out_stop => '0',
out3_out_dval => open,
out3_out_data => open
);
-----------------------------------------------------------------------------------
-- Stimulus
-----------------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
sim_count <= sim_count + 1;
if sim_count = 0 then -- reset data generation
data_rst <= '1';
we <= '0';
elsif sim_count = 20 then -- enable data generation and enable writing
report "Writing data to memory";
data_rst <= '0';
we <= '1';
elsif sim_count = 100 then -- reset data generation and disable writing
data_rst <= '1';
we <= '0';
elsif sim_count = 102 then -- enable data generation and disable writing
report "Reading data from memory";
data_rst <= '0';
we <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Data generation
-----------------------------------------------------------------------------------
process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
base_cnt <= (others =>'0');
else
base_cnt <= base_cnt + 4;
end if;
end if;
end process;
samples16bit(0) <= base_cnt + 0;
samples16bit(1) <= base_cnt + 1;
samples16bit(2) <= base_cnt + 2;
samples16bit(3) <= base_cnt + 3;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
92219af8185f1e9fb3a1ca7893dbac17
| 0.419079 | 4.063553 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue578/generics.vhdl
| 1 | 14,333 |
library ieee;
use ieee.std_logic_1164.all;
--use ieee.math_real.all;
use ieee.numeric_std.all;
package generics is
constant synthesis : boolean := true
-- synthesis translate_off
and false
-- synthesis translate_on
;
function sim_cond(cond : boolean) return boolean;
function istr(v : integer) return string;
function as_std_logic(v : boolean) return std_logic;
function rot_l(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function rot_r(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function sh_l(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function sh_r(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function log2_int(v : integer) return integer;
function log2(v : integer) return integer;
function is_log2(v : integer) return boolean;
function binary_flatten(v : std_logic_vector; n : integer) return std_logic_vector;
function min(a : integer; b : integer) return integer;
function max(a : integer; b : integer) return integer;
function find_first_bit(v : std_logic_vector) return integer;
function mask_first_bit(v : std_logic_vector) return std_logic_vector;
function next_multiple(v : integer; m : integer) return integer;
function reverse_vector(inp : std_logic_vector) return std_logic_vector;
function reorder_vector(inp : std_logic_vector) return std_logic_vector;
function htonl(inp : std_logic_vector) return std_logic_vector;
function ntohl(inp : std_logic_vector) return std_logic_vector;
function vector_all_valid(i : std_logic_vector) return boolean;
function to_integer(i : std_logic) return integer;
function integer_reverse_bits(i : integer; bits : integer) return integer;
function dbg_collapse16(d : in std_logic_vector) return std_logic_vector;
function bram_we_width(aw : integer) return integer;
function chr(sl: std_logic) return character;
function chr(i : integer) return character;
function chr(b : boolean) return character;
function vector_to_string(v : std_logic_vector) return string;
function vector_to_hex_string(v : std_logic_vector) return string;
function to_std_logic_vector(v : integer; size : integer) return std_logic_vector;
function popcnt(v : std_logic_vector) return integer;
function popcnt(v : integer; bits : integer) return integer;
function popcnt_x(v : std_logic_vector) return integer;
function maxlen_lfsr_advance(reg : std_logic_vector) return std_logic_vector;
function random_vector(len : integer; seed : integer) return std_logic_vector;
function random(max : integer; seed : integer) return integer;
function reverse_any_vector(a : in std_logic_vector) return std_logic_vector;
function sel(cond : boolean; if_true : integer; if_false : integer) return integer;
function sel(cond : boolean; if_true : std_logic_vector; if_false : std_logic_vector) return std_logic_vector;
function sel(cond : boolean; if_true : std_logic; if_false : std_logic) return std_logic;
function sel(cond : boolean; if_true : string; if_false : string) return string;
procedure clkp(signal clk : in std_logic; n : in integer);
function vector_mux(sel : std_logic_vector; i1 : std_logic_vector; i2 : std_logic_vector) return std_logic_vector;
function div_ceil(a : integer; b : integer) return integer;
function int_strlen(vv : integer) return natural;
end generics;
package body generics is
function chr(b : boolean) return character is
begin
if b then
return 't';
end if;
return 'f';
end function;
function chr(i : integer) return character is
variable s : string(1 to 10) := "0123456789";
begin
if i < 10 then
return s(i + 1);
else
return 'X';
end if;
end function;
function istr(v : integer) return string is
begin
return integer'image(v);
end function;
function as_std_logic(v : boolean) return std_logic is
begin
if v then return '1'; end if;
return '0';
end function;
function int_strlen(vv : integer) return natural is
variable ret : natural := 0;
variable v : integer := vv;
begin
if v < 0 then
ret := ret + 1;
v := -v;
end if;
while v >= 10 loop
v := v / 10;
ret := ret + 1;
end loop;
return ret + 1;
end function;
function rot_l(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(rotate_left(unsigned(v), n));
end function;
function rot_r(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(rotate_right(unsigned(v), n));
end function;
function sh_l(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(shift_left(unsigned(v), n));
end function;
function sh_r(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(shift_right(unsigned(v), n));
end function;
function log2(v : integer) return integer is
begin
return log2_int(v);
end function;
function is_log2(v : integer) return boolean is
begin
return 2 ** log2(v) = v;
end function;
function to_integer(i : std_logic) return integer is
begin
if i = '1' then
return 1;
elsif i = '0' then
return 0;
else
return -1;
end if;
end function;
function dbg_collapse16(d : in std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(0 to 15);
variable oi : integer;
begin
oi := 0;
ret := (others => '0');
for i in d'range loop
ret(oi) := ret(oi) xor d(i);
if oi < 15 then
oi := oi + 1;
else
oi := 0;
end if;
end loop;
return ret;
end function;
function random(max : integer; seed : integer) return integer is
begin
if max = 0 then return 0; end if;
return to_integer(unsigned(random_vector(log2_int(max) + 1, seed))) mod max;
end function;
function sel(cond : boolean; if_true : std_logic; if_false : std_logic) return std_logic is
begin
if cond then
return if_true;
end if;
return if_false;
end function;
function sel(cond : boolean; if_true : string; if_false : string) return string is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function;
function div_ceil(a : integer; b : integer) return integer is
begin
return a / b + sel(a mod b /= 0, 1, 0);
end function;
function sim_cond(cond : boolean) return boolean is
begin
if synthesis then
return true;
else
return cond;
end if;
end function;
function integer_reverse_bits(i : integer; bits : integer) return integer is
variable m : std_logic_vector(0 to bits - 1);
begin
m := std_logic_vector(to_unsigned(i, bits));
m := reverse_any_vector(m);
return to_integer(unsigned(m));
end function;
function vector_mux(sel : std_logic_vector; i1 : std_logic_vector; i2 : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(0 to sel'length - 1);
begin
for i in 0 to sel'length - 1 loop
if sel(sel'left + i) = '1' then
ret(i) := i1(i1'left + i);
else
ret(i) := i2(i2'left + i);
end if;
end loop;
return ret;
end function;
procedure clkp(signal clk : in std_logic; n : in integer) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
end loop;
wait for 1 ps;
end procedure;
function random_vector(len : integer; seed : integer) return std_logic_vector is
variable lfsr : std_logic_vector(0 to 7) := std_logic_vector(to_unsigned(seed, 8));
variable ret : std_logic_vector(0 to len - 1);
begin
for i in 0 to len / 8 loop
lfsr := maxlen_lfsr_advance(lfsr);
lfsr := maxlen_lfsr_advance(lfsr);
lfsr := maxlen_lfsr_advance(lfsr);
lfsr := maxlen_lfsr_advance(lfsr);
ret(i * 8 to min(ret'length, (i + 1) * 8) - 1) := lfsr(0 to min(8, ret'length - i * 8) - 1);
end loop;
return ret;
end function;
function sel(cond : boolean; if_true : integer; if_false : integer) return integer is
begin
if cond then return if_true; else return if_false; end if;
end function;
function sel(cond : boolean; if_true : std_logic_vector; if_false : std_logic_vector) return std_logic_vector is
begin
if cond then return if_true; else return if_false; end if;
end function;
function popcnt(v : integer; bits : integer) return integer is
begin
return popcnt(std_logic_vector(to_unsigned(v, bits)));
end function;
function reverse_any_vector (a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'range);
alias aa: std_logic_vector(a'reverse_range) is a;
begin
for i in aa'range loop
result(i) := aa(i);
end loop;
return result;
end;
function maxlen_lfsr_advance(reg : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(reg'range);
begin
if ret'left > ret'right then
ret(reg'left downto 1) := reg(reg'left - 1 downto 0);
else
ret(1 to reg'right) := reg(0 to reg'right - 1);
end if;
if reg'length = 3 then
ret(0) := reg(2) xnor reg(1);
elsif reg'length = 4 then
ret(0) := reg(3) xnor reg(2);
elsif reg'length = 8 then
ret(0) := reg(7) xnor reg(5) xnor reg(4) xnor reg(3);
elsif reg'length = 57 then
ret(0) := reg(56) xnor reg(49);
else
assert false report "no matching shift register configured for length " & integer'image(reg'length) severity failure;
end if;
return ret;
end function;
function vector_all_valid(i : std_logic_vector) return boolean is
begin
for j in i'range loop
if i(j) /= '1' and i(j) /= '0' then
return false;
end if;
end loop;
return true;
end function;
function popcnt_x(v : std_logic_vector) return integer is
variable ret : integer;
begin
ret := 0;
for i in v'range loop
if v(i) = 'X' then
ret := ret + 1;
end if;
end loop;
return ret;
end function;
function popcnt(v : std_logic_vector) return integer is
variable res : integer;
begin
res := 0;
for i in v'range loop
if v(i) = '1' then
res := res + 1;
end if;
end loop;
return res;
end function;
function to_std_logic_vector(v : integer; size : integer) return std_logic_vector is
variable ret : std_logic_vector(size - 1 downto 0);
variable tmp : unsigned(size - 1 downto 0);
begin
tmp := to_unsigned(v, size);
return std_logic_vector(tmp);
end function;
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function vector_to_hex_string(v : std_logic_vector) return string is
variable ret : string(1 to (v'length + 3) / 4);
type hchar_t is array(0 to 15) of character;
constant hchar : hchar_t := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f');
variable off : integer := v'length mod 4;
begin
if off /= 0 then
ret(1) := hchar(to_integer(unsigned(v(0 to off - 1))));
end if;
for i in 0 to v'length / 4 - 1 loop
ret(i + sel(off = 0, 1, 2)) := hchar(to_integer(unsigned(v(off + i * 4 to off + i * 4 + 3))));
end loop;
return ret;
end function;
function vector_to_string(v : std_logic_vector) return string is
variable ret : string(1 to v'length);
variable at : integer;
begin
at := 1;
for i in v'range loop
ret(at) := chr(v(i));
at := at + 1;
end loop;
return ret;
-- for i in 0 to v'length - 1 loop
-- ret(i + 1) := chr(v(i));
-- end loop;
-- return ret;
end function;
function bram_we_width(aw : integer) return integer is
begin
if aw > 16 then
return 4;
elsif aw > 8 then
return 2;
else
return 1;
end if;
end function;
function htonl(inp : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(inp'range);
begin
ret(31 downto 24) := inp(7 downto 0);
ret(23 downto 16) := inp(15 downto 8);
ret(15 downto 8) := inp(23 downto 16);
ret(7 downto 0) := inp(31 downto 24);
return ret;
end function;
function ntohl(inp : std_logic_vector) return std_logic_vector is
begin
return htonl(inp);
end function;
function reorder_vector(inp : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(inp'reverse_range);
begin
return inp;
if inp'left < inp'right then
for i in inp'range loop
ret(inp'right - i) := inp(i);
end loop;
elsif inp'left > inp'right then
for i in inp'range loop
ret(inp'left - i) := inp(i);
end loop;
else
ret(inp'left) := inp(inp'left);
end if;
return ret;
end function;
function reverse_vector(inp : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(inp'reverse_range);
begin
for i in inp'range loop
ret(i) := inp(i);
end loop;
return ret;
end function;
function next_multiple(v : integer; m : integer) return integer is
begin
if v mod m = 0 then
return v;
else
return v + m - v mod m;
end if;
end function;
function mask_first_bit(v : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(v'range) := (others => '0');
begin
for i in 0 to v'length - 1 loop
if v(i) = '1' then
ret(i) := '1';
return ret;
end if;
end loop;
return ret;
end function;
function find_first_bit(v : std_logic_vector) return integer is
begin
for i in 0 to v'length - 1 loop
if v(i) = '1' then return i; end if;
end loop;
return 0;
end function;
function min(a : integer; b : integer) return integer is
begin
if a < b then
return a;
end if;
return b;
end function;
function max(a : integer; b : integer) return integer is
begin
if a > b then
return a;
end if;
return b;
end function;
function binary_flatten(v : std_logic_vector; n : integer) return std_logic_vector is
variable res : std_logic_vector(n - 1 downto 0) := (others => '0');
begin
for i in 0 to n - 1 loop
if unsigned(v) = to_unsigned(i, v'length) then
res(i) := '1';
return res;
end if;
end loop;
return res;
end function;
function log2_int(v : integer) return integer is
variable vv, ret : integer;
begin
vv := v;
ret := 0;
while vv > 1 loop
ret := ret + 1;
vv := vv / 2;
end loop;
if 2 ** ret = v then
return ret;
else
return ret + 1;
end if;
--return integer(ceil(log2(real(v))));
end function;
end generics;
|
gpl-2.0
|
6408f3d75ddd9efb97b09d6133b4daad
| 0.662248 | 2.89907 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/exit01/tb_exit01.vhdl
| 1 | 806 |
entity tb_exit01 is
end tb_exit01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_exit01 is
signal v : std_logic_vector(3 downto 0);
signal r : integer;
begin
dut: entity work.exit01
port map (val => v, res => r);
process
begin
v <= "0001";
wait for 1 ns;
assert r = 0 severity failure;
v <= "0010";
wait for 1 ns;
assert r = 1 severity failure;
v <= "0100";
wait for 1 ns;
assert r = 2 severity failure;
v <= "1000";
wait for 1 ns;
assert r = 3 severity failure;
v <= "0000";
wait for 1 ns;
assert r = 4 severity failure;
v <= "0110";
wait for 1 ns;
assert r = 1 severity failure;
v <= "1001";
wait for 1 ns;
assert r = 0 severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
740b7734f4903bc5afa0d5a01b346a28
| 0.584367 | 3.386555 | false | false | false | false |
gralco/FPGA-Elevator-Project
|
MyHDL/elevator.vhd
| 1 | 3,389 |
-- File: elevator.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sun Jun 14 22:11:56 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_081.all;
entity elevator is
port (
clk: in std_logic;
reset: in std_logic;
en: in std_logic;
F: in unsigned(3 downto 0);
D: inout unsigned(3 downto 0);
Q: inout unsigned(3 downto 0);
A: inout std_logic;
B: inout std_logic;
A_latch: inout std_logic;
B_latch: inout std_logic;
LED: out unsigned(3 downto 0)
);
end entity elevator;
architecture MyHDL of elevator is
begin
ELEVATOR_ENCODER: process (en, F) is
begin
if (bool(F) and bool(en)) then
A <= stdl(bool(F(3)) or (bool(F(1)) and (not bool(F(2)))));
B <= stdl(bool(F(2)) or bool(F(3)));
end if;
end process ELEVATOR_ENCODER;
ELEVATOR_LATCH: process (reset, A, B, en, F) is
begin
if bool(reset) then
A_latch <= '0';
B_latch <= '0';
elsif (bool(F) and bool(en)) then
A_latch <= A;
B_latch <= B;
end if;
end process ELEVATOR_LATCH;
D <= unsigned'((((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(Q(0))) and bool(B_latch) and bool(A_latch)) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and (not bool(Q(0))) and (not bool(B_latch)) and (not bool(A_latch))) or (bool(Q(3)) and bool(Q(2)) and bool(Q(1)) and (not bool(Q(0)))) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(Q(0)) and (not bool(B_latch)))) & (((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(Q(0)) and (not bool(B_latch)) and (not bool(A_latch))) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and bool(B_latch) and bool(A_latch)) or (bool(Q(3)) and bool(Q(2)) and (not bool(Q(1))) and bool(Q(0))) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(Q(0))) and bool(B_latch))) & (((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(Q(0)) and (not bool(B_latch))) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(0)) and bool(B_latch)) or (bool(Q(2)) and (not bool(Q(1))) and bool(Q(0))) or ((not bool(Q(3))) and bool(Q(1)) and (not bool(Q(0))) and bool(B_latch)) or ((not bool(Q(3))) and bool(Q(2)) and bool(Q(1)) and (not bool(Q(0))))) & (((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and (not bool(Q(0))) and (not bool(B_latch)) and (not bool(A_latch))) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(B_latch)) and bool(A_latch)) or ((not bool(Q(3))) and (not bool(Q(2))) and bool(Q(1)) and bool(B_latch) and bool(A_latch)) or ((not bool(Q(3))) and (not bool(Q(2))) and (not bool(Q(1))) and (not bool(Q(0))) and bool(B_latch)) or (bool(Q(3)) and bool(Q(1)) and (not bool(Q(0)))) or ((not bool(Q(3))) and bool(Q(2)) and bool(Q(1)) and (not bool(Q(0)))) or (bool(Q(1)) and (not bool(Q(0))) and bool(A_latch))));
ELEVATOR_DFF: process (clk, reset) is
begin
if (reset = '1') then
Q <= to_unsigned(0, 4);
elsif rising_edge(clk) then
if bool(en) then
Q <= D;
end if;
end if;
end process ELEVATOR_DFF;
LED <= unsigned'((bool(Q(1)) and bool(Q(0))) & (bool(Q(1)) and (not bool(Q(0)))) & ((not bool(Q(1))) and bool(Q(0))) & ((not bool(Q(1))) and (not bool(Q(0)))));
end architecture MyHDL;
|
gpl-2.0
|
0d1733ad1fcfa354e080aec1239a2904
| 0.576276 | 2.627132 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd
| 4 | 1,461 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
gpl-2.0
|
ca34ba9ad9831f43fd78cacebc9a36d6
| 0.654346 | 4.210375 | false | false | false | false |
nickg/nvc
|
test/regress/func18.vhd
| 1 | 771 |
entity func18 is
end entity;
architecture test of func18 is
function get_array(n : in integer) return bit_vector is
-- The state struct for this function cannot be allocated on the stack
variable result : bit_vector(3 downto 0);
function get_xor return bit_vector is
begin
case n is
when 1 => return X"1";
when 2 => return X"2";
when others => return X"f";
end case;
end function;
begin
result := result xor get_xor;
return result;
end function;
begin
p1: process is
variable n : integer := 1;
begin
wait for 1 ns;
assert get_array(n) = X"1";
wait;
end process;
end architecture;
|
gpl-3.0
|
2d93b1add41486474e7d573a4a113757
| 0.553826 | 4.307263 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug0110/tb.vhdl
| 1 | 593 |
package pkg is
type my_rec is record
adr : bit_vector (7 downto 0);
end record;
end pkg;
use work.pkg.all;
entity ent is
port (v : out my_rec;
b : in bit);
end ent;
architecture behav of ent is
begin
v.adr <= (others => b);
end behav;
entity top is
end top;
use work.pkg.all;
architecture behav of top is
signal s : bit_vector (7 downto 0);
signal b : bit;
begin
dut : entity work.ent
port map (
-- ERROR: missing 1 downto 0!
v.adr (3 downto 2) => s (3 downto 2),
v.adr (7 downto 4) => s (7 downto 4),
b => b);
b <= '0';
end behav;
|
gpl-2.0
|
b1092dc5c82a3d560c1233e2247ba830
| 0.591906 | 2.994949 | false | false | false | false |
nickg/nvc
|
test/regress/attr13.vhd
| 1 | 6,913 |
--
-- Example from LRM 00 page 197
--
package P is -- P'PATH_NAME = ":lib:p:"
procedure Proc (F: inout INTEGER); -- P'INSTANCE_NAME = ":lib:p:"
constant C: INTEGER := 42; -- Proc'PATH_NAME = ":lib:p:proc"
end package P; -- Proc'INSTANCE_NAME = ":lib:p:proc"
package body P is -- C'PATH_NAME = ":lib:p:c"
procedure Proc (F: inout INTEGER) is -- C'INSTANCE_NAME = ":lib:p:c"
variable x: INTEGER; -- x'PATH_NAME = ":lib:p:proc:x"
begin -- x'INSTANCE_NAME = ":lib:p:proc:x"
assert P'PATH_NAME = ":lib:p:";
assert P'INSTANCE_NAME = ":lib:p:";
assert Proc'PATH_NAME = ":lib:p:proc:";
assert Proc'INSTANCE_NAME = ":lib:p:proc:";
assert C'PATH_NAME = ":lib:p:c";
assert C'INSTANCE_NAME = ":lib:p:c";
assert x'PATH_NAME = ":lib:p:proc:x" report x'path_name;
assert x'INSTANCE_NAME = ":lib:p:proc:x";
end;
end;
library lib;
use Lib.P.all;
entity E is -- E is the top-level design entity:
-- E'PATH_NAME = ":e:"
-- E'INSTANCE_NAME = ":e(a):"
generic (G: INTEGER); -- G'PATH_NAME = ":e:g"
-- G'INSTANCE_NAME = ":e(a):g"
port (P: in INTEGER); -- P'PATH_NAME = ":e:p"
-- P'INSTANCE_NAME = ":e(a):p"
begin
assert E'PATH_NAME = ":top:e:";
end entity E;
architecture A of E is
signal S: BIT_VECTOR (1 to G); -- S'PATH_NAME = ":e:s"
-- S'INSTANCE_NAME = ":e(a):s"
procedure Proc1 (signal sp1: NATURAL; C: out INTEGER) is
-- Proc1'PATH_NAME = ":e:proc1:"
-- Proc1'INSTANCE_NAME =:e(a):proc1:"
-- C'PATH_NAME = ":e:proc1:c"
-- C'INSTANCE_NAME = ":e(a):proc1:c"
variable max: DELAY_LENGTH; -- max'PATH_NAME = ":e:proc1:max"
-- max'INSTANCE_NAME = ":e(a):proc1:max"
begin
max := sp1 * ns;
wait on sp1 for max;
c := sp1;
end procedure Proc1;
begin
p1: process -- T'PATH_NAME = ":e:p1:t"
variable T: INTEGER := 12; -- T'INSTANCE_NAME = ":e(a):p1:t"
begin
assert lib.P'PATH_NAME = ":lib:p:";
assert lib.P'INSTANCE_NAME = ":lib:p:";
proc(t);
assert s'path_name = ":top:e:s";
assert s'instance_name = ":top(top):e@e(a):s";
assert t'path_name = ":top:e:p1:t";
assert t'instance_name = ":top(top):e@e(a):p1:t";
wait;
end process p1;
process
variable T: INTEGER := 12; -- T'PATH_NAME = ":e::t"
begin -- T'INSTANCE_NAME = ":e(a)::t"
assert t'path_name = ":top:e::t" report t'path_name;
assert t'instance_name = ":top(top):e@e(a)::t";
wait;
end process;
end architecture;
entity Bottom is
generic (GBottom : INTEGER);
port (PBottom : INTEGER);
end entity Bottom;
architecture BottomArch of Bottom is
signal SBottom : INTEGER;
begin
ProcessBottom : process
variable V : INTEGER;
begin
if GBottom = 4 then
assert V'Simple_Name = "v"
and V'Path_Name = ":top:b1:b2:g1(4):b3:l1:processbottom:v"
and V'Instance_Name =
":top(top):b1:b2:g1(4):b3:l1@bottom(bottomarch):processbottom:v";
assert GBottom'Simple_Name = "gbottom"
and GBottom'Path_Name = ":top:b1:b2:g1(4):b3:l1:gbottom"
and GBottom'Instance_Name =
":top(top):b1:b2:g1(4):b3:l1@bottom(bottomarch):gbottom";
elsif GBottom = -1 then
assert V'Simple_Name = "v"
and V'Path_Name = ":top:l2:processbottom:v"
and V'Instance_Name =
":top(top):l2@bottom(bottomarch):processbottom:v";
assert GBottom'Simple_Name = "gbottom"
and GBottom'Path_Name = ":top:l2:gbottom"
and GBottom'Instance_Name =
":top(top):l2@bottom(bottomarch):gbottom";
end if;
wait;
end process ProcessBottom;
end architecture BottomArch;
entity top is end entity;
architecture top of top is
component BComp is
generic (GComp : INTEGER);
port (PComp : INTEGER);
end component BComp;
signal S : INTEGER;
begin
B1 : block
signal S : INTEGER;
begin
B2 : block
signal S : INTEGER;
begin
G1 : for I in 1 to 10 generate
B3 : block
signal S : INTEGER;
for L1 : BComp use entity Work.Bottom(BottomArch)
generic map (GBottom => GComp)
port map (PBottom => PComp);
begin
L1 : BComp generic map (I) port map (S);
P1 : process
variable V : INTEGER;
begin
if I = 7 then
assert V'Simple_Name = "v"
and V'Path_Name = ":top:b1:b2:g1(7):b3:p1:v"
and V'Instance_Name=":top(top):b1:b2:g1(7):b3:p1:v";
assert P1'Simple_Name = "p1"
and P1'Path_Name = ":top:b1:b2:g1(7):b3:p1:"
and P1'Instance_Name = ":top(top):b1:b2:g1(7):b3:p1:";
assert S'Simple_Name = "s"
and S'Path_Name = ":top:b1:b2:g1(7):b3:s"
and S'Instance_Name = ":top(top):b1:b2:g1(7):b3:s";
assert B1.S'Simple_Name = "s"
and B1.S'Path_Name = ":top:b1:s"
and B1.S'Instance_Name = ":top(top):b1:s";
end if;
wait;
end process P1;
end block B3;
end generate;
end block B2;
end block B1;
L2 : BComp generic map (-1) port map (S);
E: entity work.E(A) generic map (1) port map (2);
end architecture top;
configuration attr13 of Top is
for Top
for L2 : BComp
use entity Work.Bottom(BottomArch)
generic map (GBottom => GComp)
port map (PBottom => PComp);
end for;
end for;
end configuration attr13;
|
gpl-3.0
|
ea71b0af0c284b7da7e66f96aaf0005f
| 0.445827 | 3.688901 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_doHist_0_1/synth/design_1_doHist_0_1.vhd
| 1 | 12,433 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHist:1.0
-- IP Revision: 1606202043
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHist_0_1 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_doHist_0_1;
ARCHITECTURE design_1_doHist_0_1_arch OF design_1_doHist_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHist_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT doHist IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT doHist;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_doHist_0_1_arch: ARCHITECTURE IS "doHist,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_doHist_0_1_arch : ARCHITECTURE IS "design_1_doHist_0_1,doHist,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF histo_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF histo_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF histo_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF histo_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF histo_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF histo_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF histo_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DOUT";
BEGIN
U0 : doHist
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 4,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
histo_Clk_A => histo_Clk_A,
histo_Rst_A => histo_Rst_A,
histo_EN_A => histo_EN_A,
histo_WEN_A => histo_WEN_A,
histo_Addr_A => histo_Addr_A,
histo_Din_A => histo_Din_A,
histo_Dout_A => histo_Dout_A
);
END design_1_doHist_0_1_arch;
|
gpl-3.0
|
a9dd07643d30620feb008d9cefac0345
| 0.704898 | 3.23355 | false | false | false | false |
nickg/nvc
|
test/simp/issue309.vhd
| 2 | 1,226 |
-- test_ng.vhd
entity issue309 is
end issue309;
architecture MODEL of issue309 is
function check return boolean is
constant org_data : bit_vector(31 downto 0) := "01110110010101000011001000010000";
variable val_data : bit_vector(31 downto 0);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(31 downto 4) := val_data(27 downto 0);
val_data( 3 downto 0) := org_data(i*4+3 downto i*4);
end loop;
return (val_data = org_data);
end function;
function check2 return boolean is
constant org_data : bit_vector(0 to 31) := "01110110010101000011001000010000";
variable val_data : bit_vector(0 to 31);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(4 to 31) := val_data(0 to 27);
val_data(0 to 3) := org_data(i*4 to i*4+3);
end loop;
return (val_data = org_data);
end function;
constant c : boolean := check;
constant d : boolean := check2;
begin
g1: if c generate
assert true report "c";
end generate;
g2: if d generate
assert true report "d";
end generate;
end MODEL;
|
gpl-3.0
|
b1306129ff99c6850cc1ff20a0703a48
| 0.58075 | 3.627219 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd
| 4 | 3,137 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_16a_types is
subtype ILLUMINANCE is REAL tolerance "DEFAULT_ILLUMINANCE";
subtype OPTIC_FLUX is REAL tolerance "DEFAULT_OPTIC_FLUX";
nature RADIANT is
ILLUMINANCE across
OPTIC_FLUX through
RADIANT_REF reference;
subtype VOLTAGE is REAL tolerance "DEFAULT_VOLTAGE";
subtype CURRENT is REAL tolerance "DEFAULT_CURRENT";
nature ELECTRICAL is
VOLTAGE across
CURRENT through
ELECTRICAL_REF reference;
-- code from book
type illuminance_vector is array ( natural range <> ) of illuminance;
nature electrical_vector is array ( natural range <> ) of electrical;
-- end code from book
end package inline_16a_types;
use work.inline_16a_types.all;
-- code from book
entity seven_segment_led is
port ( terminal segment_anodes : electrical_vector ( 1 to 7 );
terminal common_cathode : electrical;
quantity segment_illuminances : out illuminance_vector ( 1 to 7 ) );
end entity seven_segment_led;
-- end code from book
architecture basic_optics of seven_segment_led is
begin
end architecture basic_optics;
use work.inline_16a_types.all;
entity inline_16a is
end entity inline_16a;
architecture test of inline_16a is
-- code from book
terminal hour_anode_2, hour_anode_3 : electrical;
terminal anodes_unused : electrical_vector(1 to 5);
terminal hour_display_source_2, hour_display_source_3 : radiant;
quantity hour_illuminance_2 across hour_display_source_2;
quantity hour_illuminance_3 across hour_display_source_3;
quantity illuminances_unused : illuminance_vector(1 to 5);
-- end code from book
begin
-- code from book
hour_digit : entity work.seven_segment_led(basic_optics)
port map ( segment_anodes(2) => hour_anode_2,
segment_anodes(3) => hour_anode_3,
segment_anodes(1) => anodes_unused(1),
segment_anodes(4 to 7) => anodes_unused(2 to 5),
common_cathode => electrical_ref,
segment_illuminances(2) => hour_illuminance_2,
segment_illuminances(3) => hour_illuminance_3,
segment_illuminances(1) => illuminances_unused(1),
segment_illuminances(4 to 7) => illuminances_unused(2 to 5) );
-- end code from book
end architecture test;
|
gpl-2.0
|
720e6661043a91bb418654178a6eac9e
| 0.690787 | 3.955864 | false | false | false | false |
nickg/nvc
|
test/lower/protupref.vhd
| 1 | 2,746 |
package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
end protected AlertLogStructPType ;
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body AlertLogPkg is
-- synthesis translate_off
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
------------------------------------------------------------
-- Report formatting settings, with defaults
variable PrintPassedVar : boolean := TRUE ;
variable PrintAffirmationsVar : boolean := FALSE ;
variable PrintDisabledAlertsVar : boolean := FALSE ;
variable PrintRequirementsVar : boolean := FALSE ;
variable HasRequirementsVar : boolean := FALSE ;
variable PrintIfHaveRequirementsVar : boolean := TRUE ;
variable DefaultPassedGoalVar : integer := 1 ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
begin
report ALERT_NAME(Level); -- Lower crash here
end procedure alert ;
end protected body AlertLogStructPType ;
end package body AlertLogPkg ;
|
gpl-3.0
|
282d3027149aba285034627b0305b32c
| 0.525856 | 5.732777 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd
| 4 | 2,020 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc30.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b00x00p14n04i00030ent IS
END c04s03b00x00p14n04i00030ent;
ARCHITECTURE c04s03b00x00p14n04i00030arch OF c04s03b00x00p14n04i00030ent IS
signal M1 : BIT_VECTOR(0 to 7) ;
constant M2 : BIT := '1' ;
BEGIN
TESTING: PROCESS
variable V1 : BIT;
BEGIN
M1(3) <= '1' after 10 ns;
--- No_failure_here
--- M1(3) is also a signal; so this signal
--- assignment is possible.
V1 := M2;
wait for 10 ns;
assert NOT( M1(3)='1' and V1='1' )
report "***PASSED TEST: c04s03b00x00p14n04i00030"
severity NOTE;
assert ( M1(3)='1' and V1='1' )
report "***FAILED TEST:c04s03b00x00p14n04i00030 - Each subelement of that object is itself an object of the same class as the given object."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b00x00p14n04i00030arch;
|
gpl-2.0
|
5eed3a66fcb9ee461622219a3445d049
| 0.64802 | 3.54386 | false | true | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_100M_0/synth/design_1_rst_processing_system7_0_100M_0.vhd
| 1 | 6,757 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_0;
ARCHITECTURE design_1_rst_processing_system7_0_100M_0_arch OF design_1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "design_1_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "design_1_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_0_arch;
|
gpl-3.0
|
4c714e18cd7f4e6b346d9eaae82d49cc
| 0.717182 | 3.458035 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dff01/tb_dff07.vhdl
| 1 | 722 |
entity tb_dff07 is
end tb_dff07;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff07 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff07
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
23bd91da0af6aabb179174d3f6253b05
| 0.567867 | 3.389671 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/project.srcs/sources_1/ip/doHistStretch_ap_sitofp_4_no_dsp_32/synth/doHistStretch_ap_sitofp_4_no_dsp_32.vhd
| 1 | 12,510 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_sitofp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_sitofp_4_no_dsp_32;
ARCHITECTURE doHistStretch_ap_sitofp_4_no_dsp_32_arch OF doHistStretch_ap_sitofp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_sitofp_4_no_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_sitofp_4_no_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_sitofp_4_no_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=1,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0" &
",C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=0,C_B_WIDTH=32,C_B_FRACTION_WIDTH=0,C_C_WIDTH=32,C_C_FRACTION_WIDTH=0,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THRO" &
"TTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_sitofp_4_no_dsp_32_arch;
|
gpl-3.0
|
5a3e0bb5f66162b990cd41a90d1c90c9
| 0.65028 | 3.031992 | false | false | false | false |
mistryalok/FPGA
|
Xilinx/ISE/Basics/MUX2x1vi/MUX2x1vi.vhd
| 1 | 1,095 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:50:45 05/22/2013
-- Design Name:
-- Module Name: MUX2x1vi - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX2x1vi is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
S : in STD_LOGIC;
O : out STD_LOGIC);
end MUX2x1vi;
architecture Behavioral of MUX2x1vi is
begin
process(S,I)
begin
case s is
when '0' => O <= I(0);
when '1' => O <= I(1);
when others => Null;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
1a96da277c8b5045040361bd818f97dd
| 0.533333 | 3.509615 | false | false | false | false |
nickg/nvc
|
test/regress/image.vhd
| 1 | 1,365 |
package p is
type enum1 is (A, B);
procedure print_char(c : in character);
procedure print_enum1(e : in enum1);
end package;
package body p is
procedure print_char(c : in character) is
begin
report character'image(c);
end procedure;
procedure print_enum1(e : in enum1) is
begin
report enum1'image(e);
end procedure;
end package body;
entity image is
end entity;
use work.p.all;
architecture test of image is
type enum2 is (C, D);
type my_int is range 1 to 4;
type my_phys is range 1 to 100
units
UNIT_1;
UNIT_2 = 10 UNIT_1;
end units;
begin
process is
variable i : integer;
variable j : my_int;
variable e1 : enum1;
variable e2 : enum2;
begin
report integer'image(4);
report integer'image(-42);
i := 73;
j := 3;
report integer'image(i);
report "i=" & integer'image(i) & " units";
report character'image('c');
print_char('X');
wait for 10 ps;
report time'image(now);
e1 := A;
e2 := C;
wait for 1 ns;
report enum1'image(e1);
report enum2'image(e2);
print_enum1(e1);
report my_int'image(j);
report my_phys'image(2 UNIT_2);
wait;
end process;
end architecture;
|
gpl-3.0
|
5cb4920a3c79b08f7d2635100463620d
| 0.553114 | 3.563969 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/insert01/insert01.vhdl
| 1 | 426 |
library ieee;
use ieee.std_logic_1164.all;
entity insert01 is
port (a : std_logic_vector (3 downto 0);
b : std_logic;
o0, o1, o2, o3 : out std_logic_vector (3 downto 0));
end insert01;
architecture behav of insert01 is
begin
process(a, b)
begin
o0 <= a;
o0 (0) <= b;
o1 <= a;
o1 (1) <= b;
o2 <= a;
o2 (2) <= b;
o3 <= a;
o3 (3) <= b;
end process;
end behav;
|
gpl-2.0
|
a6d6311466d6b895f9828b8ca49c7a38
| 0.523474 | 2.6625 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1230/delayline.vhdl
| 1 | 778 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DelayLine is
generic (
Depth : natural := 2;
Width : natural := 16
);
port(
din : in signed(Width-1 downto 0);
clk : in std_logic;
ce : in std_logic;
dout : out signed(Width-1 downto 0)
);
end DelayLine;
architecture behavioral of DelayLine is
type DelayType is array (0 to Depth-1) of signed(Width-1 downto 0);
signal DataBuffer : DelayType;
begin
dout <= DataBuffer(Depth-1);
process (clk)
begin
if rising_edge (clk) then
if (ce = '1') then
DataBuffer(0) <= din;
DataBuffer(1 to Depth-1) <= DataBuffer(0 to Depth-2); --XX
end if;
end if;
end process;
end behavioral;
|
gpl-2.0
|
aeb22897d82139569f339c6371035ee6
| 0.59126 | 3.488789 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd
| 4 | 2,525 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3112.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p06n01i03112ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p06n01i03112ent_a;
ARCHITECTURE c05s02b00x00p06n01i03112arch_a OF c05s02b00x00p06n01i03112ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p06n01i03112arch_a;
ENTITY c05s02b00x00p06n01i03112ent IS
END c05s02b00x00p06n01i03112ent;
ARCHITECTURE c05s02b00x00p06n01i03112arch OF c05s02b00x00p06n01i03112ent IS
signal s1 : Bit := '0';
signal s2 : Bit := '1';
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
BEGIN
u1 : virtual generic map ( true ) port map (s1, s2);
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( s2 = s1 )
report "***PASSED TEST: c05s02b00x00p06n01i03112"
severity NOTE;
assert ( s2 = s1 )
report "***FAILED TEST: c05s02b00x00p06n01i03112 - Component instance configuration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p06n01i03112arch;
configuration c05s02b00x00p06n01i03112cfg of c05s02b00x00p06n01i03112ent is
for c05s02b00x00p06n01i03112arch
for u1 : virtual use entity work.c05s02b00x00p06n01i03112ent_a (c05s02b00x00p06n01i03112arch_a);
end for;
end for;
end c05s02b00x00p06n01i03112cfg;
|
gpl-2.0
|
0efa71cdf177ceb3ce8ef39d33409bb3
| 0.678416 | 3.180101 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/issue317/PoC/src/common/strings.vhdl
| 2 | 35,234 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- -------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
-- WORKAROUND: for Altera Quartus-II
-- Version: 15.0
-- Issue:
-- character 0 (NUL) causes Quartus-II to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus-II
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Solution:
-- PoC uses backtick "`" as a fill and termination symbol, if a Quartus-II
-- synthesis environment is detected.
constant C_POC_NUL : character := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is std_logic_vector(7 downto 0);
type T_RAWSTRING is array (natural range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : string) return T_IPSTYLE;
-- to_char
function to_char(Value : std_logic) return character;
function to_char(rawchar : T_RAWCHAR) return character;
function to_HexChar(Value : natural) return character;
function to_HexChar(Value : unsigned) return character;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(Value : boolean) return string;
function raw_format_bool_chr(Value : boolean) return string;
function raw_format_bool_str(Value : boolean) return string;
function raw_format_slv_bin(slv : std_logic_vector) return string;
function raw_format_slv_oct(slv : std_logic_vector) return string;
function raw_format_slv_dec(slv : std_logic_vector) return string;
function raw_format_slv_hex(slv : std_logic_vector) return string;
function raw_format_nat_bin(Value : natural) return string;
function raw_format_nat_oct(Value : natural) return string;
function raw_format_nat_dec(Value : natural) return string;
function raw_format_nat_hex(Value : natural) return string;
-- str_format_* functions
function str_format(Value : REAL; precision : natural := 3) return string;
-- to_string
function to_string(Value : boolean) return string;
function to_string(Value : integer; base : positive := 10) return string;
function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string;
function to_string(rawstring : T_RAWSTRING) return string;
function to_string(Value : T_BCD_VECTOR) return string;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return std_logic_vector;
-- digit subtypes incl. error Value (-1)
subtype T_DIGIT_BIN is integer range -1 to 1;
subtype T_DIGIT_OCT is integer range -1 to 7;
subtype T_DIGIT_DEC is integer range -1 to 9;
subtype T_DIGIT_HEX is integer range -1 to 15;
-- to_digit*
function to_digit_bin(chr : character) return T_DIGIT_BIN;
function to_digit_oct(chr : character) return T_DIGIT_OCT;
function to_digit_dec(chr : character) return T_DIGIT_DEC;
function to_digit_hex(chr : character) return T_DIGIT_HEX;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : string) return integer;
function to_natural_oct(str : string) return integer;
function to_natural_dec(str : string) return integer;
function to_natural_hex(str : string) return integer;
function to_natural(str : string; base : character := 'd') return integer;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : string; size : positive; FillChar : character := C_POC_NUL) return string;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : string) return natural;
function str_equal(str1 : string; str2 : string) return boolean;
function str_match(str1 : string; str2 : string) return boolean;
function str_imatch(str1 : string; str2 : string) return boolean;
function str_pos(str : string; chr : character; start : natural := 0) return integer;
function str_pos(str : string; pattern : string; start : natural := 0) return integer;
function str_ipos(str : string; chr : character; start : natural := 0) return integer;
function str_ipos(str : string; pattern : string; start : natural := 0) return integer;
function str_find(str : string; chr : character) return boolean;
function str_find(str : string; pattern : string) return boolean;
function str_ifind(str : string; chr : character) return boolean;
function str_ifind(str : string; pattern : string) return boolean;
function str_replace(str : string; pattern : string; replace : string) return string;
function str_substr(str : string; start : integer := 0; Length : integer := 0) return string;
function str_ltrim(str : string; char : character := ' ') return string;
function str_rtrim(str : string; char : character := ' ') return string;
function str_trim(str : string) return string;
function str_calign(str : string; Length : natural; FillChar : character := ' ') return string;
function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string;
function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string;
function str_toLower(str : string) return string;
function str_toUpper(str : string) return string;
end package;
package body strings is
--
function to_IPStyle(str : string) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(i))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
return IPSTYLE_UNKNOWN;
end function;
-- to_char
-- ===========================================================================
function to_char(Value : std_logic) return character is
begin
case Value is
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
function to_char(rawchar : T_RAWCHAR) return character is
begin
return character'val(to_integer(unsigned(rawchar)));
end function;
--
function to_HexChar(Value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(Value < 16, HEX(Value+1), 'X');
end function;
function to_HexChar(Value : unsigned) return character is
begin
return to_HexChar(to_integer(Value));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(Value : boolean) return string is
begin
return ite(Value, "1", "0");
end function;
function raw_format_bool_chr(Value : boolean) return string is
begin
return ite(Value, "T", "F");
end function;
function raw_format_bool_str(Value : boolean) return string is
begin
return str_toUpper(boolean'image(Value));
end function;
function raw_format_slv_bin(slv : std_logic_vector) return string is
variable Value : std_logic_vector(slv'length - 1 downto 0);
variable Result : string(1 to slv'length);
variable j : natural;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
j := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : std_logic_vector) return string is
variable Value : std_logic_vector(slv'length - 1 downto 0);
variable Digit : std_logic_vector(2 downto 0);
variable Result : string(1 to div_ceil(slv'length, 3));
variable j : natural;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_HexChar(unsigned(Digit));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : std_logic_vector) return string is
variable Value : std_logic_vector(slv'length - 1 downto 0);
variable Result : string(1 to div_ceil(slv'length, 3));
subtype TT_BCD is integer range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : natural;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_HexChar(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : std_logic_vector) return string is
variable Value : std_logic_vector(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : std_logic_vector(3 downto 0);
variable Result : string(1 to div_ceil(slv'length, 4));
variable j : natural;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_HexChar(unsigned(Digit));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(Value : natural) return string is
begin
return raw_format_slv_bin(to_slv(Value, log2ceilnz(Value+1)));
end function;
function raw_format_nat_oct(Value : natural) return string is
begin
return raw_format_slv_oct(to_slv(Value, log2ceilnz(Value+1)));
end function;
function raw_format_nat_dec(Value : natural) return string is
begin
return integer'image(Value);
end function;
function raw_format_nat_hex(Value : natural) return string is
begin
return raw_format_slv_hex(to_slv(Value, log2ceilnz(Value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(Value : REAL; precision : natural := 3) return string is
constant s : REAL := sign(Value);
constant val : REAL := Value * s;
constant int : integer := integer(floor(val));
constant frac : integer := integer(round((val - real(int)) * 10.0**precision));
constant overflow : boolean := frac >= 10**precision;
constant int2 : integer := ite(overflow, int+1, int);
constant frac2 : integer := ite(overflow, frac-10**precision, frac);
constant frac_str : string := integer'image(frac2);
constant res : string := integer'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(Value : boolean) return string is
begin
return raw_format_bool_str(Value);
end function;
-- convert an integer Value to a STRING using an arbitrary base
function to_string(Value : integer; base : positive := 10) return string is
constant absValue : natural := abs Value;
constant len : positive := log10ceilnz(absValue);
variable power : positive;
variable Result : string(1 to len);
begin
power := 1;
if base = 10 then
return integer'image(Value);
else
for i in len downto 1 loop
Result(i) := to_HexChar(absValue / power mod base);
power := power * base;
end loop;
if Value < 0 then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- QUESTION: rename to slv_format(..) ?
function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string is
constant int : integer := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : string := integer'image(int);
constant bin_len : positive := slv'length;
constant dec_len : positive := str'length;--log10ceilnz(int);
constant hex_len : positive := ite(((bin_len mod 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : natural := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : natural;
variable Result : string(1 to ite((Length = 0), len, imax(len, Length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- TODO: enable big integer conversion
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_HexChar(unsigned(slv((j * 4) + 3 downto (j * 4))));
j := j + 1;
end loop;
else
report "Unknown format character: " & format & "." severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return string is
variable Result : string(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
Result(i - rawstring'low + 1) := to_char(rawstring(i));
end loop;
return Result;
end function;
function to_string(Value : T_BCD_VECTOR) return string is
variable Result : string(1 to Value'length);
begin
for i in Value'range loop
Result(Result'high - (i - Value'low)) := to_HexChar(unsigned(Value(i)));
end loop;
return Result;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return std_logic_vector is
variable Result : std_logic_vector((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
Result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return Result;
end function;
-- to_digit*
-- ===========================================================================
-- convert a binary digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_bin(chr : character) return T_DIGIT_BIN is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
-- convert an octal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_oct(chr : character) return T_DIGIT_OCT is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
-- convert a adecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_dec(chr : character) return T_DIGIT_DEC is
begin
if chr_isDigit(chr) then
return character'pos(chr) - CHARACTER'pos('0');
else
return -1;
end if;
end function;
-- convert a hexadecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_hex(chr : character) return T_DIGIT_HEX is
begin
if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('A') + 10;
else return -1;
end if;
end function;
-- convert a digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity FAILURE;
return -1;
end case;
end function;
-- to_natural*
-- ===========================================================================
-- convert a binary number given as STRING to a NATURAL; return -1 on error
function to_natural_bin(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
for i in str'range loop
Digit := to_digit_bin(str(i));
if Digit /= -1 then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
-- convert an octal number given as STRING to a NATURAL; return -1 on error
function to_natural_oct(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
for i in str'range loop
Digit := to_digit_oct(str(i));
if Digit /= -1 then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
-- convert a decimal number given as STRING to a NATURAL; return -1 on error
function to_natural_dec(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
-- WORKAROUND: Xilinx Vivado Synth
-- Version: 2014.1
-- Issue:
-- INTEGER'value(...) is not supported by Vivado Synth
-- Solution:
-- implement a manual conversion using shift and multiply
for i in str'range loop
Digit := to_digit_dec(str(i));
if Digit /= -1 then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result; -- INTEGER'value(str);
end function;
-- convert a hexadecimal number given as STRING to a NATURAL; return -1 on error
function to_natural_hex(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
for i in str'range loop
Digit := to_digit_hex(str(i));
if Digit /= -1 then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
-- convert a number given as STRING to a NATURAL; return -1 on error
function to_natural(str : string; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "Unknown base character: " & base & "." severity FAILURE;
return -1;
end case;
end function;
-- to_raw*
-- ===========================================================================
-- convert a CHARACTER to a RAWCHAR
function to_RawChar(char : character) return T_RAWCHAR is
begin
return std_logic_vector(to_unsigned(character'pos(char), T_RAWCHAR'length));
end function;
-- convert a STRING to a RAWSTRING
function to_RawString(str : string) return T_RAWSTRING is
variable Result : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
Result(i - str'low) := to_RawChar(str(i));
end loop;
return Result;
end function;
-- resize
-- ===========================================================================
function resize(str : string; Size : positive; FillChar : character := C_POC_NUL) return string is
constant ConstNUL : string(1 to 1) := (others => C_POC_NUL);
variable Result : string(1 to Size);
begin
Result := (others => FillChar);
if (str'length > 0) then
-- WORKAROUND: for Altera Quartus-II
-- Version: 15.0
-- Issue: array bounds are check regardless of the hierarchy and control flow
Result(1 to bound(Size, 1, str'length)) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
-- convert an upper case CHARACTER into a lower case CHARACTER
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
-- convert a lower case CHARACTER into an upper case CHARACTER
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
-- count the length of a POC_NUL terminated STRING
function str_length(str : string) return natural is
begin
for i in str'range loop
if str(i) = C_POC_NUL then
return i - str'low;
end if;
end loop;
return str'length;
end function;
-- compare two STRINGs for equality
-- pre-check the string lengthes to suppress warnings for unqual sized string comparisons.
-- QUESTION: overload "=" operator?
function str_equal(str1 : string; str2 : string) return boolean is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
-- compare two POC_NUL terminated STRINGs
function str_match(str1 : string; str2 : string) return boolean is
constant len : natural := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
-- compare two POC_NUL terminated STRINGs; case insentitve
function str_imatch(str1 : string; str2 : string) return boolean is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
-- search for chr in a STRING and return the position; return -1 on error
function str_pos(str : string; chr : character; start : natural := 0) return integer is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if str(i) = chr then
return i;
end if;
end loop;
return -1;
end function;
-- search for pattern in a STRING and return the position; return -1 on error
-- QUESTION: implement KMP algorithm?
function str_pos(str : string; pattern : string; start : natural := 0) return integer is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
-- search for chr in a STRING and return the position; case insentitve; return -1 on error
function str_ipos(str : string; chr : character; start : natural := 0) return integer is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
-- search for pattern in a STRING and return the position; case insentitve; return -1 on error
function str_ipos(str : string; pattern : string; start : natural := 0) return integer is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
-- check if chr exists in STRING str
function str_find(str : string; chr : character) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
-- check if pattern exists in STRING str
function str_find(str : string; pattern : string) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
-- check if chr exists in STRING str; case insentitve
function str_ifind(str : string; chr : character) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
-- check if pattern exists in STRING str; case insentitve
function str_ifind(str : string; pattern : string) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
-- replace a pattern in a STRING str by the STRING replace
function str_replace(str : string; pattern : string; replace : string) return string is
variable pos : integer;
begin
pos := str_pos(str, pattern);
if pos > 0 then
if pos = 1 then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- return a sub-string of STRING str
-- EXAMPLES:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : string; start : integer := 0; Length : integer := 0) return string is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if start < 0 then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif start = 0 then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if Length < 0 then -- Length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + Length;
elsif Length = 0 then -- Length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- Length is positive -> end substring at StartOfString + Length
EndOfString := StartOfString + Length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if;
return str(StartOfString to EndOfString);
end function;
-- left-trim the STRING str
function str_ltrim(str : string; char : character := ' ') return string is
begin
for i in str'range loop
if str(i) /= char then
return str(i to str'high);
end if;
end loop;
return "";
end function;
-- right-trim the STRING str
function str_rtrim(str : string; char : character := ' ') return string is
begin
for i in str'reverse_range loop
if str(i) /= char then
return str(str'low to i);
end if;
end loop;
return "";
end function;
-- remove POC_NUL string termination characters
function str_trim(str : string) return string is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
-- center-align a STRING str in a FillChar filled STRING of length Length
function str_calign(str : string; Length : natural; FillChar : character := ' ') return string is
constant Start : positive := (Length - str'length) / 2;
variable Result : string(1 to Length);
begin
Result := (others => FillChar);
Result(Start to (Start + str'length)) := str;
return Result;
end function;
-- left-align a STRING str in a FillChar filled STRING of length Length
function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string is
variable Result : string(1 to Length);
begin
Result := (others => FillChar);
Result(1 to str'length) := str;
return Result;
end function;
-- right-align a STRING str in a FillChar filled STRING of length Length
function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string is
variable Result : string(1 to Length);
begin
Result := (others => FillChar);
Result((Length - str'length + 1) to Length) := str;
return Result;
end function;
-- convert an upper case STRING into a lower case STRING
function str_toLower(str : string) return string is
variable Result : string(str'range);
begin
for i in str'range loop
Result(i) := chr_toLower(str(i));
end loop;
return Result;
end function;
-- convert a lower case STRING into an upper case STRING
function str_toUpper(str : string) return string is
variable Result : string(str'range);
begin
for i in str'range loop
Result(i) := chr_toUpper(str(i));
end loop;
return Result;
end function;
end package body;
|
gpl-2.0
|
aef93bf116bccb2dd38a27d5ee9566fa
| 0.64608 | 3.287674 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1906.vhd
| 4 | 2,102 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1906.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p10n01i01906ent IS
END c07s01b00x00p10n01i01906ent;
ARCHITECTURE c07s01b00x00p10n01i01906arch OF c07s01b00x00p10n01i01906ent IS
type MVL is ('0','1','X','Z') ;
signal Q : MVL;
signal PP,P2 : BIT := '1' ;
signal R1 : BIT;
BEGIN
TESTING: PROCESS
function "and" (L,R : MVL) return MVL is
variable V1 : MVL;
begin
if (L = '1') then
V1 := '1' ;
end if;
return V1;
end;
BEGIN
Q <= "and"('1','Z'); -- No_failure_here
R1 <= PP and P2;
wait for 1 ns;
assert NOT((Q='1') and (R1='1'))
report "***PASSED TEST: c07s01b00x00p10n01i01906"
severity NOTE;
assert (( Q='1' ) and (R1='1'))
report "***FAILED TEST: c07s01b00x00p10n01i01906 - The identification of an overloaded operator depends on the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p10n01i01906arch;
|
gpl-2.0
|
728623178c00d4dae730d5931ad3aba6
| 0.625119 | 3.457237 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_02.vhd
| 4 | 1,774 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_02 is
end entity ch_03_02;
architecture test of ch_03_02 is
signal sel : integer range 0 to 1 := 0;
signal input_0 : integer := 0;
signal input_1 : integer := 10;
signal result : integer;
begin
process_3_1_b : process (sel, input_0, input_1) is
begin
-- code from book:
if sel = 0 then
result <= input_0; -- executed if sel = 0
else
result <= input_1; -- executed if sel /= 0
end if;
-- end of code from book
end process process_3_1_b;
stimulus : process is
begin
sel <= 1 after 40 ns;
input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
18c3627d56be4921e48cb59d0ce23ab0
| 0.617249 | 3.806867 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd
| 4 | 9,589 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc865.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00865pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal dumy : bit_vector(0 to 3);
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00865pkg;
use work.c01s03b01x00p12n01i00865pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00865pkg.all;
ENTITY c01s03b01x00p12n01i00865ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
END c01s03b01x00p12n01i00865ent;
ARCHITECTURE c01s03b01x00p12n01i00865arch OF c01s03b01x00p12n01i00865ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00865"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00865 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00865arch;
configuration c01s03b01x00p12n01i00865cfg of c01s03b01x00p12n01i00865ent is
for c01s03b01x00p12n01i00865arch
for K
for T5:test use configuration work.testbench;
end for;
for G(zero to one)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(three downto two)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
gpl-2.0
|
377b075866992a3c0696fd3dce4ab00c
| 0.574095 | 3.384751 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/issue1126/bch_128x64.vhdl
| 1 | 194,999 |
-- /* -------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Copyright: Levent Ozturk [email protected]
-- https://leventozturk.com/engineering/crc/
-- Polynomial: x128+x124+x123+x122+x114+x113+x112+x109+x106+x104+x102+x100+x99+x98+x97+x96+x94+x93+x92+x88+x85+x82+x81+x80+x79+x76+x74+x73+x72+x71+x69+x68+x67+x66+x64+x60+x59+x56+x55+x54+x53+x52+x51+x50+x46+x45+x43+x42+x40+x38+x37+x36+x34+x32+x26+x23+x22+x21+x20+x19+x16+x14+x13+x10+x9+x5+x3+x1+1
-- d63 is the first data processed
-- c is internal LFSR state and the CRC output. Not needed for other modules than CRC.
-- c width is always same as polynomial width.
-- o is the output of all modules except CRC. Not needed for CRC.
-- o width is always same as data width width
-------------------------------------------------------------------------*/
-- Based on https://leventozturk.com/engineering/crc/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bch_128x64 is
generic (
SEED : in std_ulogic_vector(127 downto 0) := (others => '0')
);
port (
clk : in std_ulogic;
reset : in std_ulogic;
fd : in std_ulogic; -- First data. 1: SEED is used (initialise and calculate), 0: Previous CRC is used (continue and calculate)
nd : in std_ulogic; -- New Data. d input has a valid data. Calculate new CRC
rdy : out std_ulogic;
d : in std_ulogic_vector( 63 downto 0); -- Data in
c : out std_ulogic_vector(127 downto 0);
-- CRC output
o : out std_ulogic_vector( 63 downto 0) -- Data output
);
end entity bch_128x64;
architecture bch_128x64 of bch_128x64 is
signal nd_q : std_ulogic;
signal fd_q : std_ulogic;
signal dq : std_ulogic_vector (127 downto 0);
signal ca : std_ulogic_vector(127 downto 0);
signal oa : std_ulogic_vector( 63 downto 0);
begin
process (clk)
begin
if (rising_edge(clk)) then
nd_q <= nd;
fd_q <= fd;
dq( 0) <= d( 62) xor d( 58) xor d( 56) xor d( 53) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 43) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 28) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 13) xor d( 10) xor d( 8) xor d( 6) xor d( 5) xor d( 4) xor d( 0);
dq( 1) <= d( 63) xor d( 62) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 49) xor d( 45) xor d( 44) xor d( 43) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 21) xor d( 20) xor d( 17) xor d( 15) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 4) xor d( 1) xor d( 0);
dq( 2) <= d( 63) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 51) xor d( 50) xor d( 46) xor d( 45) xor d( 44) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 22) xor d( 21) xor d( 18) xor d( 16) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 2) xor d( 1);
dq( 3) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 48) xor d( 43) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 21) xor d( 18) xor d( 15) xor d( 14) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 0);
dq( 4) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 51) xor d( 49) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 22) xor d( 19) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 1);
dq( 5) <= d( 63) xor d( 61) xor d( 58) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 34) xor d( 32) xor d( 31) xor d( 28) xor d( 26) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 11) xor d( 8) xor d( 7) xor d( 2) xor d( 0);
dq( 6) <= d( 62) xor d( 59) xor d( 58) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 29) xor d( 27) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 12) xor d( 9) xor d( 8) xor d( 3) xor d( 1);
dq( 7) <= d( 63) xor d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 30) xor d( 28) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 13) xor d( 10) xor d( 9) xor d( 4) xor d( 2);
dq( 8) <= d( 61) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 37) xor d( 35) xor d( 34) xor d( 31) xor d( 29) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 19) xor d( 14) xor d( 11) xor d( 10) xor d( 5) xor d( 3);
dq( 9) <= d( 61) xor d( 59) xor d( 57) xor d( 55) xor d( 53) xor d( 52) xor d( 48) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 28) xor d( 25) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 8) xor d( 5) xor d( 0);
dq( 10) <= d( 60) xor d( 54) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 31) xor d( 29) xor d( 28) xor d( 25) xor d( 23) xor d( 20) xor d( 17) xor d( 16) xor d( 15) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 1) xor d( 0);
dq( 11) <= d( 61) xor d( 55) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 32) xor d( 30) xor d( 29) xor d( 26) xor d( 24) xor d( 21) xor d( 18) xor d( 17) xor d( 16) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 6) xor d( 5) xor d( 2) xor d( 1);
dq( 12) <= d( 62) xor d( 56) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 33) xor d( 31) xor d( 30) xor d( 27) xor d( 25) xor d( 22) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 7) xor d( 6) xor d( 3) xor d( 2);
dq( 13) <= d( 63) xor d( 62) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 52) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 22) xor d( 21) xor d( 20) xor d( 17) xor d( 15) xor d( 12) xor d( 11) xor d( 10) xor d( 7) xor d( 6) xor d( 5) xor d( 3) xor d( 0);
dq( 14) <= d( 63) xor d( 62) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 42) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 28) xor d( 26) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 7) xor d( 5) xor d( 1) xor d( 0);
dq( 15) <= d( 63) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 52) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 29) xor d( 27) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 8) xor d( 6) xor d( 2) xor d( 1);
dq( 16) <= d( 62) xor d( 61) xor d( 59) xor d( 57) xor d( 56) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 39) xor d( 38) xor d( 35) xor d( 33) xor d( 30) xor d( 26) xor d( 23) xor d( 22) xor d( 17) xor d( 16) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 0);
dq( 17) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 51) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 36) xor d( 34) xor d( 31) xor d( 27) xor d( 24) xor d( 23) xor d( 18) xor d( 17) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 1);
dq( 18) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 52) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 32) xor d( 28) xor d( 25) xor d( 24) xor d( 19) xor d( 18) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2);
dq( 19) <= d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 52) xor d( 51) xor d( 45) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 29) xor d( 28) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 12) xor d( 11) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 0);
dq( 20) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 42) xor d( 39) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 24) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 12) xor d( 6) xor d( 1) xor d( 0);
dq( 21) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 40) xor d( 39) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 19) xor d( 16) xor d( 15) xor d( 14) xor d( 10) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 22) <= d( 61) xor d( 60) xor d( 57) xor d( 56) xor d( 47) xor d( 45) xor d( 43) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 23) <= d( 61) xor d( 57) xor d( 56) xor d( 53) xor d( 51) xor d( 50) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 26) xor d( 25) xor d( 23) xor d( 20) xor d( 18) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 6) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 24) <= d( 62) xor d( 58) xor d( 57) xor d( 54) xor d( 52) xor d( 51) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 27) xor d( 26) xor d( 24) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 25) <= d( 63) xor d( 59) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 28) xor d( 27) xor d( 25) xor d( 22) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2);
dq( 26) <= d( 62) xor d( 60) xor d( 59) xor d( 58) xor d( 54) xor d( 51) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 32) xor d( 29) xor d( 22) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 9) xor d( 8) xor d( 3) xor d( 0);
dq( 27) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 55) xor d( 52) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 33) xor d( 30) xor d( 23) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 10) xor d( 9) xor d( 4) xor d( 1);
dq( 28) <= d( 62) xor d( 61) xor d( 60) xor d( 56) xor d( 53) xor d( 46) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 34) xor d( 31) xor d( 24) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 12) xor d( 11) xor d( 10) xor d( 5) xor d( 2);
dq( 29) <= d( 63) xor d( 62) xor d( 61) xor d( 57) xor d( 54) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 35) xor d( 32) xor d( 25) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 13) xor d( 12) xor d( 11) xor d( 6) xor d( 3);
dq( 30) <= d( 63) xor d( 62) xor d( 58) xor d( 55) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 36) xor d( 33) xor d( 26) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 7) xor d( 4);
dq( 31) <= d( 63) xor d( 59) xor d( 56) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 37) xor d( 34) xor d( 27) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 5);
dq( 32) <= d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 53) xor d( 51) xor d( 49) xor d( 48) xor d( 44) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 26) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 0);
dq( 33) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 54) xor d( 52) xor d( 50) xor d( 49) xor d( 45) xor d( 39) xor d( 38) xor d( 35) xor d( 34) xor d( 27) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 10) xor d( 9) xor d( 6) xor d( 5) xor d( 1);
dq( 34) <= d( 60) xor d( 59) xor d( 56) xor d( 55) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 34) xor d( 33) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 8) xor d( 7) xor d( 5) xor d( 4) xor d( 2) xor d( 0);
dq( 35) <= d( 61) xor d( 60) xor d( 57) xor d( 56) xor d( 49) xor d( 48) xor d( 46) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 35) xor d( 34) xor d( 27) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 9) xor d( 8) xor d( 6) xor d( 5) xor d( 3) xor d( 1);
dq( 36) <= d( 61) xor d( 57) xor d( 56) xor d( 53) xor d( 51) xor d( 49) xor d( 48) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 33) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 9) xor d( 8) xor d( 7) xor d( 5) xor d( 2) xor d( 0);
dq( 37) <= d( 57) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 33) xor d( 28) xor d( 27) xor d( 25) xor d( 23) xor d( 21) xor d( 20) xor d( 18) xor d( 16) xor d( 14) xor d( 13) xor d( 9) xor d( 5) xor d( 4) xor d( 3) xor d( 1) xor d( 0);
dq( 38) <= d( 62) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 49) xor d( 48) xor d( 41) xor d( 40) xor d( 39) xor d( 37) xor d( 35) xor d( 33) xor d( 29) xor d( 24) xor d( 23) xor d( 18) xor d( 15) xor d( 13) xor d( 8) xor d( 2) xor d( 1) xor d( 0);
dq( 39) <= d( 63) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 52) xor d( 50) xor d( 49) xor d( 42) xor d( 41) xor d( 40) xor d( 38) xor d( 36) xor d( 34) xor d( 30) xor d( 25) xor d( 24) xor d( 19) xor d( 16) xor d( 14) xor d( 9) xor d( 3) xor d( 2) xor d( 1);
dq( 40) <= d( 62) xor d( 59) xor d( 57) xor d( 54) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 39) xor d( 34) xor d( 33) xor d( 31) xor d( 28) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 6) xor d( 5) xor d( 3) xor d( 2) xor d( 0);
dq( 41) <= d( 63) xor d( 60) xor d( 58) xor d( 55) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 35) xor d( 34) xor d( 32) xor d( 29) xor d( 26) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 16) xor d( 15) xor d( 14) xor d( 9) xor d( 7) xor d( 6) xor d( 4) xor d( 3) xor d( 1);
dq( 42) <= d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 53) xor d( 51) xor d( 49) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 37) xor d( 36) xor d( 34) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 7) xor d( 6) xor d( 2) xor d( 0);
dq( 43) <= d( 63) xor d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 43) xor d( 42) xor d( 38) xor d( 34) xor d( 33) xor d( 31) xor d( 29) xor d( 27) xor d( 25) xor d( 23) xor d( 22) xor d( 20) xor d( 18) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 1) xor d( 0);
dq( 44) <= d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 44) xor d( 43) xor d( 39) xor d( 35) xor d( 34) xor d( 32) xor d( 30) xor d( 28) xor d( 26) xor d( 24) xor d( 23) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1);
dq( 45) <= d( 61) xor d( 60) xor d( 55) xor d( 54) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 40) xor d( 37) xor d( 36) xor d( 34) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 0);
dq( 46) <= d( 61) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 44) xor d( 43) xor d( 41) xor d( 38) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 27) xor d( 25) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 11) xor d( 6) xor d( 3) xor d( 1) xor d( 0);
dq( 47) <= d( 62) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 47) xor d( 45) xor d( 44) xor d( 42) xor d( 39) xor d( 35) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 12) xor d( 7) xor d( 4) xor d( 2) xor d( 1);
dq( 48) <= d( 63) xor d( 60) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 46) xor d( 45) xor d( 43) xor d( 40) xor d( 36) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 13) xor d( 8) xor d( 5) xor d( 3) xor d( 2);
dq( 49) <= d( 61) xor d( 58) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 41) xor d( 37) xor d( 36) xor d( 35) xor d( 33) xor d( 32) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 14) xor d( 9) xor d( 6) xor d( 4) xor d( 3);
dq( 50) <= d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 54) xor d( 51) xor d( 46) xor d( 43) xor d( 42) xor d( 38) xor d( 36) xor d( 35) xor d( 31) xor d( 29) xor d( 27) xor d( 26) xor d( 24) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 7) xor d( 6) xor d( 0);
dq( 51) <= d( 62) xor d( 60) xor d( 59) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 39) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 1) xor d( 0);
dq( 52) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 54) xor d( 52) xor d( 50) xor d( 49) xor d( 48) xor d( 43) xor d( 40) xor d( 36) xor d( 31) xor d( 27) xor d( 24) xor d( 22) xor d( 21) xor d( 19) xor d( 16) xor d( 13) xor d( 11) xor d( 7) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 53) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 56) xor d( 55) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 26) xor d( 25) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 13) xor d( 12) xor d( 10) xor d( 6) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 54) <= d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 53) xor d( 51) xor d( 49) xor d( 44) xor d( 43) xor d( 42) xor d( 37) xor d( 36) xor d( 28) xor d( 27) xor d( 23) xor d( 20) xor d( 18) xor d( 17) xor d( 11) xor d( 10) xor d( 8) xor d( 7) xor d( 6) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 55) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 44) xor d( 38) xor d( 35) xor d( 34) xor d( 33) xor d( 29) xor d( 26) xor d( 24) xor d( 23) xor d( 22) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 56) <= d( 63) xor d( 61) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 43) xor d( 39) xor d( 37) xor d( 36) xor d( 33) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 22) xor d( 21) xor d( 19) xor d( 17) xor d( 15) xor d( 12) xor d( 11) xor d( 7) xor d( 5) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 57) <= d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 47) xor d( 44) xor d( 40) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 20) xor d( 18) xor d( 16) xor d( 13) xor d( 12) xor d( 8) xor d( 6) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 58) <= d( 63) xor d( 62) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 45) xor d( 41) xor d( 39) xor d( 38) xor d( 35) xor d( 32) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 23) xor d( 21) xor d( 19) xor d( 17) xor d( 14) xor d( 13) xor d( 9) xor d( 7) xor d( 5) xor d( 4) xor d( 3) xor d( 2);
dq( 59) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 15) xor d( 13) xor d( 3) xor d( 0);
dq( 60) <= d( 63) xor d( 61) xor d( 60) xor d( 57) xor d( 55) xor d( 52) xor d( 49) xor d( 47) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 27) xor d( 25) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 17) xor d( 16) xor d( 13) xor d( 10) xor d( 8) xor d( 6) xor d( 5) xor d( 1) xor d( 0);
dq( 61) <= d( 62) xor d( 61) xor d( 58) xor d( 56) xor d( 53) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 39) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 14) xor d( 11) xor d( 9) xor d( 7) xor d( 6) xor d( 2) xor d( 1);
dq( 62) <= d( 63) xor d( 62) xor d( 59) xor d( 57) xor d( 54) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 38) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 15) xor d( 12) xor d( 10) xor d( 8) xor d( 7) xor d( 3) xor d( 2);
dq( 63) <= d( 63) xor d( 60) xor d( 58) xor d( 55) xor d( 52) xor d( 50) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 23) xor d( 22) xor d( 20) xor d( 19) xor d( 16) xor d( 13) xor d( 11) xor d( 9) xor d( 8) xor d( 4) xor d( 3);
dq( 64) <= d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 38) xor d( 36) xor d( 33) xor d( 31) xor d( 29) xor d( 27) xor d( 26) xor d( 24) xor d( 22) xor d( 20) xor d( 19) xor d( 18) xor d( 13) xor d( 12) xor d( 9) xor d( 8) xor d( 6) xor d( 0);
dq( 65) <= d( 63) xor d( 62) xor d( 60) xor d( 59) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 39) xor d( 37) xor d( 34) xor d( 32) xor d( 30) xor d( 28) xor d( 27) xor d( 25) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 14) xor d( 13) xor d( 10) xor d( 9) xor d( 7) xor d( 1);
dq( 66) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 56) xor d( 53) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 29) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 13) xor d( 11) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 0);
dq( 67) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 47) xor d( 46) xor d( 44) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 20) xor d( 17) xor d( 16) xor d( 13) xor d( 12) xor d( 10) xor d( 8) xor d( 7) xor d( 4) xor d( 3) xor d( 1) xor d( 0);
dq( 68) <= d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 51) xor d( 50) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 24) xor d( 22) xor d( 19) xor d( 11) xor d( 10) xor d( 9) xor d( 6) xor d( 2) xor d( 1) xor d( 0);
dq( 69) <= d( 62) xor d( 61) xor d( 60) xor d( 57) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 25) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 70) <= d( 63) xor d( 62) xor d( 61) xor d( 58) xor d( 55) xor d( 54) xor d( 53) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 71) <= d( 63) xor d( 59) xor d( 58) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 9) xor d( 7) xor d( 3) xor d( 2) xor d( 0);
dq( 72) <= d( 62) xor d( 60) xor d( 59) xor d( 58) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 35) xor d( 32) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 16) xor d( 14) xor d( 13) xor d( 6) xor d( 5) xor d( 3) xor d( 1) xor d( 0);
dq( 73) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 55) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 42) xor d( 41) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 30) xor d( 27) xor d( 24) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 15) xor d( 13) xor d( 10) xor d( 8) xor d( 7) xor d( 5) xor d( 2) xor d( 1) xor d( 0);
dq( 74) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 47) xor d( 45) xor d( 42) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 31) xor d( 26) xor d( 25) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 75) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 48) xor d( 46) xor d( 43) xor d( 39) xor d( 37) xor d( 35) xor d( 34) xor d( 32) xor d( 27) xor d( 26) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 76) <= d( 63) xor d( 61) xor d( 60) xor d( 58) xor d( 56) xor d( 53) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 27) xor d( 26) xor d( 21) xor d( 20) xor d( 17) xor d( 15) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 8) xor d( 7) xor d( 3) xor d( 2) xor d( 0);
dq( 77) <= d( 62) xor d( 61) xor d( 59) xor d( 57) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 35) xor d( 28) xor d( 27) xor d( 22) xor d( 21) xor d( 18) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 4) xor d( 3) xor d( 1);
dq( 78) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 36) xor d( 29) xor d( 28) xor d( 23) xor d( 22) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 5) xor d( 4) xor d( 2);
dq( 79) <= d( 63) xor d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 54) xor d( 52) xor d( 50) xor d( 49) xor d( 45) xor d( 41) xor d( 40) xor d( 39) xor d( 35) xor d( 34) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 26) xor d( 24) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 15) xor d( 11) xor d( 8) xor d( 4) xor d( 3) xor d( 0);
dq( 80) <= d( 63) xor d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 55) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 36) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 6) xor d( 1) xor d( 0);
dq( 81) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 53) xor d( 51) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 38) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 23) xor d( 22) xor d( 20) xor d( 15) xor d( 11) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 82) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 47) xor d( 42) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 31) xor d( 30) xor d( 26) xor d( 24) xor d( 22) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 83) <= d( 62) xor d( 61) xor d( 60) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 48) xor d( 43) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 27) xor d( 25) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 10) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 84) <= d( 63) xor d( 62) xor d( 61) xor d( 58) xor d( 56) xor d( 55) xor d( 54) xor d( 49) xor d( 44) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 28) xor d( 26) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 11) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2);
dq( 85) <= d( 63) xor d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 53) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 20) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 8) xor d( 7) xor d( 3) xor d( 0);
dq( 86) <= d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 54) xor d( 52) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 9) xor d( 8) xor d( 4) xor d( 1);
dq( 87) <= d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 55) xor d( 53) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 22) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 10) xor d( 9) xor d( 5) xor d( 2);
dq( 88) <= d( 61) xor d( 60) xor d( 54) xor d( 53) xor d( 49) xor d( 48) xor d( 47) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 22) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 11) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 0);
dq( 89) <= d( 62) xor d( 61) xor d( 55) xor d( 54) xor d( 50) xor d( 49) xor d( 48) xor d( 43) xor d( 42) xor d( 41) xor d( 38) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 23) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 12) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 1);
dq( 90) <= d( 63) xor d( 62) xor d( 56) xor d( 55) xor d( 51) xor d( 50) xor d( 49) xor d( 44) xor d( 43) xor d( 42) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 24) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 7) xor d( 6) xor d( 5) xor d( 2);
dq( 91) <= d( 63) xor d( 57) xor d( 56) xor d( 52) xor d( 51) xor d( 50) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 25) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 8) xor d( 7) xor d( 6) xor d( 3);
dq( 92) <= d( 62) xor d( 57) xor d( 56) xor d( 52) xor d( 50) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 39) xor d( 38) xor d( 36) xor d( 28) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 0);
dq( 93) <= d( 63) xor d( 62) xor d( 57) xor d( 56) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 35) xor d( 34) xor d( 33) xor d( 29) xor d( 28) xor d( 26) xor d( 24) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 11) xor d( 7) xor d( 5) xor d( 4) xor d( 1) xor d( 0);
dq( 94) <= d( 63) xor d( 62) xor d( 57) xor d( 56) xor d( 53) xor d( 46) xor d( 44) xor d( 41) xor d( 40) xor d( 37) xor d( 36) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 95) <= d( 63) xor d( 58) xor d( 57) xor d( 54) xor d( 47) xor d( 45) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 11) xor d( 5) xor d( 3) xor d( 2) xor d( 1);
dq( 96) <= d( 62) xor d( 59) xor d( 56) xor d( 55) xor d( 53) xor d( 51) xor d( 50) xor d( 47) xor d( 45) xor d( 42) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 10) xor d( 8) xor d( 5) xor d( 3) xor d( 2) xor d( 0);
dq( 97) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 47) xor d( 45) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 32) xor d( 31) xor d( 30) xor d( 27) xor d( 25) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 16) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 3) xor d( 1) xor d( 0);
dq( 98) <= d( 63) xor d( 62) xor d( 61) xor d( 59) xor d( 56) xor d( 55) xor d( 54) xor d( 50) xor d( 47) xor d( 45) xor d( 43) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 5) xor d( 2) xor d( 1) xor d( 0);
dq( 99) <= d( 63) xor d( 60) xor d( 58) xor d( 57) xor d( 55) xor d( 53) xor d( 50) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 32) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 12) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq(100) <= d( 62) xor d( 61) xor d( 59) xor d( 54) xor d( 53) xor d( 50) xor d( 47) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 34) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 24) xor d( 22) xor d( 17) xor d( 16) xor d( 14) xor d( 9) xor d( 8) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq(101) <= d( 63) xor d( 62) xor d( 60) xor d( 55) xor d( 54) xor d( 51) xor d( 48) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 35) xor d( 30) xor d( 29) xor d( 28) xor d( 26) xor d( 25) xor d( 23) xor d( 18) xor d( 17) xor d( 15) xor d( 10) xor d( 9) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq(102) <= d( 63) xor d( 62) xor d( 61) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 11) xor d( 8) xor d( 6) xor d( 3) xor d( 2) xor d( 0);
dq(103) <= d( 63) xor d( 62) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 12) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 1);
dq(104) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 42) xor d( 39) xor d( 38) xor d( 36) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 25) xor d( 24) xor d( 22) xor d( 21) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 6) xor d( 2) xor d( 0);
dq(105) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 50) xor d( 49) xor d( 46) xor d( 45) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 7) xor d( 3) xor d( 1);
dq(106) <= d( 60) xor d( 59) xor d( 57) xor d( 54) xor d( 53) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 31) xor d( 30) xor d( 28) xor d( 27) xor d( 24) xor d( 22) xor d( 21) xor d( 16) xor d( 14) xor d( 13) xor d( 10) xor d( 6) xor d( 5) xor d( 2) xor d( 0);
dq(107) <= d( 61) xor d( 60) xor d( 58) xor d( 55) xor d( 54) xor d( 49) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 29) xor d( 28) xor d( 25) xor d( 23) xor d( 22) xor d( 17) xor d( 15) xor d( 14) xor d( 11) xor d( 7) xor d( 6) xor d( 3) xor d( 1);
dq(108) <= d( 62) xor d( 61) xor d( 59) xor d( 56) xor d( 55) xor d( 50) xor d( 47) xor d( 46) xor d( 45) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 26) xor d( 24) xor d( 23) xor d( 18) xor d( 16) xor d( 15) xor d( 12) xor d( 8) xor d( 7) xor d( 4) xor d( 2);
dq(109) <= d( 63) xor d( 60) xor d( 58) xor d( 57) xor d( 53) xor d( 50) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 31) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 18) xor d( 16) xor d( 14) xor d( 10) xor d( 9) xor d( 6) xor d( 4) xor d( 3) xor d( 0);
dq(110) <= d( 61) xor d( 59) xor d( 58) xor d( 54) xor d( 51) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 32) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 19) xor d( 17) xor d( 15) xor d( 11) xor d( 10) xor d( 7) xor d( 5) xor d( 4) xor d( 1);
dq(111) <= d( 62) xor d( 60) xor d( 59) xor d( 55) xor d( 52) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 20) xor d( 18) xor d( 16) xor d( 12) xor d( 11) xor d( 8) xor d( 6) xor d( 5) xor d( 2);
dq(112) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 51) xor d( 50) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 18) xor d( 14) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 5) xor d( 4) xor d( 3) xor d( 0);
dq(113) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 56) xor d( 53) xor d( 52) xor d( 50) xor d( 48) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 25) xor d( 24) xor d( 22) xor d( 21) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 11) xor d( 9) xor d( 1) xor d( 0);
dq(114) <= d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 39) xor d( 38) xor d( 36) xor d( 32) xor d( 31) xor d( 28) xor d( 25) xor d( 21) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 8) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq(115) <= d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 33) xor d( 32) xor d( 29) xor d( 26) xor d( 22) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 3) xor d( 2) xor d( 1);
dq(116) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 34) xor d( 33) xor d( 30) xor d( 27) xor d( 23) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 10) xor d( 8) xor d( 7) xor d( 6) xor d( 4) xor d( 3) xor d( 2);
dq(117) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 42) xor d( 41) xor d( 39) xor d( 35) xor d( 34) xor d( 31) xor d( 28) xor d( 24) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 11) xor d( 9) xor d( 8) xor d( 7) xor d( 5) xor d( 4) xor d( 3);
dq(118) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 36) xor d( 35) xor d( 32) xor d( 29) xor d( 25) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 6) xor d( 5) xor d( 4);
dq(119) <= d( 63) xor d( 62) xor d( 61) xor d( 59) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 37) xor d( 36) xor d( 33) xor d( 30) xor d( 26) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5);
dq(120) <= d( 63) xor d( 62) xor d( 60) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 45) xor d( 44) xor d( 42) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 27) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 8) xor d( 7) xor d( 6);
dq(121) <= d( 63) xor d( 61) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 46) xor d( 45) xor d( 43) xor d( 39) xor d( 38) xor d( 35) xor d( 32) xor d( 28) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 7);
dq(122) <= d( 57) xor d( 55) xor d( 54) xor d( 51) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 29) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 12) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 0);
dq(123) <= d( 62) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 23) xor d( 22) xor d( 20) xor d( 14) xor d( 8) xor d( 7) xor d( 4) xor d( 1) xor d( 0);
dq(124) <= d( 63) xor d( 62) xor d( 58) xor d( 54) xor d( 52) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 24) xor d( 22) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 10) xor d( 9) xor d( 6) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq(125) <= d( 63) xor d( 59) xor d( 55) xor d( 53) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 25) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 11) xor d( 10) xor d( 7) xor d( 5) xor d( 3) xor d( 2) xor d( 1);
dq(126) <= d( 60) xor d( 56) xor d( 54) xor d( 51) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 26) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 16) xor d( 15) xor d( 12) xor d( 11) xor d( 8) xor d( 6) xor d( 4) xor d( 3) xor d( 2);
dq(127) <= d( 61) xor d( 57) xor d( 55) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 36) xor d( 34) xor d( 33) xor d( 32) xor d( 27) xor d( 25) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 13) xor d( 12) xor d( 9) xor d( 7) xor d( 5) xor d( 4) xor d( 3);
end if;
end process;
process (clk, reset)
begin
if (reset= '1') then
ca <= SEED;
rdy <= '0';
elsif (rising_edge(clk)) then
rdy <= nd_q;
if(nd_q= '1') then
if (fd_q= '1') then
ca( 0) <= SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 92) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(126) xor dq( 0);
ca( 1) <= SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 1);
ca( 2) <= SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 2);
ca( 3) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 85) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 3);
ca( 4) <= SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 86) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 4);
ca( 5) <= SEED( 64) xor SEED( 66) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 90) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(125) xor SEED(127) xor dq( 5);
ca( 6) <= SEED( 65) xor SEED( 67) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(126) xor dq( 6);
ca( 7) <= SEED( 66) xor SEED( 68) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 7);
ca( 8) <= SEED( 67) xor SEED( 69) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor dq( 8);
ca( 9) <= SEED( 64) xor SEED( 69) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(112) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(125) xor dq( 9);
ca( 10) <= SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(124) xor dq( 10);
ca( 11) <= SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(119) xor SEED(125) xor dq( 11);
ca( 12) <= SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(126) xor dq( 12);
ca( 13) <= SEED( 64) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(126) xor SEED(127) xor dq( 13);
ca( 14) <= SEED( 64) xor SEED( 65) xor SEED( 69) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 90) xor SEED( 92) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(106) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 14);
ca( 15) <= SEED( 65) xor SEED( 66) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 91) xor SEED( 93) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 15);
ca( 16) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 94) xor SEED( 97) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 16);
ca( 17) <= SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 95) xor SEED( 98) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 17);
ca( 18) <= SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 96) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 18);
ca( 19) <= SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor dq( 19);
ca( 20) <= SEED( 64) xor SEED( 65) xor SEED( 70) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 88) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 20);
ca( 21) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(103) xor SEED(104) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 21);
ca( 22) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(125) xor dq( 22);
ca( 23) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(125) xor dq( 23);
ca( 24) <= SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(126) xor dq( 24);
ca( 25) <= SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(127) xor dq( 25);
ca( 26) <= SEED( 64) xor SEED( 67) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 93) xor SEED( 96) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(115) xor SEED(118) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 26);
ca( 27) <= SEED( 65) xor SEED( 68) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 87) xor SEED( 94) xor SEED( 97) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(116) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 27);
ca( 28) <= SEED( 66) xor SEED( 69) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 88) xor SEED( 95) xor SEED( 98) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(117) xor SEED(120) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 28);
ca( 29) <= SEED( 67) xor SEED( 70) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 89) xor SEED( 96) xor SEED( 99) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(118) xor SEED(121) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 29);
ca( 30) <= SEED( 68) xor SEED( 71) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 90) xor SEED( 97) xor SEED(100) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(119) xor SEED(122) xor SEED(126) xor SEED(127) xor dq( 30);
ca( 31) <= SEED( 69) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 91) xor SEED( 98) xor SEED(101) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(120) xor SEED(123) xor SEED(127) xor dq( 31);
ca( 32) <= SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 90) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(108) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor dq( 32);
ca( 33) <= SEED( 65) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 91) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(109) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 33);
ca( 34) <= SEED( 64) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(124) xor dq( 34);
ca( 35) <= SEED( 65) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(125) xor dq( 35);
ca( 36) <= SEED( 64) xor SEED( 66) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(125) xor dq( 36);
ca( 37) <= SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 97) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor dq( 37);
ca( 38) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 72) xor SEED( 77) xor SEED( 79) xor SEED( 82) xor SEED( 87) xor SEED( 88) xor SEED( 93) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(126) xor dq( 38);
ca( 39) <= SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 73) xor SEED( 78) xor SEED( 80) xor SEED( 83) xor SEED( 88) xor SEED( 89) xor SEED( 94) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(127) xor dq( 39);
ca( 40) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(126) xor dq( 40);
ca( 41) <= SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 41);
ca( 42) <= SEED( 64) xor SEED( 66) xor SEED( 70) xor SEED( 71) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 42);
ca( 43) <= SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(102) xor SEED(106) xor SEED(107) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 43);
ca( 44) <= SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(107) xor SEED(108) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor dq( 44);
ca( 45) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(124) xor SEED(125) xor dq( 45);
ca( 46) <= SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 70) xor SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(102) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(125) xor dq( 46);
ca( 47) <= SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 71) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(126) xor dq( 47);
ca( 48) <= SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 72) xor SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(127) xor dq( 48);
ca( 49) <= SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 73) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(125) xor dq( 49);
ca( 50) <= SEED( 64) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor dq( 50);
ca( 51) <= SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(103) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 51);
ca( 52) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 71) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 95) xor SEED(100) xor SEED(104) xor SEED(107) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 52);
ca( 53) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 89) xor SEED( 90) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 53);
ca( 54) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 91) xor SEED( 92) xor SEED(100) xor SEED(101) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor dq( 54);
ca( 55) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 55);
ca( 56) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 71) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(107) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 56);
ca( 57) <= SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(108) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 57);
ca( 58) <= SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 58);
ca( 59) <= SEED( 64) xor SEED( 67) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 59);
ca( 60) <= SEED( 64) xor SEED( 65) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 60);
ca( 61) <= SEED( 65) xor SEED( 66) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(126) xor dq( 61);
ca( 62) <= SEED( 66) xor SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 62);
ca( 63) <= SEED( 67) xor SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 63);
ca( 64) <= SEED( 0) xor SEED( 64) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 97) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 64);
ca( 65) <= SEED( 1) xor SEED( 65) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 98) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 65);
ca( 66) <= SEED( 2) xor SEED( 64) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 75) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 66);
ca( 67) <= SEED( 3) xor SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 67);
ca( 68) <= SEED( 4) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 83) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor dq( 68);
ca( 69) <= SEED( 5) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 69);
ca( 70) <= SEED( 6) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 70);
ca( 71) <= SEED( 7) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 71) xor SEED( 73) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(127) xor dq( 71);
ca( 72) <= SEED( 8) xor SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 99) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 72);
ca( 73) <= SEED( 9) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 94) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 73);
ca( 74) <= SEED( 10) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 89) xor SEED( 90) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 74);
ca( 75) <= SEED( 11) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 90) xor SEED( 91) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(107) xor SEED(110) xor SEED(112) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 75);
ca( 76) <= SEED( 12) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 90) xor SEED( 91) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 76);
ca( 77) <= SEED( 13) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 91) xor SEED( 92) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 77);
ca( 78) <= SEED( 14) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 92) xor SEED( 93) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 78);
ca( 79) <= SEED( 15) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 72) xor SEED( 75) xor SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(109) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 79);
ca( 80) <= SEED( 16) xor SEED( 64) xor SEED( 65) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 80);
ca( 81) <= SEED( 17) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 79) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 81);
ca( 82) <= SEED( 18) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(106) xor SEED(111) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 82);
ca( 83) <= SEED( 19) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(112) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 83);
ca( 84) <= SEED( 20) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(113) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 84);
ca( 85) <= SEED( 21) xor SEED( 64) xor SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(127) xor dq( 85);
ca( 86) <= SEED( 22) xor SEED( 65) xor SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor dq( 86);
ca( 87) <= SEED( 23) xor SEED( 66) xor SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor dq( 87);
ca( 88) <= SEED( 24) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 86) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(117) xor SEED(118) xor SEED(124) xor SEED(125) xor dq( 88);
ca( 89) <= SEED( 25) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 87) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(118) xor SEED(119) xor SEED(125) xor SEED(126) xor dq( 89);
ca( 90) <= SEED( 26) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 88) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(119) xor SEED(120) xor SEED(126) xor SEED(127) xor dq( 90);
ca( 91) <= SEED( 27) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 89) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(127) xor dq( 91);
ca( 92) <= SEED( 28) xor SEED( 64) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 92) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(126) xor dq( 92);
ca( 93) <= SEED( 29) xor SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(120) xor SEED(121) xor SEED(126) xor SEED(127) xor dq( 93);
ca( 94) <= SEED( 30) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(126) xor SEED(127) xor dq( 94);
ca( 95) <= SEED( 31) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(127) xor dq( 95);
ca( 96) <= SEED( 32) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(126) xor dq( 96);
ca( 97) <= SEED( 33) xor SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 97);
ca( 98) <= SEED( 34) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 98);
ca( 99) <= SEED( 35) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 99);
ca(100) <= SEED( 36) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 72) xor SEED( 73) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 98) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(111) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(123) xor SEED(125) xor SEED(126) xor dq(100);
ca(101) <= SEED( 37) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 73) xor SEED( 74) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 99) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(124) xor SEED(126) xor SEED(127) xor dq(101);
ca(102) <= SEED( 38) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(102);
ca(103) <= SEED( 39) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(126) xor SEED(127) xor dq(103);
ca(104) <= SEED( 40) xor SEED( 64) xor SEED( 66) xor SEED( 70) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq(104);
ca(105) <= SEED( 41) xor SEED( 65) xor SEED( 67) xor SEED( 71) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq(105);
ca(106) <= SEED( 42) xor SEED( 64) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(124) xor dq(106);
ca(107) <= SEED( 43) xor SEED( 65) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(125) xor dq(107);
ca(108) <= SEED( 44) xor SEED( 66) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(114) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(125) xor SEED(126) xor dq(108);
ca(109) <= SEED( 45) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(114) xor SEED(117) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq(109);
ca(110) <= SEED( 46) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(115) xor SEED(118) xor SEED(122) xor SEED(123) xor SEED(125) xor dq(110);
ca(111) <= SEED( 47) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(116) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(126) xor dq(111);
ca(112) <= SEED( 48) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 78) xor SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(114) xor SEED(115) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(112);
ca(113) <= SEED( 49) xor SEED( 64) xor SEED( 65) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq(113);
ca(114) <= SEED( 50) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 85) xor SEED( 89) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor dq(114);
ca(115) <= SEED( 51) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 86) xor SEED( 90) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor dq(115);
ca(116) <= SEED( 52) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 87) xor SEED( 91) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq(116);
ca(117) <= SEED( 53) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 88) xor SEED( 92) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(117);
ca(118) <= SEED( 54) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 89) xor SEED( 93) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(118);
ca(119) <= SEED( 55) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 90) xor SEED( 94) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(119);
ca(120) <= SEED( 56) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 91) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(124) xor SEED(126) xor SEED(127) xor dq(120);
ca(121) <= SEED( 57) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 92) xor SEED( 96) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(125) xor SEED(127) xor dq(121);
ca(122) <= SEED( 58) xor SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(121) xor dq(122);
ca(123) <= SEED( 59) xor SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 78) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(126) xor dq(123);
ca(124) <= SEED( 60) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 88) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(122) xor SEED(126) xor SEED(127) xor dq(124);
ca(125) <= SEED( 61) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(123) xor SEED(127) xor dq(125);
ca(126) <= SEED( 62) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(118) xor SEED(120) xor SEED(124) xor dq(126);
ca(127) <= SEED( 63) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(121) xor SEED(125) xor dq(127);
oa( 63) <= SEED(127) xor dq( 0);
oa( 62) <= SEED(126) xor dq( 1);
oa( 61) <= SEED(125) xor dq( 2);
oa( 60) <= SEED(124) xor dq( 3);
oa( 59) <= SEED(123) xor SEED(127) xor dq( 4);
oa( 58) <= SEED(122) xor SEED(126) xor SEED(127) xor dq( 5);
oa( 57) <= SEED(121) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 6);
oa( 56) <= SEED(120) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 7);
oa( 55) <= SEED(119) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 8);
oa( 54) <= SEED(118) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 9);
oa( 53) <= SEED(117) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 10);
oa( 52) <= SEED(116) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor dq( 11);
oa( 51) <= SEED(115) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(125) xor dq( 12);
oa( 50) <= SEED(114) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 13);
oa( 49) <= SEED(113) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 14);
oa( 48) <= SEED(112) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(126) xor dq( 15);
oa( 47) <= SEED(111) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(125) xor dq( 16);
oa( 46) <= SEED(110) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 17);
oa( 45) <= SEED(109) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 18);
oa( 44) <= SEED(108) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 19);
oa( 43) <= SEED(107) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 20);
oa( 42) <= SEED(106) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 21);
oa( 41) <= SEED(105) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 22);
oa( 40) <= SEED(104) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 23);
oa( 39) <= SEED(103) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 24);
oa( 38) <= SEED(102) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor dq( 25);
oa( 37) <= SEED(101) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 26);
oa( 36) <= SEED(100) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(126) xor dq( 27);
oa( 35) <= SEED( 99) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(125) xor SEED(127) xor dq( 28);
oa( 34) <= SEED( 98) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(126) xor dq( 29);
oa( 33) <= SEED( 97) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(125) xor dq( 30);
oa( 32) <= SEED( 96) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(124) xor dq( 31);
oa( 31) <= SEED( 95) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(123) xor dq( 32);
oa( 30) <= SEED( 94) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(127) xor dq( 33);
oa( 29) <= SEED( 93) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(119) xor SEED(121) xor SEED(126) xor SEED(127) xor dq( 34);
oa( 28) <= SEED( 92) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(120) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 35);
oa( 27) <= SEED( 91) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 36);
oa( 26) <= SEED( 90) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 37);
oa( 25) <= SEED( 89) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(117) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 38);
oa( 24) <= SEED( 88) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(114) xor SEED(116) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor dq( 39);
oa( 23) <= SEED( 87) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(115) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor dq( 40);
oa( 22) <= SEED( 86) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(114) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor dq( 41);
oa( 21) <= SEED( 85) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(113) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor dq( 42);
oa( 20) <= SEED( 84) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(112) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(127) xor dq( 43);
oa( 19) <= SEED( 83) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(126) xor dq( 44);
oa( 18) <= SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(125) xor SEED(127) xor dq( 45);
oa( 17) <= SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 46);
oa( 16) <= SEED( 80) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(108) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 47);
oa( 15) <= SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(107) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 48);
oa( 14) <= SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(106) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 49);
oa( 13) <= SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(103) xor SEED(105) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 50);
oa( 12) <= SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(104) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 51);
oa( 11) <= SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(103) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 52);
oa( 10) <= SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(102) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 53);
oa( 9) <= SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(101) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 54);
oa( 8) <= SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED(100) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(125) xor dq( 55);
oa( 7) <= SEED( 71) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 99) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 56);
oa( 6) <= SEED( 70) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 96) xor SEED( 98) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(126) xor dq( 57);
oa( 5) <= SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 97) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(127) xor dq( 58);
oa( 4) <= SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 96) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(126) xor dq( 59);
oa( 3) <= SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 95) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(125) xor dq( 60);
oa( 2) <= SEED( 66) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 94) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(124) xor dq( 61);
oa( 1) <= SEED( 65) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 93) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(127) xor dq( 62);
oa( 0) <= SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 92) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(126) xor dq( 63);
else
ca( 0) <= ca( 64) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 92) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(122) xor ca(126) xor dq( 0);
ca( 1) <= ca( 64) xor ca( 65) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(107) xor ca(108) xor ca(109) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(126) xor ca(127) xor dq( 1);
ca( 2) <= ca( 65) xor ca( 66) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(108) xor ca(109) xor ca(110) xor ca(114) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 2);
ca( 3) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 85) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(112) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 3);
ca( 4) <= ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 86) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(113) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 4);
ca( 5) <= ca( 64) xor ca( 66) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 90) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(125) xor ca(127) xor dq( 5);
ca( 6) <= ca( 65) xor ca( 67) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(126) xor dq( 6);
ca( 7) <= ca( 66) xor ca( 68) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 92) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(127) xor dq( 7);
ca( 8) <= ca( 67) xor ca( 69) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 93) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor dq( 8);
ca( 9) <= ca( 64) xor ca( 69) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(112) xor ca(116) xor ca(117) xor ca(119) xor ca(121) xor ca(123) xor ca(125) xor dq( 9);
ca( 10) <= ca( 64) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 95) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(118) xor ca(124) xor dq( 10);
ca( 11) <= ca( 65) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 96) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(119) xor ca(125) xor dq( 11);
ca( 12) <= ca( 66) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(120) xor ca(126) xor dq( 12);
ca( 13) <= ca( 64) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(126) xor ca(127) xor dq( 13);
ca( 14) <= ca( 64) xor ca( 65) xor ca( 69) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 90) xor ca( 92) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(106) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(126) xor ca(127) xor dq( 14);
ca( 15) <= ca( 65) xor ca( 66) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 91) xor ca( 93) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq( 15);
ca( 16) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 94) xor ca( 97) xor ca( 99) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(120) xor ca(121) xor ca(123) xor ca(125) xor ca(126) xor dq( 16);
ca( 17) <= ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 81) xor ca( 82) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 95) xor ca( 98) xor ca(100) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(115) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq( 17);
ca( 18) <= ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 96) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(116) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 18);
ca( 19) <= ca( 64) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(109) xor ca(115) xor ca(116) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor dq( 19);
ca( 20) <= ca( 64) xor ca( 65) xor ca( 70) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 88) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(103) xor ca(106) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 20);
ca( 21) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(103) xor ca(104) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 21);
ca( 22) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(107) xor ca(109) xor ca(111) xor ca(120) xor ca(121) xor ca(124) xor ca(125) xor dq( 22);
ca( 23) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 70) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(125) xor dq( 23);
ca( 24) <= ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(115) xor ca(116) xor ca(118) xor ca(121) xor ca(122) xor ca(126) xor dq( 24);
ca( 25) <= ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(123) xor ca(127) xor dq( 25);
ca( 26) <= ca( 64) xor ca( 67) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 93) xor ca( 96) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(115) xor ca(118) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 26);
ca( 27) <= ca( 65) xor ca( 68) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 87) xor ca( 94) xor ca( 97) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(116) xor ca(119) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 27);
ca( 28) <= ca( 66) xor ca( 69) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 88) xor ca( 95) xor ca( 98) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(117) xor ca(120) xor ca(124) xor ca(125) xor ca(126) xor dq( 28);
ca( 29) <= ca( 67) xor ca( 70) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 89) xor ca( 96) xor ca( 99) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(118) xor ca(121) xor ca(125) xor ca(126) xor ca(127) xor dq( 29);
ca( 30) <= ca( 68) xor ca( 71) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 90) xor ca( 97) xor ca(100) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(119) xor ca(122) xor ca(126) xor ca(127) xor dq( 30);
ca( 31) <= ca( 69) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 91) xor ca( 98) xor ca(101) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(120) xor ca(123) xor ca(127) xor dq( 31);
ca( 32) <= ca( 64) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 90) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(108) xor ca(112) xor ca(113) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor dq( 32);
ca( 33) <= ca( 65) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 91) xor ca( 98) xor ca( 99) xor ca(102) xor ca(103) xor ca(109) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 33);
ca( 34) <= ca( 64) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(119) xor ca(120) xor ca(123) xor ca(124) xor dq( 34);
ca( 35) <= ca( 65) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(110) xor ca(112) xor ca(113) xor ca(120) xor ca(121) xor ca(124) xor ca(125) xor dq( 35);
ca( 36) <= ca( 64) xor ca( 66) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(112) xor ca(113) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(125) xor dq( 36);
ca( 37) <= ca( 64) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 97) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor dq( 37);
ca( 38) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 72) xor ca( 77) xor ca( 79) xor ca( 82) xor ca( 87) xor ca( 88) xor ca( 93) xor ca( 97) xor ca( 99) xor ca(101) xor ca(103) xor ca(104) xor ca(105) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(126) xor dq( 38);
ca( 39) <= ca( 65) xor ca( 66) xor ca( 67) xor ca( 73) xor ca( 78) xor ca( 80) xor ca( 83) xor ca( 88) xor ca( 89) xor ca( 94) xor ca( 98) xor ca(100) xor ca(102) xor ca(104) xor ca(105) xor ca(106) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(127) xor dq( 39);
ca( 40) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(103) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(118) xor ca(121) xor ca(123) xor ca(126) xor dq( 40);
ca( 41) <= ca( 65) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(119) xor ca(122) xor ca(124) xor ca(127) xor dq( 41);
ca( 42) <= ca( 64) xor ca( 66) xor ca( 70) xor ca( 71) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 98) xor ca(100) xor ca(101) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(115) xor ca(117) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 42);
ca( 43) <= ca( 64) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(102) xor ca(106) xor ca(107) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 43);
ca( 44) <= ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(103) xor ca(107) xor ca(108) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor dq( 44);
ca( 45) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 98) xor ca(100) xor ca(101) xor ca(104) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(118) xor ca(119) xor ca(124) xor ca(125) xor dq( 45);
ca( 46) <= ca( 64) xor ca( 65) xor ca( 67) xor ca( 70) xor ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(102) xor ca(105) xor ca(107) xor ca(108) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(125) xor dq( 46);
ca( 47) <= ca( 65) xor ca( 66) xor ca( 68) xor ca( 71) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(103) xor ca(106) xor ca(108) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(126) xor dq( 47);
ca( 48) <= ca( 66) xor ca( 67) xor ca( 69) xor ca( 72) xor ca( 77) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(100) xor ca(104) xor ca(107) xor ca(109) xor ca(110) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(124) xor ca(127) xor dq( 48);
ca( 49) <= ca( 67) xor ca( 68) xor ca( 70) xor ca( 73) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(100) xor ca(101) xor ca(105) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(125) xor dq( 49);
ca( 50) <= ca( 64) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 99) xor ca(100) xor ca(102) xor ca(106) xor ca(107) xor ca(110) xor ca(115) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor dq( 50);
ca( 51) <= ca( 64) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(103) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(123) xor ca(124) xor ca(126) xor dq( 51);
ca( 52) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 71) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 95) xor ca(100) xor ca(104) xor ca(107) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 52);
ca( 53) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 89) xor ca( 90) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 53);
ca( 54) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 91) xor ca( 92) xor ca(100) xor ca(101) xor ca(106) xor ca(107) xor ca(108) xor ca(113) xor ca(115) xor ca(117) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor dq( 54);
ca( 55) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(102) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 55);
ca( 56) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 71) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 97) xor ca(100) xor ca(101) xor ca(103) xor ca(107) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor ca(127) xor dq( 56);
ca( 57) <= ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 72) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(104) xor ca(108) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 57);
ca( 58) <= ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 99) xor ca(102) xor ca(103) xor ca(105) xor ca(109) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 58);
ca( 59) <= ca( 64) xor ca( 67) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 59);
ca( 60) <= ca( 64) xor ca( 65) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(116) xor ca(119) xor ca(121) xor ca(124) xor ca(125) xor ca(127) xor dq( 60);
ca( 61) <= ca( 65) xor ca( 66) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(117) xor ca(120) xor ca(122) xor ca(125) xor ca(126) xor dq( 61);
ca( 62) <= ca( 66) xor ca( 67) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(118) xor ca(121) xor ca(123) xor ca(126) xor ca(127) xor dq( 62);
ca( 63) <= ca( 67) xor ca( 68) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(119) xor ca(122) xor ca(124) xor ca(127) xor dq( 63);
ca( 64) <= ca( 0) xor ca( 64) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 97) xor ca(100) xor ca(102) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 64);
ca( 65) <= ca( 1) xor ca( 65) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 98) xor ca(101) xor ca(103) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 65);
ca( 66) <= ca( 2) xor ca( 64) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 75) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 93) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(120) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 66);
ca( 67) <= ca( 3) xor ca( 64) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(108) xor ca(110) xor ca(111) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 67);
ca( 68) <= ca( 4) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 83) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(114) xor ca(115) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor dq( 68);
ca( 69) <= ca( 5) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(121) xor ca(124) xor ca(125) xor ca(126) xor dq( 69);
ca( 70) <= ca( 6) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq( 70);
ca( 71) <= ca( 7) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 71) xor ca( 73) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(122) xor ca(123) xor ca(127) xor dq( 71);
ca( 72) <= ca( 8) xor ca( 64) xor ca( 65) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 99) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 72);
ca( 73) <= ca( 9) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 94) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(119) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 73);
ca( 74) <= ca( 10) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 89) xor ca( 90) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(106) xor ca(109) xor ca(111) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 74);
ca( 75) <= ca( 11) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 90) xor ca( 91) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(107) xor ca(110) xor ca(112) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 75);
ca( 76) <= ca( 12) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 90) xor ca( 91) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(122) xor ca(124) xor ca(125) xor ca(127) xor dq( 76);
ca( 77) <= ca( 13) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 91) xor ca( 92) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(121) xor ca(123) xor ca(125) xor ca(126) xor dq( 77);
ca( 78) <= ca( 14) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 92) xor ca( 93) xor ca(100) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq( 78);
ca( 79) <= ca( 15) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 72) xor ca( 75) xor ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(103) xor ca(104) xor ca(105) xor ca(109) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 79);
ca( 80) <= ca( 16) xor ca( 64) xor ca( 65) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 80);
ca( 81) <= ca( 17) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 79) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(102) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 81);
ca( 82) <= ca( 18) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(106) xor ca(111) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 82);
ca( 83) <= ca( 19) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(107) xor ca(112) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(124) xor ca(125) xor ca(126) xor dq( 83);
ca( 84) <= ca( 20) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(108) xor ca(113) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq( 84);
ca( 85) <= ca( 21) xor ca( 64) xor ca( 67) xor ca( 71) xor ca( 72) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(117) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(127) xor dq( 85);
ca( 86) <= ca( 22) xor ca( 65) xor ca( 68) xor ca( 72) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor dq( 86);
ca( 87) <= ca( 23) xor ca( 66) xor ca( 69) xor ca( 73) xor ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(117) xor ca(119) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor dq( 87);
ca( 88) <= ca( 24) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 86) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(111) xor ca(112) xor ca(113) xor ca(117) xor ca(118) xor ca(124) xor ca(125) xor dq( 88);
ca( 89) <= ca( 25) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 87) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(112) xor ca(113) xor ca(114) xor ca(118) xor ca(119) xor ca(125) xor ca(126) xor dq( 89);
ca( 90) <= ca( 26) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 88) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(106) xor ca(107) xor ca(108) xor ca(113) xor ca(114) xor ca(115) xor ca(119) xor ca(120) xor ca(126) xor ca(127) xor dq( 90);
ca( 91) <= ca( 27) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 89) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(114) xor ca(115) xor ca(116) xor ca(120) xor ca(121) xor ca(127) xor dq( 91);
ca( 92) <= ca( 28) xor ca( 64) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 92) xor ca(100) xor ca(102) xor ca(103) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(120) xor ca(121) xor ca(126) xor dq( 92);
ca( 93) <= ca( 29) xor ca( 64) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(120) xor ca(121) xor ca(126) xor ca(127) xor dq( 93);
ca( 94) <= ca( 30) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(108) xor ca(110) xor ca(117) xor ca(120) xor ca(121) xor ca(126) xor ca(127) xor dq( 94);
ca( 95) <= ca( 31) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(118) xor ca(121) xor ca(122) xor ca(127) xor dq( 95);
ca( 96) <= ca( 32) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(106) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(117) xor ca(119) xor ca(120) xor ca(123) xor ca(126) xor dq( 96);
ca( 97) <= ca( 33) xor ca( 64) xor ca( 65) xor ca( 67) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(109) xor ca(111) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq( 97);
ca( 98) <= ca( 34) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(109) xor ca(111) xor ca(114) xor ca(118) xor ca(119) xor ca(120) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 98);
ca( 99) <= ca( 35) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 96) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(114) xor ca(117) xor ca(119) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq( 99);
ca(100) <= ca( 36) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 72) xor ca( 73) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 98) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(111) xor ca(114) xor ca(117) xor ca(118) xor ca(123) xor ca(125) xor ca(126) xor dq(100);
ca(101) <= ca( 37) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 73) xor ca( 74) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 99) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(112) xor ca(115) xor ca(118) xor ca(119) xor ca(124) xor ca(126) xor ca(127) xor dq(101);
ca(102) <= ca( 38) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq(102);
ca(103) <= ca( 39) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(126) xor ca(127) xor dq(103);
ca(104) <= ca( 40) xor ca( 64) xor ca( 66) xor ca( 70) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(100) xor ca(102) xor ca(103) xor ca(106) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq(104);
ca(105) <= ca( 41) xor ca( 65) xor ca( 67) xor ca( 71) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(109) xor ca(110) xor ca(113) xor ca(114) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq(105);
ca(106) <= ca( 42) xor ca( 64) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(117) xor ca(118) xor ca(121) xor ca(123) xor ca(124) xor dq(106);
ca(107) <= ca( 43) xor ca( 65) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(118) xor ca(119) xor ca(122) xor ca(124) xor ca(125) xor dq(107);
ca(108) <= ca( 44) xor ca( 66) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(114) xor ca(119) xor ca(120) xor ca(123) xor ca(125) xor ca(126) xor dq(108);
ca(109) <= ca( 45) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 95) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(114) xor ca(117) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq(109);
ca(110) <= ca( 46) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 96) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(115) xor ca(118) xor ca(122) xor ca(123) xor ca(125) xor dq(110);
ca(111) <= ca( 47) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(116) xor ca(119) xor ca(123) xor ca(124) xor ca(126) xor dq(111);
ca(112) <= ca( 48) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 78) xor ca( 82) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(114) xor ca(115) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq(112);
ca(113) <= ca( 49) xor ca( 64) xor ca( 65) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(112) xor ca(114) xor ca(116) xor ca(117) xor ca(120) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq(113);
ca(114) <= ca( 50) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 85) xor ca( 89) xor ca( 92) xor ca( 95) xor ca( 96) xor ca(100) xor ca(102) xor ca(103) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor dq(114);
ca(115) <= ca( 51) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 86) xor ca( 90) xor ca( 93) xor ca( 96) xor ca( 97) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor dq(115);
ca(116) <= ca( 52) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 87) xor ca( 91) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq(116);
ca(117) <= ca( 53) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 88) xor ca( 92) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(103) xor ca(105) xor ca(106) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq(117);
ca(118) <= ca( 54) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 89) xor ca( 93) xor ca( 96) xor ca( 99) xor ca(100) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq(118);
ca(119) <= ca( 55) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 90) xor ca( 94) xor ca( 97) xor ca(100) xor ca(101) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq(119);
ca(120) <= ca( 56) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 91) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(106) xor ca(108) xor ca(109) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(124) xor ca(126) xor ca(127) xor dq(120);
ca(121) <= ca( 57) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 92) xor ca( 96) xor ca( 99) xor ca(102) xor ca(103) xor ca(107) xor ca(109) xor ca(110) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(125) xor ca(127) xor dq(121);
ca(122) <= ca( 58) xor ca( 64) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(115) xor ca(118) xor ca(119) xor ca(121) xor dq(122);
ca(123) <= ca( 59) xor ca( 64) xor ca( 65) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 78) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(126) xor dq(123);
ca(124) <= ca( 60) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 88) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(116) xor ca(118) xor ca(122) xor ca(126) xor ca(127) xor dq(124);
ca(125) <= ca( 61) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(117) xor ca(119) xor ca(123) xor ca(127) xor dq(125);
ca(126) <= ca( 62) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(115) xor ca(118) xor ca(120) xor ca(124) xor dq(126);
ca(127) <= ca( 63) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(119) xor ca(121) xor ca(125) xor dq(127);
oa( 63) <= ca(127) xor dq( 0);
oa( 62) <= ca(126) xor dq( 1);
oa( 61) <= ca(125) xor dq( 2);
oa( 60) <= ca(124) xor dq( 3);
oa( 59) <= ca(123) xor ca(127) xor dq( 4);
oa( 58) <= ca(122) xor ca(126) xor ca(127) xor dq( 5);
oa( 57) <= ca(121) xor ca(125) xor ca(126) xor ca(127) xor dq( 6);
oa( 56) <= ca(120) xor ca(124) xor ca(125) xor ca(126) xor dq( 7);
oa( 55) <= ca(119) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 8);
oa( 54) <= ca(118) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 9);
oa( 53) <= ca(117) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 10);
oa( 52) <= ca(116) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor dq( 11);
oa( 51) <= ca(115) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(125) xor dq( 12);
oa( 50) <= ca(114) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(124) xor ca(127) xor dq( 13);
oa( 49) <= ca(113) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(123) xor ca(126) xor ca(127) xor dq( 14);
oa( 48) <= ca(112) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(122) xor ca(125) xor ca(126) xor dq( 15);
oa( 47) <= ca(111) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(121) xor ca(124) xor ca(125) xor dq( 16);
oa( 46) <= ca(110) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(120) xor ca(123) xor ca(124) xor ca(127) xor dq( 17);
oa( 45) <= ca(109) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(119) xor ca(122) xor ca(123) xor ca(126) xor ca(127) xor dq( 18);
oa( 44) <= ca(108) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(121) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq( 19);
oa( 43) <= ca(107) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(124) xor ca(125) xor ca(126) xor dq( 20);
oa( 42) <= ca(106) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(119) xor ca(120) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 21);
oa( 41) <= ca(105) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(118) xor ca(119) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 22);
oa( 40) <= ca(104) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(117) xor ca(118) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 23);
oa( 39) <= ca(103) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(116) xor ca(117) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor dq( 24);
oa( 38) <= ca(102) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(112) xor ca(115) xor ca(116) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor dq( 25);
oa( 37) <= ca(101) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 26);
oa( 36) <= ca(100) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(110) xor ca(113) xor ca(114) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(126) xor dq( 27);
oa( 35) <= ca( 99) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(109) xor ca(112) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(125) xor ca(127) xor dq( 28);
oa( 34) <= ca( 98) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(108) xor ca(111) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(124) xor ca(126) xor dq( 29);
oa( 33) <= ca( 97) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(107) xor ca(110) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(123) xor ca(125) xor dq( 30);
oa( 32) <= ca( 96) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(106) xor ca(109) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(122) xor ca(124) xor dq( 31);
oa( 31) <= ca( 95) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(105) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(121) xor ca(123) xor dq( 32);
oa( 30) <= ca( 94) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(104) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(117) xor ca(120) xor ca(122) xor ca(127) xor dq( 33);
oa( 29) <= ca( 93) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(119) xor ca(121) xor ca(126) xor ca(127) xor dq( 34);
oa( 28) <= ca( 92) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(118) xor ca(120) xor ca(125) xor ca(126) xor ca(127) xor dq( 35);
oa( 27) <= ca( 91) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(117) xor ca(119) xor ca(124) xor ca(125) xor ca(126) xor dq( 36);
oa( 26) <= ca( 90) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(100) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 37);
oa( 25) <= ca( 89) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 99) xor ca(102) xor ca(103) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(117) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 38);
oa( 24) <= ca( 88) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 98) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(114) xor ca(116) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor dq( 39);
oa( 23) <= ca( 87) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 97) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(115) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor dq( 40);
oa( 22) <= ca( 86) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 99) xor ca(100) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(114) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor dq( 41);
oa( 21) <= ca( 85) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(113) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor dq( 42);
oa( 20) <= ca( 84) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(112) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(127) xor dq( 43);
oa( 19) <= ca( 83) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(126) xor dq( 44);
oa( 18) <= ca( 82) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(110) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(125) xor ca(127) xor dq( 45);
oa( 17) <= ca( 81) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(109) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(124) xor ca(126) xor ca(127) xor dq( 46);
oa( 16) <= ca( 80) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(106) xor ca(108) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 47);
oa( 15) <= ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(107) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 48);
oa( 14) <= ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(100) xor ca(101) xor ca(104) xor ca(106) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 49);
oa( 13) <= ca( 77) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(100) xor ca(103) xor ca(105) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 50);
oa( 12) <= ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(102) xor ca(104) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 51);
oa( 11) <= ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(103) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 52);
oa( 10) <= ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(102) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor ca(127) xor dq( 53);
oa( 9) <= ca( 73) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(101) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(126) xor dq( 54);
oa( 8) <= ca( 72) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 98) xor ca(100) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(125) xor dq( 55);
oa( 7) <= ca( 71) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 99) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq( 56);
oa( 6) <= ca( 70) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 96) xor ca( 98) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(113) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(123) xor ca(126) xor dq( 57);
oa( 5) <= ca( 69) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 97) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(122) xor ca(125) xor ca(127) xor dq( 58);
oa( 4) <= ca( 68) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 96) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(121) xor ca(124) xor ca(126) xor dq( 59);
oa( 3) <= ca( 67) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 95) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(125) xor dq( 60);
oa( 2) <= ca( 66) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 94) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(124) xor dq( 61);
oa( 1) <= ca( 65) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 93) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(118) xor ca(121) xor ca(123) xor ca(127) xor dq( 62);
oa( 0) <= ca( 64) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 92) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(122) xor ca(126) xor dq( 63);
end if;
end if;
end if;
end process;
c <= ca;
o <= oa;
end bch_128x64;
|
gpl-2.0
|
fb6ccce8c0f5c5e66a3a49799ac90a15
| 0.603511 | 2.45217 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1273/tb_assert2.vhdl
| 1 | 460 |
entity tb_assert2 is
end tb_assert2;
architecture behav of tb_assert2 is
signal v, res : natural;
signal en : boolean := false;
begin
dut: entity work.assert2
port map (v, en, res);
process
begin
en <= True;
v <= 2;
wait for 1 ns;
assert res = 3 severity failure;
v <= 11;
en <= False;
wait for 1 ns;
assert res = 0 severity failure;
-- wait for 10 ns;
-- en <= True;
wait;
end process;
end behav;
|
gpl-2.0
|
263059c7079ea6dba1140c810a352623
| 0.593478 | 3.309353 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1096.vhd
| 4 | 2,071 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1096.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01096ent IS
END c06s05b00x00p03n01i01096ent;
ARCHITECTURE c06s05b00x00p03n01i01096arch OF c06s05b00x00p03n01i01096ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V2 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (3 to 3);
-- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01096 - Prefix of a slice must be appropraite for a one-dimensional array object."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01096arch;
|
gpl-2.0
|
830fd67ad810166ff7cfcedb920d59ef
| 0.66055 | 3.639719 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/dff02/tb_dff08d.vhdl
| 1 | 994 |
entity tb_dff08d is
end tb_dff08d;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08d is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff08d
port map (
q => dout,
d => din,
en => en,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = x"aa" severity failure;
rst <= '1';
pulse;
assert dout = x"aa" severity failure;
rst <= '0';
din <= x"38";
pulse;
assert dout = x"38" severity failure;
din <= x"af";
pulse;
assert dout = x"af" severity failure;
en <= '1';
rst <= '1';
din <= x"b5";
pulse;
assert dout = x"aa" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
b8472d88cb839f1bd1740036c329d669
| 0.555332 | 3.269737 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/if01/tb_if01.vhdl
| 1 | 621 |
entity tb_if01 is
end tb_if01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_if01 is
signal c0, c1 : std_logic;
signal r : std_logic;
begin
dut: entity work.if01
port map (c0, c1, r);
process
begin
c0 <= '1';
c1 <= '0';
wait for 1 ns;
assert r = '0' severity failure;
c0 <= '0';
c1 <= '0';
wait for 1 ns;
assert r = '0' severity failure;
c0 <= '1';
c1 <= '1';
wait for 1 ns;
assert r = '1' severity failure;
c0 <= '0';
c1 <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
20dcc4e1db924d622f850f80e6ca683f
| 0.547504 | 2.848624 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue807/reproct.vhdl
| 1 | 1,324 |
entity reproct is
generic ( lowb : integer := 1 ;
highb : integer := 10 ;
lowb_i2 : integer := 0 ;
highb_i2 : integer := 1000 );
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
end;
architecture ARCH of reproct is
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
begin
L1:
block
port (i_t_rec1_1 : inout t_rec1 := c_st_rec1_1 ) ;
port map (i_t_rec1_1) ;
begin
i_t_rec1_1 <= c_st_rec1_2 ;
end block L1 ;
end ARCH ;
|
gpl-2.0
|
3a8e5df04b7c8a30e3cad3c645566efb
| 0.518127 | 2.835118 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd
| 4 | 1,551 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity std_logic_to_analog is
port ( d : in std_logic;
terminal a : electrical );
end entity std_logic_to_analog;
----------------------------------------------------------------
architecture ideal of std_logic_to_analog is
constant v_low : real := 0.0;
constant v_high : real := 5.0;
constant v_unknown : real := 2.0;
signal v_in : real := 0.0;
quantity v_out across i_out through a to electrical_ref;
begin
v_in <= v_high when d = '1' or d = 'H' else
v_low when d = '0' or d = 'L' else
v_unknown;
v_out == v_in'slew(2.0e+9, -1.0e+9);
end architecture ideal;
|
gpl-2.0
|
24bfe8ec76e38802b4015873a95ecb19
| 0.650548 | 3.728365 | false | false | false | false |
nickg/nvc
|
test/regress/issue434.vhd
| 1 | 3,533 |
-- test_ng.vhd
library ieee;
use ieee.std_logic_1164.all;
entity SAMPLE is
generic (
WORD_BITS : integer := 8;
STRB_BITS : integer := 1;
O_WIDTH : integer := 1;
QUEUE_SIZE : integer := 3
);
port (
CLK : in std_logic;
RST : in std_logic;
O_DATA : out std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0);
O_STRB : out std_logic_vector(O_WIDTH*STRB_BITS-1 downto 0);
O_VAL : out std_logic;
O_RDY : in std_logic
);
end entity;
architecture RTL of SAMPLE is
type WORD_TYPE is record
DATA : std_logic_vector(WORD_BITS-1 downto 0);
STRB : std_logic_vector(STRB_BITS-1 downto 0);
VAL : boolean;
end record;
constant WORD_NULL : WORD_TYPE := (DATA => (others => '0'),
STRB => (others => '0'),
VAL => FALSE);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
signal curr_queue : WORD_VECTOR(0 to QUEUE_SIZE-1);
begin
curr_queue <= (others => WORD_NULL);
process (curr_queue) begin
for i in 0 to O_WIDTH-1 loop
O_DATA((i+1)*WORD_BITS-1 downto i*WORD_BITS) <= curr_queue(i).DATA;
O_STRB((i+1)*STRB_BITS-1 downto i*STRB_BITS) <= curr_queue(i).STRB;
end loop;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
entity issue434 is
end entity;
architecture MODEL of issue434 is
constant PERIOD : time := 10 ns;
constant DELAY : time := 1 ns;
constant WORD_BITS : integer := 8;
constant STRB_BITS : integer := WORD_BITS/8;
constant O_WIDTH : integer := 2;
constant QUEUE_SIZE : integer := 4;
signal CLK_ENA : std_logic;
signal CLK : std_logic;
signal RST : std_logic;
signal O_DATA : std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0);
signal O_STRB : std_logic_vector(O_WIDTH*STRB_BITS-1 downto 0);
signal O_VAL : std_logic;
signal O_RDY : std_logic;
begin
DUT: entity WORK.SAMPLE
generic map (
WORD_BITS => WORD_BITS ,
STRB_BITS => STRB_BITS ,
O_WIDTH => O_WIDTH ,
QUEUE_SIZE => QUEUE_SIZE
)
port map(
CLK => CLK ,
RST => RST ,
O_DATA => O_DATA ,
O_STRB => O_STRB ,
O_VAL => O_VAL ,
O_RDY => O_RDY
);
process begin
loop
CLK <= '1'; wait for PERIOD/2;
CLK <= '0'; wait for PERIOD/2;
exit when(CLK_ENA = '0');
end loop;
CLK <= '0';
wait;
end process;
process
procedure WAIT_CLK(CNT:integer) is
begin
if (CNT > 0) then
for i in 1 to CNT loop
wait until (CLK'event and CLK = '1');
end loop;
end if;
wait for DELAY;
end WAIT_CLK;
begin
CLK_ENA <= '1';
RST <= '1';
O_RDY <= '0';
WAIT_CLK(1);
RST <= '0';
WAIT_CLK(10);
CLK_ENA <= '0';
assert o_data = X"0000";
wait;
end process;
end MODEL;
|
gpl-3.0
|
b933bc65803c6d1ff08b73f0861fbfb3
| 0.453156 | 3.649793 | false | false | false | false |
nickg/nvc
|
test/regress/attr16.vhd
| 1 | 554 |
entity attr16 is
end entity;
architecture test of attr16 is
type int_vec_2d is array (natural range <>, natural range <>) of integer;
signal s1, s2 : integer_vector(1 to 5) := (others => 0);
signal s3, s4 : int_vec_2d(1 to 2, 5 to 5) := (others => (others => 0));
begin
check: process is
begin
assert s1'range(1)'low = 1;
assert s1'range(1)'right = 5;
assert s3'range(1)'left = 1;
assert s3'range(2)'left = 5;
assert s3'range(2)'right = 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
58f36bc53d65f187938ae35a6b56cea6
| 0.583032 | 3.129944 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/cnt01/tb_cnt04.vhdl
| 1 | 687 |
entity tb_cnt04 is
end tb_cnt04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cnt04 is
signal clk : std_logic;
signal rst : std_logic;
signal counter : std_logic_vector (7 downto 0);
begin
dut: entity work.cnt04
port map (clk => clk, rst => rst, counter => counter);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert counter = x"01" severity failure;
rst <= '0';
pulse;
assert counter = x"02" severity failure;
pulse;
assert counter = x"03" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
d0f77e1bcb09fdd07be04c6175a34920
| 0.608443 | 3.435 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1069/ram5.vhdl
| 1 | 1,662 |
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH : positive := 7;
WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH - 1 downto 0);
clk_b : in std_logic;
read_b : in std_logic;
write_b : in std_logic;
addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
variable store : ram_t := (others => (others => '0'));
begin
if rising_edge(clk_a) then
if write_a = '1' then
store(to_integer(unsigned(addr_a))) := data_write_a;
end if;
if read_a = '1' then
data_read_a <= store(to_integer(unsigned(addr_a)));
end if;
end if;
if rising_edge(clk_b) then
if write_b = '1' then
store(to_integer(unsigned(addr_b))) := data_write_b;
end if;
if read_b = '1' then
data_read_b <= store(to_integer(unsigned(addr_b)));
end if;
end if;
end process;
end behavioral;
|
gpl-2.0
|
11d3736ec21179722ff5112242cafe29
| 0.524669 | 3.324 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/oper01/snum05.vhdl
| 1 | 630 |
entity snum05 is
port (ok : out boolean);
end snum05;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum05 is
-- add uns nat
constant a1 : signed (7 downto 0) := x"1d";
constant b1 : signed (3 downto 0) := x"5";
constant r1 : signed (11 downto 0) := a1 * b1;
signal er1 : signed (11 downto 0) := x"091";
constant a2 : signed (7 downto 0) := x"fe";
constant b2 : signed (3 downto 0) := x"f";
constant r2 : signed (11 downto 0) := a2 * b2;
signal er2 : signed (11 downto 0) := x"002";
begin
-- ok <= r1 = x"20";
ok <= r1 = er1 and r2 = er2;
end behav;
|
gpl-2.0
|
f9aa7c35766dc63a264989bb9663c66f
| 0.607937 | 2.787611 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd
| 4 | 2,629 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_address_decoder is
end entity tb_address_decoder;
architecture test of tb_address_decoder is
use work.cpu_types.all;
signal addr : address := X"000000";
signal status : status_value := idle;
signal mem_sel, int_sel, io_sel : bit;
begin
dut : entity work.address_decoder
port map ( addr => addr, status => status,
mem_sel => mem_sel, int_sel => int_sel, io_sel => io_sel );
stimulus : process is
begin
wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
addr <= X"EFFFFF"; wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
addr <= X"F00000"; wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
addr <= X"FFFFFF"; wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
7ff9a06e89c63343688d77f0529a0884
| 0.628376 | 3.631215 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug049/rng1.vhdl
| 2 | 1,353 |
use std.textio.all;
entity sliding_index is
end entity;
architecture foo of sliding_index is
type integer_vector is array (natural range <>) of integer;
function to_string(inp: integer_vector) return string is
variable retn: line;
begin
for i in inp'range loop
if i = inp'RIGHT then
write (retn, integer'image(inp(i)));
else
write (retn, integer'image(inp(i)) & ',');
end if;
end loop;
return retn(1 to retn'length); -- the string value of the line
end function;
constant ivec: integer_vector := (1,2,3,4,5,6,7);
signal sum: integer_vector (ivec'range);
-- signal sum: integer_vector (0 to 6);
begin
sum <= (
0 => ( ivec(0) + ivec(1)),
1 => (ivec(0) + ivec(1) + ivec(2)),
2 => (ivec(1) + ivec(2) + ivec(3)),
3 => (ivec(2) + ivec(3) + ivec(4)),
4 => (ivec(3) + ivec(4) + ivec(5)),
5 => (ivec(4) + ivec(5) + ivec(6)),
6 => (ivec(5) + ivec(6) )
);
process
begin
wait for 0 ns;
report "ivec = " & to_string(ivec);
report "sum = " & to_string(sum);
wait;
end process;
end architecture;
|
gpl-2.0
|
2d250d2b1cede9981215e3d591d58d7d
| 0.469327 | 3.637097 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/ticket11/tb3.vhdl
| 3 | 561 |
entity tb3 is
end entity;
architecture arch of tb3 is
signal s: integer := 0;
begin
process is
begin
wait for 1 us;
s <= 1;
s <= reject 1 ns inertial 2 after 2 us;
assert s = 0;
wait on s;
report "s = " & integer'image(s);
assert s = 1 severity failure;
assert now = 1 us severity failure;
wait on s;
report "s = " & integer'image(s);
assert s = 2 severity failure;
assert now = 3 us severity failure;
wait;
end process;
end architecture;
|
gpl-2.0
|
5aea5416e38bf35d94318b7865dfc958
| 0.547237 | 3.923077 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_sfifo_autord.vhd
| 7 | 23,020 |
-------------------------------------------------------------------------------
-- axi_datamover_sfifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_datamover_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_datamover_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
NON_BLK_MEM : if (C_USE_BLKMEM = 0)
generate
fifo_read_enable <= SFIFO_Rd_en or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH
-- C_PRELOAD_REGS => 0, -- 1 = first word fall through
-- C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate NON_BLK_MEM;
BLK_MEM : if (C_USE_BLKMEM = 1)
generate
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
end generate BLK_MEM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
gpl-3.0
|
1db7830fa3eeb7091385b4ede6039090
| 0.412554 | 4.925118 | false | false | false | false |
nickg/nvc
|
test/regress/wait24.vhd
| 1 | 516 |
library nvc;
use nvc.sim_pkg.all;
entity wait24 is
end entity;
architecture test of wait24 is
begin
p1: process is
begin
assert now = 0 ns;
assert current_delta_cycle = 0;
wait for 0 ns;
assert now = 0 ns;
assert current_delta_cycle = 1;
for i in 1 to 5 loop
wait for 0 ns;
end loop;
assert current_delta_cycle = 6;
wait for 1 ps;
assert current_delta_cycle = 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
f36a71f0178917002db0a1b111def894
| 0.571705 | 3.73913 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/non_compliant/ch_02_ch_02_01.vhd
| 3 | 14,390 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_02_ch_02_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_02_01 is
end entity ch_02_01;
----------------------------------------------------------------
architecture test of ch_02_01 is
begin
section_2_1_a : process is
-- code from book:
constant number_of_bytes : integer := 4;
constant number_of_bits : integer := 8 * number_of_bytes;
constant e : real := 2.718281828;
constant prop_delay : time := 3 ns;
constant size_limit, count_limit : integer := 255;
--
variable index : integer := 0;
variable sum, average, largest : real;
variable start, finish : time := 0 ns;
-- end of code from book
begin
wait;
end process section_2_1_a;
----------------
section_2_1_b : process is
-- code from book:
variable start : time := 0 ns;
variable finish : time := 0 ns;
-- end of code from book
variable program_counter : integer;
variable index : integer;
begin
-- code from book:
program_counter := 0;
index := index + 1;
-- end of code from book
wait;
end process section_2_1_b;
----------------
section_2_2_a : process is
-- code from book:
type apples is range 0 to 100;
type oranges is range 0 to 100;
--
type day_of_month is range 0 to 31;
type year is range 0 to 2100;
variable today : day_of_month := 9;
variable start_year : year := 1987;
--
constant number_of_bits : integer := 32;
type bit_index is range 0 to number_of_bits - 1;
--
type set_index_range is range 21 downto 11;
type mode_pos_range is range 5 to 7;
variable set_index : set_index_range;
variable mode_pos : mode_pos_range;
--
type input_level is range -10.0 to +10.0;
type probability is range 0.0 to 1.0;
--
variable input_A : input_level;
-- end of code from book
begin
-- code from book:
-- error: Incompatible types for assignment
-- start_year := today;
-- end of code from book
wait;
end process section_2_2_a;
----------------
section_2_2_b : process is
-- code from book:
type resistance is range 0 to 1E9
units
ohm;
end units resistance;
-- end of code from book
begin
wait;
end process section_2_2_b;
----------------
section_2_2_c : process is
-- code from book:
type resistance is range 0 to 1E9
units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units resistance;
-- end of code from book
begin
wait;
end process section_2_2_c;
----------------
section_2_2_d : process is
-- code from book:
type length is range 0 to 1E9
units
um; -- primary unit: micron
mm = 1000 um; -- metric units
m = 1000 mm;
mil = 254 um; -- imperial units
inch = 1000 mil;
end units length;
-- end of code from book
begin
wait;
end process section_2_2_d;
----------------
section_2_2_e : process is
-- code from book:
-- type time is range implementation_defined
type time is range integer'low to integer'high
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
-- end of code from book
begin
wait;
end process section_2_2_e;
----------------
section_2_2_f : process is
-- code from book:
type alu_function is (disable, pass, add, subtract, multiply, divide);
--
type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
--
variable alu_op : alu_function;
variable last_digit : octal_digit := '0';
--
type logic_level is (unknown, low, undriven, high);
variable control : logic_level;
type water_level is (dangerously_low, low, ok);
variable water_sensor : water_level;
-- end of code from book
begin
-- code from book:
alu_op := subtract;
last_digit := '7';
--
control := low;
water_sensor := low;
-- end of code from book
wait;
end process section_2_2_f;
----------------
section_2_2_g : process is
-- code from book:
type severity_level is (note, warning, error, failure);
-- end of code from book
begin
wait;
end process section_2_2_g;
----------------
section_2_2_h : process is
-- code from book:
variable cmd_char, terminator : character;
-- end of code from book
begin
-- code from book:
cmd_char := 'P';
terminator := cr;
-- end of code from book
wait;
end process section_2_2_h;
----------------
section_2_2_i : process is
-- code from book:
type boolean is (false, true);
--
type bit is ('0', '1');
-- end of code from book
begin
wait;
end process section_2_2_i;
----------------
section_2_2_j : process is
variable write_enable_n, select_reg_n, write_reg_n : bit;
begin
-- code from book:
write_reg_n := not ( not write_enable_n and not select_reg_n );
-- end of code from book
wait;
end process section_2_2_j;
----------------
section_2_2_k : process is
-- code from book:
type std_ulogic is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing zero
'1', -- Forcing one
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak zero
'H', -- Weak one
'-' ); -- Don't care
-- end of code from book
begin
wait;
end process section_2_2_k;
----------------
section_2_3_a : process is
-- code from book:
subtype small_int is integer range -128 to 127;
--
variable deviation : small_int;
variable adjustment : integer;
--
subtype bit_index is integer range 31 downto 0;
-- end of code from book
begin
deviation := 0;
adjustment := 0;
-- code from book:
deviation := deviation + adjustment;
-- end of code from book
wait;
end process section_2_3_a;
----------------
section_2_3_b : process is
constant highest_integer : integer := integer'high;
constant highest_time : time := time'high;
-- code from book:
subtype natural is integer range 0 to highest_integer;
subtype positive is integer range 1 to highest_integer;
--
subtype delay_length is time range 0 fs to highest_time;
-- end of code from book
begin
wait;
end process section_2_3_b;
----------------
section_2_3_c : process is
-- code from book:
type logic_level is (unknown, low, undriven, high);
type system_state is (unknown, ready, busy);
--
subtype valid_level is logic_level range low to high;
-- end of code from book
begin
wait;
end process section_2_3_c;
----------------
section_2_4_a : process is
-- code from book:
type resistance is range 0 to 1E9
units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units resistance;
type set_index_range is range 21 downto 11;
type logic_level is (unknown, low, undriven, high);
-- end of code from book
begin
-- output from vsim: "2000"
report resistance'image(2 kohm);
-- code from book:
assert resistance'left = 0 ohm;
assert resistance'right = 1E9 ohm;
assert resistance'low = 0 ohm;
assert resistance'high = 1E9 ohm;
assert resistance'ascending = true;
assert resistance'image(2 kohm) = "2000 ohm";
assert resistance'value("5 Mohm") = 5_000_000 ohm;
assert set_index_range'left = 21;
assert set_index_range'right = 11;
assert set_index_range'low = 11;
assert set_index_range'high = 21;
assert set_index_range'ascending = false;
assert set_index_range'image(14) = "14";
assert set_index_range'value("20") = 20;
assert logic_level'left = unknown;
assert logic_level'right = high;
assert logic_level'low = unknown;
assert logic_level'high = high;
assert logic_level'ascending = true;
assert logic_level'image(undriven) = "undriven";
assert logic_level'value("Low") = low;
--
assert logic_level'pos(unknown) = 0;
assert logic_level'val(3) = high;
assert logic_level'succ(unknown) = low;
assert logic_level'pred(undriven) = low;
--
assert time'pos(4 ns) = 4_000_000;
-- end of code from book
wait;
end process section_2_4_a;
----------------
section_2_4_b : process is
-- code from book:
type length is range integer'low to integer'high
units
mm;
end units length;
type area is range integer'low to integer'high
units
square_mm;
end units area;
--
variable L1, L2 : length;
variable A : area;
-- end of code from book
begin
-- TG: avoid overflow in multiplication
L1 := 1 mm;
-- code from book:
-- error: No feasible entries for infix op: "*"
-- A := L1 * L2; -- this is incorrect
--
A := area'val( length'pos(L1) * length'pos(L2) );
-- end of code from book
wait;
end process section_2_4_b;
----------------
section_2_4_c : process is
-- code from book:
type opcode is (nop, load, store, add, subtract, negate, branch, halt);
subtype arith_op is opcode range add to negate;
-- end of code from book
begin
-- code from book:
assert arith_op'base'left = nop;
assert arith_op'base'succ(negate) = branch;
-- end of code from book
wait;
end process section_2_4_c;
end architecture test;
|
gpl-2.0
|
4063e22d8354f414f0b39da730f98f20
| 0.421473 | 5.092003 | false | false | false | false |
lfmunoz/vhdl
|
templates/simulation/fmc160_model/fmc160_model.vhd
| 1 | 12,574 |
--------------------------------------------------------------------------------
-- file name : fmc160_model.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 05-12-2006 new version
--
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity fmc160_model is
generic (
CLOCK_PERIOD : time := 400 ps -- VCO = 2500MHz
);
port (
i2c_scl : inout std_logic;
i2c_sda : inout std_logic;
i2c_ga0 : in std_logic;
i2c_ga1 : in std_logic;
ext_trigger_p : out std_logic;
ext_trigger_n : out std_logic;
dac_dco_p : out std_logic;
dac_dco_n : out std_logic;
dac_dci_p : in std_logic;
dac_dci_n : in std_logic;
dac_frm_p : in std_logic;
dac_frm_n : in std_logic;
dac_p0_p : in std_logic_vector(13 downto 0);
dac_p0_n : in std_logic_vector(13 downto 0);
dac_p1_p : in std_logic_vector(13 downto 0);
dac_p1_n : in std_logic_vector(13 downto 0);
adc_i_dclk_p : out std_logic;
adc_i_dclk_n : out std_logic;
adc_i_d_p : out std_logic_vector(11 downto 0);
adc_i_d_n : out std_logic_vector(11 downto 0);
adc_i_dly_p : out std_logic_vector(11 downto 0);
adc_i_dly_n : out std_logic_vector(11 downto 0);
adc_q_dclk_p : out std_logic;
adc_q_dclk_n : out std_logic;
adc_q_d_p : out std_logic_vector(11 downto 0);
adc_q_d_n : out std_logic_vector(11 downto 0);
adc_q_dly_p : out std_logic_vector(11 downto 0);
adc_q_dly_n : out std_logic_vector(11 downto 0);
pg_c2m : in std_logic;
pg_m2c : out std_logic;
prsnt_m2c_l : out std_logic
);
end entity fmc160_model;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture fmc160_model_beh of fmc160_model is
--------------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------------
constant PTTRN : std_logic_vector(11 downto 0) := "111111100000";
-----------------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------------
signal clk4mhz : std_logic := '0';
signal adc_clock : std_logic := '0';
signal adc_dco : std_logic := '0';
signal dac_clock : std_logic := '0';
signal dac_dco : std_logic := '0';
signal adc_i_d : std_logic_vector(11 downto 0) := "000000000000";
signal adc_i_dly : std_logic_vector(11 downto 0) := "000000000001";
signal adc_q_d : std_logic_vector(11 downto 0) := "000000000000";
signal adc_q_dly : std_logic_vector(11 downto 0) := "000000000010";
signal adc_sdio : std_logic;
signal dac_sdio : std_logic;
signal vm_n_int : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component i2c_slave_model is
generic (
I2C_ADR : std_logic_vector(6 downto 0) := "1001010"
);
port (
scl : in std_logic;
sda : inout std_logic
);
end component;
component fmc160_cpld is
port (
CLK4MHZ : in std_logic;
I2C_SCL : in std_logic;
I2C_SDA : inout std_logic;
I2C_GA0 : in std_logic;
I2C_GA1 : in std_logic;
PG_C2M : in std_logic;
PG_M2C : out std_logic;
PS_EN : in std_logic;
PS_PG : in std_logic;
CPLD_LED : out std_logic;
REF_EN : out std_logic; --0=OFF/1=ON
REF_SEL : out std_logic; --0=EXT REF/1=INT REF
EXT_CLK_REF_SEL : out std_logic; --0=EXT CLK/1=EXT REF
DAC_CLK_SEL : out std_logic; --0=PLL/1=EXT
ADC_CLK_SEL : out std_logic; --0=PLL/1=DIV
SYNCSRC_SEL0 : out std_logic;
SYNCSRC_SEL1 : out std_logic;
SCLK_PLL : out std_logic;
SDI_PLL : out std_logic;
LE_PLL : out std_logic;
CE_PLL : out std_logic;
PDBRF_PLL : out std_logic;
PLL_MUXOUT : in std_logic;
PLL_LD : in std_logic;
ADC_SCLK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
ADC_CS_L : out std_logic;
ADC_CAL_DLY : out std_logic;
ADC_ND_MODE : out std_logic;
ADC_CAL : out std_logic;
ADC_CAL_RUN : in std_logic;
ADC_I_PD : out std_logic;
ADC_Q_PD : out std_logic;
ADC_TP_MODE : out std_logic;
ADC_DDRPH : out std_logic;
ADC_DES : out std_logic;
ADC_ECE_L : out std_logic;
DAC_SCLK : out std_logic;
DAC_SDIO : inout std_logic;
DAC_CS_L : out std_logic;
DAC_IRQ : in std_logic;
DAC_RESET : out std_logic;
EEPROM_WP : out std_logic;
VM_N_INT : in std_logic;
FRONT_IO_HDMI0 : in std_logic;
FRONT_IO_HDMI1 : in std_logic;
FRONT_IO_HDMI2 : in std_logic;
FRONT_IO_HDMI3 : in std_logic
);
end component;
begin
--------------------------------------------------------------------------------
-- CPLD
--------------------------------------------------------------------------------
fmc160_cpld_inst : fmc160_cpld
port map (
clk4mhz => clk4mhz,
i2c_scl => i2c_scl,
i2c_sda => i2c_sda,
i2c_ga0 => '0',
i2c_ga1 => '0',
pg_c2m => pg_c2m,
pg_m2c => pg_m2c,
ps_en => '1',
ps_pg => '1',
cpld_led => open,
ref_en => open,
ref_sel => open,
ext_clk_ref_sel => open,
dac_clk_sel => open,
adc_clk_sel => open,
syncsrc_sel0 => open,
syncsrc_sel1 => open,
sclk_pll => open,
sdi_pll => open,
ce_pll => open,
le_pll => open,
pdbrf_pll => open,
pll_muxout => '0',
pll_ld => '1',
adc_sclk => open,
adc_sdi => adc_sdio,
adc_sdo => adc_sdio, --not actually connected together on FMC160
adc_cs_l => open,
adc_cal_dly => open,
adc_nd_mode => open,
adc_cal => open,
adc_cal_run => '0',
adc_i_pd => open,
adc_q_pd => open,
adc_tp_mode => open,
adc_ddrph => open,
adc_des => open,
adc_ece_l => open,
dac_sclk => open,
dac_sdio => dac_sdio,
dac_cs_l => open,
dac_irq => '0',
dac_reset => open,
eeprom_wp => open,
vm_n_int => vm_n_int,
front_io_hdmi0 => '0',
front_io_hdmi1 => '0',
front_io_hdmi2 => '0',
front_io_hdmi3 => '0'
);
dac_sdio <= 'H';
--------------------------------------------------------------------------------
--Clocking model
--------------------------------------------------------------------------------
clk4mhz <= not clk4mhz after 125 ns;
adc_clock <= not adc_clock after (CLOCK_PERIOD/2)*4; -- Divide by 2
adc_dco <= not adc_dco after (CLOCK_PERIOD/2)*8; -- Divide by 8
dac_clock <= not dac_clock after (CLOCK_PERIOD/2)*1; -- Divide by 1
dac_dco <= not dac_dco after (CLOCK_PERIOD/2)*4; -- Divide by 4
--------------------------------------------------------------------------------
-- ADC model, clock outputs
--------------------------------------------------------------------------------
adc_i_dclk_p <= adc_dco;
adc_i_dclk_n <= not adc_dco;
adc_i_d_p <= adc_i_d;
adc_i_d_n <= not adc_i_d;
adc_i_dly_p <= adc_i_dly;
adc_i_dly_n <= not adc_i_dly;
adc_q_dclk_p <= adc_dco;
adc_q_dclk_n <= not adc_dco;
adc_q_d_p <= adc_q_d;
adc_q_d_n <= not adc_q_d;
adc_q_dly_p <= adc_q_dly;
adc_q_dly_n <= not adc_q_dly;
process (adc_clock)
begin
if (rising_edge(adc_clock)) then
adc_i_d <= adc_i_d + 2;
adc_i_dly <= adc_i_dly + 2;
adc_q_d <= adc_q_d + 4;
adc_q_dly <= adc_q_dly + 4;
end if;
end process;
--------------------------------------------------------------------------------
-- DAC model, clock outputs
--------------------------------------------------------------------------------
dac_dco_p <= dac_dco;
dac_dco_n <= not dac_dco;
--------------------------------------------------------------------------------
-- Trigger model
--------------------------------------------------------------------------------
process
begin
ext_trigger_p <= '0';
ext_trigger_n <= '1';
wait for 80 us;
ext_trigger_p <= '1';
ext_trigger_n <= '0';
wait for 20 us;
ext_trigger_p <= '0';
ext_trigger_n <= '1';
wait;
end process;
--------------------------------------------------------------------------------
-- Output
--------------------------------------------------------------------------------
prsnt_m2c_l <= '0';
--------------------------------------------------------------------------------
-- Monitoring
--------------------------------------------------------------------------------
adt7411: i2c_slave_model
generic map (
I2C_ADR => "1010111"
)
port map (
scl => i2c_scl,
sda => i2c_sda
);
i2c_scl <= 'H';
i2c_sda <= 'H';
vm_n_int <= 'H';
--------------------------------------------------------------------------------
-- End
--------------------------------------------------------------------------------
end architecture fmc160_model_beh;
|
mit
|
6b1c2d6c85d0d69975cb67a70fb3d36b
| 0.409734 | 3.663753 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd
| 4 | 1,987 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
generic ( res : resistance );
port ( terminal p1, p2 : electrical );
end entity resistor;
architecture ideal of resistor is
quantity v across i through p1 to p2;
begin
v == i * res;
end architecture ideal;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : resistance );
port ( terminal p1, p2 : electrical );
end entity capacitor;
architecture ideal of capacitor is
quantity v across i through p1 to p2;
begin
i == cap * v'dot;
end architecture ideal;
-- end not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity lowpass is
port ( terminal input : electrical;
terminal output : electrical );
end entity lowpass;
----------------------------------------------------------------
architecture RC of lowpass is
begin
R : entity work.resistor(ideal)
generic map ( res => 15.9e3 )
port map ( p1 => input, p2 => output );
C : entity work.capacitor(ideal)
generic map ( cap => 1.0e-6 )
port map ( p1 => output, p2 => electrical_ref );
end architecture RC;
|
gpl-2.0
|
608ec1164a13985c7f56531f99c6b20c
| 0.694011 | 3.98996 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/sip_check_data/LFSR_0.vhd
| 2 | 3,098 |
-------------------------------------------------------------------------------------
-- FILE NAME : LFSR.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity LFSR_0 is
generic (
WIDTH : natural := 8
);
port (
clk_in : in std_logic;
rst_in : in std_logic;
reg_out : out std_logic_vector(WIDTH-1 downto 0)
);
end LFSR_0;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of LFSR_0 is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant INIT_VALUE : std_logic_vector(WIDTH-1 downto 0) := (2 => '1', others => '0');
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal shift_reg : std_logic_vector(WIDTH-1 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
process(clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
shift_reg <= INIT_VALUE;
else
-- right shift the registers
--shift_reg(WIDTH-2 downto 0) <= shift_reg(WIDTH-1 downto 1);
-- xor bits to generate new value comming in from the msb
--shift_reg(WIDTH-1) <= shift_reg(2) xor (shift_reg(1) xor (shift_reg(0) xor shift_reg(0)));
shift_reg(0) <= shift_reg(2);
shift_reg(1) <= shift_reg(2) xor shift_reg(0);
shift_reg(2) <= shift_reg(1);
end if;
end if;
reg_out <= shift_reg;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
eecddc7fc9b9f147802532c8fb08779d
| 0.298257 | 5.673993 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3034.vhd
| 4 | 3,042 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3034.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03034ent IS
END c12s02b01x00p01n02i03034ent;
ARCHITECTURE c12s02b01x00p01n02i03034arch OF c12s02b01x00p01n02i03034ent IS
subtype subi is integer range 1 to 10;
subtype subr is real range 1.0 to 10.0;
subtype subb is bit range '1' to '1';
type c_r is
record
i : subi;
r : subr;
b : subb;
end record;
signal s1, s2, s3 : c_r;
BEGIN
-- test record generics
bl4: block
generic(gr : c_r);
generic map (gr => (1,1.0,'1'));
port (s11 : OUT c_r);
port map (s11 => s1);
begin
assert ((gr.i=1) and (gr.r=1.0) and (gr.b='1'))
report "Generic record GR did not take on the correct low value"
severity failure;
s11 <= gr;
end block;
bl5: block
generic(gr : c_r);
generic map (gr => (5,5.0,'1'));
port (s22 : OUT c_r);
port map (s22 => s2);
begin
assert ((gr.i=5) and (gr.r=5.0) and (gr.b='1'))
report "Generic record GR did not take on the correct middle value"
severity failure;
s22 <= gr;
end block;
bl6: block
generic(gr : c_r);
generic map (gr => (10,10.0,'1'));
port (s33 : OUT c_r);
port map (s33 => s3);
begin
assert ((gr.i=10) and (gr.r=10.0) and (gr.b='1'))
report "Generic record GR did not take on the correct high value"
severity failure;
s33 <= gr;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = (1,1.0,'1') and s2 = (5,5.0,'1') and s3 = (10,10.0,'1') )
report "***PASSED TEST: c12s02b01x00p01n02i03034"
severity NOTE;
assert ( s1 = (1,1.0,'1') and s2 = (5,5.0,'1') and s3 = (10,10.0,'1') )
report "***FAILED TEST: c12s02b01x00p01n02i03034 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03034arch;
|
gpl-2.0
|
0786893344ab41f5418b897687f5a572
| 0.612755 | 3.232731 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd
| 4 | 1,753 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity dac_12_bit is
port ( signal bus_in : in std_ulogic_vector (11 downto 0);
terminal analog_out : electrical );
end entity dac_12_bit;
----------------------------------------------------------------
architecture behavioral of dac_12_bit is
constant v_max : real := 3.3;
signal s_out : real := 0.0;
quantity v_out across i_out through analog_out to electrical_ref;
begin
convert : process ( bus_in ) is
variable sum : natural;
begin
sum := 0;
for i in bus_in'range loop
sum := sum * 2 + boolean'pos( bus_in(i) = '1' or bus_in(i) = 'H' );
end loop;
s_out <= v_max * real(sum) / real(2**12 - 1);
end process convert;
v_out == s_out'ramp(1.0E-6);
end architecture behavioral;
|
gpl-2.0
|
97a6350b353b6fb26d98d00913b3a38a
| 0.624073 | 3.904232 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug060/corelib_List.v08.vhdl
| 2 | 11,382 |
-- EMACS settings: -*- tab-width: 2;indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2;replace-tabs off;indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Protected type implementations.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
package corelib_List is
generic (
type ELEMENT_TYPE;
InitialMasterListSize : POSITIVE := 4;
InitialChunkListSize : POSITIVE := 8;
MasterListResize : POSITIVE := 8;
ChunkListResize : POSITIVE := 8
);
type ELEMENT_ARRAY is array(NATURAL range <>) of ELEMENT_TYPE;
-- protected list implementation
type PT_LIST is protected
procedure Init;
-- procedure Clear;
procedure Append(Value : ELEMENT_TYPE);
impure function Append(Value : ELEMENT_TYPE) return NATURAL;
procedure Append(Values : ELEMENT_ARRAY);
impure function Append(Values : ELEMENT_ARRAY) return NATURAL;
-- procedure Prepend(Value : ELEMENT_TYPE);
-- impure function Prepend(Value : ELEMENT_TYPE) return NATURAL;
-- procedure Prepend(Values : ELEMENT_ARRAY);
-- impure function Prepend(Values : ELEMENT_ARRAY) return NATURAL;
-- procedure Insert(Index : NATURAL; Value : ELEMENT_TYPE);
-- procedure Insert(Index : NATURAL; Values : ELEMENT_ARRAY);
impure function IndexOf(Value : ELEMENT_TYPE) return INTEGER;
procedure Set(Index : NATURAL; Value : ELEMENT_TYPE);
impure function Set(Index : NATURAL; Value : ELEMENT_TYPE) return ELEMENT_TYPE;
impure function Get(Index : NATURAL) return ELEMENT_TYPE;
procedure RemoveAt(Index : NATURAL);
impure function RemoveAt(Index : NATURAL) return ELEMENT_TYPE;
procedure Remove(Value : ELEMENT_TYPE);
impure function Remove(Value : ELEMENT_TYPE) return NATURAL;
-- procedure Remove(Values : ELEMENT_ARRAY);
impure function ToArray(Start : INTEGER := 0; Stop : INTEGER := -1; COUNT : NATURAL := 0) return ELEMENT_ARRAY;
impure function Count return natural;
impure function Size return positive;
-- procedure Resize(Size : positive);
end protected;
end package;
package body corelib_List is
-- protected list implementation
type PT_LIST is protected body
subtype T_Chunk is ELEMENT_ARRAY;
type P_Chunk is access T_Chunk;
type T_MasterListItem is record
Count : NATURAL;
Pointer : P_Chunk;
end record;
type T_MasterList is array(NATURAL range <>) of T_MasterListItem;
type P_MasterList is access T_MasterList;
type T_AddressTuple is record
MasterIndex : INTEGER;
ChunkIndex : INTEGER;
ListIndex : INTEGER;
end record;
variable I_Count : NATURAL := 0;
variable I_MasterList_Size : POSITIVE := InitialMasterListSize;
variable I_MasterList_Count : NATURAL := 0;
variable I_MasterList_Last : NATURAL := 0;
variable I_MasterList : P_MasterList := null;
procedure Init is
begin
I_Count := 0;
I_MasterList_Size := InitialMasterListSize;
I_MasterList_Count := 1;
I_MasterList_Last := 0;
I_MasterList := new T_MasterList(0 to InitialMasterListSize - 1);
I_MasterList(0).Count := 0;
I_MasterList(0).Pointer := new T_Chunk(0 to InitialChunkListSize - 1);
end procedure;
procedure CheckResize(Size : positive) is
variable i : NATURAL;
variable j : NATURAL;
variable Remaining : INTEGER;
variable New_Chunks : NATURAL;
variable New_MasterList_Size : NATURAL;
variable New_MasterList : P_MasterList;
begin
Remaining := Size;
i := I_MasterList_Last;
Remaining := Remaining - (InitialChunkListSize - I_MasterList(i).Count);
New_Chunks := (Remaining + ChunkListResize - 1) / ChunkListResize;
if ((I_MasterList_Size - I_MasterList_Count) < New_Chunks) then
New_MasterList_Size := I_MasterList_Size + ((New_Chunks + MasterListResize - 1) / MasterListResize) * MasterListResize;
New_MasterList := new T_MasterList(0 to New_MasterList_Size - 1);
for j in 0 to I_MasterList_Count - 1 loop
New_MasterList(j).Count := I_MasterList(j).Count;
New_MasterList(j).Pointer := I_MasterList(j).Pointer;
end loop;
deallocate(I_MasterList);
I_MasterList := New_MasterList;
I_MasterList_Size := New_MasterList_Size;
end if;
for j in I_MasterList_Count to I_MasterList_Count + New_Chunks - 1 loop
I_MasterList(j).Count := 0;
I_MasterList(j).Pointer := new T_Chunk(0 to InitialChunkListSize - 1);
end loop;
I_MasterList_Count := I_MasterList_Count + New_Chunks;
end procedure;
-- procedure Clear is
-- begin
-- end procedure;
procedure Append(Value : ELEMENT_TYPE) is
variable i : NATURAL;
variable j : NATURAL;
begin
CheckResize(1);
i := I_MasterList_Last;
if (I_MasterList(i).Count >= InitialChunkListSize) then
i := i + 1;
I_MasterList_Last := i;
end if;
j := I_MasterList(i).Count;
I_MasterList(i).Pointer(j) := Value;
I_MasterList(i).Count := j + 1;
I_Count := I_Count + 1;
end procedure;
impure function Append(Value : ELEMENT_TYPE) return NATURAL is
begin
Append(Value);
return I_Count - 1;
end function;
procedure Append(Values : ELEMENT_ARRAY) is
begin
end procedure;
impure function Append(Values : ELEMENT_ARRAY) return NATURAL is
begin
Append(Values);
return I_Count - Values'length;
end function;
-- procedure Prepend(Value : ELEMENT_TYPE) is
-- begin
-- end procedure;
-- impure function Prepend(Value : ELEMENT_TYPE) return NATURAL is
-- begin
-- end function;
-- procedure Prepend(Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
-- impure function Prepend(Values : ELEMENT_ARRAY) return NATURAL is
-- begin
-- end function;
-- procedure Insert(Index : NATURAL; Value : ELEMENT_TYPE) is
-- begin
-- end procedure;
-- procedure Insert(Index : NATURAL; Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
impure function AddressOf(Value : ELEMENT_TYPE) return T_AddressTuple is
variable k : NATURAL;
begin
k := 0;
for i in 0 to I_MasterList_Count - 1 loop
for j in 0 to I_MasterList(i).Count - 1 loop
if (I_MasterList(i).Pointer(j) = Value) then
return (i, j, k);
end if;
k := k + 1;
end loop;
end loop;
return (-1, -1, -1);
end function;
impure function AddressOf(Index : NATURAL) return T_AddressTuple is
variable j : NATURAL;
variable k : NATURAL;
begin
if (Index >= I_Count) then
report "Index is out of range." severity ERROR;
return (-1, -1, -1);
end if;
k := Index;
for i in 0 to I_MasterList_Count - 1 loop
j := I_MasterList(i).Count;
if (k < j) then
return (i, k, Index);
else
k := k - j;
end if;
end loop;
return (-1, -1, -1);
end function;
impure function IndexOf(Value : ELEMENT_TYPE) return INTEGER is
constant idx : T_AddressTuple := AddressOf(Value);
begin
return idx.ListIndex;
end function;
procedure Set(Index : NATURAL; Value : ELEMENT_TYPE) is
constant idx : T_AddressTuple := AddressOf(Index);
begin
if (idx.ListIndex /= -1) then
I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex) := Value;
end if;
end procedure;
impure function Set(Index : NATURAL; Value : ELEMENT_TYPE) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
variable old : ELEMENT_TYPE;
begin
if (idx.ListIndex /= -1) then
old := I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex);
I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex) := Value;
end if;
return old;
end function;
impure function Get(Index : NATURAL) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
variable Empty : ELEMENT_TYPE;
begin
if (idx.ListIndex /= -1) then
return I_MasterList(idx.MasterIndex).Pointer(idx.ChunkIndex);
end if;
return Empty;
end function;
procedure RemoveChunk(ChunkIndex : NATURAL) is
begin
deallocate(I_MasterList(ChunkIndex).Pointer);
for i in ChunkIndex to I_MasterList_Count - 2 loop
I_MasterList(i).Count := I_MasterList(i + 1).Count;
I_MasterList(i).Pointer := I_MasterList(i + 1).Pointer;
end loop;
I_MasterList_Count := I_MasterList_Count - 1;
end procedure;
procedure Remove(Idx : T_AddressTuple) is
constant i : INTEGER := idx.MasterIndex;
begin
if ((Idx.ChunkIndex = 0) and (I_MasterList(i).Count = 1)) then
RemoveChunk(i);
else
for j in Idx.ChunkIndex to InitialChunkListSize - 2 loop
I_MasterList(i).Pointer(j) := I_MasterList(i).Pointer(j + 1);
end loop;
I_MasterList(i).Count := I_MasterList(i).Count - 1;
end if;
I_Count := I_Count - 1;
end procedure;
procedure RemoveAt(Index : NATURAL) is
begin
Remove(AddressOf(Index));
end procedure;
impure function RemoveAt(Index : NATURAL) return ELEMENT_TYPE is
constant idx : T_AddressTuple := AddressOf(Index);
constant i : INTEGER := idx.MasterIndex;
constant j : INTEGER := idx.ChunkIndex;
constant Value : ELEMENT_TYPE := I_MasterList(i).Pointer(j);
begin
Remove(idx);
return Value;
end function;
procedure Remove(Value : ELEMENT_TYPE) is
begin
Remove(AddressOf(Value));
end procedure;
impure function Remove(Value : ELEMENT_TYPE) return NATURAL is
constant idx : T_AddressTuple := AddressOf(Value);
begin
Remove(idx);
return idx.ListIndex;
end function;
-- procedure Remove(Values : ELEMENT_ARRAY) is
-- begin
-- end procedure;
impure function ToArray(Start : INTEGER := 0; Stop : INTEGER := -1; COUNT : NATURAL := 0) return ELEMENT_ARRAY is
variable Result : ELEMENT_ARRAY(0 to I_Count - 1);
variable k : NATURAL;
begin
k := 0;
for i in 0 to I_MasterList_Count - 1 loop
for j in 0 to I_MasterList(i).Count - 1 loop
Result(k) := I_MasterList(i).Pointer(j);
k := k + 1;
end loop;
end loop;
return Result;
end function;
impure function Count return natural is
begin
return I_Count;
end function;
impure function Size return positive is
begin
return I_MasterList_Size * InitialChunkListSize;
end function;
-- procedure Resize(Size : positive) is
-- begin
-- end procedure;
end protected body;
end package body;
|
gpl-2.0
|
e25f27addc1c8c167af1ca41726ff3ad
| 0.649359 | 3.420072 | false | false | false | false |
tgingold/ghdl
|
libraries/ieee2008/numeric_bit-body.vhdl
| 1 | 93,982 |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body NUMERIC_BIT is
-- null range array constants
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNSIGNED; C : BIT) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNSIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : SIGNED; C : BIT) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(L_LEFT downto 0) is R;
variable RESULT : SIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNSIGNED; XQUOT, XREMAIN : out UNSIGNED) is
variable TEMP : UNSIGNED(NUM'length downto 0);
variable QUOT : UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0);
alias DENOM : UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_BIT.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_BIT.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
---------------- Local Subprograms - Relational Operators --------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- ====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT : SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : SIGNED(ARG_LEFT downto 0);
variable CBIT : BIT := '1';
begin
if ARG'length < 1 then return NAS;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.3R
function "+" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.4R
function "+" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.9R
function "-" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.10R
function "-" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable RESULT : UNSIGNED((L'length+R'length-1) downto 0) := (others => '0');
variable ADVAL : UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable RESULT : SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL : SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
QNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
RNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
RNEG := true;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function ">";
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function ">";
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function "<";
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function "<";
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function "<=";
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "<=";
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function ">=";
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function ">=";
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'length), R);
end function "=";
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "=";
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'length), R));
end function "/=";
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length)));
end function "/=";
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.53
function "?>" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.54
function "?>" (L : SIGNED; R : INTEGER) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.59
function "?<" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.60
function "?<" (L : SIGNED; R : INTEGER) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.66
function "?<=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.72
function "?>=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.77
function "?=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.78
function "?=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.84
function "?/=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER is
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
if ARG(ARG'left) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED is
variable RESULT : UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER;
SIZE : NATURAL) return SIGNED is
variable RESULT : SIGNED(SIZE-1 downto 0);
variable B_VAL : BIT := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED is
alias INVEC : SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : SIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNSIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : SIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNSIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : SIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNSIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : SIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNSIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : SIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNSIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : SIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNSIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function TO_OSTRING (value : UNSIGNED) return STRING is
begin
return TO_OSTRING(BIT_VECTOR (value));
end function TO_OSTRING;
function TO_OSTRING (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(1 to (result_length*3 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return TO_OSTRING(pad & BIT_VECTOR (value));
end function TO_OSTRING;
function to_hstring (value : UNSIGNED) return STRING is
begin
return to_hstring(BIT_VECTOR (value));
end function to_hstring;
function to_hstring (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(1 to (result_length*4 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & BIT_VECTOR (value));
end function to_hstring;
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
GOOD := true;
else
GOOD := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
GOOD := true;
else
GOOD := false;
end if;
end if;
else
GOOD := true;
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
if not ok then
GOOD := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
end if;
else
GOOD := true;
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - VALUE'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_BIT;
|
gpl-2.0
|
23678880b37f05c625f1f39c453b7181
| 0.545158 | 3.952976 | false | false | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0_inst.vhd
| 1 | 4,666 |
component pr_region_default_mm_bridge_0 is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_logic := 'X'; -- clk
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
m0_write : out std_logic; -- write
m0_read : out std_logic; -- read
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
reset : in std_logic := 'X'; -- reset
s0_waitrequest : out std_logic; -- waitrequest
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
s0_readdatavalid : out std_logic; -- readdatavalid
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
s0_write : in std_logic := 'X'; -- write
s0_read : in std_logic := 'X'; -- read
s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
s0_debugaccess : in std_logic := 'X' -- debugaccess
);
end component pr_region_default_mm_bridge_0;
u0 : component pr_region_default_mm_bridge_0
generic map (
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE
)
port map (
clk => CONNECTED_TO_clk, -- clk.clk
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
m0_address => CONNECTED_TO_m0_address, -- .address
m0_write => CONNECTED_TO_m0_write, -- .write
m0_read => CONNECTED_TO_m0_read, -- .read
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess
reset => CONNECTED_TO_reset, -- reset.reset
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
s0_address => CONNECTED_TO_s0_address, -- .address
s0_write => CONNECTED_TO_s0_write, -- .write
s0_read => CONNECTED_TO_s0_read, -- .read
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess
);
|
mit
|
cf07cfdeda23db2546c58f0cb025d82d
| 0.493785 | 3.781199 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/lit01/aggr02.vhdl
| 1 | 883 |
library ieee;
use ieee.std_logic_1164.all;
entity aggr02 is
port (i0 : natural range 0 to 5;
o : out std_logic_vector (7 downto 0));
end;
architecture behav of aggr02 is
type my_enum5 is (e0, e1, e2, e3, e4);
type my_rec is record
en : my_enum5;
cnt : std_logic_vector (3 downto 0);
b : boolean;
c : character;
end record;
type rec_arr is array (0 to 5) of my_rec;
constant aggr : rec_arr :=
(0 => (e0, x"0", false, '0'),
1 => (e1, x"1", false, '1'),
2 => (e2, x"2", false, '2'),
3 => (e3, x"3", false, '3'),
4 => (e4, x"4", false, '4'),
5 => (e3, x"5", true, '5'));
begin
process (i0)
variable v : my_rec;
variable r : my_enum5;
begin
v := aggr (i0);
o(3 downto 0) <= v.cnt;
r := e1;
o(7 downto 4) <= x"0";
if v.en = r then
o (7) <= '1';
end if;
end process;
end behav;
|
gpl-2.0
|
0c1ea0839ecf4b08770f244a36001a9d
| 0.516421 | 2.597059 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd
| 4 | 60,047 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc520.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00520pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00520pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00520pkg;
USE work.c03s03b00x00p03n04i00520pkg.ALL;ENTITY c03s03b00x00p03n04i00520ent IS
END c03s03b00x00p03n04i00520ent;
ARCHITECTURE c03s03b00x00p03n04i00520arch OF c03s03b00x00p03n04i00520ent IS
--
-- Access type declarations
--
TYPE at_usa1_1 IS ACCESS t_usa1_1 ;
TYPE at_usa1_2 IS ACCESS t_usa1_2 ;
TYPE at_usa1_3 IS ACCESS t_usa1_3 ;
TYPE at_usa1_4 IS ACCESS t_usa1_4 ;
TYPE at_csa1_1 IS ACCESS t_csa1_1 ;
TYPE at_csa1_2 IS ACCESS t_csa1_2 ;
TYPE at_csa1_3 IS ACCESS t_csa1_3 ;
TYPE at_csa1_4 IS ACCESS t_csa1_4 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_usa1_1 : at_usa1_1 ;
VARIABLE AV2_usa1_1 : at_usa1_1 ;
VARIABLE AV0_usa1_2 : at_usa1_2 ;
VARIABLE AV2_usa1_2 : at_usa1_2 ;
VARIABLE AV0_usa1_3 : at_usa1_3 ;
VARIABLE AV2_usa1_3 : at_usa1_3 ;
VARIABLE AV0_usa1_4 : at_usa1_4 ;
VARIABLE AV2_usa1_4 : at_usa1_4 ;
VARIABLE AV0_csa1_1 : at_csa1_1 ;
VARIABLE AV2_csa1_1 : at_csa1_1 ;
VARIABLE AV0_csa1_2 : at_csa1_2 ;
VARIABLE AV2_csa1_2 : at_csa1_2 ;
VARIABLE AV0_csa1_3 : at_csa1_3 ;
VARIABLE AV2_csa1_3 : at_csa1_3 ;
VARIABLE AV0_csa1_4 : at_csa1_4 ;
VARIABLE AV2_csa1_4 : at_csa1_4 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_usa1_1 := NEW t_usa1_1 (st_ind1 ) ;
AV0_usa1_2 := NEW t_usa1_2 (st_ind2 ) ;
AV0_usa1_3 := NEW t_usa1_3 (st_ind3 ) ;
AV0_usa1_4 := NEW t_usa1_4 (st_ind4 ) ;
AV0_csa1_1 := NEW t_csa1_1 ;
AV0_csa1_2 := NEW t_csa1_2 ;
AV0_csa1_3 := NEW t_csa1_3 ;
AV0_csa1_4 := NEW t_csa1_4 ;
---
AV2_usa1_1 := NEW t_usa1_1 ' ( C2_csa1_1 ) ;
AV2_usa1_2 := NEW t_usa1_2 ' ( C2_csa1_2 ) ;
AV2_usa1_3 := NEW t_usa1_3 ' ( C2_csa1_3 ) ;
AV2_usa1_4 := NEW t_usa1_4 ' ( C2_csa1_4 ) ;
AV2_csa1_1 := NEW t_csa1_1 ' ( C2_csa1_1 ) ;
AV2_csa1_2 := NEW t_csa1_2 ' ( C2_csa1_2 ) ;
AV2_csa1_3 := NEW t_csa1_3 ' ( C2_csa1_3 ) ;
AV2_csa1_4 := NEW t_csa1_4 ' ( C2_csa1_4 ) ;
--
--
ASSERT AV0_usa1_1.all = C0_csa1_1
REPORT "Improper initialization of AV0_usa1_1" SEVERITY FAILURE;
ASSERT AV2_usa1_1.all = C2_csa1_1
REPORT "Improper initialization of AV2_usa1_1" SEVERITY FAILURE;
ASSERT AV0_usa1_2.all = C0_csa1_2
REPORT "Improper initialization of AV0_usa1_2" SEVERITY FAILURE;
ASSERT AV2_usa1_2.all = C2_csa1_2
REPORT "Improper initialization of AV2_usa1_2" SEVERITY FAILURE;
ASSERT AV0_usa1_3.all = C0_csa1_3
REPORT "Improper initialization of AV0_usa1_3" SEVERITY FAILURE;
ASSERT AV2_usa1_3.all = C2_csa1_3
REPORT "Improper initialization of AV2_usa1_3" SEVERITY FAILURE;
ASSERT AV0_usa1_4.all = C0_csa1_4
REPORT "Improper initialization of AV0_usa1_4" SEVERITY FAILURE;
ASSERT AV2_usa1_4.all = C2_csa1_4
REPORT "Improper initialization of AV2_usa1_4" SEVERITY FAILURE;
ASSERT AV0_csa1_1.all = C0_csa1_1
REPORT "Improper initialization of AV0_csa1_1" SEVERITY FAILURE;
ASSERT AV2_csa1_1.all = C2_csa1_1
REPORT "Improper initialization of AV2_csa1_1" SEVERITY FAILURE;
ASSERT AV0_csa1_2.all = C0_csa1_2
REPORT "Improper initialization of AV0_csa1_2" SEVERITY FAILURE;
ASSERT AV2_csa1_2.all = C2_csa1_2
REPORT "Improper initialization of AV2_csa1_2" SEVERITY FAILURE;
ASSERT AV0_csa1_3.all = C0_csa1_3
REPORT "Improper initialization of AV0_csa1_3" SEVERITY FAILURE;
ASSERT AV2_csa1_3.all = C2_csa1_3
REPORT "Improper initialization of AV2_csa1_3" SEVERITY FAILURE;
ASSERT AV0_csa1_4.all = C0_csa1_4
REPORT "Improper initialization of AV0_csa1_4" SEVERITY FAILURE;
ASSERT AV2_csa1_4.all = C2_csa1_4
REPORT "Improper initialization of AV2_csa1_4" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_usa1_1.all = C0_csa1_1 )
and ( AV2_usa1_1.all = C2_csa1_1 )
and ( AV0_usa1_2.all = C0_csa1_2 )
and ( AV2_usa1_2.all = C2_csa1_2 )
and ( AV0_usa1_3.all = C0_csa1_3 )
and ( AV2_usa1_3.all = C2_csa1_3 )
and ( AV0_usa1_4.all = C0_csa1_4 )
and ( AV2_usa1_4.all = C2_csa1_4 )
and ( AV0_csa1_1.all = C0_csa1_1 )
and ( AV2_csa1_1.all = C2_csa1_1 )
and ( AV0_csa1_2.all = C0_csa1_2 )
and ( AV2_csa1_2.all = C2_csa1_2 )
and ( AV0_csa1_3.all = C0_csa1_3 )
and ( AV2_csa1_3.all = C2_csa1_3 )
and ( AV0_csa1_4.all = C0_csa1_4 )
and ( AV2_csa1_4.all = C2_csa1_4 ))
report "***PASSED TEST: c03s03b00x00p03n04i00520"
severity NOTE;
assert ( ( AV0_usa1_1.all = C0_csa1_1 )
and ( AV2_usa1_1.all = C2_csa1_1 )
and ( AV0_usa1_2.all = C0_csa1_2 )
and ( AV2_usa1_2.all = C2_csa1_2 )
and ( AV0_usa1_3.all = C0_csa1_3 )
and ( AV2_usa1_3.all = C2_csa1_3 )
and ( AV0_usa1_4.all = C0_csa1_4 )
and ( AV2_usa1_4.all = C2_csa1_4 )
and ( AV0_csa1_1.all = C0_csa1_1 )
and ( AV2_csa1_1.all = C2_csa1_1 )
and ( AV0_csa1_2.all = C0_csa1_2 )
and ( AV2_csa1_2.all = C2_csa1_2 )
and ( AV0_csa1_3.all = C0_csa1_3 )
and ( AV2_csa1_3.all = C2_csa1_3 )
and ( AV0_csa1_4.all = C0_csa1_4 )
and ( AV2_csa1_4.all = C2_csa1_4 ))
report "***FAILED TEST: c03s03b00x00p03n04i00520 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00520arch;
|
gpl-2.0
|
31e3cd5239f9855db5088683d8d0b465
| 0.478625 | 3.101281 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd
| 4 | 2,463 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity DRAM_controller is
port ( rd, wr, mem : in bit;
ras, cas, we, ready : out bit );
end entity DRAM_controller;
-- end of code from book
----------------------------------------------------------------
architecture fpld of DRAM_controller is
begin
end architecture fpld;
----------------------------------------------------------------
entity ch_05_18 is
end entity ch_05_18;
----------------------------------------------------------------
architecture test of ch_05_18 is
begin
block_05_4_a : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy );
-- end of code from book
end block block_05_4_a;
----------------
block_05_4_b : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( rd => cpu_rd, wr => cpu_wr,
mem => cpu_mem, ready => cpu_rdy,
ras => mem_ras, cas => mem_cas, we => mem_we );
-- end of code from book
end block block_05_4_b;
end architecture test;
|
gpl-2.0
|
761bcbd6409d7456c971add2297b354b
| 0.534714 | 4.02451 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/w_split6.vhd
| 2 | 1,359 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split6 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split6;
architecture augh of w_split6 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
gpl-2.0
|
d5c070523c51e880bd722c5e0526785a
| 0.66961 | 2.843096 | false | false | false | false |
nickg/nvc
|
lib/std.19/env-body.vhd
| 1 | 15,494 |
-------------------------------------------------------------------------------
-- Copyright (C) 2022 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
package body env is
-- Forward slash is a legal separator on both Windows and Unix
constant DIR_SEPARATOR : string := "/";
procedure stop_impl(finish, have_status : boolean; status : integer);
attribute foreign of stop_impl : procedure is "_std_env_stop";
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
impure function localtime return time_record is
begin
return localtime(epoch);
end function;
impure function gmtime return time_record is
begin
return gmtime(epoch);
end function;
impure function epoch return real is
impure function impl return real;
attribute foreign of impl : function is "_std_env_epoch";
begin
return impl;
end function;
function localtime (timer : real) return time_record is
procedure impl (timer : real; tr : out time_record);
attribute foreign of impl : procedure is "_std_env_localtime";
variable result : time_record;
begin
impl(timer, result);
return result;
end function;
function gmtime (timer : real) return time_record is
procedure impl (timer : real; tr : out time_record);
attribute foreign of impl : procedure is "_std_env_gmtime";
variable result : time_record;
begin
impl(timer, result);
return result;
end function;
function epoch (trec : time_record) return real is
begin
report "not implemented" severity failure;
end function;
function localtime (trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function gmtime (trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function "+" (trec : time_record; delta : real) return time_record is
begin
report "not implemented" severity failure;
end function;
function "+" (delta : real; trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function "-" (trec : time_record; delta : real) return time_record is
begin
report "not implemented" severity failure;
end function;
function "-" (delta : real; trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function "-" (tr1, tr2 : time_record) return real is
begin
report "not implemented" severity warning;
return 0.0;
end function;
function time_to_seconds (time_val : in time) return real is
begin
report "not implemented" severity warning;
return 0.0;
end function;
function seconds_to_time (real_val : in real) return time is
begin
report "not implemented" severity warning;
return 0 fs;
end function;
function to_string (trec : time_record;
frac_digits : integer range 0 to 6 := 0)
return string
is
function zero_pad (value, width : integer) return string is
variable result : string(1 to width);
variable temp : integer := value;
begin
for i in width downto 1 loop
result(i to i) := to_string(temp rem 10);
temp := temp / 10;
end loop;
return result;
end function;
variable buf : string(1 to 26);
begin
buf(1 to 4) := zero_pad(trec.year, 4);
buf(5) := '-';
buf(6 to 7) := zero_pad(trec.month, 2);
buf(8) := '-';
buf(9 to 10) := zero_pad(trec.day, 2);
buf(11) := 'T';
buf(12 to 13) := zero_pad(trec.hour, 2);
buf(14) := ':';
buf(15 to 16) := zero_pad(trec.minute, 2);
buf(17) := ':';
buf(18 to 19) := zero_pad(trec.second, 2);
if frac_digits > 0 then
buf(20) := '.';
buf(21 to 26) := zero_pad(trec.microsecond, 6);
return buf(1 to 20 + frac_digits);
else
return buf(1 to 19);
end if;
end function;
impure function getenv (name : string) return string is
impure function impl (name : string) return string;
attribute foreign of impl : function is "_std_env_getenv";
begin
return impl(name);
end function;
impure function getenv (name : string) return line is
begin
return new string'(getenv(name));
end function;
impure function vhdl_version return STRING is
impure function impl return string;
attribute foreign of impl : function is "_std_env_vhdl_version";
begin
return impl;
end function;
function tool_type return STRING is
begin
return "SIMULATION";
end function;
function tool_vendor return string is
begin
return "https://www.nickg.me.uk/nvc";
end function;
function tool_name return string is
begin
return "nvc";
end function;
function tool_edition return string is
begin
return "";
end function;
function tool_version return string is
function impl return string;
attribute foreign of impl : function is "_std_env_tool_version";
begin
return impl;
end function;
procedure dir_open (dir : out directory;
path : in string;
status : out dir_open_status) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_open (dir : out directory;
path : in string) return dir_open_status is
begin
report "not implemented" severity failure;
end function;
procedure dir_close (variable dir : inout directory) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_itemexists (path : in string) return boolean is
impure function impl (path : in string) return boolean;
attribute foreign of impl : function is "_std_env_itemexists";
begin
return impl(path);
end function;
impure function dir_itemisdir (path : in string) return boolean is
impure function impl (path : in string) return boolean;
attribute foreign of impl : function is "_std_env_itemisdir";
begin
return impl(path);
end function;
impure function dir_itemisfile (path : in string) return boolean is
impure function impl (path : in string) return boolean;
attribute foreign of impl : function is "_std_env_itemisfile";
begin
return impl(path);
end function;
procedure dir_workingdir (path : in string;
status : out dir_open_status) is
procedure impl (path : in string;
status : out dir_open_status);
attribute foreign of impl : procedure is "_std_env_set_workingdir";
begin
impl(path, status);
end procedure;
impure function dir_workingdir (path : in string)
return dir_open_status
is
variable status : dir_open_status;
begin
dir_workingdir(path, status);
return status;
end function;
impure function dir_workingdir return string is
impure function impl return string;
attribute foreign of impl : function is "_std_env_get_workingdir";
begin
return impl;
end function;
procedure dir_createdir (path : in string;
status : out dir_create_status) is
begin
dir_createdir(path, false, status);
end procedure;
procedure dir_createdir (path : in string;
parents : in boolean;
status : out dir_create_status) is
procedure impl (path : in string;
parents : in boolean;
status : out dir_create_status);
attribute foreign of impl : procedure is "_std_env_createdir";
begin
assert not parents report "PARENTS flag not supported"
severity failure;
impl(path, parents, status);
end procedure;
impure function dir_createdir (path : in string;
parents : in boolean := false)
return dir_create_status
is
variable status : dir_create_status;
begin
dir_createdir(path, parents, status);
return status;
end function;
procedure dir_deletedir (path : in string;
status : out dir_delete_status) is
begin
report "not implemented" severity failure;
end procedure;
procedure dir_deletedir (path : in string;
recursive : in boolean;
status : out dir_delete_status) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_deletedir (path : in string;
recursive : in boolean := false)
return dir_delete_status is
begin
report "not implemented" severity failure;
end function;
procedure dir_deletefile (path : in string;
status : out file_delete_status) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_deletefile (path : in string) return file_delete_status is
begin
report "not implemented" severity failure;
end function;
impure function to_string (variable call_path : inout call_path_element)
return string is
begin
report "not implemented" severity failure;
end function;
impure function to_string (variable call_path : inout call_path_vector;
separator : string := "" & lf)
return string is
begin
report "not implemented" severity failure;
end function;
impure function to_string (variable call_path : inout call_path_vector_ptr; separator : string := "" & lf) return string is
begin
report "not implemented" severity failure;
end function;
impure function get_call_path return call_path_vector_ptr is
begin
report "not implemented" severity failure;
end function;
impure function file_name return line is
begin
report "not implemented" severity failure;
end function;
impure function file_name return string is
begin
report "not implemented" severity failure;
end function;
impure function file_path return line is
begin
report "not implemented" severity failure;
end function;
impure function file_path return string is
begin
report "not implemented" severity failure;
end function;
impure function file_line return positive is
begin
report "not implemented" severity failure;
end function;
impure function file_line return string is
begin
report "not implemented" severity failure;
end function;
impure function IsVhdlAssertFailed return boolean is
begin
report "not implemented" severity failure;
end function;
impure function IsVhdlAssertFailed (Level : severity_level)
return boolean is
begin
report "not implemented" severity failure;
end function;
impure function GetVhdlAssertCount return natural is
begin
report "not implemented" severity failure;
end function;
impure function GetVhdlAssertCount (Level : severity_level)
return natural is
begin
report "not implemented" severity failure;
end function;
procedure ClearVhdlAssert is
begin
report "not implemented" severity failure;
end procedure;
procedure SetVhdlAssertEnable (Enable : boolean := true) is
begin
report "not implemented" severity failure;
end procedure;
procedure SetVhdlAssertEnable (Level : severity_level := note;
Enable : boolean := true) is
begin
report "not implemented" severity failure;
end procedure;
impure function GetVhdlAssertEnable (Level : severity_level := note)
return boolean is
begin
report "not implemented" severity failure;
end function;
procedure SetVhdlAssertFormat(Level : SEVERITY_LEVEL;
Format : string) is
begin
report "not implemented" severity failure;
end procedure;
procedure SetVhdlAssertFormat (Level : severity_level;
Format : string;
Valid : out boolean) is
begin
report "not implemented" severity failure;
end procedure;
impure function GetVhdlAssertFormat (Level : severity_level)
return string is
begin
report "not implemented" severity failure;
end function;
procedure SetVhdlReadSeverity (Level : severity_level := failure) is
begin
report "not implemented" severity failure;
end procedure;
impure function GetVhdlReadSeverity return severity_level is
begin
report "not implemented" severity failure;
end function;
impure function PslAssertFailed return boolean is
begin
report "not implemented" severity failure;
end function;
impure function PslIsCovered return boolean is
begin
report "not implemented" severity failure;
end function;
procedure SetPslCoverAssert (Enable : boolean := TRUE) is
begin
report "not implemented" severity warning;
end procedure;
impure function GetPslCoverAssert return boolean is
begin
report "not implemented" severity warning;
return false;
end function;
impure function PslIsAssertCovered return boolean is
begin
report "not implemented" severity warning;
return false;
end function;
procedure ClearPslState is
begin
report "not implemented" severity warning;
end procedure;
end package body;
|
gpl-3.0
|
94b63fe63198b50e50fc096933b1c987
| 0.615658 | 4.752761 | false | false | false | false |
nickg/nvc
|
test/perf/bigcase.vhd
| 1 | 102,941 |
library ieee;
use ieee.std_logic_1164.all;
library work;
entity LogTable_0_10_74_F400_uid60 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(9 downto 0);
Y : out std_logic_vector(73 downto 0) );
end entity;
architecture arch of LogTable_0_10_74_F400_uid60 is
signal TableOut, TableOut_d1 : std_logic_vector(73 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
TableOut_d1 <= TableOut;
end if;
end process;
with X select TableOut <=
"11111111111111101111111111111100000000000000000000000000000000000000000000" when "0000000000",
"11111111111111101111111111111100000000000000000000000000000000000000000000" when "0000000001",
"00000000001111110000011111111101010101011001010101100010001001001100110101" when "0000000010",
"00000000011111110010000000000110101011101010110001000100111011110011100001" when "0000000011",
"00000000101111110100100000100000000101000100110000101110000000110100101101" when "0000000100",
"00000000111111111000000001010001100101011000100010110011010101111110010110" when "0000000101",
"00000001001111111100100010100011010001111000011110001110000111000111011111" when "0000000110",
"00000001100000000010000100011101010001011000011010110101010000001110000011" when "0000000111",
"00000001110000001000100111000111101100001110001001111111101010101110110111" when "0000001000",
"00000010000000010000001010101010101100010001101111001110001001010001100110" when "0000001001",
"00000010010000011000101111001110011100111101111000111101000100100011100011" when "0000001010",
"00000010100000100010010100111011001011010000011001011101111100011101010110" when "0000001011",
"00000010110000101100111011111001000101101010011111111000110000010001010100" when "0000001100",
"00000011000000111000100100010000011100010001010001010101010001000001001011" when "0000001101",
"00000011010001000101001110001001100000101110000010001100010000111011001010" when "0000001110",
"00000011100001010010111001101100100110001110101111100000110011000000001100" when "0000001111",
"00000011110001100001100111000010000001100110011000100001011101110101110001" when "0000010000",
"00000100000001110001010110010010001001001101011000010001110100100111110010" when "0000010001",
"00000100010010000010000111100101010101000001111111011011111001011111111011" when "0000010010",
"00000100100010010011111011000011111110101000101110001001111100011001010001" when "0000010011",
"00000100110010100110110000110110100001001100101110001000011001011000100110" when "0000010100",
"00000101000010111010101001000101011001100000001100110000001001110011001001" when "0000010101",
"00000101010011001111100011111001000101111100110101011001001011001110100110" when "0000010110",
"00000101100011100101100001011010000110100100001011110101011111100111000101" when "0000010111",
"00000101110011111100100001110000111101000000000110110100101001101001000100" when "0000011000",
"00000110000100010100100101000110001100100011001010101111101000101110011011" when "0000011001",
"00000110010100101101101011100010011010001001000100011101010111101111100110" when "0000011010",
"00000110100101000111110101001110001100010111000100001111110001111011000010" when "0000011011",
"00000110110101100011000010010010001011011100011000111001100001000110111001" when "0000011100",
"00000111000101111111010010110111000001010010101010111100011000110001111111" when "0000011101",
"00000111010110011100100111000101011001011110011000000000100001001010111101" when "0000011110",
"00000111100110111010111111000110000001001111001110010100010101110101101101" when "0000011111",
"00000111110111011010011011000001100111100000101000010101011011001001001110" when "0000100000",
"00000111110111011010011011000001100111100000101000010101011011001001001110" when "0000100001",
"00001000000111111010111011000000111100111010001000100010001110000000101110" when "0000100010",
"00001000011000011100011111001100110011101111110101010100110001011101010100" when "0000100011",
"00001000101000111111000111101110000000000010110101000110011101010110010111" when "0000100100",
"00001000111001100010110100101101010111100001101010011100110001111000110110" when "0000100101",
"00001001001010000111100110010011110001101000110000011111010011010111000000" when "0000100110",
"00001001011010101101011100101010000111100010110111010110110001101011101010" when "0000100111",
"00001001101011010100010111111001010100001001100000110101011111010101111100" when "0000101000",
"00001001111011111100011000001010010100000101011101001000111011010011111110" when "0000101001",
"00001010001100100101011101100110000101101111000111110100110001100100010100" when "0000101010",
"00001010011101001111101000010101101001001111000100110111010101111000010010" when "0000101011",
"00001010101101111010111000100010000000011110011101110111011100100010000001" when "0000101100",
"00001010111110100111001110010100001111000111011111011011110100101100000000" when "0000101101",
"00001011001111010100101001110101011010100101110110101100001000001000001010" when "0000101110",
"00001011001111010100101001110101011010100101110110101100001000001000001010" when "0000101111",
"00001011100000000011001011001110101010000111001110111011100100000111011100" when "0000110000",
"00001011110000110010110010101001000110101011101111011101001111001011111000" when "0000110001",
"00001100000001100011100000001101111011000110011001100010001111101001000011" when "0000110010",
"00001100010010010101010100000110010011111101100110100001100110101000110000" when "0000110011",
"00001100100011001000001110011011011111101011100110001010000011101011000001" when "0000110100",
"00001100110011111100001111010110101110011110111100111101110100011011000101" when "0000110101",
"00001101000100110001010111000001010010011011000010111000010100110011111110" when "0000110110",
"00001101010101100111100101100100011111011000100001111110000011010001101010" when "0000110111",
"00001101100110011110111011001001101011000101110101010110011101001101011011" when "0000111000",
"00001101100110011110111011001001101011000101110101010110011101001101011011" when "0000111001",
"00001101110111010111010111111010001101000111101000010000000111100101110100" when "0000111010",
"00001110001000010000111011111111011110111001010101001111000111110100100110" when "0000111011",
"00001110011001001011100111100010111011101101100101100101110000110110111000" when "0000111100",
"00001110101010000111011010101110000000101110110000110111101000101101010111" when "0000111101",
"00001110111011000100010101101010001100111111011100100111001010011100110110" when "0000111110",
"00001111001100000010011000100001000001011010111100001101101000111000101110" when "0000111111",
"00001111011101000001100011011100000000110101110000111101110110000011011000" when "0001000000",
"00001111101110000001110110100100101111111110001010010001010011110010001011" when "0001000001",
"00001111111111000011010010000100110101011100100110000000010001100100110000" when "0001000010",
"00001111111111000011010010000100110101011100100110000000010001100100110000" when "0001000011",
"00010000010000000101110110000101111001110100010001000100011100000001011101" when "0001000100",
"00010000100001001001100010110001100111100011101000000110100010001010010000" when "0001000101",
"00010000110010001110011000010001101011000100111000010110110101000000010011" when "0001000110",
"00010001000011010100010110101111110010101110100000110000100101101101011111" when "0001000111",
"00010001010100011011011110010101101110110011110011001000100110101101111100" when "0001001000",
"00010001100101100011101111001101010001100101010101100110110100010101010100" when "0001001001",
"00010001110110101101001001100000001111010001100100001011001001001101100110" when "0001001010",
"00010001110110101101001001100000001111010001100100001011001001001101100110" when "0001001011",
"00010010000111110111101101011000011110000101010010011101100011001111110000" when "0001001100",
"00010010011001000011011010111111110110001100001101101001011101011000000101" when "0001001101",
"00010010101010010000010010100000010001110001011110100100100010111010100011" when "0001001110",
"00010010111011011110010100000011101101000000001100000001000000111101101111" when "0001001111",
"00010011001100101101011111110100000110000011111101001011011010100100101011" when "0001010000",
"00010011011101111101110101111011011101001001011100010100000100010010100100" when "0001010001",
"00010011011101111101110101111011011101001001011100010100000100010010100100" when "0001010010",
"00010011101111001111010110100011110100011110111001100100001011110101001100" when "0001010011",
"00010100000000100010000001110111010000010100101101111110110000100101010101" when "0001010100",
"00010100010001110101110111111111110110111101111110101101010001101110100011" when "0001010101",
"00010100100011001010111001000111110000110001000000011000010110110010000010" when "0001010110",
"00010100110100100001000101011001001000000111111010101100010111011010011111" when "0001010111",
"00010101000101111000011100111110001001100001001100001010000111011001011001" when "0001011000",
"00010101000101111000011100111110001001100001001100001010000111011001011001" when "0001011001",
"00010101010111010001000000000001000011100000001110000011101011101000000110" when "0001011010",
"00010101101000101010101110101100000110101101111000100101011101001001111010" when "0001011011",
"00010101111010000101101001001001100101111001000111001011011111001110000111" when "0001011100",
"00010110001011100001101111100011110101110111011101000011001101010100000010" when "0001011101",
"00010110011100111111000010000101001101100101101001111001100110010100110010" when "0001011110",
"00010110011100111111000010000101001101100101101001111001100110010100110010" when "0001011111",
"00010110101110011101100000111000000110001000001110110101111001111001100000" when "0001100000",
"00010110111111111101001100000110111010101100000011100000111101000110110101" when "0001100001",
"00010111010001011110000011111100001000100110111011011001001011101001001000" when "0001100010",
"00010111100011000000001000100010001111011000001011010011011010101111001010" when "0001100011",
"00010111110100100011011010000011110000101001001111001000100011000011111010" when "0001100100",
"00010111110100100011011010000011110000101001001111001000100011000011111010" when "0001100101",
"00011000000110000111111000101011010000001110001111110000000110111001111101" when "0001100110",
"00011000010111101101100100100011010100000110101001000111111001111110011010" when "0001100111",
"00011000101001010100011101110110100100011101110000101000110000001010111110" when "0001101000",
"00011000111010111100100100101111101011101011011011101000011000110010000011" when "0001101001",
"00011001001100100101111001011001010110010100100110001000101011100001110110" when "0001101010",
"00011001001100100101111001011001010110010100100110001000101011100001110110" when "0001101011",
"00011001011110010000011011111110010011001011111001110100001100111110100011" when "0001101100",
"00011001101111111100001100101001010011010010010101001000001111110110000110" when "0001101101",
"00011010000001101001001011100101001001110111110010101100011000110010011011" when "0001101110",
"00011010010011010111011000111100101100011011110000110111101010010010100011" when "0001101111",
"00011010010011010111011000111100101100011011110000110111101010010010100011" when "0001110000",
"00011010100101000110110100111010110010101101111001100011011110010100110000" when "0001110001",
"00011010110110110111011111101010010110101110101010001100010011011111011001" when "0001110010",
"00011011001000101001011001010110010100101111111100000000010011011000100011" when "0001110011",
"00011011011010011100100010001001101011010101101100011011110111111111010100" when "0001110100",
"00011011101100010000111010001111011011010110100101110100010101111100101011" when "0001110101",
"00011011101100010000111010001111011011010110100101110100010101111100101011" when "0001110110",
"00011011111110000110100001110010100111111100101000010000110001100100011011" when "0001110111",
"00011100001111111101011000111110010110100101110010110001000100100001110100" when "0001111000",
"00011100100001110101011111111101101111000100101100100011011010001110001101" when "0001111001",
"00011100110011101110110110111011111011100001001110101000001000110011000000" when "0001111010",
"00011100110011101110110110111011111011100001001110101000001000110011000000" when "0001111011",
"00011101000101101001011110000100001000011001001101100100001100111011011000" when "0001111100",
"00011101010111100101010101100001100100100001000011100010001110011100110000" when "0001111101",
"00011101101001100010011101011111100001000100011010100010010100000000100000" when "0001111110",
"00011101101001100010011101011111100001000100011010100010010100000000100000" when "0001111111",
"00011101111011100000110110001001010001100110110110111000101011111011111011" when "0010000000",
"00011110001101100000011111101010001100000100100001111011010000100111001101" when "0010000001",
"00011110011111100001011010001101101000110010110100111110001110100110010001" when "0010000010",
"00011110110001100011100101111111000010100001000100011111110010111010100000" when "0010000011",
"00011110110001100011100101111111000010100001000100011111110010111010100000" when "0010000100",
"00011111000011100111000011001001110110011001001011100011000111110110110001" when "0010000101",
"00011111010101101011110001111001100100000000010111011010100110110010011111" when "0010000110",
"00011111100111110001110010011001101101010111110011100001100101011100000011" when "0010000111",
"00011111111001111001000100110101110110111101010101100101100101001101100001" when "0010001000",
"00011111111001111001000100110101110110111101010101100101100101001101100001" when "0010001001",
"00100000001100000001101001011001100111101100001001111111001011001010001110" when "0010001010",
"00100000011110001011100000010000101000111101100000011010100111001111000110" when "0010001011",
"00100000110000010110101001100110100110101001011000110000010001100010100001" when "0010001100",
"00100000110000010110101001100110100110101001011000110000010001100010100001" when "0010001101",
"00100001000010100011000101100111001111000111010000001101000100010100100000" when "0010001110",
"00100001010100110000110100011110010011001110101110101010111001100010100100" when "0010001111",
"00100001100110111111110110010111100110011000010100011001010010110110101100" when "0010010000",
"00100001111001010000001011011110111110011110000111110110010010111011111001" when "0010010001",
"00100001111001010000001011011110111110011110000111110110010010111011111001" when "0010010010",
"00100010001011100001110100000000010011111100100011110111101111000110011100" when "0010010011",
"00100010011101110100110000000111100001110011000110000101000000010001001110" when "0010010100",
"00100010110000001001000000000000100101100100111101100001011010010101010010" when "0010010101",
"00100010110000001001000000000000100101100100111101100001011010010101010010" when "0010010110",
"00100011000010011110100011110111011111011001111001100111010001000100010111" when "0010010111",
"00100011010100110101011011111000010001111110111001010011110001110010001000" when "0010011000",
"00100011100111001101101000001111000010100110111010100011111000111100011100" when "0010011001",
"00100011100111001101101000001111000010100110111010100011111000111100011100" when "0010011010",
"00100011111001100111001001000111111001001011101010000010001011000101100101" when "0010011011",
"00100100001100000001111110101111000000001110010011000101111000011000000011" when "0010011100",
"00100100011110011110001001010000100100111000010000000011010010001110010000" when "0010011101",
"00100100011110011110001001010000100100111000010000000011010010001110010000" when "0010011110",
"00100100110000111011101000111000110110111011111010101101011010011101000100" when "0010011111",
"00100101000011011010011101110100001000110101011101001001010011100011010110" when "0010100000",
"00100101010101111010101000001110101111101011100010110010111001100100101111" when "0010100001",
"00100101010101111010101000001110101111101011100010110010111001100100101111" when "0010100010",
"00100101101000011100001000010101000011010000001001110011101011011001100110" when "0010100011",
"00100101111010111110111110010011011110000001010100101011001100000010000110" when "0010100100",
"00100110001101100011001010010110011101001001111100001001100011101110001110" when "0010100101",
"00100110001101100011001010010110011101001001111100001001100011101110001110" when "0010100110",
"00100110100000001000101100101010100000100010100001011100001000110000100000" when "0010100111",
"00100110110010101111100101011100001010110010000000101100010111110101000001" when "0010101000",
"00100111000101010111110100111000000001001110100011110001000011111010101110" when "0010101001",
"00100111000101010111110100111000000001001110100011110001000011111010101110" when "0010101010",
"00100111011000000001011011001010101011111110010101010010000101110000110110" when "0010101011",
"00100111101010101100011000100000110101111000010011111110110010111110000101" when "0010101100",
"00100111101010101100011000100000110101111000010011111110110010111110000101" when "0010101101",
"00100111111101011000101101000111001100100101000110010111000100111100000011" when "0010101110",
"00101000010000000110011001001010100000011111101110100111010111110100111000" when "0010101111",
"00101000100010110101011100110111100100110110011110110111101001110101100100" when "0010110000",
"00101000100010110101011100110111100100110110011110110111101001110101100100" when "0010110001",
"00101000110101100101111000011011001111101011101101101101100011001011111000" when "0010110010",
"00101001001000010111101100000010011001110110101011000001101111001010101010" when "0010110011",
"00101001011011001010110111111001111111000100010101001000101110110011110110" when "0010110100",
"00101001011011001010110111111001111111000100010101001000101110110011110110" when "0010110101",
"00101001101101111111011100001110111101111000001110001111001101101100000110" when "0010110110",
"00101010000000110101011001001110010111101101010010001010000001011111111101" when "0010110111",
"00101010000000110101011001001110010111101101010010001010000001011111111101" when "0010111000",
"00101010010011101100101111000101010000110110101100011001111101000111001011" when "0010111001",
"00101010100110100101011110000000110000100000101110100011011111110111001100" when "0010111010",
"00101010111001011111100110001110000000110001100110111010101001111010011011" when "0010111011",
"00101010111001011111100110001110000000110001100110111010101001111010011011" when "0010111100",
"00101011001100011011000111111010001110101010010111100010111110100110100010" when "0010111101",
"00101011011111011000000011010010101010000111101101100011111101110000010100" when "0010111110",
"00101011011111011000000011010010101010000111101101100011111101110000010100" when "0010111111",
"00101011110010010110011000100100100110000010111000110001111101000000110001" when "0011000000",
"00101100000101010110000111111101011000010010100011101011101010010011011010" when "0011000001",
"00101100011000010111010001101010011001101011101011101100100000101010110001" when "0011000010",
"00101100011000010111010001101010011001101011101011101100100000101010110001" when "0011000011",
"00101100101011011001110101111001000110000010011001110011111000101100101100" when "0011000100",
"00101100111110011101110100110110111100001010111011100001011101111100111110" when "0011000101",
"00101100111110011101110100110110111100001010111011100001011101111100111110" when "0011000110",
"00101101010001100011001110110001011101111010011100000110110010110001100110" when "0011000111",
"00101101100100101010000011110110010000000111111110001110001100000001010000" when "0011001000",
"00101101110111110010010100010010111010101101010101110111001110010000110101" when "0011001001",
"00101101110111110010010100010010111010101101010101110111001110010000110101" when "0011001010",
"00101110001010111100000000010101001000101000000010101000110110001010110000" when "0011001011",
"00101110011110000111001000001010100111111010001010011001010101101111001100" when "0011001100",
"00101110011110000111001000001010100111111010001010011001010101101111001100" when "0011001101",
"00101110110001010011101100000001001001101011010100001100010000010001110000" when "0011001110",
"00101111000100100001101100000110100010001001100011100110011110111110010000" when "0011001111",
"00101111000100100001101100000110100010001001100011100110011110111110010000" when "0011010000",
"00101111010111110001001000101000101000101010010100011000101000000011010100" when "0011010001",
"00101111101011000010000001110101010111101011010110011111110010100111010000" when "0011010010",
"00101111101011000010000001110101010111101011010110011111110010100111010000" when "0011010011",
"00101111111110010100010111111010101100110011101010011101000001010000001100" when "0011010100",
"00110000010001101000001011000110101000110100011110000011011101101110011010" when "0011010101",
"00110000100100111101011011100111001111101010001001011101011111111101010100" when "0011010110",
"00110000100100111101011011100111001111101010001001011101011111111101010100" when "0011010111",
"00110000111000010100001001101010101000011101001100101000111010110100001100" when "0011011000",
"00110001001011101100010101011110111101100011001101001010011001000110010000" when "0011011001",
"00110001001011101100010101011110111101100011001101001010011001000110010000" when "0011011010",
"00110001011111000101111111010010011100011111110100011000010101010110101010" when "0011011011",
"00110001110010100001000111010011010110000101101101111101010111001010101101" when "0011011100",
"00110001110010100001000111010011010110000101101101111101010111001010101101" when "0011011101",
"00110010000101111101101101101111111110010111100110110010100000101010001001" when "0011011110",
"00110010011001011011110010110110101100101001001100010001010111000011101011" when "0011011111",
"00110010011001011011110010110110101100101001001100010001010111000011101011" when "0011100000",
"00110010101100111011010110110101111011100000001011111110010001010000101100" when "0011100001",
"00110011000000011100011001111100001000110101010011101010110111011001111010" when "0011100010",
"00110011000000011100011001111100001000110101010011101010110111011001111010" when "0011100011",
"00110011010011111110111100010111110101110101010001110000111110100011111100" when "0011100100",
"00110011100111100010111110010111100111000001110110000110001011110001000011" when "0011100101",
"00110011100111100010111110010111100111000001110110000110001011110001000011" when "0011100110",
"00110011111011001000100000001010000100010010110011001000001001101011010001" when "0011100111",
"00110100001110101111100001111101111000110110111111100001111100001111111111" when "0011101000",
"00110100001110101111100001111101111000110110111111100001111100001111111111" when "0011101001",
"00110100100010011000000100000001110011010101011000001010011101111100100000" when "0011101010",
"00110100110110000010000110100100100101101110000010011100010010000000111111" when "0011101011",
"00110100110110000010000110100100100101101110000010011100010010000000111111" when "0011101100",
"00110101001001101101101001110101000101011011001111000110110111100101011111" when "0011101101",
"00110101011101011010101110000010001011010010011101011001101001010011010100" when "0011101110",
"00110101011101011010101110000010001011010010011101011001101001010011010100" when "0011101111",
"00110101110001001001010011011010110011100101011110101000110101011010111001" when "0011110000",
"00110110000100111001011010001101111110000011011010001100011010010101001000" when "0011110001",
"00110110000100111001011010001101111110000011011010001100011010010101001000" when "0011110010",
"00110110011000101011000010101010101101111001110001111001010011100101011001" when "0011110011",
"00110110101100011110001101000000001001110101100110110101000011101000001111" when "0011110100",
"00110110101100011110001101000000001001110101100110110101000011101000001111" when "0011110101",
"00110111000000010010111001011101011100000100011110100100000110100000111100" when "0011110110",
"00110111000000010010111001011101011100000100011110100100000110100000111100" when "0011110111",
"00110111010100001001001000010001110010010101101000110010111001111111010001" when "0011111000",
"00110111101000000000111001101100011101111011000101011010000111011101001101" when "0011111001",
"00110111101000000000111001101100011101111011000101011010000111011101001101" when "0011111010",
"00110111111011111010001101111100110011101010101010111101111100011011010000" when "0011111011",
"00111000001111110101000101010010001011111111001101101000111110001000110101" when "0011111100",
"00111000001111110101000101010010001011111111001101101000111110001000110101" when "0011111101",
"00111000100011110001011111111100000010111001100110100010100101001101011000" when "0011111110",
"00111000110111101111011110001001111000000001111011100001001110001101001110" when "0011111111",
"00111000110111101111011110001001111000000001111011100001001110001101001110" when "0100000000",
"00111001001011101111000000001011001110101000100111011000101100001101010010" when "0100000001",
"00111001011111110000000110001111101101100111100010100100101010011110100011" when "0100000010",
"00111001011111110000000110001111101101100111100010100100101010011110100011" when "0100000011",
"00111001110011110010110000100110111111100011001100001111101010100010111100" when "0100000100",
"00111001110011110010110000100110111111100011001100001111101010100010111100" when "0100000101",
"00111010000111110110111111100000110010101011110011110110101100000011000101" when "0100000110",
"00111010011011111100110011001100111000111110100011001001101011110100110010" when "0100000111",
"00111010011011111100110011001100111000111110100011001001101011110100110010" when "0100001000",
"00111010110000000100001011111011001000000110101000101001000111111001000001" when "0100001001",
"00111011000100001101001001111011011001011110100010100000110101111111110111" when "0100001010",
"00111011000100001101001001111011011001011110100010100000110101111111110111" when "0100001011",
"00111011011000010111101101011101101010010001001010000000011010101000010010" when "0100001100",
"00111011101100100011110110110001111011011010111111010001001110011001011001" when "0100001101",
"00111011101100100011110110110001111011011010111111010001001110011001011001" when "0100001110",
"00111100000000110001100110001000010001101011010101101010011111111010100100" when "0100001111",
"00111100000000110001100110001000010001101011010101101010011111111010100100" when "0100010000",
"00111100010101000000111011110000110101100101100000100011100000010111011110" when "0100010001",
"00111100101001010001110111111011110011100010000000100100001001000100111011" when "0100010010",
"00111100101001010001110111111011110011100010000000100100001001000100111011" when "0100010011",
"00111100111101100100011010111001011011101111110001010100001000100011101110" when "0100010100",
"00111101010001111000100100111010000010010101010111101001000101100110001110" when "0100010101",
"00111101010001111000100100111010000010010101010111101001000101100110001110" when "0100010110",
"00111101100110001110010110001101111111010010010000010011100111000101110000" when "0100010111",
"00111101100110001110010110001101111111010010010000010011100111000101110000" when "0100011000",
"00111101111010100101101111000101101110011111111111001011101111011101010101" when "0100011001",
"00111110001110111110101111110001101111110011011110111100111010100110110100" when "0100011010",
"00111110001110111110101111110001101111110011011110111100111010100110110100" when "0100011011",
"00111110100011011001011000100010100110111110010001010001101101100000111000" when "0100011100",
"00111110100011011001011000100010100110111110010001010001101101100000111000" when "0100011101",
"00111110110111110101101001101000111011101111101111011111100110101011101010" when "0100011110",
"00111111001100010011100011010101011001110110011011110010111110110011001010" when "0100011111",
"00111111001100010011100011010101011001110110011011110010111110110011001010" when "0100100000",
"00111111100000110011000101111000110001000001010010111011101001000110111100" when "0100100001",
"00111111100000110011000101111000110001000001010010111011101001000110111100" when "0100100010",
"00111111110101010100010001100011110101000000111110011010000011000110111100" when "0100100011",
"01000000001001110111000110100111011101101001000111001101100011010110100010" when "0100100100",
"01000000001001110111000110100111011101101001000111001101100011010110100010" when "0100100101",
"01000000011110011011100101010100100110110001101001000011110111001111101100" when "0100100110",
"01000000110011000001101101111100010000011000000110001001111111111000101010" when "0100100111",
"01000000110011000001101101111100010000011000000110001001111111111000101010" when "0100101000",
"01000001000111101001100000101111011110100000111011011110111110001000011010" when "0100101001",
"01000001000111101001100000101111011110100000111011011110111110001000011010" when "0100101010",
"01000001011100010010111101111111011001011000110101101000011110001110001111" when "0100101011",
"01000001110000111110000101111101001101010110000110001001110011011011000110" when "0100101100",
"01000001110000111110000101111101001101010110000110001001110011011011000110" when "0100101101",
"01000010000101101010111000111010001010111001111001011101010100010011111101" when "0100101110",
"01000010000101101010111000111010001010111001111001011101010100010011111101" when "0100101111",
"01000010011010011001010111000111100110110001101101010000101000011110000110" when "0100110000",
"01000010101111001001100000110110111001111000100111100011111000011111101010" when "0100110001",
"01000010101111001001100000110110111001111000100111100011111000011111101010" when "0100110010",
"01000011000011111011010110011001100001011000101110001100010001011000101100" when "0100110011",
"01000011000011111011010110011001100001011000101110001100010001011000101100" when "0100110100",
"01000011011000101110111000000000111110101100011110111010001100100010001000" when "0100110101",
"01000011011000101110111000000000111110101100011110111010001100100010001000" when "0100110110",
"01000011101101100100000101111110110111100000001000000011001101101010010111" when "0100110111",
"01000100000010011011000000100100110101110011000001110000001000010001000000" when "0100111000",
"01000100000010011011000000100100110101110011000001110000001000010001000000" when "0100111001",
"01000100010111010011101000000100100111111001000111101111011110001100111000" when "0100111010",
"01000100010111010011101000000100100111111001000111101111011110001100111000" when "0100111011",
"01000100101100001101111100110000000000011100010011101100101001010010001010" when "0100111100",
"01000101000001001001111110111000110110011101111000001100000001111000001001" when "0100111101",
"01000101000001001001111110111000110110011101111000001100000001111000001001" when "0100111110",
"01000101010110000111101110110001000101010111111100001100010100101001000000" when "0100111111",
"01000101010110000111101110110001000101010111111100001100010100101001000000" when "0101000000",
"01000101101011000111001100101010101100111110110111001101011001101111110000" when "0101000001",
"01000101101011000111001100101010101100111110110111001101011001101111110000" when "0101000010",
"01000110000000001000011000110111110001100010101101111101000000000011011110" when "0101000011",
"01000110010101001011010011101010011011110000101111101001011110111001110110" when "0101000100",
"01000110010101001011010011101010011011110000101111101001011110111001110110" when "0101000101",
"01000110101010001111111101010100111000110100110011111011000001010100101100" when "0101000110",
"01000110101010001111111101010100111000110100110011111011000001010100101100" when "0101000111",
"01000110111111010110010110001001011010011010111001010011011101101010100010" when "0101001000",
"01000110111111010110010110001001011010011010111001010011011101101010100010" when "0101001001",
"01000111010100011110011110011010010110110000100100010101001100110011111000" when "0101001010",
"01000111101001101000010110011010001000100110011111010001010100010010110001" when "0101001011",
"01000111101001101000010110011010001000100110011111010001010100010010110001" when "0101001100",
"01000111111110110011111110011011001111010001111010011101010110110101000101" when "0101001101",
"01000111111110110011111110011011001111010001111010011101010110110101000101" when "0101001110",
"01001000010100000001010110110000001110101110001101010000111110111101011101" when "0101001111",
"01001000010100000001010110110000001110101110001101010000111110111101011101" when "0101010000",
"01001000101001010000011111101011101111011110010111101011110111101001111110" when "0101010001",
"01001000111110100001011001100000011110101110100100100100000110111011011110" when "0101010010",
"01001000111110100001011001100000011110101110100100100100000110111011011110" when "0101010011",
"01001001010011110100000100100001001110010101101100011101011110101100000100" when "0101010100",
"01001001010011110100000100100001001110010101101100011101011110101100000100" when "0101010101",
"01001001101001001000100001000000110100110110111001001001111000001110111110" when "0101010110",
"01001001101001001000100001000000110100110110111001001001111000001110111110" when "0101010111",
"01001001111110011110101111010010001101100011001001110011001110111111111110" when "0101011000",
"01001010010011110110101111101000011000011010110111101111001111010100100011" when "0101011001",
"01001010010011110110101111101000011000011010110111101111001111010100100011" when "0101011010",
"01001010101001010000100010010110011010001111011011111101001110001101010101" when "0101011011",
"01001010101001010000100010010110011010001111011011111101001110001101010101" when "0101011100",
"01001010111110101100000111101111011100100100110101001110011111010010010100" when "0101011101",
"01001010111110101100000111101111011100100100110101001110011111010010010100" when "0101011110",
"01001011010100001001100000000110101101110011001110111001011110010001000110" when "0101011111",
"01001011010100001001100000000110101101110011001110111001011110010001000110" when "0101100000",
"01001011101001101000101011101111100001001000101000011000000001100000100101" when "0101100001",
"01001011111111001001101010111101001110101010011101010001001011011010110000" when "0101100010",
"01001011111111001001101010111101001110101010011101010001001011011010110000" when "0101100011",
"01001100010100101100011110000011010011010111001110001110110000101001011010" when "0101100100",
"01001100010100101100011110000011010011010111001110001110110000101001011010" when "0101100101",
"01001100101010010001000101010101010001001000001010011111001001010000001010" when "0101100110",
"01001100101010010001000101010101010001001000001010011111001001010000001010" when "0101100111",
"01001100111111110111100001000110101110110010111010000011100011001010101010" when "0101101000",
"01001100111111110111100001000110101110110010111010000011100011001010101010" when "0101101001",
"01001101010101011111110001101011011000001011001000101011001100100011101101" when "0101101010",
"01001101010101011111110001101011011000001011001000101011001100100011101101" when "0101101011",
"01001101101011001001110111010110111110000100010001011011101100110110110001" when "0101101100",
"01001110000000110101110010011101010110010011001011000111000011011011011000" when "0101101101",
"01001110000000110101110010011101010110010011001011000111000011011011011000" when "0101101110",
"01001110010110100011100011010010011011101111110101001111100011000111010101" when "0101101111",
"01001110010110100011100011010010011011101111110101001111100011000111010101" when "0101110000",
"01001110101100010011001010001010001110010111000101111010000010000010001000" when "0101110001",
"01001110101100010011001010001010001110010111000101111010000010000010001000" when "0101110010",
"01001111000010000100100111011000110011001100011000001110110101010010110110" when "0101110011",
"01001111000010000100100111011000110011001100011000001110110101010010110110" when "0101110100",
"01001111010111110111111011010010010100011011011011101001110000011110101011" when "0101110101",
"01001111010111110111111011010010010100011011011011101001110000011110101011" when "0101110110",
"01001111101101101101000110001011000001011010000011111001100000111101011010" when "0101110111",
"01010000000011100100001000010111001110101001111001101110111101010111010001" when "0101111000",
"01010000000011100100001000010111001110101001111001101110111101010111010001" when "0101111001",
"01010000011001011101000010001011010101111010001100011100100001101101110110" when "0101111010",
"01010000011001011101000010001011010101111010001100011100100001101101110110" when "0101111011",
"01010000101111010111110011111011110110001001100100000110010001000000111110" when "0101111100",
"01010000101111010111110011111011110110001001100100000110010001000000111110" when "0101111101",
"01010001000101010100011101111101010011100111110100100010110101001110110110" when "0101111110",
"01010001000101010100011101111101010011100111110100100010110101001110110110" when "0101111111",
"01010001011011010011000000100100010111110111110001001101110110111110001100" when "0110000000",
"01010001011011010011000000100100010111110111110001001101110110111110001100" when "0110000001",
"01010001110001010011011100000101110001110001000001101100000110001111101101" when "0110000010",
"01010001110001010011011100000101110001110001000001101100000110001111101101" when "0110000011",
"01010010000111010101110000110110010101100001110111000001101110000100011010" when "0110000100",
"01010010000111010101110000110110010101100001110111000001101110000100011010" when "0110000101",
"01010010011101011001111111001010111100110001000001111011001100110100110110" when "0110000110",
"01010010011101011001111111001010111100110001000001111011001100110100110110" when "0110000111",
"01010010110011100000000111011000100110011111101001101001001011100101111111" when "0110001000",
"01010011001001101000001001110100010111001011000011101111101110110111001010" when "0110001001",
"01010011001001101000001001110100010111001011000011101111101110110111001010" when "0110001010",
"01010011011111110010000110110011011000101110101100101001011011010101111000" when "0110001011",
"01010011011111110010000110110011011000101110101100101001011011010101111000" when "0110001100",
"01010011110101111101111110101010111010100110000000111110101001110011010011" when "0110001101",
"01010011110101111101111110101010111010100110000000111110101001110011010011" when "0110001110",
"01010100001100001011110001110000010001101110010111110001100101001000000110" when "0110001111",
"01010100001100001011110001110000010001101110010111110001100101001000000110" when "0110010000",
"01010100100010011011100000011000111000101000111101011111001110000100000011" when "0110010001",
"01010100100010011011100000011000111000101000111101011111001110000100000011" when "0110010010",
"01010100111000101101001010111010001111011100101111110110000000010111001000" when "0110010011",
"01010100111000101101001010111010001111011100101111110110000000010111001000" when "0110010100",
"01010101001111000000110001101001111011111000011010100010010101010011000000" when "0110010101",
"01010101001111000000110001101001111011111000011010100010010101010011000000" when "0110010110",
"01010101100101010110010100111101101001010100010100110001011111110100101100" when "0110010111",
"01010101100101010110010100111101101001010100010100110001011111110100101100" when "0110011000",
"01010101111011101101110101001011001000110100011111101011011110110111101110" when "0110011001",
"01010101111011101101110101001011001000110100011111101011011110110111101110" when "0110011010",
"01010110010010000111010010101000010001001010100101100100000010100101100010" when "0110011011",
"01010110010010000111010010101000010001001010100101100100000010100101100010" when "0110011100",
"01010110101000100010101101101010111110110111111010000011100001100100111110" when "0110011101",
"01010110101000100010101101101010111110110111111010000011100001100100111110" when "0110011110",
"01010110111111000000000110101001010100001111011011000111111011100000101001" when "0110011111",
"01010110111111000000000110101001010100001111011011000111111011100000101001" when "0110100000",
"01010111010101011111011101111001011001010111110010111110100110101011111100" when "0110100001",
"01010111010101011111011101111001011001010111110010111110100110101011111100" when "0110100010",
"01010111101100000000110011110001011100001101011010110111000110100001001000" when "0110100011",
"01010111101100000000110011110001011100001101011010110111000110100001001000" when "0110100100",
"01011000000010100100001000100111110000100100011110101111101001000101110111" when "0110100101",
"01011000000010100100001000100111110000100100011110101111101001000101110111" when "0110100110",
"01011000011001001001011100110010110000001011000001111011101010010101000000" when "0110100111",
"01011000011001001001011100110010110000001011000001111011101010010101000000" when "0110101000",
"01011000101111110000110000101000111010101011000100100100111011100000110010" when "0110101001",
"01011000101111110000110000101000111010101011000100100100111011100000110010" when "0110101010",
"01011001000110011010000100100000110101101100101010000111101110010010010111" when "0110101011",
"01011001000110011010000100100000110101101100101010000111101110010010010111" when "0110101100",
"01011001011101000101011000110001001100111000000000101010100010011111101010" when "0110101101",
"01011001011101000101011000110001001100111000000000101010100010011111101010" when "0110101110",
"01011001110011110010101101110000110001110111101001010001110110100011101010" when "0110101111",
"01011001110011110010101101110000110001110111101001010001110110100011101010" when "0110110000",
"01011010001010100010000011110110011100011010100001010000011010011001001110" when "0110110001",
"01011010001010100010000011110110011100011010100001010000011010011001001110" when "0110110010",
"01011010100001010011011011011001001010010110001100010100100101001100001010" when "0110110011",
"01011010100001010011011011011001001010010110001100010100100101001100001010" when "0110110100",
"01011010111000000110110100101111111111101000111111110011001110101000011010" when "0110110101",
"01011010111000000110110100101111111111101000111111110011001110101000011010" when "0110110110",
"01011011001110111100010000010010000110011100001110110000101100100100010010" when "0110110111",
"01011011001110111100010000010010000110011100001110110000101100100100010010" when "0110111000",
"01011011100101110011101110010110101111000110010111001000010110010101111100" when "0110111001",
"01011011100101110011101110010110101111000110010111001000010110010101111100" when "0110111010",
"01011011111100101101001111010101010000001101001111110011001111011010100000" when "0110111011",
"01011011111100101101001111010101010000001101001111110011001111011010100000" when "0110111100",
"01011100010011101000110011100101000110101000010111101110011011001001100010" when "0110111101",
"01011100010011101000110011100101000110101000010111101110011011001001100010" when "0110111110",
"01011100101010100110011011011101110101100011000110000001011100000100110010" when "0110111111",
"01011100101010100110011011011101110101100011000110000001011100000100110010" when "0111000000",
"01011101000001100110000111010111000110011110111011000101100001001010010100" when "0111000001",
"01011101000001100110000111010111000110011110111011000101100001001010010100" when "0111000010",
"01011101011000100111110111101000101001010101110010101110000100000100001010" when "0111000011",
"01011101011000100111110111101000101001010101110010101110000100000100001010" when "0111000100",
"01011101101111101011101100101010010100011100010111010010111011100111001010" when "0111000101",
"01011101101111101011101100101010010100011100010111010010111011100111001010" when "0111000110",
"01011110000110110001100110110100000100100100010101111101000110001000101000" when "0111000111",
"01011110000110110001100110110100000100100100010101111101000110001000101000" when "0111001000",
"01011110000110110001100110110100000100100100010101111101000110001000101000" when "0111001001",
"01011110011101111001100110011101111100111110110011110110001111101001011110" when "0111001010",
"01011110011101111001100110011101111100111110110011110110001111101001011110" when "0111001011",
"01011110110101000011101100000000000111011110100100011011111000001011011000" when "0111001100",
"01011110110101000011101100000000000111011110100100011011111000001011011000" when "0111001101",
"01011111001100001111110111110010110100011010100000110110011110111100100000" when "0111001110",
"01011111001100001111110111110010110100011010100000110110011110111100100000" when "0111001111",
"01011111100011011110001010001110011010110000000000010101010111011101000110" when "0111010000",
"01011111100011011110001010001110011010110000000000010101010111011101000110" when "0111010001",
"01011111111010101110100011101011011000000101010001101111101101111001110000" when "0111010010",
"01011111111010101110100011101011011000000101010001101111101101111001110000" when "0111010011",
"01100000010010000001000100100010010000101011110110001011100000101101011010" when "0111010100",
"01100000010010000001000100100010010000101011110110001011100000101101011010" when "0111010101",
"01100000101001010101101101001011101111100010111100101010110101010101110100" when "0111010110",
"01100000101001010101101101001011101111100010111100101010110101010101110100" when "0111010111",
"01100001000000101100011110000000100110011001111111000000001110111101110111" when "0111011000",
"01100001000000101100011110000000100110011001111111000000001110111101110111" when "0111011001",
"01100001011000000101010111011001101101110010111111101010101101111001100110" when "0111011010",
"01100001011000000101010111011001101101110010111111101010101101111001100110" when "0111011011",
"01100001011000000101010111011001101101110010111111101010101101111001100110" when "0111011100",
"01100001101111100000011001110000000101000101001000111001111111001000111100" when "0111011101",
"01100001101111100000011001110000000101000101001000111001111111001000111100" when "0111011110",
"01100010000110111101100101011100110010011111001100111011100011101111000001" when "0111011111",
"01100010000110111101100101011100110010011111001100111011100011101111000001" when "0111100000",
"01100010011110011100111010111001000011001010000111010001011000000110000100" when "0111100001",
"01100010011110011100111010111001000011001010000111010001011000000110000100" when "0111100010",
"01100010110101111110011010011110001011001011011111010010100011110000110100" when "0111100011",
"01100010110101111110011010011110001011001011011111010010100011110000110100" when "0111100100",
"01100011001101100010000100100101100101101000001011110110111010100101011010" when "0111100101",
"01100011001101100010000100100101100101101000001011110110111010100101011010" when "0111100110",
"01100011100101000111111001101000110100100110111000001101111000100111011001" when "0111100111",
"01100011100101000111111001101000110100100110111000001101111000100111011001" when "0111101000",
"01100011100101000111111001101000110100100110111000001101111000100111011001" when "0111101001",
"01100011111100101111111010000001100001010010101010000001100010100001100010" when "0111101010",
"01100011111100101111111010000001100001010010101010000001100010100001100010" when "0111101011",
"01100100010100011010000110001001011011111101101000100110010100101011010001" when "0111101100",
"01100100010100011010000110001001011011111101101000100110010100101011010001" when "0111101101",
"01100100101100000110011110011010011100000011100101011000001011100000011101" when "0111101110",
"01100100101100000110011110011010011100000011100101011000001011100000011101" when "0111101111",
"01100101000011110101000011001110100000001100100101100101110000001110010010" when "0111110000",
"01100101000011110101000011001110100000001100100101100101110000001110010010" when "0111110001",
"01100101011011100101110100111111101110001111101101001010010101010011111010" when "0111110010",
"01100101011011100101110100111111101110001111101101001010010101010011111010" when "0111110011",
"01100101011011100101110100111111101110001111101101001010010101010011111010" when "0111110100",
"01100101110011011000110100001000010011010101101010110111001110110001011011" when "0111110101",
"01100101110011011000110100001000010011010101101010110111001110110001011011" when "0111110110",
"01100110001011001110000001000010100011111011100101101101010010011101001100" when "0111110111",
"01100110001011001110000001000010100011111011100101101101010010011101001100" when "0111111000",
"01100110100011000101011100001000111011110101101011100111001101010011010101" when "0111111001",
"01100110100011000101011100001000111011110101101011100111001101010011010101" when "0111111010",
"01100110111010111111000101110101111110010010000001010101011010110001110000" when "0111111011",
"01100110111010111111000101110101111110010010000001010101011010110001110000" when "0111111100",
"01100110111010111111000101110101111110010010000001010101011010110001110000" when "0111111101",
"01100111010010111010111110100100010101111011010011101100001100001111011110" when "0111111110",
"01100111010010111010111110100100010101111011010011101100001100001111011110" when "0111111111",
"10110110001110010111100110110111000000011110101100001011000011100000101000" when "1000000000",
"10110110011010010111100000110111001100011110011101001011011101111001100100" when "1000000001",
"10110110100110010111111110111000100000100010011100011000010000111101110111" when "1000000010",
"10110110110010011001000000111110010101000100000000011101110101111000000100" when "1000000011",
"10110110111110011010100111001100000010111010111111110000000000001100111000" when "1000000100",
"10110111001010011100110001100101000011011101110101111000111011010000011000" when "1000000101",
"10110111001010011100110001100101000011011101110101111000111011010000011000" when "1000000110",
"10110111010110011111100000001100110000100001101001101001011101101111011000" when "1000000111",
"10110111100010100010110011000110100100011010010010101010110100000100110110" when "1000001000",
"10110111101110100110101010010101111001111010011111010001100001110100011000" when "1000001001",
"10110111111010101011000101111110001100010011111010010001111010100001111010" when "1000001010",
"10111000000110110000000110000010110111010111010000110101110010011111111000" when "1000001011",
"10111000010010110101101010100111010111010100011000010011100111101100001010" when "1000001100",
"10111000011110111011110011101111001000111010010100000111000011010101011001" when "1000001101",
"10111000011110111011110011101111001000111010010100000111000011010101011001" when "1000001110",
"10111000101011000010100001011101101001010111011011101010110100100001011101" when "1000001111",
"10111000110111001001110011110110010110011001100000010100000100001110010111" when "1000010000",
"10111001000011010001101010111100101110001101110011001111000011000111010010" when "1000010001",
"10111001001111011010000110110100001111100001001011011101010001100110110111" when "1000010010",
"10111001011011100011000111100000011001100000001011110101000010100000110010" when "1000010011",
"10111001100111101100101101000100101011110111001001000010011000101100001100" when "1000010100",
"10111001110011110110110111100100100110110010001111101001100000001001000011" when "1000010101",
"10111001110011110110110111100100100110110010001111101001100000001001000011" when "1000010110",
"10111010000000000001100111000011101010111101101010001010100010111010011101" when "1000010111",
"10111010001100001100111011100101011001100101100111000110111010010000000001" when "1000011000",
"10111010011000011000110101001101010100010110011111000111111100011000110100" when "1000011001",
"10111010100100100101010011111110111101011100111011000111000111011010010100" when "1000011010",
"10111010110000110010010111111101110111100101111010010111101001100101111000" when "1000011011",
"10111010111101000000000001001101100101111110111000110001100111100111101001" when "1000011100",
"10111010111101000000000001001101100101111110111000110001100111100111101001" when "1000011101",
"10111011001001001110001111110001101100010101110100111110100001001001101000" when "1000011110",
"10111011010101011101000011101101101110111001010110100111010100000110000101" when "1000011111",
"10111011100001101100011101000101010010011000110100100011111111000100100000" when "1000100000",
"10111011101101111100011011111011111100000100011011001100100011011100001010" when "1000100001",
"10111011111010001101000000010101010001101101010010101011100111011000000110" when "1000100010",
"10111100000110011110001010010100111001100101100101010010011000010111111100" when "1000100011",
"10111100000110011110001010010100111001100101100101010010011000010111111100" when "1000100100",
"10111100010010101111111001111110011010100000100101101110001110101001010000" when "1000100101",
"10111100011111000010001111010101011011110010110101011111110001110101100010" when "1000100110",
"10111100101011010101001010011101100101010010001011010011011111100000100111" when "1000100111",
"10111100110111101000101011011010011111010101111001011011110011110100000000" when "1000101000",
"10111101000011111100110010001111110010110110110100001100110100110011001110" when "1000101001",
"10111101010000010001011111000001001001001111011000011001100000110101101110" when "1000101010",
"10111101010000010001011111000001001001001111011000011001100000110101101110" when "1000101011",
"10111101011100100110110001110010001100011011110001110010100000100011000000" when "1000101100",
"10111101101000111100101010100110100110111010000001100110011100101101111110" when "1000101101",
"10111101110101010011001001100010000011101010000101000011111000101011111101" when "1000101110",
"10111110000001101010001110101000001110001101111011111100110001100100111101" when "1000101111",
"10111110001110000001111001111100110010101001101111001011100010111010010000" when "1000110000",
"10111110001110000001111001111100110010101001101111001011100010111010010000" when "1000110001",
"10111110011010011010001011100011011101100011110111011001110001000000100110" when "1000110010",
"10111110100110110011000011011111111100000101000011101000011001101011110100" when "1000110011",
"10111110110011001100100001110101111011111000011111111001101011101001010001" when "1000110100",
"10111110111111100110100110101001001011001011111011111100100101000111011000" when "1000110101",
"10111111001100000001010001111101011000101111110001111001111010000111110110" when "1000110110",
"10111111001100000001010001111101011000101111110001111001111010000111110110" when "1000110111",
"10111111011000011100100011110110010011110111001101000011000010111011000110" when "1000111000",
"10111111100100111000011100010111101100011000010000100010010011000011001101" when "1000111001",
"10111111110001010100111011100101010010101011111110001100111001011100101011" when "1000111010",
"10111111111101110010000001100010110111101110011101010110101010001011111101" when "1000111011",
"10111111111101110010000001100010110111101110011101010110101010001011111101" when "1000111100",
"11000000001010001111101110010100001100111111000001100111010010001110011010" when "1000111101",
"11000000010110101110000001111101000100100000010001110001010101101101110011" when "1000111110",
"11000000100011001100111100100001010000111000001110101010111001010101010110" when "1000111111",
"11000000101111101100011110000100100101010000011010000111110111000111111011" when "1001000000",
"11000000111100001100100110101010110101010101111101110101111111010110101001" when "1001000001",
"11000000111100001100100110101010110101010101111101110101111111010110101001" when "1001000010",
"11000001001000101101010110010111110101011001110010011010100101110111101011" when "1001000011",
"11000001010101001110101101001111011010010000100110010001111100011101000001" when "1001000100",
"11000001100001110000101011010101011001010011000100110000011010101011011001" when "1001000101",
"11000001101110010011010000101101101000011101111101000101010011110001010000" when "1001000110",
"11000001101110010011010000101101101000011101111101000101010011110001010000" when "1001000111",
"11000001111010110110011101011011111110010010001001011111011010111110011100" when "1001001000",
"11000010000111011010010001100100010001110100110110010011010110111100111001" when "1001001001",
"11000010010011111110101101001010011010101111101001000011100100101011001000" when "1001001010",
"11000010100000100011110000010010010001010000100111101010001010011001100010" when "1001001011",
"11000010101101001001011010111111101110001010011111100100011011001011001110" when "1001001100",
"11000010101101001001011010111111101110001010011111100100011011001011001110" when "1001001101",
"11000010111001101111101101010110101010110100101101000000001011011100000010" when "1001001110",
"11000011000110010110100111011011000001001011100010001010110111001100110010" when "1001001111",
"11000011010010111110001001010000101011110000001110100010011010010111101000" when "1001010000",
"11000011011111100110010010111011100101101001000110000111111011101110000010" when "1001010001",
"11000011011111100110010010111011100101101001000110000111111011101110000010" when "1001010010",
"11000011101100001111000100011111101010100001101000110100001011000010101100" when "1001010011",
"11000011111000111000011110000000110110101010101001101101110011000000111111" when "1001010100",
"11000100000101100010011111100011000110111010010110100001011111010100111101" when "1001010101",
"11000100010010001101001001001010011000101100011110111011110111100101110001" when "1001010110",
"11000100010010001101001001001010011000101100011110111011110111100101110001" when "1001010111",
"11000100011110111000011010111010101010000010011100000101001111100101100111" when "1001011000",
"11000100101011100100010100110111111001100011010111111111001101011001111101" when "1001011001",
"11000100111000010000110111000110000110011100010101000100000101111111000100" when "1001011010",
"11000101000100111110000001101001010000100000010101101000010000101010001011" when "1001011011",
"11000101000100111110000001101001010000100000010101101000010000101010001011" when "1001011100",
"11000101010001101011110100100101011000001000100011011101010010001101111000" when "1001011101",
"11000101011110011010001111111110011110010100010111010111000000000011111110" when "1001011110",
"11000101101011001001010011111000100100101001100000110010011100000001001010" when "1001011111",
"11000101101011001001010011111000100100101001100000110010011100000001001010" when "1001100000",
"11000101110111111001000000010111101101010100001101011110101001010110010000" when "1001100001",
"11000110000100101001010101011111111011000111010001000111011011100011001100" when "1001100010",
"11000110010001011010010011010101010001011100001101000001111111100000011010" when "1001100011",
"11000110011110001011111001111011110100010011010111111011011111100011001011" when "1001100100",
"11000110011110001011111001111011110100010011010111111011011111100011001011" when "1001100101",
"11000110101010111110001001010111101000010100000101101001100011000001100011" when "1001100110",
"11000110110111110001000001101100110010101100101110111100101001111011010001" when "1001100111",
"11000111000100100100100010111111011001010010111001010100100101001100100110" when "1001101000",
"11000111010001011000101101010011100010100011011110110110101100010000100110" when "1001101001",
"11000111010001011000101101010011100010100011011110110110101100010000100110" when "1001101010",
"11000111011110001101100000101101010101100010110110000110010000011000101101" when "1001101011",
"11000111101011000010111101010000111001111100111001111110101110011110111110" when "1001101100",
"11000111110111111001000011000010011000000101010001101111111111111001101000" when "1001101101",
"11000111110111111001000011000010011000000101010001101111111111111001101000" when "1001101110",
"11001000000100101111110010000101111000110111011000111100101010110101110000" when "1001101111",
"11001000010001100111001010011111100101110110100111011010010010111111110111" when "1001110000",
"11001000011110011111001100010011101001001110011001010011101011000000110010" when "1001110001",
"11001000011110011111001100010011101001001110011001010011101011000000110010" when "1001110010",
"11001000101011010111110111100110001101110010010111001101000111010110000100" when "1001110011",
"11001000111000010001001100011011011110111110011110001010110011001100111000" when "1001110100",
"11001001000101001011001010110111101000110111000111111001001000000110100011" when "1001110101",
"11001001010010000101110010111110111000001001010010110111001000101110110000" when "1001110110",
"11001001010010000101110010111110111000001001010010110111001000101110110000" when "1001110111",
"11001001011111000001000100110101011010001010101010100010111111101010100110" when "1001111000",
"11001001101011111101000000011111011100111001101111101000100010101001000010" when "1001111001",
"11001001111000111001100110000001001110111110000000010001111010111100011100" when "1001111010",
"11001001111000111001100110000001001110111110000000010001111010111100011100" when "1001111011",
"11001010000101110110110101011110111111101000000000011010010011100110001101" when "1001111100",
"11001010010010110100101110111100111110110001100010000010101101111100100000" when "1001111101",
"11001010011111110011010010011111011100111101101101101000111101010011100110" when "1001111110",
"11001010011111110011010010011111011100111101101101101000111101010011100110" when "1001111111",
"11001010101100110010100000001010101011011001001010100000101010010011011010" when "1010000000",
"11001010111001110010011000000010111011111010000111001110011110100011000100" when "1010000001",
"11001011000110110010111010001100100001000000100010000101011001010011011110" when "1010000010",
"11001011000110110010111010001100100001000000100010000101011001010011011110" when "1010000011",
"11001011010011110100000110101011101101110110010001100110001101110011011000" when "1010000100",
"11001011100000110101111101100100110110001111001101000001001011110110010011" when "1010000101",
"11001011101101111000011110111100001110101001010100111001110011011001001000" when "1010000110",
"11001011101101111000011110111100001110101001010100111001110011011001001000" when "1010000111",
"11001011111010111011101010110110001100001100111011101100110011101110011010" when "1010001000",
"11001100000111111111100001010111000100101100101110011000010110111101101000" when "1010001001",
"11001100010101000100000010100011001110100101111101000110011010011111110001" when "1010001010",
"11001100010101000100000010100011001110100101111101000110011010011111110001" when "1010001011",
"11001100100010001001001110011111000001000000100011111001010101000101000100" when "1010001100",
"11001100101111001111000101001110110011101111010011011010101011001110111000" when "1010001101",
"11001100111100010101100110110110111111001111111001101100010010101001101100" when "1010001110",
"11001100111100010101100110110110111111001111111001101100010010101001101100" when "1010001111",
"11001101001001011100110011011011111100101011001010111011100101010011000110" when "1010010000",
"11001101010110100100101011000010000101110101001010010111000100110111110110" when "1010010001",
"11001101100011101101001101101101110101001101010011000110001111010110101001" when "1010010010",
"11001101100011101101001101101101110101001101010011000110001111010110101001" when "1010010011",
"11001101110000110110011011100011100101111110100001000011100101010100001000" when "1010010100",
"11001101111110000000010100100111110011111111011001111001000010101101010000" when "1010010101",
"11001110001011001010111000111110111011110010010101111110101010110100111011" when "1010010110",
"11001110001011001010111000111110111011110010010101111110101010110100111011" when "1010010111",
"11001110011000010110001000101101011010100101101001011011101000001010101001" when "1010011000",
"11001110100101100010000011110111101110010011101101001001100000110111110000" when "1010011001",
"11001110110010101110101010100010010101100011000111111010000000100001001011" when "1010011010",
"11001110110010101110101010100010010101100011000111111010000000100001001011" when "1010011011",
"11001110111111111011111100110001101111100110110111011110110111111100000000" when "1010011100",
"11001111001101001001111010101010011100011110011001110100010011110011010011" when "1010011101",
"11001111011010011000100100010000111100110101110110001101101010101101111101" when "1010011110",
"11001111011010011000100100010000111100110101110110001101101010101101111101" when "1010011111",
"11001111100111100111111001101001110010000110000110100100100011100011100100" when "1010100000",
"11001111110100110111111010111001011110010101000000101010010100101111100100" when "1010100001",
"11001111110100110111111010111001011110010101000000101010010100101111100100" when "1010100010",
"11010000000010001000101000000100100100010101011111011011111101010010010010" when "1010100011",
"11010000001111011010000001001111100111100111101100011000011000001111100010" when "1010100100",
"11010000011100101100000110011111001100011001001000111001001011011011001100" when "1010100101",
"11010000011100101100000110011111001100011001001000111001001011011011001100" when "1010100110",
"11010000101001111110110111110111110111100100110111101101110010000011100101" when "1010100111",
"11010000110111010010010101011110001110110011100110011001000100001010110010" when "1010101000",
"11010000110111010010010101011110001110110011100110011001000100001010110010" when "1010101001",
"11010001000100100110011111010110111000011011110110110001011011011111100110" when "1010101010",
"11010001010001111011010101100110011011100010001000100011010110100111010001" when "1010101011",
"11010001011111010000111000010001011111111001000010110110011011001001100100" when "1010101100",
"11010001011111010000111000010001011111111001000010110110011011001001100100" when "1010101101",
"11010001101100100111000111011100101110000001011101110100110111110000111010" when "1010101110",
"11010001111001111110000011001100101111001010101100010101100110110000100101" when "1010101111",
"11010010000111010101101011100110001101010010100101101000110010000011011011" when "1010110000",
"11010010000111010101101011100110001101010010100101101000110010000011011011" when "1010110001",
"11010010010100101110000000101101110011000101101111000110111001010101011100" when "1010110010",
"11010010100010000111000010101000001011111111100110000010011011001011011100" when "1010110011",
"11010010100010000111000010101000001011111111100110000010011011001011011100" when "1010110100",
"11010010101111100000110001011010000100001010101001011100000001111011101110" when "1010110101",
"11010010111100111011001101001000001000100000100011111001010101001011011000" when "1010110110",
"11010011001010010110010101110111000110101010010101011110010000100100000001" when "1010110111",
"11010011001010010110010101110111000110101010010101011110010000100100000001" when "1010111000",
"11010011010111110010001011101011101101000000011101101001000000110101110110" when "1010111001",
"11010011100101001110101110101010101010101011000101010000100111111010101001" when "1010111010",
"11010011100101001110101110101010101010101011000101010000100111111010101001" when "1010111011",
"11010011110010101011111110111000101111100010001000100110001000101110010000" when "1010111100",
"11010100000000001001111100011010101100001101100001011000011011110001100001" when "1010111101",
"11010100000000001001111100011010101100001101100001011000011011110001100001" when "1010111110",
"11010100001101101000100111010101010010000101010000111010101101001100111100" when "1010111111",
"11010100011011000111111111101101010011010001101010001101100101001000110011" when "1011000000",
"11010100101000101000000101100111100010101011011100001010111011010000100000" when "1011000001",
"11010100101000101000000101100111100010101011011100001010111011010000100000" when "1011000010",
"11010100110110001000111001001000110011111011111011110100010110010111010010" when "1011000011",
"11010101000011101010011010010101111011011101001110100100011000110101000110" when "1011000100",
"11010101000011101010011010010101111011011101001110100100011000110101000110" when "1011000101",
"11010101010001001100101001010011101110011010010100100010011010110010001010" when "1011000110",
"11010101011110101111100110000111000010101111010010111001010010111000100101" when "1011000111",
"11010101011110101111100110000111000010101111010010111001010010111000100101" when "1011001000",
"11010101101100010011010000110100101111001001011110010000101110100011100000" when "1011001001",
"11010101111001110111101001100001101011000111100101001001011010100011010111" when "1011001010",
"11010110000111011100110000010010101110111001111010011011111100101111101100" when "1011001011",
"11010110000111011100110000010010101110111001111010011011111100101111101100" when "1011001100",
"11010110010101000010100101001100110011100010011111111010011111111110101001" when "1011001101",
"11010110100010101001001000010100110010110101010000110101010010111011010000" when "1011001110",
"11010110100010101001001000010100110010110101010000110101010010111011010000" when "1011001111",
"11010110110000010000011001101111100111011000001100100001111010110011010000" when "1011010000",
"11010110111101111000011001100010001100100011100001000101011010110110001110" when "1011010001",
"11010110111101111000011001100010001100100011100001000101011010110110001110" when "1011010010",
"11010111001011100001000111110001011110100001110110000001010001011111100011" when "1011010011",
"11010111011001001010100100100010011010010000010111000011001100000101100001" when "1011010100",
"11010111011001001010100100100010011010010000010111000011001100000101100001" when "1011010101",
"11010111100110110100101111111001111101011110111110110111110010000111110010" when "1011010110",
"11010111110100011111101001111101000110110000100010000000001000111000010000" when "1011010111",
"11010111110100011111101001111101000110110000100010000000001000111000010000" when "1011011000",
"11011000000010001011010010110000110101011010111001101010010000011001010011" when "1011011001",
"11011000001111110111101010011010001001100111001110101100011010101100111010" when "1011011010",
"11011000011101100100110000111110000100010010000100100011011110010000100101" when "1011011011",
"11011000011101100100110000111110000100010010000100100011011110010000100101" when "1011011100",
"11011000101011010010100110100001100111001011100100010100000100100010000011" when "1011011101",
"11011000111001000001001011001001110100110111100111101110110101101001100010" when "1011011110",
"11011000111001000001001011001001110100110111100111101110110101101001100010" when "1011011111",
"11011001000110110000011110111011110000101110000100010111100010000110010011" when "1011100000",
"11011001010100100000100001111100011110111010110110101111001011011010110010" when "1011100001",
"11011001010100100000100001111100011110111010110110101111001011011010110010" when "1011100010",
"11011001100010010001010100010001000100011110001101100001001100110101110100" when "1011100011",
"11011001110000000010110101111110100111001100110100110011100100110111001011" when "1011100100",
"11011001110000000010110101111110100111001100110100110011100100110111001011" when "1011100101",
"11011001111101110101000111001010001101110000000001011010000000101101011101" when "1011100110",
"11011010001011101000000111111000111111100101111100001100001010101100001010" when "1011100111",
"11011010001011101000000111111000111111100101111100001100001010101100001010" when "1011101000",
"11011010011001011011111000010000000101000001101101011110111100011001000111" when "1011101001",
"11011010100111010000011000010100100111001011101000100000110101110000011101" when "1011101010",
"11011010100111010000011000010100100111001011101000100000110101110000011101" when "1011101011",
"11011010110101000101101000001011110000000001010110111001011001111111010001" when "1011101100",
"11011011000010111011100111111010101010010110000100001011110011010100110100" when "1011101101",
"11011011000010111011100111111010101010010110000100001011110011010100110100" when "1011101110",
"11011011010000110010010111100110100001110010101001011100011110101011000100" when "1011101111",
"11011011011110101001110111010100100010110101111000111010000000000111100100" when "1011110000",
"11011011011110101001110111010100100010110101111000111010000000000111100100" when "1011110001",
"11011011101100100010000111001001111010110100101001101001000001010101110000" when "1011110010",
"11011011111010011011000111001011110111111010000011010011011010111100101110" when "1011110011",
"11011011111010011011000111001011110111111010000011010011011010111100101110" when "1011110100",
"11011100001000010100110111011111101001000111101001111010101001110010010000" when "1011110101",
"11011100010110001111011000001010011110010101101001101101010001001101111101" when "1011110110",
"11011100010110001111011000001010011110010101101001101101010001001101111101" when "1011110111",
"11011100100100001010101001010001101000010011000010111111101011011111010000" when "1011111000",
"11011100110010000110101010111010011000100101110110001000001001001001011000" when "1011111001",
"11011100110010000110101010111010011000100101110110001000001001001001011000" when "1011111010",
"11011101000000000011011101001010000001101011001111011110000000101001011111" when "1011111011",
"11011101001110000001000000000101110110110111110011011100001111001010100000" when "1011111100",
"11011101001110000001000000000101110110110111110011011100001111001010100000" when "1011111101",
"11011101011011111111010011110011001100010111101010100111001011101011110000" when "1011111110",
"11011101101001111110011000010111010111001110101101110101101101011110110001" when "1011111111",
"11011101101001111110011000010111010111001110101101110101101101011110110001" when "1100000000",
"11011101110111111110001101110111101101011000110010011101100111000010000110" when "1100000001",
"11011110000101111110110100011001100101101001110110100011010110011110100010" when "1100000010",
"11011110000101111110110100011001100101101001110110100011010110011110100010" when "1100000011",
"11011110010100000000001100000010010111101110001101001101001100101101000100" when "1100000100",
"11011110010100000000001100000010010111101110001101001101001100101101000100" when "1100000101",
"11011110100010000010010100110111011100001010101010111001101100001100001101" when "1100000110",
"11011110110000000101001110111110001100011100110001111001100000101011100011" when "1100000111",
"11011110110000000101001110111110001100011100110001111001100000101011100011" when "1100001000",
"11011110111110001000111010011100000010111010111110101100110000110101001110" when "1100001001",
"11011111001100001101010111010110011010110100110100100011101010111100111010" when "1100001010",
"11011111001100001101010111010110011010110100110100100011101010111100111010" when "1100001011",
"11011111011010010010100101110010110000010011001010000010101101111100110100" when "1100001100",
"11011111101000011000100101110110100000011000010101101010001111101001011101" when "1100001101",
"11011111101000011000100101110110100000011000010101101010001111101001011101" when "1100001110",
"11011111110110011111010111100111001001000000011010100001100001100101001000" when "1100001111",
"11100000000100100110111011001010001001000001010101000101010101011101000111" when "1100010000",
"11100000000100100110111011001010001001000001010101000101010101011101000111" when "1100010001",
"11100000010010101111010000100101000000001011000111111010000010011010010001" when "1100010010",
"11100000010010101111010000100101000000001011000111111010000010011010010001" when "1100010011",
"11100000100000111000010111111101001111001000001000100001001100001111110100" when "1100010100",
"11100000101111000010010001011000010111011101001100010010101101110011001100" when "1100010101",
"11100000101111000010010001011000010111011101001100010010101101110011001100" when "1100010110",
"11100000111101001100111100111011111011101001110101011001100111101000001101" when "1100010111",
"11100001001011011000011010101101011111001000011111110100010100001101110101" when "1100011000",
"11100001001011011000011010101101011111001000011111110100010100001101110101" when "1100011001",
"11100001011001100100101010110010100110001110101110011000100010110111011001" when "1100011010",
"11100001100111110001101101010000110110001101010111111010111010011111011101" when "1100011011",
"11100001100111110001101101010000110110001101010111111010111010011111011101" when "1100011100",
"11100001110101111111100010001101110101010000110100011010000101100001010110" when "1100011101",
"11100001110101111111100010001101110101010000110100011010000101100001010110" when "1100011110",
"11100010000100001110001001101111001010100001001010001101101000000111001010" when "1100011111",
"11100010010010011101100011111010011110000010011011011000100001111010100101" when "1100100000",
"11100010010010011101100011111010011110000010011011011000100001111010100101" when "1100100001",
"11100010100000101101110000110101011000110100110010111111011100100110111010" when "1100100010",
"11100010101110111110110000100101100100110100110010100010101000011011110010" when "1100100011",
"11100010101110111110110000100101100100110100110010100010101000011011110010" when "1100100100",
"11100010111101010000100011010000101100111011011111011011101000000000000000" when "1100100101",
"11100011001011100011001000111100011100111110110000011110101100100100101100" when "1100100110",
"11100011001011100011001000111100011100111110110000011110101100100100101100" when "1100100111",
"11100011011001110110100001101110100001110001011011100000000100001001011110" when "1100101000",
"11100011011001110110100001101110100001110001011011100000000100001001011110" when "1100101001",
"11100011101000001010101101101100101001000011100010111100111010100010101000" when "1100101010",
"11100011110110011111101100111100100001100010100011101000001110110010111100" when "1100101011",
"11100011110110011111101100111100100001100010100011101000001110110010111100" when "1100101100",
"11100100000100110101011111100011111010111001100010011011011110001011011100" when "1100101101",
"11100100010011001100000101101000100101110001011010001011000110000011010101" when "1100101110",
"11100100010011001100000101101000100101110001011010001011000110000011010101" when "1100101111",
"11100100100001100011011111010000010011110001001001011110111101111011110001" when "1100110000",
"11100100100001100011011111010000010011110001001001011110111101111011110001" when "1100110001",
"11100100101111111011101100100000110111011110000000101110101011000010011100" when "1100110010",
"11100100111110010100101101100000000100011011110000000001101110100111110100" when "1100110011",
"11100100111110010100101101100000000100011011110000000001101110100111110100" when "1100110100",
"11100101001100101110100010010011101111001100110101010011110000011101000001" when "1100110101",
"11100101001100101110100010010011101111001100110101010011110000011101000001" when "1100110110",
"11100101011011001001001011000001101101010010101010011100100110101111010001" when "1100110111",
"11100101101001100100100111101111110101001101110011011100011100110101110010" when "1100111000",
"11100101101001100100100111101111110101001101110011011100011100110101110010" when "1100111001",
"11100101111000000000111000100011111110011110001100101011111010001001001000" when "1100111010",
"11100110000110011101111101100100000001100011011001010000001010011010010110" when "1100111011",
"11100110000110011101111101100100000001100011011001010000001010011010010110" when "1100111100",
"11100110010100111011110110110101110111111100110001010011001001000001001101" when "1100111101",
"11100110010100111011110110110101110111111100110001010011001001000001001101" when "1100111110",
"11100110100011011010100100011111011100001001110000011111110000011001101100" when "1100111111",
"11100110110001111010000110100110101001101010000100100010001111001000110010" when "1101000000",
"11100110110001111010000110100110101001101010000100100010001111001000110010" when "1101000001",
"11100111000000011010011101010001011100111101111011101100100100000001101111" when "1101000010",
"11100111000000011010011101010001011100111101111011101100100100000001101111" when "1101000011",
"11100111001110111011101000100101110011100110010011011111000010100101001101" when "1101000100",
"11100111011101011101101000101001101100000101000111010101000001010100010100" when "1101000101",
"11100111011101011101101000101001101100000101000111010101000001010100010100" when "1101000110",
"11100111101100000000011101100011000101111101011111010101110011010010010010" when "1101000111",
"11100111101100000000011101100011000101111101011111010101110011010010010010" when "1101001000",
"11100111111010100100000111011000000001110011111111001001101110001111110001" when "1101001001",
"11101000001001001000100110001110100001001110110100110011011110111011101110" when "1101001010",
"11101000001001001000100110001110100001001110110100110011011110111011101110" when "1101001011",
"11101000010111101101111010001100100110110110000111101101101100110101111010" when "1101001100",
"11101000010111101101111010001100100110110110000111101101101100110101111010" when "1101001101",
"11101000100110010100000011011000010110010100000111101100101111000000001110" when "1101001110",
"11101000110100111011000001110111110100010101011100000100110011001100000000" when "1101001111",
"11101000110100111011000001110111110100010101011100000100110011001100000000" when "1101010000",
"11101001000011100010110101110001000110101001010010110100011001000001101110" when "1101010001",
"11101001000011100010110101110001000110101001010010110100011001000001101110" when "1101010010",
"11101001010010001011011111001010010100000001101111110011000010100001001110" when "1101010011",
"11101001100000110100111110001001100100010011111100000100011011011010010011" when "1101010100",
"11101001100000110100111110001001100100010011111100000100011011011010010011" when "1101010101",
"11101001101111011111010010110101000000011000010101001111111000111100111101" when "1101010110",
"11101001101111011111010010110101000000011000010101001111111000111100111101" when "1101010111",
"11101001111110001010011101010010110010001010111100111100010011100010000100" when "1101011000",
"11101010001100110110011101101001000100101011101000010000011011101101011010" when "1101011001",
"11101010001100110110011101101001000100101011101000010000011011101101011010" when "1101011010",
"11101010011011100011010011111110000011111110001111010111101100001010100100" when "1101011011",
"11101010011011100011010011111110000011111110001111010111101100001010100100" when "1101011100",
"11101010101010010001000000010111111101001010111101001011011010000111001110" when "1101011101",
"11101010111000111111100010111100111110011110011111000000100101101101100010" when "1101011110",
"11101010111000111111100010111100111110011110011111000000100101101101100010" when "1101011111",
"11101011000111101110111011110011010111001010010100011010001100000010000011" when "1101100000",
"11101011000111101110111011110011010111001010010100011010001100000010000011" when "1101100001",
"11101011010110011111001011000001010111100100111110111111111100001001100001" when "1101100010",
"11101011010110011111001011000001010111100100111110111111111100001001100001" when "1101100011",
"11101011100101010000010000101101010001001010010010011001110000111011000011" when "1101100100",
"11101011110100000010001100111101010110011011100100001111110001000100010110" when "1101100101",
"11101011110100000010001100111101010110011011100100001111110001000100010110" when "1101100110",
"11101100000010110100111111110111111010111111111100001110110111000101101010" when "1101100111",
"11101100000010110100111111110111111010111111111100001110110111000101101010" when "1101101000",
"11101100010001101000101001100011010011100100100100010010000010101100101001" when "1101101001",
"11101100100000011101001010000101110101111100111000110000010101010100110111" when "1101101010",
"11101100100000011101001010000101110101111100111000110000010101010100110111" when "1101101011",
"11101100101111010010100001100101111001000010111000101111011011010110011010" when "1101101100",
"11101100101111010010100001100101111001000010111000101111011011010110011010" when "1101101101",
"11101100111110001000110000001001110100110111010110011011000011101011000100" when "1101101110",
"11101100111110001000110000001001110100110111010110011011000011101011000100" when "1101101111",
"11101101001100111111110101111000000010100010000111100001000111010011010110" when "1101110000",
"11101101011011110111110010110110111100010010010101110010100010100101011000" when "1101110001",
"11101101011011110111110010110110111100010010010101110010100010100101011000" when "1101110010",
"11101101101010110000100111001100111101011110101111101001000001110000010010" when "1101110011",
"11101101101010110000100111001100111101011110101111101001000001110000010010" when "1101110100",
"11101101111001101010010011000000100010100101111000110001100010011111100100" when "1101110101",
"11101110001000100100110110011000001001001110011010111011101100001010000110" when "1101110110",
"11101110001000100100110110011000001001001110011010111011101100001010000110" when "1101110111",
"11101110010111100000010001011010010000000111010110101110000000011001111010" when "1101111000",
"11101110010111100000010001011010010000000111010110101110000000011001111010" when "1101111001",
"11101110100110011100100100001101010111001000010100011111000101111001110110" when "1101111010",
"11101110100110011100100100001101010111001000010100011111000101111001110110" when "1101111011",
"11101110110101011001101110110111111111010001110101010011101110110111010100" when "1101111100",
"11101111000100010111110001100000101010101101100100000001111101000110110101" when "1101111101",
"11101111000100010111110001100000101010101101100100000001111101000110110101" when "1101111110",
"11101111010011010110101100001101111100101110100110011001000101011011000010" when "1101111111",
"11101111010011010110101100001101111100101110100110011001000101011011000010" when "1110000000",
"11101111100010010110011111000110011001110001101110001110110011111110010011" when "1110000001",
"11101111100010010110011111000110011001110001101110001110110011111110010011" when "1110000010",
"11101111110001010111001010010000100111011101101010110001010011011111110011" when "1110000011",
"11110000000000011000101101110011001100100011011001111110011001000101111011" when "1110000100",
"11110000000000011000101101110011001100100011011001111110011001000101111011" when "1110000101",
"11110000001111011011001001110100110000111110011001111111110110011000001110" when "1110000110",
"11110000001111011011001001110100110000111110011001111111110110011000001110" when "1110000111",
"11110000011110011110011110011011111101110100111010101100110011110100000110" when "1110001000",
"11110000011110011110011110011011111101110100111010101100110011110100000110" when "1110001001",
"11110000101101100010101011101111011101011000001111010000010101000000001111" when "1110001010",
"11110000101101100010101011101111011101011000001111010000010101000000001111" when "1110001011",
"11110000111100100111110001110101111011000100111111110101001000110011001001" when "1110001100",
"11110001001011101101110000110110000011100011011011010110100111000010011100" when "1110001101",
"11110001001011101101110000110110000011100011011011010110100111000010011100" when "1110001110",
"11110001011010110100101000110110100100100111101001010110111101110000111000" when "1110001111",
"11110001011010110100101000110110100100100111101001010110111101110000111000" when "1110010000",
"11110001101001111100011001111110001101010001111011111010101111110010000001" when "1110010001",
"11110001101001111100011001111110001101010001111011111010101111110010000001" when "1110010010",
"11110001111001000101000100010011101101101111000001101001100110011011001010" when "1110010011",
"11110001111001000101000100010011101101101111000001101001100110011011001010" when "1110010100",
"11110010001000001110100111111101110111011000010111110100011000011010010001" when "1110010101",
"11110010010111011001000101000011011100110100011100100000100111101011100110" when "1110010110",
"11110010010111011001000101000011011100110100011100100000100111101011100110" when "1110010111",
"11110010100110100100011011101011010001110111000000111001011000001000100000" when "1110011000",
"11110010100110100100011011101011010001110111000000111001011000001000100000" when "1110011001",
"11110010110101110000101011111100001011100001011011100101100001001010000001" when "1110011010",
"11110010110101110000101011111100001011100001011011100101100001001010000001" when "1110011011",
"11110011000100111101110101111101000000000010111011000011011011111010110010" when "1110011100",
"11110011000100111101110101111101000000000010111011000011011011111010110010" when "1110011101",
"11110011010100001011111001110100100110111000111000001010010000010100110000" when "1110011110",
"11110011100011011010110111101001111000101111001000110000100010100111111110" when "1110011111",
"11110011100011011010110111101001111000101111001000110000100010100111111110" when "1110100000",
"11110011110010101010101111100011101111100000010010011000100011101000010011" when "1110100001",
"11110011110010101010101111100011101111100000010010011000100011101000010011" when "1110100010",
"11110100000001111011100001101001000110010101111101000010000101100001000111" when "1110100011",
"11110100000001111011100001101001000110010101111101000010000101100001000111" when "1110100100",
"11110100010001001101001110000000111001101001000110000001110111001110010110" when "1110100101",
"11110100010001001101001110000000111001101001000110000001110111001110010110" when "1110100110",
"11110100100000011111110100110010000111000010010010111110101000011011111001" when "1110100111",
"11110100101111110011010110000011101101011010000100110011111000001100000110" when "1110101000",
"11110100101111110011010110000011101101011010000100110011111000001100000110" when "1110101001",
"11110100111111000111110001111100101100111001001010111010010000001000000110" when "1110101010",
"11110100111111000111110001111100101100111001001010111010010000001000000110" when "1110101011",
"11110101001110011101001000100100000110111000110110010101101110011100101011" when "1110101100",
"11110101001110011101001000100100000110111000110110010101101110011100101011" when "1110101101",
"11110101011101110011011010000000111110000011001101001001100000100111101011" when "1110101110",
"11110101011101110011011010000000111110000011001101001001100000100111101011" when "1110101111",
"11110101101101001010100110011010010110010011011101110001110000111010110101" when "1110110000",
"11110101101101001010100110011010010110010011011101110001110000111010110101" when "1110110001",
"11110101111100100010101101110111010100110110010010100011001000111001100001" when "1110110010",
"11110101111100100010101101110111010100110110010010100011001000111001100001" when "1110110011",
"11110110001011111011110000011111000000001010000101010000001010110111111101" when "1110110100",
"11110110011011010101101110011000011111111111010010110100100100100011011111" when "1110110101",
"11110110011011010101101110011000011111111111010010110100100100100011011111" when "1110110110",
"11110110101010110000100111101010111101011000101111000110011100111011110101" when "1110110111",
"11110110101010110000100111101010111101011000101111000110011100111011110101" when "1110111000",
"11110110111010001100011100011101100010101011111000101101011111100111000010" when "1110111001",
"11110110111010001100011100011101100010101011111000101101011111100111000010" when "1110111010",
"11110111001001101001001100110111011011100001001101000000000111101001101100" when "1110111011",
"11110111001001101001001100110111011011100001001101000000000111101001101100" when "1110111100",
"11110111011001000110111000111111110100110100011100000110101100001110110111" when "1110111101",
"11110111011001000110111000111111110100110100011100000110101100001110110111" when "1110111110",
"11110111101000100101100000111101111100110100111101000100110001001011011110" when "1110111111",
"11110111101000100101100000111101111100110100111101000100110001001011011110" when "1111000000",
"11110111111000000101000100111001000011000110000010001000011101101001111100" when "1111000001",
"11111000000111100101100100111000011000011111001100111111111011001100000111" when "1111000010",
"11111000000111100101100100111000011000011111001100111111111011001100000111" when "1111000011",
"11111000010111000111000001000011001111001100100011010100111111010001111100" when "1111000100",
"11111000010111000111000001000011001111001100100011010100111111010001111100" when "1111000101",
"11111000100110101001011001100000111010101111000011001111000001110100110101" when "1111000110",
"11111000100110101001011001100000111010101111000011001111000001110100110101" when "1111000111",
"11111000110110001100101110011000101111111100110111111011000010101000001011" when "1111001000",
"11111000110110001100101110011000101111111100110111111011000010101000001011" when "1111001001",
"11111001000101110000111111110010000101000001101110011010000000010000101100" when "1111001010",
"11111001000101110000111111110010000101000001101110011010000000010000101100" when "1111001011",
"11111001010101010110001101110100010001011111001010010101100010100101000111" when "1111001100",
"11111001010101010110001101110100010001011111001010010101100010100101000111" when "1111001101",
"11111001100100111100011000100110101110001100111010111010111011001011111110" when "1111001110",
"11111001100100111100011000100110101110001100111010111010111011001011111110" when "1111001111",
"11111001110100100011100000010000110101011001001111111100011110001010100110" when "1111010000",
"11111001110100100011100000010000110101011001001111111100011110001010100110" when "1111010001",
"11111010000100001011100100111010000010101001001110111001010101011011011000" when "1111010010",
"11111010000100001011100100111010000010101001001110111001010101011011011000" when "1111010011",
"11111010010011110100100110101001110010111001001000001011110001000001011000" when "1111010100",
"11111010100011011110100101100111100100011100101100011101110110110001000011" when "1111010101",
"11111010100011011110100101100111100100011100101100011101110110110001000011" when "1111010110",
"11111010110011001001100001111010110110111111100010000100110011100110100010" when "1111010111",
"11111010110011001001100001111010110110111111100010000100110011100110100010" when "1111011000",
"11111011000010110101011011101011001011100101011010100010110001000011001011" when "1111011001",
"11111011000010110101011011101011001011100101011010100010110001000011001011" when "1111011010",
"11111011010010100010010011000000000100101010101000001111010001001100110000" when "1111011011",
"11111011010010100010010011000000000100101010101000001111010001001100110000" when "1111011100",
"11111011100010010000001000000001000110000100010100000110010011101010000100" when "1111011101",
"11111011100010010000001000000001000110000100010100000110010011101010000100" when "1111011110",
"11111011110001111110111010110101110101000000110011011110000101111001110000" when "1111011111",
"11111011110001111110111010110101110101000000110011011110000101111001110000" when "1111100000",
"11111100000001101110101011100101111000000111111110000011100001100000110001" when "1111100001",
"11111100000001101110101011100101111000000111111110000011100001100000110001" when "1111100010",
"11111100010001011111011010011000110111011011100011111101011010101111100010" when "1111100011",
"11111100010001011111011010011000110111011011100011111101011010101111100010" when "1111100100",
"11111100100001010001000111010110011100010111100011110110100001111101101000" when "1111100101",
"11111100100001010001000111010110011100010111100011110110100001111101101000" when "1111100110",
"11111100110001000011110010100110010001110010100001001110011010011100110110" when "1111100111",
"11111100110001000011110010100110010001110010100001001110011010011100110110" when "1111101000",
"11111101000000110111011100010000000011111101111010110001001001000101101101" when "1111101001",
"11111101000000110111011100010000000011111101111010110001001001000101101101" when "1111101010",
"11111101010000101100000100011011100000100110100000110101111101100000101010" when "1111101011",
"11111101010000101100000100011011100000100110100000110101111101100000101010" when "1111101100",
"11111101100000100001101011010000010110110100101100000100111000001111111110" when "1111101101",
"11111101100000100001101011010000010110110100101100000100111000001111111110" when "1111101110",
"11111101110000011000010000110110010111001100110100000011010000011111111111" when "1111101111",
"11111101110000011000010000110110010111001100110100000011010000011111111111" when "1111110000",
"11111110000000001111110101010101010011101111100110000111011100000011110010" when "1111110001",
"11111110000000001111110101010101010011101111100110000111011100000011110010" when "1111110010",
"11111110010000001000011000110100111111111010011100010011011100000110010110" when "1111110011",
"11111110010000001000011000110100111111111010011100010011011100000110010110" when "1111110100",
"11111110100000000001111011011101010000100111110100010110110001011000011111" when "1111110101",
"11111110100000000001111011011101010000100111110100010110110001011000011111" when "1111110110",
"11111110101111111100011101010101111100001111100110110111011010100101101100" when "1111110111",
"11111110101111111100011101010101111100001111100110110111011010100101101100" when "1111111000",
"11111110111111110111111110100110111010100111011110100001111111011010111111" when "1111111001",
"11111110111111110111111110100110111010100111011110100001111111011010111111" when "1111111010",
"11111111001111110100011111011000000101000011001111100001001011001011101100" when "1111111011",
"11111111001111110100011111011000000101000011001111100001001011001011101100" when "1111111100",
"11111111011111110001111111110001010110010101001110111100011001100001110110" when "1111111101",
"11111111011111110001111111110001010110010101001110111100011001100001110110" when "1111111110",
"11111111101111110000011111111010101010101110101010011101111000001000100000" when "1111111111",
"--------------------------------------------------------------------------" when others;
Y <= TableOut_d1;
end architecture;
-------------------------------------------------------------------------------
entity bigcase is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of bigcase is
signal clk, rst : std_logic;
signal X : std_logic_vector(9 downto 0);
signal Y : std_logic_vector(73 downto 0);
begin
LogTable_0_10_74_F400_uid60_1: entity work.LogTable_0_10_74_F400_uid60
port map (
clk => clk,
rst => rst,
X => X,
Y => Y );
p1: process is
variable ctr : unsigned(9 downto 0);
begin
for rep in 1 to 10000 loop
for i in 1 to 2**9 - 1 loop
X <= std_logic_vector(ctr);
ctr := ctr + 1;
wait for 1 ns;
end loop;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
dfee2cafa5b3826b129598b60ac2f209
| 0.883108 | 5.992258 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_09.vhd
| 4 | 1,735 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_09.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity edge_triggered_register is
port ( clock : in bit;
d_in : in real; d_out : out real );
end entity edge_triggered_register;
architecture check_timing of edge_triggered_register is
begin
store_and_check : process (clock) is
variable stored_value : real;
variable pulse_start : time;
begin
case clock is
when '1' =>
pulse_start := now;
stored_value := d_in;
d_out <= stored_value;
when '0' =>
assert now = 0 ns or (now - pulse_start) >= 5 ns
report "clock pulse too short";
end case;
end process store_and_check;
end architecture check_timing;
|
gpl-2.0
|
3a34f98487243577834723ada6575eeb
| 0.596542 | 4.200969 | false | false | false | false |
nickg/nvc
|
lib/std.19/reflection.vhdl
| 1 | 12,299 |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
package REFLECTION is
type INDEX is range INTEGER'low to INTEGER'high;
subtype NATURAL_INDEX is INDEX range 0 to INDEX'high;
subtype POSITIVE_INDEX is INDEX range 1 to INDEX'high;
subtype DIMENSION is INDEX range 1 to INDEX'high;
type INDEX_VECTOR is array(DIMENSION range <>) of INDEX;
-- Incomplete type declarations
type VALUE_MIRROR;
type SUBTYPE_MIRROR;
-- Enumeration subtype/value mirror
type ENUMERATION_SUBTYPE_MIRROR;
type ENUMERATION_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return ENUMERATION_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
impure function pos return INTEGER;
impure function image return STRING;
end protected;
type ENUMERATION_VALUE_MIRROR is access ENUMERATION_VALUE_MIRROR_PT;
type ENUMERATION_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function enumeration_literal(literal_idx : NATURAL_INDEX) return ENUMERATION_VALUE_MIRROR;
impure function enumeration_literal(literal_name : STRING) return ENUMERATION_VALUE_MIRROR;
impure function simple_name return STRING;
impure function left return ENUMERATION_VALUE_MIRROR;
impure function right return ENUMERATION_VALUE_MIRROR;
impure function low return ENUMERATION_VALUE_MIRROR;
impure function high return ENUMERATION_VALUE_MIRROR;
impure function length return POSITIVE_INDEX;
impure function ascending return BOOLEAN;
end protected;
type ENUMERATION_SUBTYPE_MIRROR is access ENUMERATION_SUBTYPE_MIRROR_PT;
-- Integer subtype/value mirror
type INTEGER_SUBTYPE_MIRROR;
type INTEGER_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return INTEGER_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
impure function value return INTEGER;
impure function image return STRING;
end protected;
type INTEGER_VALUE_MIRROR is access INTEGER_VALUE_MIRROR_PT;
type INTEGER_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function simple_name return STRING;
impure function left return INTEGER_VALUE_MIRROR;
impure function right return INTEGER_VALUE_MIRROR;
impure function low return INTEGER_VALUE_MIRROR;
impure function high return INTEGER_VALUE_MIRROR;
impure function length return INDEX;
impure function ascending return BOOLEAN;
end protected;
type INTEGER_SUBTYPE_MIRROR is access INTEGER_SUBTYPE_MIRROR_PT;
-- Floating-point subtype/value mirror
type FLOATING_SUBTYPE_MIRROR;
type FLOATING_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return FLOATING_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
impure function value return REAL;
impure function image return STRING;
end protected;
type FLOATING_VALUE_MIRROR is access FLOATING_VALUE_MIRROR_PT;
type FLOATING_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function simple_name return STRING;
impure function left return FLOATING_VALUE_MIRROR;
impure function right return FLOATING_VALUE_MIRROR;
impure function low return FLOATING_VALUE_MIRROR;
impure function high return FLOATING_VALUE_MIRROR;
impure function ascending return BOOLEAN;
end protected;
type FLOATING_SUBTYPE_MIRROR is access FLOATING_SUBTYPE_MIRROR_PT;
-- Physical subtype/value mirror
type PHYSICAL_SUBTYPE_MIRROR;
type PHYSICAL_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return PHYSICAL_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
impure function unit_index return INDEX;
impure function value return INTEGER;
impure function image return STRING;
end protected;
type PHYSICAL_VALUE_MIRROR is access PHYSICAL_VALUE_MIRROR_PT;
type PHYSICAL_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function units_length return INDEX;
impure function unit_name (unit_idx: INDEX) return STRING;
impure function unit_index(unit_name : STRING) return INDEX;
impure function scale(unit_idx: INDEX) return NATURAL;
impure function scale(unit_name: STRING) return NATURAL;
impure function simple_name return STRING;
impure function left return PHYSICAL_VALUE_MIRROR;
impure function right return PHYSICAL_VALUE_MIRROR;
impure function low return PHYSICAL_VALUE_MIRROR;
impure function high return PHYSICAL_VALUE_MIRROR;
impure function length return INDEX;
impure function ascending return BOOLEAN;
end protected;
type PHYSICAL_SUBTYPE_MIRROR is access PHYSICAL_SUBTYPE_MIRROR_PT;
-- Record subtype/value mirror
type RECORD_SUBTYPE_MIRROR;
type RECORD_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return RECORD_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
impure function get(element_idx : INDEX) return VALUE_MIRROR;
impure function get(element_name : STRING) return VALUE_MIRROR;
end protected;
type RECORD_VALUE_MIRROR is access RECORD_VALUE_MIRROR_PT;
type RECORD_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function length return INDEX;
impure function element_name(element_idx : INDEX) return STRING;
impure function element_index(element_name : STRING) return INDEX;
impure function element_subtype(element_idx : INDEX) return SUBTYPE_MIRROR;
impure function element_subtype(element_name : STRING) return SUBTYPE_MIRROR;
impure function simple_name return STRING;
end protected;
type RECORD_SUBTYPE_MIRROR is access RECORD_SUBTYPE_MIRROR_PT;
-- Array subtype/value mirror
type ARRAY_SUBTYPE_MIRROR;
type ARRAY_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return ARRAY_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
impure function get(idx : INDEX) return VALUE_MIRROR;
impure function get(idx1, idx2 : INDEX) return VALUE_MIRROR;
impure function get(idx1, idx2, idx3 : INDEX) return VALUE_MIRROR;
impure function get(idx : INDEX_VECTOR) return VALUE_MIRROR;
end protected;
type ARRAY_VALUE_MIRROR is access ARRAY_VALUE_MIRROR_PT;
type ARRAY_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function dimensions return DIMENSION;
impure function index_subtype(idx : DIMENSION := 1) return SUBTYPE_MIRROR;
impure function element_subtype return SUBTYPE_MIRROR;
impure function simple_name return STRING;
impure function left(idx : DIMENSION := 1) return INDEX;
impure function right(idx : DIMENSION := 1) return INDEX;
impure function low(idx : DIMENSION := 1) return INDEX;
impure function high(idx : DIMENSION := 1) return INDEX;
impure function length(idx : DIMENSION := 1) return INDEX;
impure function ascending(idx : DIMENSION := 1) return BOOLEAN;
end protected;
type ARRAY_SUBTYPE_MIRROR is access ARRAY_SUBTYPE_MIRROR_PT;
-- Access subtype/value mirror
type ACCESS_SUBTYPE_MIRROR;
type ACCESS_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return ACCESS_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
--
impure function get return VALUE_MIRROR;
impure function is_null return BOOLEAN;
end protected;
type ACCESS_VALUE_MIRROR is access ACCESS_VALUE_MIRROR_PT;
type ACCESS_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function simple_name return STRING;
impure function designated_subtype return SUBTYPE_MIRROR;
end protected;
type ACCESS_SUBTYPE_MIRROR is access ACCESS_SUBTYPE_MIRROR_PT;
-- File subtype/value mirror
type FILE_SUBTYPE_MIRROR;
type FILE_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return FILE_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
impure function get_file_logical_name return STRING;
impure function get_file_open_kind return FILE_OPEN_KIND;
end protected;
type FILE_VALUE_MIRROR is access FILE_VALUE_MIRROR_PT;
type FILE_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function simple_name return STRING;
impure function designated_subtype return SUBTYPE_MIRROR;
end protected;
type FILE_SUBTYPE_MIRROR is access FILE_SUBTYPE_MIRROR_PT;
-- Protected subtype/value mirror
type PROTECTED_SUBTYPE_MIRROR;
type PROTECTED_VALUE_MIRROR_PT is protected
impure function get_subtype_mirror return PROTECTED_SUBTYPE_MIRROR;
impure function to_value_mirror return VALUE_MIRROR;
end protected;
type PROTECTED_VALUE_MIRROR is access PROTECTED_VALUE_MIRROR_PT;
type PROTECTED_SUBTYPE_MIRROR_PT is protected
impure function to_subtype_mirror return SUBTYPE_MIRROR;
impure function simple_name return STRING;
end protected;
type PROTECTED_SUBTYPE_MIRROR is access PROTECTED_SUBTYPE_MIRROR_PT;
-- Type classes and sub-classes
type TYPE_CLASS is (
CLASS_ENUMERATION,
CLASS_INTEGER,
CLASS_FLOATING,
CLASS_PHYSICAL,
CLASS_RECORD,
CLASS_ARRAY,
CLASS_ACCESS,
CLASS_FILE,
CLASS_PROTECTED
);
alias VALUE_CLASS is TYPE_CLASS;
-- Subtype/value mirror
type SUBTYPE_MIRROR_PT is protected
impure function get_type_class return TYPE_CLASS;
-- Get the corresponding representation
impure function to_enumeration return ENUMERATION_SUBTYPE_MIRROR;
impure function to_integer return INTEGER_SUBTYPE_MIRROR;
impure function to_floating return FLOATING_SUBTYPE_MIRROR;
impure function to_physical return PHYSICAL_SUBTYPE_MIRROR;
impure function to_record return RECORD_SUBTYPE_MIRROR;
impure function to_array return ARRAY_SUBTYPE_MIRROR;
impure function to_access return ACCESS_SUBTYPE_MIRROR;
impure function to_file return FILE_SUBTYPE_MIRROR;
impure function to_protected return PROTECTED_SUBTYPE_MIRROR;
impure function simple_name return STRING;
end protected;
type SUBTYPE_MIRROR is access SUBTYPE_MIRROR_PT;
type VALUE_MIRROR_PT is protected
impure function get_value_class return VALUE_CLASS;
impure function get_subtype_mirror return SUBTYPE_MIRROR;
-- Get the corresponding representation
impure function to_enumeration return ENUMERATION_VALUE_MIRROR;
impure function to_integer return INTEGER_VALUE_MIRROR;
impure function to_floating return FLOATING_VALUE_MIRROR;
impure function to_physical return PHYSICAL_VALUE_MIRROR;
impure function to_record return RECORD_VALUE_MIRROR;
impure function to_array return ARRAY_VALUE_MIRROR;
impure function to_access return ACCESS_VALUE_MIRROR;
impure function to_file return FILE_VALUE_MIRROR;
impure function to_protected return PROTECTED_VALUE_MIRROR;
end protected;
type VALUE_MIRROR is access VALUE_MIRROR_PT;
end package REFLECTION;
|
gpl-3.0
|
953ecdb4881e9e3c7e1cce19a4a1f6f9
| 0.729897 | 4.541728 | false | false | false | false |
snow4life/PipelinedDLX
|
alu/comparator/comparator_generic.vhd
| 1 | 2,037 |
-- This block set the putput to 1 if the input (result of the subtraction of the two operand) match the relation applied to the control input, 0 otherwise.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
use work.reduce_pack.all;
entity COMPARATOR_GENERIC is
generic(N: integer);
port( SUB: in std_logic_vector(N-1 downto 0);
CARRY: in std_logic;
EQUAL: in std_logic;
NOT_EQUAL: in std_logic;
GREATER: in std_logic;
GREATER_EQUAL: in std_logic;
LOWER: in std_logic;
LOWER_EQUAL: in std_logic;
COMPARATOR_OUT: out std_logic_vector(N-1 downto 0);
ZERO: out std_logic);
end entity COMPARATOR_GENERIC;
architecture BEHAVIORAL of COMPARATOR_GENERIC is
signal ZERO_INT: std_logic;
signal EQUAL_INT: std_logic;
signal NOT_EQUAL_INT: std_logic;
signal GREATER_INT: std_logic;
signal GREATER_EQUAL_INT: std_logic;
signal LOWER_INT: std_logic;
signal LOWER_EQUAL_INT: std_logic;
signal EQUAL_AND: std_logic;
signal NOT_EQUAL_AND: std_logic;
signal GREATER_AND: std_logic;
signal GREATER_EQUAL_AND: std_logic;
signal LOWER_AND: std_logic;
signal LOWER_EQUAL_AND: std_logic;
begin
ZERO_INT<= reduce_pack.nor_reduce(SUB);
ZERO <= ZERO_INT;
EQUAL_INT <= ZERO_INT;
NOT_EQUAL_INT <= not ZERO_INT;
GREATER_INT <= NOT_EQUAL_INT and GREATER_EQUAL_INT;
GREATER_EQUAL_INT <= CARRY;
LOWER_INT <= not GREATER_EQUAL_INT;
LOWER_EQUAL_INT <= EQUAL_INT or LOWER_INT;
EQUAL_AND <= EQUAL_INT and EQUAL;
NOT_EQUAL_AND <= NOT_EQUAL_INT and NOT_EQUAL;
GREATER_AND <= GREATER_INT and GREATER;
GREATER_EQUAL_AND <= GREATER_EQUAL_INT and GREATER_EQUAL;
LOWER_AND <= LOWER_INT and LOWER;
LOWER_EQUAL_AND <= LOWER_EQUAL_INT and LOWER_EQUAL;
COMPARATOR_OUT(0) <= EQUAL_AND or NOT_EQUAL_AND or GREATER_AND or GREATER_EQUAL_AND or LOWER_AND or LOWER_EQUAL_AND;
COMPARATOR_OUT(N-1 downto 1) <= (others => '0');
end architecture BEHAVIORAL;
|
lgpl-2.1
|
e067163f54ab111c7cf60a3dc1d84fdc
| 0.689249 | 2.760163 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd
| 4 | 2,587 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
subtype coeff_ram_address is integer range 0 to 63;
-- code from book:
type coeff_array is array (coeff_ram_address) of real;
-- end of code from book
begin
process_1_c : process is
-- code from book:
type point is array (1 to 3) of real;
constant origin : point := (0.0, 0.0, 0.0);
variable view_point : point := (10.0, 20.0, 0.0);
-- end of code from book
begin
wait;
end process process_1_c;
process_1_d : process is
type point is array (1 to 3) of real;
-- code from book:
variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0);
-- end of code from book
begin
wait;
end process process_1_d;
process_1_e : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0);
-- end of code from book
begin
wait;
end process process_1_e;
process_1_f : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0);
-- end of code from book
begin
wait;
end process process_1_f;
process_1_g : process is
-- code from book:
variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0);
-- end of code from book
begin
wait;
end process process_1_g;
process_1_h : process is
-- code from book:
-- error: Associations in array aggregate must be all named or all positional
-- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0); -- illegal
-- end of code from book
begin
wait;
end process process_1_h;
end architecture test;
|
gpl-2.0
|
f3016cecb92e8e0279031affa81ed6d4
| 0.61925 | 3.588072 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/packer_12bit/pack_16to12.vhd
| 1 | 6,210 |
--------------------------------------------------------------------------------
-- file name : pack_16to12.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -pack_16to12
-- arch_itecture - arch_pack_16to12
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-11-2008 new version
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
entity pack_16to12 is
port (
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
data_in_dval : in std_logic;
data_in : in std_logic_vector(63 downto 0);
data_in_stop : out std_logic;
data_out_dval : out std_logic;
data_out : out std_logic_vector(63 downto 0);
data_out_stop : in std_logic
);
end pack_16to12;
architecture pack_16to12_syn of pack_16to12 is
-----------------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------------
signal cycle : std_logic_vector(1 downto 0);
signal data_pr : std_logic_vector(63 downto 0);
signal data_12_dval : std_logic;
signal data_12 : std_logic_vector(63 downto 0);
signal data_in0 : std_logic_vector(11 downto 0);
signal data_in1 : std_logic_vector(11 downto 0);
signal data_in2 : std_logic_vector(11 downto 0);
signal data_in3 : std_logic_vector(11 downto 0);
signal data_pr0 : std_logic_vector(11 downto 0);
signal data_pr1 : std_logic_vector(11 downto 0);
signal data_pr2 : std_logic_vector(11 downto 0);
signal data_pr3 : std_logic_vector(11 downto 0);
begin
data_in0 <= data_in(11 downto 00);
data_in1 <= data_in(27 downto 16);
data_in2 <= data_in(43 downto 32);
data_in3 <= data_in(59 downto 48);
data_pr0 <= data_pr(11 downto 00);
data_pr1 <= data_pr(27 downto 16);
data_pr2 <= data_pr(43 downto 32);
data_pr3 <= data_pr(59 downto 48);
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
process(clk)
begin
if (rst = '1') then
cycle <= (others => '0');
data_12_dval <= '0';
data_pr <= (others => '0');
data_12 <= (others => '0');
data_out_dval <= '0';
data_out <= (others => '0');
elsif (rising_edge(clk)) then
-- When packing four input cycles goes into 3 output cycles
-- 4cycles x 4samples x 12bit = 3cycles x 64bit
if (data_in_dval = '1') then
cycle <= cycle + 1;
end if;
-- Output data on the 2nd, 3rd, and 4th cycle
if (data_in_dval = '1' and cycle /= 0) then
data_12_dval <= '1';
else
data_12_dval <= '0';
end if;
-- Keep the input data for one clock cycle
data_pr <= data_in;
-- Generate output data on the 2nd, 3rd, and 4th cycle
if (data_in_dval = '1') then
case cycle is
when "01" => data_12 <= data_in1(3 downto 0) & data_in0 & data_pr3 & data_pr2 & data_pr1 & data_pr0;
when "10" => data_12 <= data_in2(7 downto 0) & data_in1 & data_in0 & data_pr3 & data_pr2 & data_pr1(11 downto 4);
when "11" => data_12 <= data_in3 & data_in2 & data_in1 & data_in0 & data_pr3 & data_pr2(11 downto 8);
when others =>
end case;
end if;
-- Output Multiplexer
if (enable = '1') then
data_out_dval <= data_12_dval;
data_out <= data_12;
else
data_out_dval <= data_in_dval;
data_out <= data_in;
end if;
end if;
end process;
data_in_stop <= data_out_stop;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end pack_16to12_syn;
|
mit
|
e2dd80e26273b0ee0d00d74336104e78
| 0.481965 | 3.883677 | false | false | false | false |
hubertokf/VHDL-Fast-Adders
|
RCA/8bits/RCA/RCA.vhd
| 1 | 2,129 |
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (7 downto 0);
SomaResult: out std_logic_vector (7 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (7 downto 1);
signal CarryInTemp: std_logic;
signal CarryOutTemp0,CarryOutTemp1: std_logic;
signal A, B, Ssoma: std_logic_vector(7 downto 0);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg8Bit
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>CarryInTemp
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>CarryOutTemp0,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Ssoma,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
--somador--
Som0: Soma1 PORT MAP (
CarryInTemp,
A(0),
B(0),
Ssoma(0),
carry(1)
);
Som1: Soma1 PORT MAP (
carry(1),
A(1),
B(1),
Ssoma(1),
carry(2)
);
Som2: Soma1 PORT MAP (
carry(2),
A(2),
B(2),
Ssoma(2),
carry(3)
);
Som3: Soma1 PORT MAP (
carry(3),
A(3),
B(3),
Ssoma(3),
carry(4)
);
Som4: Soma1 PORT MAP (
carry(4),
A(4),
B(4),
Ssoma(4),
carry(5)
);
Som5: Soma1 PORT MAP (
carry(5),
A(5),
B(5),
Ssoma(5),
carry(6)
);
Som6: Soma1 PORT MAP (
carry(6),
A(6),
B(6),
Ssoma(6),
carry(7)
);
Som7: Soma1 PORT MAP (
carry(7),
A(7),
B(7),
Ssoma(7),
CarryOutTemp0
);
END strc_RCA ;
|
mit
|
9979567be62cc9fa65fad16fabd91080
| 0.60263 | 2.368187 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug017/case1.vhdl
| 2 | 597 |
entity case1 is
end;
architecture behav of case1 is
begin
process
begin
for i in 1 to 10 loop
case i is
when 1 =>
report "one";
wait for 1 ns;
when 2 =>
report "two";
wait for 2 ns;
when 3 =>
report "three";
wait for 3 ns;
when 4 to 9 =>
report "a big digit";
wait for 5 ns;
when others =>
report "a number"; -- including 0.
wait for 10 ns;
end case;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
gpl-2.0
|
174e1c676506416a87afa7a39800b98b
| 0.470687 | 4.145833 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1241/tb_top.vhdl
| 1 | 668 |
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_top is
signal sel : unsigned(1 downto 0);
signal data : std_logic_vector(3 downto 0);
signal q : std_logic;
begin
dut: entity work.top
port map (sel, data, q);
process
begin
data <= "1001";
sel <= "10";
wait for 1 ns;
assert q = '0' severity failure;
sel <= "11";
wait for 1 ns;
assert q = '1' severity failure;
sel <= "00";
wait for 1 ns;
assert q = '1' severity failure;
sel <= "01";
wait for 1 ns;
assert q = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
da48bfc2cfc6d22f8b890565da570ab2
| 0.601796 | 3.211538 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd
| 4 | 1,833 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity add_1 is
port ( d0, d1, d2, d3 : in bit;
y0, y1, y2, y3 : out bit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y0 <= not d0 after 4 ns;
y1 <= (not d1 and d0)
or (d1 and not d0) after 4 ns;
y2 <= (not d2 and d1 and d0)
or (d2 and not (d1 and d0)) after 4 ns;
y3 <= (not d3 and d2 and d1 and d0)
or (d3 and not (d2 and d1 and d0)) after 4 ns;
end architecture boolean_eqn;
entity buf4 is
port ( a0, a1, a2, a3 : in bit;
y0, y1, y2, y3 : out bit );
end entity buf4;
architecture basic of buf4 is
begin
y0 <= a0 after 2 ns;
y1 <= a1 after 2 ns;
y2 <= a2 after 2 ns;
y3 <= a3 after 2 ns;
end architecture basic;
package counter_types is
subtype digit is bit_vector(3 downto 0);
end package counter_types;
|
gpl-2.0
|
9f866a73992bb50b7b9539a8745f73d4
| 0.615385 | 3.284946 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/synth8/test3.vhdl
| 1 | 557 |
library ieee;
use ieee.std_logic_1164.all;
entity test3 is
port (led: out std_logic_vector (7 downto 0);
rst : std_logic;
clk : std_logic);
end test3;
architecture synth of test3 is
signal int : std_logic_vector(1 downto 0);
begin
-- led(7) <= '0';
-- led(6) <= '1';
-- led(5) <= '0';
-- led(3 downto 0) <= x"9";
process (clk) is
begin
if rising_edge (clk) then
if rst = '1' then
int(1) <= '0';
else
int(1) <= not int(1);
end if;
end if;
end process;
led(5) <= int (1);
end synth;
|
gpl-2.0
|
c395d57594e4c913229f7ca436247a1f
| 0.5386 | 2.771144 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd
| 4 | 2,020 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2083.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02083ent IS
END c07s02b04x00p20n01i02083ent;
ARCHITECTURE c07s02b04x00p20n01i02083arch OF c07s02b04x00p20n01i02083ent IS
TYPE int_vector is array (INTEGER range <>) of INTEGER;
BEGIN
TESTING: PROCESS
VARIABLE target : int_vector (1 to 7) ;
VARIABLE slice_1 : int_vector (1 to 4) := (1,2,3,4);
VARIABLE slice_2 : int_vector (-2 to 4) := (5,6,7,8,9,10,11);
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
assert NOT(target=(1,2,3,6,7,8,9))
report "***PASSED TEST: c07s02b04x00p20n01i02083"
severity NOTE;
assert (target=(1,2,3,6,7,8,9))
report "***FAILED TEST: c07s02b04x00p20n01i02083 - One dimensional array of INTEGER type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02083arch;
|
gpl-2.0
|
cca30d708639a0d3d6195908fd3483cb
| 0.661386 | 3.447099 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/arr02/tb_arr03.vhdl
| 1 | 889 |
entity tb_arr03 is
end tb_arr03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr03 is
signal a : std_logic_vector (31 downto 0);
signal sel : natural range 0 to 3;
signal clk : std_logic;
signal res : std_logic_vector (3 downto 0);
begin
dut: entity work.arr03
port map (a, sel, clk, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"a1b2c3d4";
sel <= 0;
pulse;
pulse;
assert res = b"0100" severity failure;
sel <= 1;
pulse;
assert res = b"0100" severity failure;
sel <= 2;
pulse;
assert res = b"0110" severity failure;
sel <= 3;
pulse;
assert res = b"1000" severity failure;
sel <= 0;
pulse;
assert res = b"1010" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
d8bdc8a37285bf9c6908723368647dc2
| 0.590551 | 3.292593 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue872/alu.vhdl
| 1 | 873 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
clk : in std_logic;
rst : in std_logic;
opcode : in std_logic_vector(15 downto 0);
a : in std_logic;
b : in std_logic;
y : out std_logic
);
end alu;
architecture mux of alu is
signal ci : std_logic;
signal co : std_logic;
signal mux1, mux2: std_logic_vector(7 downto 0);
begin
process(a, b, ci, mux1, mux2)
variable sel : unsigned(2 downto 0);
begin
sel := a & b & ci;
y <= mux1(to_integer(sel));
co <= mux2(to_integer(sel));
end process;
process(clk, rst)
begin
if(rst = '0') then
ci <= '0';
mux1 <= (others => '0');
mux2 <= (others => '0');
elsif(rising_edge(clk)) then
ci <= co;
mux1 <= opcode(15 downto 8);
mux2 <= opcode(7 downto 0);
end if;
end process;
end mux;
|
gpl-2.0
|
280c9292a9ab4a9518c3f9697b409f90
| 0.572738 | 3 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/lpm_add_sub_db0.vhd
| 1 | 4,965 |
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub_db0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub_db0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_add_sub_db0;
ARCHITECTURE SYN OF lpm_add_sub_db0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(8 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL dataa[8..0]
-- Retrieval info: USED_PORT: datab 0 0 9 0 INPUT NODEFVAL datab[8..0]
-- Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL result[8..0]
-- Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 datab 0 0 9 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub_db0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
ae5aea27d955547e811e00b19ab983f1
| 0.642497 | 3.516289 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/func01/func05.vhdl
| 1 | 436 |
library ieee;
use ieee.std_logic_1164.all;
entity func05 is
port (s : natural;
r : out std_logic_vector (15 downto 0));
end func05;
architecture behav of func05 is
function mapv (sel : natural) return std_logic_vector
is
variable res : std_logic_vector(15 downto 0) := (others => '0');
begin
if sel = 2 then
res := x"1234";
end if;
return res;
end mapv;
begin
r <= mapv (s);
end behav;
|
gpl-2.0
|
e1d5f36a15cd0b98c1a4c370d13684b5
| 0.619266 | 3.182482 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue301/packages/pkg_param_derived.vhd
| 7 | 2,420 |
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Derived parameters
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
--! @details This constants are derived from constants defined in pkg_param.
--! In order to prevent errors, there is no user choice for these parameters.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_helper.all;
package pkg_param_derived is
-- Calculation of constraint length.
function calc_constraint_length return natural;
-- Memory depth of the encoder shift register.
constant ENCODER_MEMORY_DEPTH : natural;
-- Number of trellis states corresponds to the nubmer of ACS units.
constant NUMBER_TRELLIS_STATES : natural;
-- Number of branch units for a single polynomial set
constant NUMBER_BRANCH_UNITS : natural;
-- Bitwidth constants are needed for type conversions
constant BW_TRELLIS_STATES : natural;
constant BW_MAX_WINDOW_LENGTH : natural;
constant BW_BRANCH_RESULT : natural;
constant BW_MAX_PROBABILITY : natural;
end package pkg_param_derived;
package body pkg_param_derived is
function calc_constraint_length return natural is
variable v_maximum : natural := 0;
begin
-- Find the position of the leftmost bit in the polynomials.
for i in NUMBER_PARITY_BITS - 1 downto 0 loop
v_maximum := max(v_maximum, no_bits_natural(PARITY_POLYNOMIALS(i)));
end loop;
v_maximum := max(v_maximum, no_bits_natural(FEEDBACK_POLYNOMIAL));
return v_maximum;
end function calc_constraint_length;
constant ENCODER_MEMORY_DEPTH : natural := calc_constraint_length - 1;
constant NUMBER_TRELLIS_STATES : natural := 2 ** ENCODER_MEMORY_DEPTH;
constant NUMBER_BRANCH_UNITS : natural := 2 ** NUMBER_PARITY_BITS;
constant BW_TRELLIS_STATES : natural := no_bits_natural(NUMBER_TRELLIS_STATES - 1);
constant BW_MAX_WINDOW_LENGTH : natural := no_bits_natural(MAX_WINDOW_LENGTH - 1);
constant BW_BRANCH_RESULT : natural := no_bits_natural((2 ** (BW_LLR_INPUT - 1)) * NUMBER_PARITY_BITS) + 1;
constant BW_MAX_PROBABILITY : natural := no_bits_natural(((2 ** (BW_LLR_INPUT - 1)) * NUMBER_PARITY_BITS) * 4 * ENCODER_MEMORY_DEPTH);
end package body pkg_param_derived;
|
gpl-2.0
|
7ddbca62b57f680ed9ae09cd186b66a5
| 0.72314 | 3.579882 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug040/jpegfilebuf.vhd
| 2 | 1,463 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity jpegfilebuf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(12 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(12 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end jpegfilebuf;
architecture augh of jpegfilebuf is
-- Embedded RAM
type ram_type is array (0 to 5309) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 5310 else (others => '-');
end architecture;
|
gpl-2.0
|
d9c3e0e5abb8817b607c03ca813fcd4a
| 0.673958 | 2.908549 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1163/bug2.vhdl
| 1 | 889 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug2 is
generic(
W : positive := 4;
N : positive := 4
);
port(
clk : in std_ulogic;
reset_n : in std_ulogic;
o : out std_ulogic
);
end bug2;
architecture behav of bug2 is
type queue_info_t is record
dummy : integer range 0 to W-1;
strb : std_ulogic_vector(W-1 downto 0);
end record;
type queues_t is array (0 to N-1) of queue_info_t;
signal queues : queues_t;
begin
process(clk, reset_n)
variable index : integer range 0 to N-1;
begin
if reset_n = '0' then
index := 0;
elsif rising_edge(clk) then
for i in 0 to W-1 loop
queues(index).strb(i) <= '0';
end loop;
index := (index + 1) mod N;
end if;
end process;
o <= queues (0).strb (0);
end architecture;
|
gpl-2.0
|
ea79b6620039edbe8411bcfbf513aead
| 0.563555 | 3.003378 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd
| 4 | 6,627 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc625.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:46 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00625ent IS
END c03s04b01x00p01n01i00625ent;
ARCHITECTURE c03s04b01x00p01n01i00625arch OF c03s04b01x00p01n01i00625ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
i: record_array_st;
end record;
type record_of_records_file is file of record_of_records;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C28 : boolean_vector_st :=(others => C1);
constant C29 : severity_level_vector_st:= (others => C4);
constant C30 : integer_vector_st:=(others => C5);
constant C31 : real_vector_st:=(others => C6);
constant C32 : time_vector_st:=(others => C7);
constant C33 : natural_vector_st:=(others => C8);
constant C34 : positive_vector_st:=(others => C9);
constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
constant C37 : record_of_records := (C26,C27,C35);
BEGIN
TESTING: PROCESS
file filein : record_of_records_file open write_mode is "iofile.35";
BEGIN
for i in 1 to 100 loop
write(filein, C37);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00625 - The output file will be verified by test s010272.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00625arch;
|
gpl-2.0
|
83078610c462fd157024f374648c9aea
| 0.570847 | 3.784694 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/lit01/tb_aggr02.vhdl
| 1 | 519 |
entity tb_aggr02 is
end tb_aggr02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_aggr02 is
signal i0 : natural range 0 to 5;
signal o : std_logic_vector(7 downto 0);
begin
dut: entity work.aggr02
port map (i0, o);
process
begin
i0 <= 0;
wait for 1 ns;
assert o = x"00" severity failure;
i0 <= 1;
wait for 1 ns;
assert o = x"81" severity failure;
i0 <= 2;
wait for 1 ns;
assert o = x"02" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
95cb99ee75338a8ae5dc842939c02277
| 0.624277 | 3.071006 | false | false | false | false |
nickg/nvc
|
test/regress/textio6.vhd
| 1 | 3,023 |
entity textio6 is
end entity;
use std.textio.all;
architecture test of textio6 is
begin
test_sread: process is
variable l : line;
variable s : string(1 to 5);
variable n : natural;
begin
l := new string'(" word foo bar_baz end");
sread(l, s, n);
report s(1 to n);
assert n = 4;
assert s(1 to n) = "word";
sread(l, s, n);
report s(1 to n);
assert n = 3;
assert s(1 to n) = "foo";
sread(l, s, n);
report s(1 to n);
assert n = 5;
assert s(1 to n) = "bar_b";
sread(l, s, n);
report s(1 to n);
assert n = 2;
assert s(1 to n) = "az";
sread(l, s, n);
report s(1 to n);
assert n = 3;
assert s(1 to n) = "end";
sread(l, s, n);
assert n = 0;
deallocate(l);
wait;
end process;
test_hread: process is
variable l : line;
variable b : bit_vector(1 to 16);
variable bv4 : bit_vector(12 downto 0);
variable bv7 : bit_vector(10 downto 0);
variable good : boolean;
begin
l := new string'(" 1 2 ab23 12_34 dead 12 1__2");
hread(l, b(1 to 4));
assert b(1 to 4) = "0001";
hread(l, b(1 to 4));
assert b(1 to 4) = "0010";
hread(l, b(1 to 16));
assert b(1 to 16) = X"ab23";
hread(l, b(1 to 16));
assert b(1 to 16) = X"1234";
hread(l, b(1 to 16));
assert b(1 to 16) = X"dead";
hread(l, b(1 to 16), good);
assert not good;
hread(l, b(1 to 8), good);
assert not good;
deallocate(l);
l := new string'("0ABC");
hread (L, bv4, good);
assert (good and bv4 = "0101010111100")
report "h) short std.textio.hread " & to_string (bv4) severity error;
deallocate (l);
L := new string'("821"); -- one bit too many
hread (L, bv7, good);
assert (not good)
report "l) std.textio.hread reported good read" severity error;
deallocate(l);
wait;
end process;
test_oread: process is
variable l : line;
variable b : bit_vector(1 to 6);
variable good : boolean;
begin
l := new string'(" 1 2 5_2");
oread(l, b(1 to 3));
assert b(1 to 3) = "001";
oread(l, b(1 to 3));
assert b(1 to 3) = "010";
oread(l, b(1 to 6));
report to_string(b(1 to 6));
assert b(1 to 6) = "101010";
deallocate(l);
wait;
end process;
test_ohwrite: process is
variable l : line;
begin
hwrite(l, "1010", field => 5);
assert l.all = " A";
deallocate(l);
hwrite(l, X"abc", field => 5, justified => left);
assert l.all = "ABC ";
deallocate(l);
owrite(l, o"77");
assert l.all = "77";
deallocate(l);
wait;
end process;
end architecture;
|
gpl-3.0
|
e2aca34038381a2c85564ac74d8f1a06
| 0.475025 | 3.389013 | false | false | false | false |
nickg/nvc
|
test/regress/issue112.vhd
| 1 | 3,059 |
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test2 is
port(
A,B,C : in bit_vector(7 downto 0);
D0 : out bit_vector(7 downto 0);
D1 : out bit_vector(7 downto 0);
D2 : out bit_vector(7 downto 0);
D3 : out bit_vector(7 downto 0);
D4 : out bit_vector(7 downto 0);
D5 : out bit_vector(7 downto 0);
D6 : out bit_vector(7 downto 0);
D7 : out bit_vector(7 downto 0)
);
end test2;
architecture rtl of test2 is
type T_IN_DSP_PC_ARR is array(0 to 7,0 to 7) of bit;
signal s_pout : T_IN_DSP_PC_ARR;
begin
D0 <= s_pout(0,7)&s_pout(0,6)&s_pout(0,5)&s_pout(0,4)&s_pout(0,3)&s_pout(0,2)&s_pout(0,1)&s_pout(0,0);
D1 <= s_pout(1,7)&s_pout(1,6)&s_pout(1,5)&s_pout(1,4)&s_pout(1,3)&s_pout(1,2)&s_pout(1,1)&s_pout(1,0);
D2 <= s_pout(2,7)&s_pout(2,6)&s_pout(2,5)&s_pout(2,4)&s_pout(2,3)&s_pout(2,2)&s_pout(2,1)&s_pout(2,0);
D3 <= s_pout(3,7)&s_pout(3,6)&s_pout(3,5)&s_pout(3,4)&s_pout(3,3)&s_pout(3,2)&s_pout(3,1)&s_pout(3,0);
D4 <= s_pout(4,7)&s_pout(4,6)&s_pout(4,5)&s_pout(4,4)&s_pout(4,3)&s_pout(4,2)&s_pout(4,1)&s_pout(4,0);
D5 <= s_pout(5,7)&s_pout(5,6)&s_pout(5,5)&s_pout(5,4)&s_pout(5,3)&s_pout(5,2)&s_pout(5,1)&s_pout(5,0);
D6 <= s_pout(6,7)&s_pout(6,6)&s_pout(6,5)&s_pout(6,4)&s_pout(6,3)&s_pout(6,2)&s_pout(6,1)&s_pout(6,0);
D7 <= s_pout(7,7)&s_pout(7,6)&s_pout(7,5)&s_pout(7,4)&s_pout(7,3)&s_pout(7,2)&s_pout(7,1)&s_pout(7,0);
VGEN: for V in 0 to 7 generate
UGEN: for I in 0 to 7 generate
signal C_C :bit;
begin
process (C) is
begin
if I=0 then
C_C <= '0';
else
C_C <= C(I-1);
end if;
end process;
UX: entity work.t1
port map(A(I),B(I),C_C,s_pout(V,I));
end generate UGEN;
end generate VGEN;
end rtl;
entity issue112 is
end entity;
architecture test of issue112 is
signal A, B, C : bit_vector(7 downto 0);
signal D0 : bit_vector(7 downto 0);
signal D1 : bit_vector(7 downto 0);
signal D2 : bit_vector(7 downto 0);
signal D3 : bit_vector(7 downto 0);
signal D4 : bit_vector(7 downto 0);
signal D5 : bit_vector(7 downto 0);
signal D6 : bit_vector(7 downto 0);
signal D7 : bit_vector(7 downto 0);
begin
test2_1: entity work.test2
port map (
A => A,
B => B,
C => C,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
D4 => D4,
D5 => D5,
D6 => D6,
D7 => D7);
process is
begin
wait for 1 ns;
assert D0 = X"00";
A <= X"0f";
B <= X"03";
C <= X"01";
wait for 1 ns;
assert D0 = X"02";
wait;
end process;
end architecture;
|
gpl-3.0
|
e12bfee0997a6b4eb4f38867f1f775da
| 0.48676 | 2.491042 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_06.vhd
| 4 | 3,280 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_fg_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture system_level of computer is
type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
-- not in book:
nop);
-- end not in book
type reg_number is range 0 to 31;
constant r0 : reg_number := 0; constant r1 : reg_number := 1; -- . . .
-- not in book:
constant r2 : reg_number := 2;
-- end not in book
type instruction is record
opcode : opcodes;
source_reg1, source_reg2, dest_reg : reg_number;
displacement : integer;
end record instruction;
type word is record
instr : instruction;
data : bit_vector(31 downto 0);
end record word;
signal address : natural;
signal read_word, write_word : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : instruction;
variable PC : natural;
-- . . . -- other declarations for register file, etc.
begin
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_word.instr;
mem_read <= '0';
-- not in book:
wait until mem_ready = '0';
-- end not in book
PC := PC + 4;
case instr_reg.opcode is -- execute the instruction
-- . . .
-- not in book:
when others => null;
-- end not in book
end case;
end process cpu;
memory : process is
type memory_array is array (0 to 2**14 - 1) of word;
variable store : memory_array :=
( 0 => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
1 => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
-- . . .
40 => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
begin
-- . . .
-- not in book:
wait until mem_read = '1';
read_word <= store(address);
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
-- end not in book
end process memory;
end architecture system_level;
|
gpl-2.0
|
de1754c81ca2ae3fc09c62d3d58fe211
| 0.52439 | 3.961353 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug090/crash10.vhdl
| 1 | 1,182 |
library ieee;
use ieee.s_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic);
end component;
begin
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report 2start of tb" severity note;
for i in 0 to 10 loop
case i is
when 0 | 3 =>
for i,in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 =>ehav;
|
gpl-2.0
|
265c66889468b7b8aff1ba7f920e20b0
| 0.58714 | 3.329577 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue632/bug.vhdl
| 1 | 6,004 |
----------------------------------------------------------------------------------
-- Author: Stefan Lohse
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package utilities_pkg is
type t_frequency is range 0 to natural'high units
Hz; -- primary unit
kHz = 1000 Hz; -- secondary unit
MHz = 1000 kHz; -- secondary unit
GHz = 1000 MHz; -- secondary unit
end units;
function to_period(b: t_frequency) return time;
function log2_ceil(a : integer) return natural;
function isSimulation return boolean;
-- ite = if-then-else
function ite( cond: boolean; A: integer; B : integer) return integer;
constant SIMULATION : boolean; -- deferred constant declaration
end package;
package body utilities_pkg is
function to_period(b: t_frequency) return time is
constant result : real := 1.0/real(t_frequency'pos(B));
begin
return result * 1 sec;
end function;
function log2_ceil(a : integer) return natural is
variable pow2 : natural; -- equivalent zu := natural'left
begin
if a = 0 then
return 1;
end if;
for i in 0 to 31 loop
pow2 := 2**i;
if pow2 > a then
return i;
end if;
end loop;
end function;
function isSimulation return boolean is
begin
return is_x('X');
end function;
constant SIMULATION : boolean := isSimulation;
function ite( cond: boolean; A: integer; B : integer) return integer is
begin
if cond then
return A;
else
return B;
end if;
end function;
end package body;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use work.utilities_pkg.all;
package uart_pkg is
type t_baudrate is range 0 to natural'high units -- oder (natural'low to natural'high) oder (1 to 1000000)
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
end units;
function to_period(b: t_baudrate) return time;
function timing_to_cycles(period: time; frequency: t_frequency) return integer;
function ite( cond: boolean; A: t_baudrate; B : t_baudrate) return t_baudrate;
end package;
package body uart_pkg is
function to_period(b: t_baudrate) return time is
constant result : real := 1.0/real(t_baudrate'pos(B));
begin
return result * 1 sec;
end function;
function timing_to_cycles(period: time; frequency: t_frequency) return integer is
variable res_real : real;
begin
res_real := real(time'pos(period)) / 1.0E12;
res_real := real(t_frequency'pos(frequency)) * res_real;
return integer(ceil(res_real));
end function;
function ite( cond: boolean; A: t_baudrate; B : t_baudrate) return t_baudrate is
begin
if cond then
return A;
else
return B;
end if;
end function;
end package body;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.uart_pkg.ALL;
use work.utilities_pkg.all;
entity uart is
generic (
uart_oversampling : positive := 16;
num_of_databits : positive := 8
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx : in STD_LOGIC;
valid : out STD_LOGIC;
error : out STD_LOGIC;
data : out STD_LOGIC_VECTOR(num_of_databits-1 downto 0);
uart_strobe : in STD_LOGIC
);
end entity;
architecture rtl of uart is
signal shift_reg : std_logic_vector(num_of_databits-1 downto 0);
signal shift_en : std_logic;
signal cntbit_value : unsigned(log2ceil(num_of_databits) downto 0);
signal cntbit_en : std_logic;
signal cntbit_rst : std_logic;
signal cntsamp_value : unsigned(log2ceil(num_of_databits) downto 0);
signal cntsamp_en : std_logic;
signal cntsamp_rst : std_logic;
type t_state is (s_idle, s_startbit, s_receive, s_stopbit, s_error);
signal current_state : t_state := s_idle;
signal next_state : t_state;
begin
shift: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
shift_reg <= (others => '0');
elsif shift_en = '1' then
shift_reg <= rx & shift_reg(shift_reg'right downto 1);
end if;
end if;
end process;
data <= shift_reg;
cntbit: process(clk)
begin
if rising_edge(clk) then
if cntbit_rst = '1' then
cntbit_value <= (others => '0');
elsif cntbit_en = '1' then
cntbit_value <= cntbit_value + 1;
end if;
end if;
end process;
cntsamp: process(clk)
begin
if rising_edge(clk) then
if cntsamp_rst = '1' then
cntsamp_value <= (others => '0');
elsif cntsamp_en = '1' then
cntsamp_value <= cntsamp_value + 1;
end if;
end if;
end process;
-- FSM
fsmreg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
current_state <= s_idle;
else
current_state <= next_state;
end if;
end if;
end process;
fsmcomb: process(current_state, uart_strobe, rx, cntbit_value, cntsamp_value)
begin
-- default values;
next_state <= current_state;
valid <= '0';
error <= '0';
cntbit_en <= '0';
cntbit_rst <= '0';
cntsamp_en <= '0';
cntsamp_rst <= '0';
case current_state is
when s_idle =>
cntsamp_rst <= '1';
cntbit_rst <= '1';
if rx = '0' then
next_state <= s_startbit;
end if;
when s_startbit =>
cntsamp_en <= uart_strobe;
if cntsamp_value = (uart_oversampling/2)-1 then
cntsamp_rst <= '1';
next_state <= s_receive;
end if;
when s_receive =>
cntsamp_en <= uart_strobe;
if cntsamp_value = uart_oversampling-1 then
cntsamp_rst <= '1';
cntbit_en <= '1';
shift_en <= '1';
end if;
if cntbit_value = num_of_databits then
cntsamp_rst <= '1';
next_state <= s_stopbit;
end if;
when s_stopbit =>
cntsamp_en <= uart_strobe;
valid <= '1';
if (cntsamp_value = 15) and rx = '1' then
next_state <= s_idle;
elsif (cntsamp_value = 15) and rx = '0' then
next_state <= s_error;
end if;
when s_error =>
error <= '1';
end case;
end process;
end architecture;
|
gpl-2.0
|
bdad1b4a323adb99dd654df73f59af5a
| 0.610759 | 3.060143 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue317/PoC/src/sim/sim_global.v08.vhdl
| 2 | 1,681 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Global simulation constants and shared varibales.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
use PoC.FileIO.all;
use PoC.sim_protected.all;
package sim_global is
-- The default global status objects.
-- ===========================================================================
shared variable globalSimulationStatus : T_SIM_STATUS;
shared variable globalLogFile : T_LOGFILE;
shared variable globalStdOut : T_STDOUT;
end package;
|
gpl-2.0
|
62b5e26a380956896099f3be546d60c7
| 0.568114 | 4.65651 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/func01/func06.vhdl
| 1 | 527 |
library ieee;
use ieee.std_logic_1164.all;
entity func06 is
port (s : natural;
r : out std_logic_vector (15 downto 0));
end func06;
architecture behav of func06 is
function mapv (sel : natural) return std_logic_vector
is
variable res : std_logic_vector(15 downto 0) := (others => '0');
begin
case sel is
when 2 =>
res := x"1234";
when 3 =>
res := x"5678";
when others =>
null;
end case;
return res;
end mapv;
begin
r <= mapv (s);
end behav;
|
gpl-2.0
|
d46ffc7483c6cb73b12b4b6c00d66451
| 0.574953 | 3.356688 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd
| 1 | 4,311 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_10a is
end entity inline_10a;
architecture test of inline_10a is
constant R : real := 10_000.0;
constant R1 : real := 10_000.0;
constant R2 : real := 10_000.0;
-- code from book
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
-- end code from book
begin
block_1 : block is
-- code from book
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
-- end code from book
begin
-- code from book
bus_v == bus_i * R;
-- end code from book
end block block_1;
block_2 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
bus_v.databus(1) == bus_i.databus(1) * R;
-- ...
-- not in book
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
-- end not in book
bus_v.databus(7) == bus_i.databus(7) * R;
-- end code from book
end block block_2;
block_3 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R;
-- end code from book
end block block_3;
block_4 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v / R == i;
-- end code from book
end block block_4;
block_5 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
-- end code from book
bus_v.databus(1) == bus_i.databus(1) * R;
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
bus_v.databus(7) == bus_i.databus(7) * R;
end block block_5;
block_6 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2; -- illegal
-- end code from book
end block block_6;
block_7 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance "current_tolerance";
-- end code from book
end block block_7;
block_8 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance i2'tolerance;
-- end code from book
end block block_8;
block_9 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R tolerance i'tolerance;
-- end code from book
end block block_9;
end architecture test;
|
gpl-2.0
|
b2308764f5f133c7ddcd6b83567f3db4
| 0.62097 | 3.231634 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd
| 4 | 10,579 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxi.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.dlx_types.all;
package dlx_instr is
subtype dlx_opcode is bit_vector(0 to 5);
subtype dlx_sp_func is bit_vector(0 to 5);
subtype dlx_fp_func is bit_vector(0 to 4);
subtype dlx_reg_addr is bit_vector(0 to 4);
subtype dlx_immed16 is bit_vector(0 to 15);
subtype dlx_immed26 is bit_vector(0 to 25);
constant op_special : dlx_opcode := B"000000";
constant op_fparith : dlx_opcode := B"000001";
constant op_j : dlx_opcode := B"000010";
constant op_jal : dlx_opcode := B"000011";
constant op_beqz : dlx_opcode := B"000100";
constant op_bnez : dlx_opcode := B"000101";
constant op_bfpt : dlx_opcode := B"000110";
constant op_bfpf : dlx_opcode := B"000111";
constant op_addi : dlx_opcode := B"001000";
constant op_addui : dlx_opcode := B"001001";
constant op_subi : dlx_opcode := B"001010";
constant op_subui : dlx_opcode := B"001011";
constant op_andi : dlx_opcode := B"001100";
constant op_ori : dlx_opcode := B"001101";
constant op_xori : dlx_opcode := B"001110";
constant op_lhi : dlx_opcode := B"001111";
constant op_rfe : dlx_opcode := B"010000";
constant op_trap : dlx_opcode := B"010001";
constant op_jr : dlx_opcode := B"010010";
constant op_jalr : dlx_opcode := B"010011";
constant op_slli : dlx_opcode := B"010100";
constant op_undef_15 : dlx_opcode := B"010101";
constant op_srli : dlx_opcode := B"010110";
constant op_srai : dlx_opcode := B"010111";
constant op_seqi : dlx_opcode := B"011000";
constant op_snei : dlx_opcode := B"011001";
constant op_slti : dlx_opcode := B"011010";
constant op_sgti : dlx_opcode := B"011011";
constant op_slei : dlx_opcode := B"011100";
constant op_sgei : dlx_opcode := B"011101";
constant op_undef_1E : dlx_opcode := B"011110";
constant op_undef_1F : dlx_opcode := B"011111";
constant op_lb : dlx_opcode := B"100000";
constant op_lh : dlx_opcode := B"100001";
constant op_undef_22 : dlx_opcode := B"100010";
constant op_lw : dlx_opcode := B"100011";
constant op_lbu : dlx_opcode := B"100100";
constant op_lhu : dlx_opcode := B"100101";
constant op_lf : dlx_opcode := B"100110";
constant op_ld : dlx_opcode := B"100111";
constant op_sb : dlx_opcode := B"101000";
constant op_sh : dlx_opcode := B"101001";
constant op_undef_2A : dlx_opcode := B"101010";
constant op_sw : dlx_opcode := B"101011";
constant op_undef_2C : dlx_opcode := B"101100";
constant op_undef_2D : dlx_opcode := B"101101";
constant op_sf : dlx_opcode := B"101110";
constant op_sd : dlx_opcode := B"101111";
constant op_sequi : dlx_opcode := B"110000";
constant op_sneui : dlx_opcode := B"110001";
constant op_sltui : dlx_opcode := B"110010";
constant op_sgtui : dlx_opcode := B"110011";
constant op_sleui : dlx_opcode := B"110100";
constant op_sgeui : dlx_opcode := B"110101";
constant op_undef_36 : dlx_opcode := B"110110";
constant op_undef_37 : dlx_opcode := B"110111";
constant op_undef_38 : dlx_opcode := B"111000";
constant op_undef_39 : dlx_opcode := B"111001";
constant op_undef_3A : dlx_opcode := B"111010";
constant op_undef_3B : dlx_opcode := B"111011";
constant op_undef_3C : dlx_opcode := B"111100";
constant op_undef_3D : dlx_opcode := B"111101";
constant op_undef_3E : dlx_opcode := B"111110";
constant op_undef_3F : dlx_opcode := B"111111";
constant sp_func_nop : dlx_sp_func := B"000000";
constant sp_func_undef_01 : dlx_sp_func := B"000001";
constant sp_func_undef_02 : dlx_sp_func := B"000010";
constant sp_func_undef_03 : dlx_sp_func := B"000011";
constant sp_func_sll : dlx_sp_func := B"000100";
constant sp_func_undef_05 : dlx_sp_func := B"000101";
constant sp_func_srl : dlx_sp_func := B"000110";
constant sp_func_sra : dlx_sp_func := B"000111";
constant sp_func_undef_08 : dlx_sp_func := B"001000";
constant sp_func_undef_09 : dlx_sp_func := B"001001";
constant sp_func_undef_0A : dlx_sp_func := B"001010";
constant sp_func_undef_0B : dlx_sp_func := B"001011";
constant sp_func_undef_0C : dlx_sp_func := B"001100";
constant sp_func_undef_0D : dlx_sp_func := B"001101";
constant sp_func_undef_0E : dlx_sp_func := B"001110";
constant sp_func_undef_0F : dlx_sp_func := B"001111";
constant sp_func_sequ : dlx_sp_func := B"010000";
constant sp_func_sneu : dlx_sp_func := B"010001";
constant sp_func_sltu : dlx_sp_func := B"010010";
constant sp_func_sgtu : dlx_sp_func := B"010011";
constant sp_func_sleu : dlx_sp_func := B"010100";
constant sp_func_sgeu : dlx_sp_func := B"010101";
constant sp_func_undef_16 : dlx_sp_func := B"010110";
constant sp_func_undef_17 : dlx_sp_func := B"010111";
constant sp_func_undef_18 : dlx_sp_func := B"011000";
constant sp_func_undef_19 : dlx_sp_func := B"011001";
constant sp_func_undef_1A : dlx_sp_func := B"011010";
constant sp_func_undef_1B : dlx_sp_func := B"011011";
constant sp_func_undef_1C : dlx_sp_func := B"011100";
constant sp_func_undef_1D : dlx_sp_func := B"011101";
constant sp_func_undef_1E : dlx_sp_func := B"011110";
constant sp_func_undef_1F : dlx_sp_func := B"011111";
constant sp_func_add : dlx_sp_func := B"100000";
constant sp_func_addu : dlx_sp_func := B"100001";
constant sp_func_sub : dlx_sp_func := B"100010";
constant sp_func_subu : dlx_sp_func := B"100011";
constant sp_func_and : dlx_sp_func := B"100100";
constant sp_func_or : dlx_sp_func := B"100101";
constant sp_func_xor : dlx_sp_func := B"100110";
constant sp_func_undef_27 : dlx_sp_func := B"100111";
constant sp_func_seq : dlx_sp_func := B"101000";
constant sp_func_sne : dlx_sp_func := B"101001";
constant sp_func_slt : dlx_sp_func := B"101010";
constant sp_func_sgt : dlx_sp_func := B"101011";
constant sp_func_sle : dlx_sp_func := B"101100";
constant sp_func_sge : dlx_sp_func := B"101101";
constant sp_func_undef_2E : dlx_sp_func := B"101110";
constant sp_func_undef_2F : dlx_sp_func := B"101111";
constant sp_func_movi2s : dlx_sp_func := B"110000";
constant sp_func_movs2i : dlx_sp_func := B"110001";
constant sp_func_movf : dlx_sp_func := B"110010";
constant sp_func_movd : dlx_sp_func := B"110011";
constant sp_func_movfp2i : dlx_sp_func := B"110100";
constant sp_func_movi2fp : dlx_sp_func := B"110101";
constant sp_func_undef_36 : dlx_sp_func := B"110110";
constant sp_func_undef_37 : dlx_sp_func := B"110111";
constant sp_func_undef_38 : dlx_sp_func := B"111000";
constant sp_func_undef_39 : dlx_sp_func := B"111001";
constant sp_func_undef_3A : dlx_sp_func := B"111010";
constant sp_func_undef_3B : dlx_sp_func := B"111011";
constant sp_func_undef_3C : dlx_sp_func := B"111100";
constant sp_func_undef_3D : dlx_sp_func := B"111101";
constant sp_func_undef_3E : dlx_sp_func := B"111110";
constant sp_func_undef_3F : dlx_sp_func := B"111111";
constant fp_func_addf : dlx_fp_func := B"00000";
constant fp_func_subf : dlx_fp_func := B"00001";
constant fp_func_multf : dlx_fp_func := B"00010";
constant fp_func_divf : dlx_fp_func := B"00011";
constant fp_func_addd : dlx_fp_func := B"00100";
constant fp_func_subd : dlx_fp_func := B"00101";
constant fp_func_multd : dlx_fp_func := B"00110";
constant fp_func_divd : dlx_fp_func := B"00111";
constant fp_func_cvtf2d : dlx_fp_func := B"01000";
constant fp_func_cvtf2i : dlx_fp_func := B"01001";
constant fp_func_cvtd2f : dlx_fp_func := B"01010";
constant fp_func_cvtd2i : dlx_fp_func := B"01011";
constant fp_func_cvti2f : dlx_fp_func := B"01100";
constant fp_func_cvti2d : dlx_fp_func := B"01101";
constant fp_func_mult : dlx_fp_func := B"01110";
constant fp_func_div : dlx_fp_func := B"01111";
constant fp_func_eqf : dlx_fp_func := B"10000";
constant fp_func_nef : dlx_fp_func := B"10001";
constant fp_func_ltf : dlx_fp_func := B"10010";
constant fp_func_gtf : dlx_fp_func := B"10011";
constant fp_func_lef : dlx_fp_func := B"10100";
constant fp_func_gef : dlx_fp_func := B"10101";
constant fp_func_multu : dlx_fp_func := B"10110";
constant fp_func_divu : dlx_fp_func := B"10111";
constant fp_func_eqd : dlx_fp_func := B"11000";
constant fp_func_ned : dlx_fp_func := B"11001";
constant fp_func_ltd : dlx_fp_func := B"11010";
constant fp_func_gtd : dlx_fp_func := B"11011";
constant fp_func_led : dlx_fp_func := B"11100";
constant fp_func_ged : dlx_fp_func := B"11101";
constant fp_func_undef_1E : dlx_fp_func := B"11110";
constant fp_func_undef_1F : dlx_fp_func := B"11111";
subtype dlx_opcode_num is natural range 0 to 63;
subtype dlx_sp_func_num is natural range 0 to 63;
subtype dlx_fp_func_num is natural range 0 to 31;
subtype instr_name is string(1 to 8);
type opcode_name_array is array (dlx_opcode_num) of instr_name;
type sp_func_name_array is array (dlx_sp_func_num) of instr_name;
type fp_func_name_array is array (dlx_fp_func_num) of instr_name;
constant opcode_names : opcode_name_array;
constant sp_func_names : sp_func_name_array;
constant fp_func_names : fp_func_name_array;
subtype reg_index is natural range 0 to 31;
constant link_reg : reg_index := 31;
procedure disassemble ( instr : dlx_bv_word;
disassembled_instr : out string; len : out positive );
end package dlx_instr;
|
gpl-2.0
|
8a1bf7bbf6bb94a84a81a93fc182e407
| 0.633141 | 2.9733 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc666.vhd
| 4 | 3,749 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc666.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:57 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00666ent IS
END c03s04b01x00p01n01i00666ent;
ARCHITECTURE c03s04b01x00p01n01i00666arch OF c03s04b01x00p01n01i00666ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C58 : array_rec_cons (0 to 7) := (others => C27);
type array_rec_cons_file is file of array_rec_cons;
BEGIN
TESTING: PROCESS
file filein : array_rec_cons_file open write_mode is "iofile.13";
BEGIN
for i in 1 to 100 loop
write(filein,C58);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00666 - The output file will be verified by test s010116.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00666arch;
|
gpl-2.0
|
af129c2ebba91b3635f7d02b3397f4c9
| 0.598826 | 3.749 | false | true | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_fmul_2_max_dsp_32/sim/doHistStretch_ap_fmul_2_max_dsp_32.vhd
| 1 | 10,803 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fmul_2_max_dsp_32;
ARCHITECTURE doHistStretch_ap_fmul_2_max_dsp_32_arch OF doHistStretch_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fmul_2_max_dsp_32_arch;
|
gpl-3.0
|
4c5432681768345cdb5403d23f7f2f8f
| 0.632787 | 3.219011 | false | false | false | false |
nickg/nvc
|
test/bounds/issue477a.vhd
| 1 | 2,690 |
package test_pkg is
type t_segment_type is (
TYPE_0,
TYPE_1,
TYPE_2,
TYPE_3,
TYPE_4,
TYPE_5
);
type unsigned is array (natural range <>) of bit;
type t_data_segment is record
data_word : bit_vector(15 downto 0); -- 0: 16
word_idx : unsigned(11 downto 0); -- 16: 12
segment_type : t_segment_type; -- 28: 1+3
word_length : natural range 1 to 2; -- 32: 4
crc_check : boolean; -- 36: 1+3
table : natural range 1 to 2; -- 40: 4
end record;
type t_data_segment_template is array(t_segment_type) of t_data_segment;
constant C_SEGMENT_RECORDS : t_data_segment_template := (
TYPE_0 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_0,
word_length => 1,
crc_check => false,
table => 16#a0#),
TYPE_1 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_1,
word_length => 2,
crc_check => false,
table => 1),
TYPE_2 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_2,
word_length => 1,
crc_check => false,
table => 16#a1#),
TYPE_3 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_3,
word_length => 2,
crc_check => true,
table => 16#a2#),
TYPE_4 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_4,
word_length => 2,
crc_check => true,
table => 16#a3#),
TYPE_5 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_5,
word_length => 2,
crc_check => true,
table => 16#a4#)
);
constant C_DATA_INVALID_VERSION : bit_vector(7 downto 0) := x"FF";
constant C_DATA_VERSION : bit_vector(C_SEGMENT_RECORDS(TYPE_2).word_length*8-1 downto 0) := C_DATA_INVALID_VERSION;
end package;
|
gpl-3.0
|
f3d0053fea6b5cadac981da321884b7d
| 0.381041 | 3.955882 | false | false | false | false |
tgingold/ghdl
|
libraries/openieee/v93/numeric_std.vhdl
| 2 | 10,556 |
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
type UNSIGNED is array (natural range <>) of STD_LOGIC;
type SIGNED is array (natural range <>) of STD_LOGIC;
function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED;
function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED;
-- Convert 'H' and '1' to '1', 'L' and '0' to '0'.
-- If any other value is present, return (others => XMAP)
-- Issue a warning in that case, and if S is a null array.
-- Result index range is S'Length - 1 downto 0.
function std_match (l, r : std_ulogic) return boolean;
function std_match (l, r : std_ulogic_vector) return boolean;
function std_match (l, r : std_logic_vector) return boolean;
function std_match (l, r : UNSIGNED) return boolean;
function std_match (l, r : SIGNED) return boolean;
-- Return True iff L and R matches.
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
function TO_INTEGER (ARG : SIGNED) return INTEGER;
-- Convert ARG to an integer.
-- Simulation is aborted in case of overflow.
-- Issue a warning in case of non-logical value.
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
-- Convert ARG to unsigned.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
-- Convert ARG to signed.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED;
-- Result index range is NEW_SIZE - 1 downto 0 (unless null array).
-- For SIGNED, the sign of the result is the sign of ARG.
function "=" (L, R : UNSIGNED) return BOOLEAN;
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "/=" (L, R : UNSIGNED) return BOOLEAN;
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<" (L, R : UNSIGNED) return BOOLEAN;
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<=" (L, R : UNSIGNED) return BOOLEAN;
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">" (L, R : UNSIGNED) return BOOLEAN;
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">=" (L, R : UNSIGNED) return BOOLEAN;
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "=" (L, R : SIGNED) return BOOLEAN;
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "/=" (L, R : SIGNED) return BOOLEAN;
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<" (L, R : SIGNED) return BOOLEAN;
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<=" (L, R : SIGNED) return BOOLEAN;
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">" (L, R : SIGNED) return BOOLEAN;
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">=" (L, R : SIGNED) return BOOLEAN;
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Issue a warning in case of non-logical value.
function "-" (ARG : SIGNED) return SIGNED;
-- Compute -ARG.
-- Result index range is Arg'length - 1 downto 0.
function "abs" (ARG : SIGNED) return SIGNED;
-- Compute abs ARG.
-- Result index range is Arg'length - 1 downto 0.
function "+" (L, R : UNSIGNED) return UNSIGNED;
function "+" (L, R : SIGNED) return SIGNED;
function "-" (L, R : UNSIGNED) return UNSIGNED;
function "-" (L, R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is max (L'Length, R'Length) - 1 downto 0.
-- Issue a warning in case of non-logical value.
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "+" (L : SIGNED; R : INTEGER) return SIGNED;
function "+" (L : INTEGER; R : SIGNED) return SIGNED;
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "-" (L : SIGNED; R : INTEGER) return SIGNED;
function "-" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is V'Length - 1 downto 0, where V is the vector
-- parameter.
-- Issue a warning in case of non-logical value.
-- Issue a warning if value is truncated.
function "*" (L, R : UNSIGNED) return UNSIGNED;
function "*" (L, R : SIGNED) return SIGNED;
-- Compute L * R
-- Result index range is L'Length + R'Length - 1 downto 0.
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "*" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L * R
-- R is converted to a vector of length L'length
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "*" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L * R
-- L is converted to a vector of length R'length
function "/" (L, R : UNSIGNED) return UNSIGNED;
function "/" (L, R : SIGNED) return SIGNED;
function "rem" (L, R : UNSIGNED) return UNSIGNED;
function "rem" (L, R : SIGNED) return SIGNED;
function "mod" (L, R : UNSIGNED) return UNSIGNED;
function "mod" (L, R : SIGNED) return SIGNED;
-- Compute L op R
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "/" (L : SIGNED; R : INTEGER) return SIGNED;
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "rem" (L : SIGNED; R : INTEGER) return SIGNED;
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "mod" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L op R.
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "/" (L : INTEGER; R : SIGNED) return SIGNED;
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "rem" (L : INTEGER; R : SIGNED) return SIGNED;
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "mod" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L op R.
-- Result index range is R'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
-- Result may be truncated.
function "not" (l : UNSIGNED) return UNSIGNED;
function "not" (l : SIGNED) return SIGNED;
function "and" (l, r : UNSIGNED) return UNSIGNED;
function "and" (l, r : SIGNED) return SIGNED;
function "nand" (l, r : UNSIGNED) return UNSIGNED;
function "nand" (l, r : SIGNED) return SIGNED;
function "or" (l, r : UNSIGNED) return UNSIGNED;
function "or" (l, r : SIGNED) return SIGNED;
function "nor" (l, r : UNSIGNED) return UNSIGNED;
function "nor" (l, r : SIGNED) return SIGNED;
function "xor" (l, r : UNSIGNED) return UNSIGNED;
function "xor" (l, r : SIGNED) return SIGNED;
function "xnor" (l, r : UNSIGNED) return UNSIGNED;
function "xnor" (l, r : SIGNED) return SIGNED;
-- Compute L OP R.
-- Result index range is L'Length - 1 downto 0.
-- No specific handling of null array: the index range of the result
-- would be -1 downto 0 (without warning). This it not what is specified
-- in 1076.3, but corresponds to the standard implementation.
-- No specific handling of non-logical values. Behaviour is compatible
-- with std_logic_1164.
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function rotate_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function rotate_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function "rol" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "rol" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
function "ror" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "ror" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
end NUMERIC_STD;
|
gpl-2.0
|
e52694c8861702d53b1b95c442a80cb7
| 0.648352 | 3.594144 | false | false | false | false |
nickg/nvc
|
test/regress/logical2.vhd
| 1 | 2,510 |
entity logical2 is
end entity;
architecture test of logical2 is
signal x : bit;
signal one : bit := '1';
signal zero : bit := '0';
signal vec : bit_vector(0 to 1) := ('0', '1');
begin
process is
variable v : boolean := true;
begin
x <= '0';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = zero;
assert (x or zero) = zero;
assert (x or one) = one;
assert (x xor zero) = zero;
assert (x xor one) = one;
assert (x xnor zero) = one;
assert (x xnor one) = zero;
assert (x nand zero) = one;
assert (x nand one) = one;
assert (x nor zero) = one;
assert (x nor one) = zero;
x <= '1';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = one;
assert (x or zero) = one;
assert (x or one) = one;
assert (x xor zero) = one;
assert (x xor one) = zero;
assert (x xnor zero) = zero;
assert (x xnor one) = one;
assert (x nand zero) = one;
assert (x nand one) = zero;
assert (x nor zero) = zero;
assert (x nor one) = zero;
v := v and v; assert v;
v := v or v; assert v;
v := v nand v; assert not v;
v := v nor v; assert v;
v := v xor v; assert not v;
v := v xnor v; assert v;
v := v xnor v; assert v;
-- This tests short circuiting
x <= '0';
wait for 1 ns;
assert (x and vec(0)) = zero;
assert (x and vec(1)) = zero;
assert (x or vec(0)) = zero;
assert (x or vec(1)) = one;
assert (x xor vec(0)) = zero;
assert (x xor vec(1)) = one;
assert (x xnor vec(0)) = one;
assert (x xnor vec(1)) = zero;
assert (x nand vec(0)) = one;
assert (x nand vec(1)) = one;
assert (x nor vec(0)) = one;
assert (x nor vec(1)) = zero;
x <= '1';
wait for 1 ns;
assert (x and vec(0)) = zero;
assert (x and vec(1)) = one;
assert (x or vec(0)) = one;
assert (x or vec(1)) = one;
assert (x xor vec(0)) = one;
assert (x xor vec(1)) = zero;
assert (x xnor vec(0)) = zero;
assert (x xnor vec(1)) = one;
assert (x nand vec(0)) = one;
assert (x nand vec(1)) = zero;
assert (x nor vec(0)) = zero;
assert (x nor vec(1)) = zero;
wait;
end process;
end architecture;
|
gpl-3.0
|
363efe894d19da417f6a4842af78f19c
| 0.473705 | 3.369128 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd
| 4 | 115,232 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal ll_in : electrical;
terminal ll_out : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
servo_limiter : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => ll_out,
output => servo_out
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
k => 400.0,
f1 => 5.0,
f2 => 2000.0
)
port map(
input => ll_in,
output => ll_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang'above(ang_max) use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang'above(ang_min) use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Constant Voltage Source (Includes Frequency Domain settings)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_constant IS
-- Initialize parameters
GENERIC (
level : VOLTAGE; -- Constant voltage value (V)
ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
ac_phase : real := 0.0); -- AC phase (degrees)
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_constant;
-- Ideal Architecture (I = constant)
ARCHITECTURE ideal OF v_constant IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
v == level;
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical sinusoidal voltage source (stick.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY stick IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL v_out : ELECTRICAL);
END ENTITY stick;
-- Ideal Architecture
ARCHITECTURE ideal OF stick IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity RF_xmtr_rcvr is
generic (td : time := 0ns);
port
(
tdm_in : in std_logic ;
tdm_out : out std_logic
);
end RF_xmtr_rcvr;
architecture behavioral of RF_xmtr_rcvr is
begin
tdm_out <= tdm_in after td;
end;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Simple Digital-Controlled Two-position Switch Model
-- Switch position 1 ('0') or switch position 2 ('1')
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY switch_dig_2in is
GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
r_closed : RESISTANCE := 0.001; -- Closed switch resistance
trans_time : real := 0.00001); -- Transition time to each position
PORT (sw_state : in std_logic; -- Digital control input
TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
END ENTITY switch_dig_2in;
ARCHITECTURE ideal OF switch_dig_2in IS
-- CONSTANT log_r_open : real := log10(r_open);
-- CONSTANT log_r_closed : real := log10(r_closed);
-- SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance
-- SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance
SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
BEGIN
PROCESS (sw_state) -- Sensitivity to digital control input
BEGIN
IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
END IF;
END PROCESS;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1*i1; -- Apply Ohm's law to in1
v2 == r2*i2; -- Apply Ohm's law to in2
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Digital clock with 50% duty cycle
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock IS
GENERIC (
period : time); -- Clock period
PORT (
clk_out : OUT std_logic);
END ENTITY clock;
ARCHITECTURE ideal OF clock IS
BEGIN
-- clock process
process
begin
clk_out <= '0';
wait for period/2;
clk_out <= '1';
wait for period/2;
end process;
END ARCHITECTURE ideal;
--
-- This digital clock allows user to specify the duty cycle using
-- the parameters "on_time" and "off_time"
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY clock_duty IS
GENERIC (
on_time : time := 20 us;
off_time : time := 19.98 ms
);
PORT (
clock_out : OUT std_logic := '0');
END ENTITY clock_duty;
ARCHITECTURE ideal OF clock_duty IS
BEGIN
-- clock process
process
begin
clock_out <= '1';
wait for on_time;
clock_out <= '0';
wait for off_time;
end process;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rc_clk is
port(
clk_100k : out std_logic;
clk_6K : out std_logic;
clk_50 : out std_logic
);
end rc_clk;
architecture rc_clk of rc_clk is
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.clock(ideal)
generic map(
period => 10us
)
port map(
CLK_OUT => clk_100k
);
XCMP2 : entity work.clock(ideal)
generic map(
period => 150us
)
port map(
CLK_OUT => clk_6K
);
clk_50Hz : entity work.clock_duty(ideal)
generic map(
on_time => 20 us,
off_time => 19.98 ms
)
port map(
CLOCK_OUT => clk_50
);
end rc_clk;
--
-- This model counts the number of input clock transitions and outputs
-- a '1' when this number equals the value of the user-defined constant 'count'
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity bit_cnt is
generic (
count : integer -- User-defined value to count up to
);
port
(
bit_in : in std_logic ;
clk : in std_logic ;
dly_out : out std_logic
);
end bit_cnt;
architecture behavioral of bit_cnt is
begin
serial_clock : process is
begin
wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
wait until clk'event AND (clk = '1' OR clk = 'H');
END LOOP ;
dly_out <= '1'; -- After count is reached, set output high
wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
dly_out <= '0'; -- Reset output to '0' on next clock input
end process serial_clock;
end;
--
--//////////////////////////////////////////////////////////////////
-- NOTE: This is an intermediate file for HDL inspection only.
-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg.
-- Generated by sde2hdl version 16.1.0.2
--//////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach1 IS
PORT (
a2d_eoc : IN std_logic;
clk_50 : IN std_logic;
clk_100k : IN std_logic;
clk_6k : IN std_logic;
ser_done : IN std_logic;
ch_sel : OUT std_logic;
frm_gen : OUT std_logic;
a2d_oe : OUT std_logic;
a2d_start : OUT std_logic;
p2s_oe : OUT std_logic;
p2s_load : OUT std_logic;
parity_oe : OUT std_logic;
ser_cnt : OUT std_logic;
p2s_clr : OUT std_logic);
END state_mach1;
ARCHITECTURE state_diagram OF state_mach1 IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
, load, ad_ch2, delay);
SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
SIGNAL FB_frm_gen : std_logic;
SIGNAL FB_p2s_load : std_logic;
SIGNAL FB_ch_sel : std_logic;
BEGIN
frm_gen <= FB_frm_gen ;
p2s_load <= FB_p2s_load ;
ch_sel <= FB_ch_sel ;
sm1:
PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
BEGIN
CASE CS_state_mach1_sm1 IS
WHEN V_begin =>
FB_frm_gen <= ('1');
a2d_start <= ('0');
a2d_oe <= ('0');
FB_p2s_load <= ('0');
p2s_clr <= ('0');
p2s_oe <= ('0');
FB_ch_sel <= ('0');
parity_oe <= ('0');
ser_cnt <= ('0');
IF ((FB_frm_gen = '1')) THEN
NS_state_mach1_sm1 <= frm_rd;
ELSE
NS_state_mach1_sm1 <= V_begin;
END IF;
WHEN frm_rd =>
FB_p2s_load <= ('1');
IF ((FB_p2s_load = '1')) THEN
NS_state_mach1_sm1 <= ser_oe;
ELSE
NS_state_mach1_sm1 <= frm_rd;
END IF;
WHEN ser_oe =>
p2s_oe <= ('1');
FB_frm_gen <= ('0');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF ((ser_done = '1')) THEN
NS_state_mach1_sm1 <= ch1;
ELSE
NS_state_mach1_sm1 <= ser_oe;
END IF;
WHEN ch1 =>
p2s_oe <= ('0');
FB_ch_sel <= ('0');
a2d_start <= ('1');
ser_cnt <= ('0');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ch1;
END IF;
WHEN data_en =>
a2d_start <= ('0');
a2d_oe <= ('1');
parity_oe <= ('1');
NS_state_mach1_sm1 <= load;
WHEN tdm_oe =>
a2d_oe <= ('0');
parity_oe <= ('0');
p2s_oe <= ('1');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
NS_state_mach1_sm1 <= ch2;
ELSE
NS_state_mach1_sm1 <= tdm_oe;
END IF;
WHEN ch2 =>
p2s_oe <= ('0');
ser_cnt <= ('0');
FB_ch_sel <= ('1');
NS_state_mach1_sm1 <= delay;
WHEN load =>
FB_p2s_load <= ('1');
NS_state_mach1_sm1 <= tdm_oe;
WHEN ad_ch2 =>
a2d_start <= ('1');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ad_ch2;
END IF;
WHEN delay =>
NS_state_mach1_sm1 <= ad_ch2;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach1_sm1 <= V_begin;
ELSE
CS_state_mach1_sm1 <= NS_state_mach1_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt is
port(
a2d_eoc : in std_logic;
clk_50 : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
p2s_load : out std_logic;
p2s_oe : out std_logic;
parity_oe : out std_logic;
a2d_start : out std_logic;
a2d_oe : out std_logic;
frm_gen : out std_logic;
ch_sel : out std_logic;
p2s_clr : out std_logic
);
end sm_cnt;
architecture sm_cnt of sm_cnt is
-- Component declarations
-- Signal declarations
signal ser_done : std_logic;
signal serial_cnt : std_logic;
begin
-- Signal assignments
-- Component instances
bit_cnt1 : entity work.bit_cnt(behavioral)
generic map(
count => 15
)
port map(
bit_in => serial_cnt,
clk => clk_6k,
dly_out => ser_done
);
state_mach16 : entity work.state_mach1
port map(
ser_cnt => serial_cnt,
ch_sel => ch_sel,
frm_gen => frm_gen,
a2d_oe => a2d_oe,
a2d_start => a2d_start,
parity_oe => parity_oe,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
p2s_clr => p2s_clr,
clk_6k => clk_6k,
clk_100k => clk_100k,
clk_50 => clk_50,
a2d_eoc => a2d_eoc,
ser_done => ser_done
);
end sm_cnt;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd)
--DESCRIPTION:
--
--This is a VHDL-AMS model of a simple analog to digital converter. The model
--describes the general behavior of A/D converters for system level design and
--verification.
--The format of the digital output is binary coding.
--
--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
--
-- Use IEEE natures and packages
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity a2d_nbit is
generic (
Vmax: REAL := 5.0 ; -- ADC's maximum range
Nbits: INTEGER := 10 ; -- number bits in ADC's output
delay: TIME := 10 us -- ADC's conversion time
);
port (
signal start: in std_logic ; -- Start signal
signal clk: in std_logic ; -- Strobe clock
signal oe: in std_logic ; -- Output enable
terminal ain: ELECTRICAL ; -- ADC's analog input terminal
signal eoc: out std_logic := '0' ; -- End Of Conversion pin
signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
end entity a2d_nbit;
architecture sar of a2d_nbit is
type states is (input, convert, output) ; -- Three states of A2D Conversion
constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process
variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
variable status: states := input ; -- Begin with "input" CASE
variable bit_cnt: integer := Nbits -1 ;
begin
CASE status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H' ;
thresh := Vmax ;
Vtmp := Vin ;
eoc <= '0' ;
status := convert ; -- Go to convert state
when convert => -- Begin successive approximation conversion
thresh := thresh / 2.0 ; -- Get value of MSB
wait on clk until clk = '1' OR clk = 'H';
if Vtmp > thresh then
dtmp(bit_cnt) := '1' ;
Vtmp := Vtmp - thresh ;
else
dtmp(bit_cnt) := '0' ;
end if ;
bit_cnt := bit_cnt - 1 ;
if (bit_cnt + 1) < 1 then
status := output ; -- Go to output state
end if;
when output => -- Wait for output enable, then put data on output pins
eoc <= '1' after delay ;
wait on oe until oe = '1' OR oe = 'H' ;
FOR i in bit_range DOWNTO 0 LOOP
dout(i) <= dtmp(i) ;
END LOOP ;
wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
FOR i in bit_range DOWNTO 0 LOOP
dout <= "ZZZZZZZZZZ" ;
END LOOP ;
bit_cnt := bit_range ;
status := input ; -- Set up for next conversion
END CASE ;
end process sa_adc ;
Iin == 0.0 ; -- Ideal input draws no current
end architecture sar ;
--
-- Parallel input/serial output shift register
-- With 4 trailing zeros
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity shift_reg is
generic ( td : time := 0 ns);
port
(
bus_in : in std_logic_vector ; -- Input bus
clk : in std_logic ; -- Shift clock
oe : in std_logic ; -- Output enable
ser_out : out std_logic := '0'; -- Output port
load : in std_logic ; -- Parallel input load
clr : in std_logic -- Clear register
);
end entity shift_reg;
architecture behavioral of shift_reg is
begin
control_proc : process
VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
begin
IF (clr = '1' OR clr = 'H') then
bit_val := "000000000000"; -- Set all input bits to zero
ELSE
wait until load'event AND (load = '1' OR load = 'H');
FOR i IN bus_in'high DOWNTO bus_in'low LOOP
bit_val(i) := bus_in(i) ; -- Transfer input data to variable
END LOOP ;
END IF;
wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
FOR i IN bit_val'high DOWNTO bit_val'low LOOP
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= bit_val(i) ;
END LOOP ;
FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= '0';
END LOOP;
END process;
end architecture behavioral;
--
-- This model generates a 12-bit data frame synchronization code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_gen is
port
(
oe : in std_logic := '0';
sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
end entity frame_gen;
architecture simple of frame_gen is
begin
enbl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
sync_out <= "010101010101"; -- Sync code
ELSE
sync_out <= "ZZZZZZZZZZZZ";
END IF;
END PROCESS;
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input XOR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY xor2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY xor2;
ARCHITECTURE ideal OF xor2 IS
BEGIN
output <= in1 XOR in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- level_set_tri.vhd
-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
-- If OE = '0' set output to high impedance
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set_tri IS
GENERIC (
logic_val : std_logic := 'Z');
PORT (
OE : IN std_logic;
level : OUT std_logic := 'Z');
END ENTITY level_set_tri;
-- Simple architecture
ARCHITECTURE ideal OF level_set_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
level <= logic_val;
ELSE
level <= 'Z';
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Simple Tri-state Buffer with delay time
-- If OE = 1, output = input after delay
-- If OE /= 1, output = Z after delay
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY buffer_tri IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
OE : IN std_logic;
output : OUT std_logic);
END ENTITY buffer_tri;
ARCHITECTURE ideal OF buffer_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE, input;
IF OE = '1' THEN
output <= input AFTER delay;
ELSE
output <= 'Z' AFTER delay;
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- ideal one bit D/A converter
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY d2a_bit IS
GENERIC (vlow : real :=0.0; -- output high voltage
vhigh : real :=5.0); -- output low voltage
PORT (D : IN std_logic; -- digital (std_logic) intout
TERMINAL A : electrical); -- analog (electrical) output
END ENTITY d2a_bit;
ARCHITECTURE ideal OF d2a_bit IS
QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
SIGNAL vin : real := 0.0;
BEGIN
vin <= vhigh WHEN D = '1' ELSE vlow;
-- Use 'RAMP for discontinuous signal
vout == vin'RAMP(1.0e-9);
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_gen is
port(
parity : in std_logic_vector(1 to 10);
oe : in std_logic;
parity_out : out std_logic_vector(0 to 11)
);
end parity_gen;
architecture parity_gen of parity_gen is
-- Component declarations
-- Signal declarations
terminal par_bit_gen_a : electrical;
signal XSIG010002 : std_logic;
signal XSIG010003 : std_logic;
signal XSIG010004 : std_logic;
signal XSIG010005 : std_logic;
signal XSIG010006 : std_logic;
signal XSIG010007 : std_logic;
signal XSIG010008 : std_logic;
signal XSIG010009 : std_logic;
signal XSIG010098 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => parity(1),
in2 => parity(2),
output => XSIG010002
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => parity(3),
in2 => parity(4),
output => XSIG010003
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => parity(5),
in2 => parity(6),
output => XSIG010004
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => parity(7),
in2 => parity(8),
output => XSIG010005
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => parity(9),
in2 => parity(10),
output => XSIG010008
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010002,
in2 => XSIG010003,
output => XSIG010006
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010004,
in2 => XSIG010005,
output => XSIG010007
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010006,
in2 => XSIG010007,
output => XSIG010009
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010009,
in2 => XSIG010008,
output => XSIG010098
);
XCMP18 : entity work.level_set_tri(ideal)
generic map(
logic_val => '1'
)
port map(
level => parity_out(11),
oe => oe
);
XCMP19 : entity work.buffer_tri(ideal)
port map(
input => parity(1),
output => parity_out(1),
oe => oe
);
XCMP20 : entity work.buffer_tri(ideal)
port map(
input => parity(2),
output => parity_out(2),
oe => oe
);
XCMP21 : entity work.buffer_tri(ideal)
port map(
input => parity(3),
output => parity_out(3),
oe => oe
);
XCMP22 : entity work.buffer_tri(ideal)
port map(
input => parity(4),
output => parity_out(4),
oe => oe
);
XCMP23 : entity work.buffer_tri(ideal)
port map(
input => parity(5),
output => parity_out(5),
oe => oe
);
XCMP24 : entity work.buffer_tri(ideal)
port map(
input => parity(6),
output => parity_out(6),
oe => oe
);
XCMP25 : entity work.buffer_tri(ideal)
port map(
input => parity(7),
output => parity_out(7),
oe => oe
);
XCMP26 : entity work.buffer_tri(ideal)
port map(
input => parity(8),
output => parity_out(8),
oe => oe
);
XCMP27 : entity work.buffer_tri(ideal)
port map(
input => parity(9),
output => parity_out(9),
oe => oe
);
XCMP28 : entity work.buffer_tri(ideal)
port map(
input => parity(10),
output => parity_out(10),
oe => oe
);
XCMP29 : entity work.buffer_tri(ideal)
port map(
input => XSIG010098,
output => parity_out(0),
oe => oe
);
XCMP30 : entity work.d2a_bit(ideal)
port map(
D => XSIG010098,
A => par_bit_gen_a
);
end parity_gen;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tdm_encoder is
port(
clk : in std_logic;
p2s_oe : in std_logic;
p2s_load : in std_logic;
frm_gen : in std_logic;
parity_oe : in std_logic;
tdm_out : out std_logic;
p2s_clr : in std_logic;
a2d_data : in std_logic_vector(1 to 10)
);
end tdm_encoder;
architecture tdm_encoder of tdm_encoder is
-- Component declarations
-- Signal declarations
signal sync_par : std_logic_vector(0 to 11);
begin
-- Signal assignments
-- Component instances
p2s1 : entity work.shift_reg(behavioral)
port map(
bus_in => sync_par,
clk => clk,
oe => p2s_oe,
ser_out => tdm_out,
load => p2s_load,
clr => p2s_clr
);
sync_gen1 : entity work.frame_gen(simple)
port map(
oe => frm_gen,
sync_out => sync_par
);
par_gen1 : entity work.parity_gen
port map(
parity => a2d_data,
parity_out => sync_par,
oe => parity_oe
);
end tdm_encoder;
--
-- Manchester Encoder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY menc_rsc IS
port ( dig_in : in STD_LOGIC; -- digital input
clk : in STD_LOGIC; -- TX internal clock
reset: in STD_LOGIC; -- not reset
-- bit_out : inout real); -- real output
bit_out : out std_logic); -- real output
END ENTITY menc_rsc;
ARCHITECTURE bhv OF menc_rsc IS
-- signal bhigh:real:= 1.0; -- bit encoding
-- signal blow:real:= -1.0; -- bit encoding
-- signal bnormal:real:=0.0; -- bit encoding
signal bit1:STD_LOGIC;
signal bhigh:std_logic:= '1'; -- bit encoding
signal blow:std_logic:= '0'; -- bit encoding
begin
-- proc1: process (dig_in, clk, bit1,bhigh,blow,bnormal)
proc1: process (dig_in, clk, bit1,bhigh,blow)
begin
if (reset = '1') then
bit1 <= '0';
else
bit1 <= dig_in XOR clk; -- manchester encoding
end if;
if (bit1 = '1') then
bit_out <= bhigh;
else
bit_out <= blow;
-- elsif bit1 = '0' then
-- bit_out <= blow;
-- else
-- bit_out <= bnormal;
end if;
end process;
end architecture bhv;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Digitize_Encode_Man is
port(
tdm_out : out std_logic;
terminal ch1_in : electrical;
terminal ch2_in : electrical
);
end Digitize_Encode_Man;
architecture Digitize_Encode_Man of Digitize_Encode_Man is
-- Component declarations
-- Signal declarations
terminal a2d_ana_in : electrical;
signal ch_bus : std_logic_vector(1 to 10);
signal clk_6K : std_logic;
signal dig_in : std_logic;
signal frm_gen_ctl : std_logic;
signal p2s_clr : std_logic;
signal p2s_load : std_logic;
signal p2s_oe : std_logic;
signal par_oe : std_logic;
signal reset : std_logic;
signal reset_m : std_logic;
signal start_a2d1 : std_logic;
signal sw_ctl : std_logic;
signal XSIG010091 : std_logic;
signal XSIG010190 : std_logic;
signal XSIG010196 : std_logic;
begin
-- Signal assignments
-- Component instances
A_SWITCH1 : entity work.switch_dig_2in(ideal)
port map(
p_in1 => ch1_in,
p_out => a2d_ana_in,
sw_state => sw_ctl,
p_in2 => ch2_in
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => reset,
clk_6K => clk_6K,
clk_100k => XSIG010190
);
sm_xmtr1 : entity work.sm_cnt
port map(
clk_100k => XSIG010190,
a2d_start => start_a2d1,
a2d_eoc => XSIG010091,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
ch_sel => sw_ctl,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
a2d_oe => XSIG010196,
clk_50 => reset,
clk_6k => clk_6K,
p2s_clr => p2s_clr
);
a2d1 : entity work.a2d_nbit(sar)
generic map(
Vmax => 4.8
)
port map(
dout => ch_bus,
ain => a2d_ana_in,
clk => XSIG010190,
start => start_a2d1,
eoc => XSIG010091,
oe => XSIG010196
);
tdm_enc1 : entity work.tdm_encoder
port map(
clk => clk_6K,
p2s_oe => p2s_oe,
tdm_out => dig_in,
p2s_load => p2s_load,
a2d_data => ch_bus,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
p2s_clr => p2s_clr
);
menc_rsc3 : entity work.menc_rsc(bhv)
port map(
dig_in => dig_in,
clk => clk_6K,
reset => reset_m,
bit_out => tdm_out
);
XCMP90 : entity work.clock_duty(ideal)
generic map(
off_time => 19.98 sec
)
port map(
CLOCK_OUT => reset_m
);
end Digitize_Encode_Man;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input AND gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY and2;
ARCHITECTURE ideal OF and2 IS
BEGIN
output <= in1 AND in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- D Flip Flop with reset (negative edge triggered)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d_latch_n_edge_rst IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
data, clk : IN std_logic;
q : OUT std_logic := '0';
qn : OUT std_logic := '1';
rst : IN std_logic := '0'); -- reset
END ENTITY d_latch_n_edge_rst ;
ARCHITECTURE behav OF d_latch_n_edge_rst IS
BEGIN
data_in : PROCESS(clk, rst) IS
BEGIN
IF clk = '0' AND clk'event AND rst /= '1' THEN
q <= data AFTER delay;
qn <= NOT data AFTER delay;
ELSIF rst = '1' THEN
q <= '0';
qn <= '1';
END IF;
END PROCESS data_in; -- End of process data_in
END ARCHITECTURE behav;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity counter_12 is
port(
cnt : out std_logic_vector(0 to 11);
reset : in std_logic;
enable : in std_logic;
clk : in std_logic
);
end counter_12;
architecture counter_12 of counter_12 is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
signal XSIG010078 : std_logic;
signal XSIG010081 : std_logic;
signal XSIG010083 : std_logic;
signal XSIG010085 : std_logic;
signal XSIG010087 : std_logic;
signal XSIG010101 : std_logic;
signal XSIG010102 : std_logic;
signal XSIG010103 : std_logic;
signal XSIG010104 : std_logic;
signal XSIG010115 : std_logic;
signal XSIG010116 : std_logic;
signal XSIG010117 : std_logic;
signal XSIG010132 : std_logic;
begin
-- Signal assignments
cnt(0) <= cdb2vhdl_tmp_1(0);
cnt(1) <= cdb2vhdl_tmp_1(1);
cnt(2) <= cdb2vhdl_tmp_1(2);
cnt(3) <= cdb2vhdl_tmp_1(3);
cnt(4) <= cdb2vhdl_tmp_1(4);
cnt(5) <= cdb2vhdl_tmp_1(5);
cnt(6) <= cdb2vhdl_tmp_1(6);
cnt(7) <= cdb2vhdl_tmp_1(7);
cnt(8) <= cdb2vhdl_tmp_1(8);
cnt(9) <= cdb2vhdl_tmp_1(9);
cnt(10) <= cdb2vhdl_tmp_1(10);
cnt(11) <= cdb2vhdl_tmp_1(11);
-- Component instances
XCMP92 : entity work.and2(ideal)
port map(
in1 => clk,
in2 => enable,
output => XSIG010132
);
XCMP93 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => XSIG010132,
DATA => XSIG010078,
QN => XSIG010078,
Q => cdb2vhdl_tmp_1(0),
RST => reset
);
XCMP94 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(0),
DATA => XSIG010081,
QN => XSIG010081,
Q => cdb2vhdl_tmp_1(1),
RST => reset
);
XCMP95 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(1),
DATA => XSIG010083,
QN => XSIG010083,
Q => cdb2vhdl_tmp_1(2),
RST => reset
);
XCMP96 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(2),
DATA => XSIG010085,
QN => XSIG010085,
Q => cdb2vhdl_tmp_1(3),
RST => reset
);
XCMP97 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(3),
DATA => XSIG010087,
QN => XSIG010087,
Q => cdb2vhdl_tmp_1(4),
RST => reset
);
XCMP98 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(4),
DATA => XSIG010101,
QN => XSIG010101,
Q => cdb2vhdl_tmp_1(5),
RST => reset
);
XCMP99 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(5),
DATA => XSIG010102,
QN => XSIG010102,
Q => cdb2vhdl_tmp_1(6),
RST => reset
);
XCMP100 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(6),
DATA => XSIG010103,
QN => XSIG010103,
Q => cdb2vhdl_tmp_1(7),
RST => reset
);
XCMP101 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(7),
DATA => XSIG010104,
QN => XSIG010104,
Q => cdb2vhdl_tmp_1(8),
RST => reset
);
XCMP102 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(8),
DATA => XSIG010115,
QN => XSIG010115,
Q => cdb2vhdl_tmp_1(9),
RST => reset
);
XCMP103 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(9),
DATA => XSIG010116,
QN => XSIG010116,
Q => cdb2vhdl_tmp_1(10),
RST => reset
);
XCMP104 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(10),
DATA => XSIG010117,
QN => XSIG010117,
Q => cdb2vhdl_tmp_1(11),
RST => reset
);
end counter_12;
--
-- 12-bit digital comparator model
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity dig_cmp is
port
(
eq : out std_logic := '0';
in1 : in std_logic_vector (0 to 11);
in2 : in std_logic_vector (0 to 11);
latch_in1 : in std_logic := '0'; -- Currently unused
latch_in2 : in std_logic := '0';
cmp : in std_logic := '0';
clk : in std_logic
);
end entity dig_cmp ;
architecture simple of dig_cmp is
begin
compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
BEGIN
if latch_in2 = '1' then -- in2 data is latched and stored
in2_hold := in2;
end if;
if cmp = '1' then
if in1 = in2_hold then -- latched in2 checked against current in1
eq <= '0';
else eq <= '1';
end if;
end if;
END PROCESS;
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Digital clock with 50% duty cycle and enable pin
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock_en IS
GENERIC (
pw : time); -- Clock pulse width
PORT (
enable : IN std_logic ;
clock_out : INOUT std_logic := '0');
END ENTITY clock_en;
ARCHITECTURE ideal OF clock_en IS
BEGIN
-- clock process
process (clock_out, enable) is
begin
if clock_out = '0' AND enable = '1' THEN
clock_out <= '1' after pw, '0' after 2*pw;
end if;
end process;
END ARCHITECTURE ideal;
--
-- Set/reset flip flop
-- When S goes high, Q is set high until reset
-- When R goes high, Q is set low until set
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sr_ff is
port
(
S : in std_logic ;
R : in std_logic ;
Q : out std_logic
);
end sr_ff ;
architecture simple of sr_ff is
begin
set_reset: PROCESS(S, R) IS
BEGIN
-- assert S='1' nand R='1' -- Warning if both inputs are high
-- report "S and R are both active. Use with caution"
-- severity warning;
if S'event AND S = '1' then
Q <= '1';
end if;
if R'event AND R = '1' then
Q <= '0';
end if;
END PROCESS set_reset;
end;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Inverter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY inverter IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
output : OUT std_logic);
END ENTITY inverter;
ARCHITECTURE ideal OF inverter IS
BEGIN
output <= NOT input AFTER delay;
END ARCHITECTURE ideal;
--
--//////////////////////////////////////////////////////////////////
-- NOTE: This is an intermediate file for HDL inspection only.
-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg.
-- Generated by sde2hdl version 16.1.0.2
--//////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach_rcvr IS
PORT (
clk_50 : IN std_logic;
clk_100k : IN std_logic;
ser_done : IN std_logic;
par_det : IN std_logic;
frm_det : IN std_logic;
clk_6k : IN std_logic;
start_pulse : IN std_logic;
dly_done : IN std_logic;
s2p_rst : OUT std_logic;
s2p_en : OUT std_logic;
cnt1_en : OUT std_logic;
cnt1_rst : OUT std_logic;
cmp1_ltch1 : OUT std_logic;
cmp1_ltch2 : OUT std_logic;
cnt2_en : OUT std_logic;
cnt2_rst : OUT std_logic;
cmp2_ltch1 : OUT std_logic;
cmp2_ltch2 : OUT std_logic;
da_latch : OUT std_logic;
ser_cnt : OUT std_logic;
dly_cnt : OUT std_logic;
par_oe : OUT std_logic);
END state_mach_rcvr;
ARCHITECTURE state_diagram OF state_mach_rcvr IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
, s_bit, par1, par2);
SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
BEGIN
sm1:
PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
BEGIN
CASE CS_state_mach_rcvr_sm1 IS
WHEN V_begin =>
cnt1_en <= ('0');
cnt1_rst <= ('1');
cmp1_ltch1 <= ('0');
cmp1_ltch2 <= ('0');
cnt2_en <= ('0');
cnt2_rst <= ('1');
cmp2_ltch1 <= ('0');
cmp2_ltch2 <= ('0');
s2p_en <= ('1');
s2p_rst <= ('0');
da_latch <= ('0');
ser_cnt <= ('0');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((frm_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= s_bit;
ELSE
NS_state_mach_rcvr_sm1 <= V_begin;
END IF;
WHEN cnt =>
ser_cnt <= ('1');
cnt1_rst <= ('0');
cnt2_rst <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par1;
ELSE
NS_state_mach_rcvr_sm1 <= cnt;
END IF;
WHEN ch1 =>
cmp1_ltch2 <= ('1');
ser_cnt <= ('0');
dly_cnt <= ('1');
IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= ch1;
END IF;
WHEN rst1 =>
cmp1_ltch2 <= ('0');
ser_cnt <= ('1');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par2;
ELSE
NS_state_mach_rcvr_sm1 <= rst1;
END IF;
WHEN ch2 =>
cmp2_ltch2 <= ('1');
ser_cnt <= ('0');
da_latch <= ('1');
NS_state_mach_rcvr_sm1 <= rst2;
WHEN rst2 =>
cmp2_ltch2 <= ('0');
s2p_en <= ('0');
par_oe <= ('0');
da_latch <= ('0');
NS_state_mach_rcvr_sm1 <= cnt_cmp;
WHEN cnt_cmp =>
cnt1_en <= ('1');
cmp1_ltch1 <= ('1');
cnt2_en <= ('1');
cmp2_ltch1 <= ('1');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN rst_cnt =>
cnt1_en <= ('0');
cmp1_ltch1 <= ('0');
cnt2_en <= ('0');
cmp2_ltch1 <= ('0');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN s_bit =>
IF ((start_pulse = '1')) THEN
NS_state_mach_rcvr_sm1 <= cnt;
ELSE
NS_state_mach_rcvr_sm1 <= s_bit;
END IF;
WHEN par1 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch1;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= par1;
END IF;
WHEN par2 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch2;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst2;
ELSE
NS_state_mach_rcvr_sm1 <= par2;
END IF;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach_rcvr_sm1 <= V_begin;
ELSE
CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt_rcvr is
port(
cmp1_ltch1 : out std_logic;
cmp2_ltch1 : out std_logic;
s2p_en : out std_logic;
s2p_rst : out std_logic;
frm_det : in std_logic;
par_det : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
clk_50 : in std_logic;
start_pulse : in std_logic;
cnt1_en : out std_logic;
cnt1_rst : out std_logic;
cmp1_ltch2 : out std_logic;
cnt2_en : out std_logic;
cnt2_rst : out std_logic;
cmp2_ltch2 : out std_logic;
da_latch : out std_logic;
par_oe : out std_logic
);
end sm_cnt_rcvr;
architecture sm_cnt_rcvr of sm_cnt_rcvr is
-- Component declarations
-- Signal declarations
terminal dly_cnt_a : electrical;
terminal dly_done_a : electrical;
terminal ser_cnt_a : electrical;
terminal ser_done_a : electrical;
signal XSIG010001 : std_logic;
signal XSIG010002 : std_logic;
signal XSIG010145 : std_logic;
signal XSIG010146 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.d2a_bit(ideal)
port map(
D => XSIG010001,
A => ser_cnt_a
);
XCMP2 : entity work.d2a_bit(ideal)
port map(
D => XSIG010002,
A => ser_done_a
);
bit_cnt3 : entity work.bit_cnt(behavioral)
generic map(
count => 2
)
port map(
bit_in => XSIG010145,
clk => clk_6k,
dly_out => XSIG010146
);
bit_cnt4 : entity work.bit_cnt(behavioral)
generic map(
count => 10
)
port map(
bit_in => XSIG010001,
clk => clk_6k,
dly_out => XSIG010002
);
XCMP8 : entity work.d2a_bit(ideal)
port map(
D => XSIG010145,
A => dly_cnt_a
);
XCMP9 : entity work.d2a_bit(ideal)
port map(
D => XSIG010146,
A => dly_done_a
);
state_mach_rcvr8 : entity work.state_mach_rcvr
port map(
clk_100k => clk_100k,
clk_50 => clk_50,
s2p_rst => s2p_rst,
s2p_en => s2p_en,
cnt1_en => cnt1_en,
cnt1_rst => cnt1_rst,
cmp1_ltch1 => cmp1_ltch1,
cmp1_ltch2 => cmp1_ltch2,
cnt2_en => cnt2_en,
cnt2_rst => cnt2_rst,
cmp2_ltch1 => cmp2_ltch1,
cmp2_ltch2 => cmp2_ltch2,
da_latch => da_latch,
ser_cnt => XSIG010001,
ser_done => XSIG010002,
par_det => par_det,
frm_det => frm_det,
clk_6k => clk_6k,
start_pulse => start_pulse,
dly_done => XSIG010146,
dly_cnt => XSIG010145,
par_oe => par_oe
);
end sm_cnt_rcvr;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- level_set.vhd
-- Set digital output "level" with parameter "logic_val" (default is '1')
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set IS
GENERIC (
logic_val : std_logic := '1');
PORT (
level : OUT std_logic);
END ENTITY level_set;
-- Simple architecture
ARCHITECTURE ideal OF level_set IS
BEGIN
level <= logic_val;
END ARCHITECTURE ideal;
--
-- Serial to parallel data converter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity ser2par is
port
(
par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
clk : in std_logic ;
load_en : in std_logic ;
ser_in : in std_logic ;
reset : in std_logic
);
begin
end ser2par;
architecture a1 of ser2par is
BEGIN
sr_sm: PROCESS (load_en, clk, reset, ser_in)
BEGIN
if (reset = '1' and load_en = '1') then
par_out <= "000000000000"; -- Reset the parallel data out
elsif (clk'event and clk = '1') then
if (load_en ='1') then
-- The register will shift when load is enabled
-- and will shift at rising edge of clock
par_out(0) <= ser_in; -- Input data shifts into bit 0
par_out(1) <= par_out(0);
par_out(2) <= par_out(1);
par_out(3) <= par_out(2);
par_out(4) <= par_out(3);
par_out(5) <= par_out(4);
par_out(6) <= par_out(5);
par_out(7) <= par_out(6);
par_out(8) <= par_out(7);
par_out(9) <= par_out(8);
par_out(10) <= par_out(9);
par_out(11) <= par_out(10);
else
-- The otput data will not change
-- if load_en is not enabled
par_out <= "ZZZZZZZZZZZZ";
end if;
end if;
END PROCESS;
end;
--
-- This model ouputs a '1' when a specific bit pattern is encountered
-- Otherwise, it outputs a zero
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_det is
port
(
bus_in : in std_logic_vector (0 to 11);
clk : in std_logic;
frm_bit : out std_logic := '0' -- Initialize output to zero
);
end entity frame_det;
architecture simple of frame_det is
begin
enbl: PROCESS (bus_in, clk) -- Sensitivity list
BEGIN
if bus_in = "010101010101" then -- This is the pre-defined bit pattern
if clk'event AND clk = '0' then -- Output updated synchronously
frm_bit <= '1';
end if;
else frm_bit <= '0';
end if;
END PROCESS;
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_det is
port(
bus_in : in std_logic_vector(0 to 11);
par_bit : out std_logic;
oe : in std_logic
);
end parity_det;
architecture parity_det of parity_det is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic;
terminal par_bit_a : electrical;
signal XSIG010010 : std_logic;
signal XSIG010011 : std_logic;
signal XSIG010012 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010014 : std_logic;
signal XSIG010015 : std_logic;
signal XSIG010016 : std_logic;
signal XSIG010017 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010057 : std_logic;
begin
-- Signal assignments
par_bit <= cdb2vhdl_tmp_1;
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => bus_in(1),
in2 => bus_in(2),
output => XSIG010010
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => bus_in(3),
in2 => bus_in(4),
output => XSIG010011
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => bus_in(5),
in2 => bus_in(6),
output => XSIG010012
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => bus_in(7),
in2 => bus_in(8),
output => XSIG010013
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => bus_in(9),
in2 => bus_in(10),
output => XSIG010016
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010010,
in2 => XSIG010011,
output => XSIG010014
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010012,
in2 => XSIG010013,
output => XSIG010015
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010014,
in2 => XSIG010015,
output => XSIG010017
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010017,
in2 => XSIG010016,
output => XSIG010019
);
XCMP10 : entity work.xor2(ideal)
port map(
in1 => XSIG010019,
in2 => bus_in(0),
output => XSIG010057
);
XCMP11 : entity work.d2a_bit(ideal)
port map(
D => cdb2vhdl_tmp_1,
A => par_bit_a
);
XCMP12 : entity work.and2(ideal)
port map(
in1 => oe,
in2 => XSIG010057,
output => cdb2vhdl_tmp_1
);
end parity_det;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY d2a_nbit IS
GENERIC (
vmax : real := 5.0; -- High output
vmin : real := 0.0; -- Low output
high_bit : integer := 9; -- High end of bit range for D/A
low_bit : integer := 0); -- Low end of bit range for D/A
PORT (
SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
SIGNAL latch : IN STD_LOGIC;
TERMINAL ana_out : electrical); -- analog output
END ENTITY d2a_nbit ;
ARCHITECTURE behavioral OF d2a_nbit IS
SIGNAL sout : real := 0.0;
QUANTITY vout across iout through ana_out TO electrical_ref;
BEGIN -- ARCHITECTURE behavioral
proc : PROCESS
VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
VARIABLE delt_v : real; -- Represents the voltage value of each bit
BEGIN
WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
v_sum := vmin;
delt_v := vmax - vmin;
FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
delt_v := delt_v / 2.0;
IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
v_sum := v_sum + delt_v;
END IF;
END LOOP;
sout <= v_sum;
END PROCESS;
vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
END ARCHITECTURE behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TDM_Demux_dbg is
port(
s2p_en : in std_logic;
tdm_in : in std_logic;
clk_6k : in std_logic;
s2p_rst : in std_logic;
par_det : out std_logic;
frm_det : out std_logic;
da_latch : in std_logic;
par_oe : in std_logic;
data_bus : out std_logic_vector(1 to 10);
start_bit : out std_logic
);
end TDM_Demux_dbg;
architecture TDM_Demux_dbg of TDM_Demux_dbg is
-- Component declarations
-- Signal declarations
terminal d2a_out : electrical;
signal rcvr_bus : std_logic_vector(0 to 11);
begin
-- Signal assignments
data_bus(1) <= rcvr_bus(1);
data_bus(2) <= rcvr_bus(2);
data_bus(3) <= rcvr_bus(3);
data_bus(4) <= rcvr_bus(4);
data_bus(5) <= rcvr_bus(5);
data_bus(6) <= rcvr_bus(6);
data_bus(7) <= rcvr_bus(7);
data_bus(8) <= rcvr_bus(8);
data_bus(9) <= rcvr_bus(9);
data_bus(10) <= rcvr_bus(10);
start_bit <= rcvr_bus(0);
-- Component instances
s2p1 : entity work.ser2par(a1)
port map(
par_out => rcvr_bus,
clk => clk_6k,
load_en => s2p_en,
ser_in => tdm_in,
reset => s2p_rst
);
frm_det1 : entity work.frame_det(simple)
port map(
bus_in => rcvr_bus,
frm_bit => frm_det,
clk => clk_6k
);
par_det1 : entity work.parity_det
port map(
bus_in => rcvr_bus,
par_bit => par_det,
oe => par_oe
);
XCMP113 : entity work.d2a_nbit(behavioral)
generic map(
low_bit => 1,
high_bit => 10,
vmax => 4.8
)
port map(
bus_in => rcvr_bus(1 to 10),
ana_out => d2a_out,
latch => da_latch
);
end TDM_Demux_dbg;
--
-- Manchester Decoder with clock recovery using 8x referenced clock
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mdec_rsc is
-- port ( din: in real; -- real input
port ( din: in std_logic; -- real input
clk16x: in std_logic; -- 16x referenced clock
reset: in std_logic; -- not reset
bout: out std_logic := '0'; -- digital output
clk_out: inout std_logic := '0'); -- recovered clock
end entity mdec_rsc;
architecture bhv of mdec_rsc is
-- signal bhigh:real:= 1.0; -- bit decoding
-- signal blow:real:= -1.0; -- bit decoding
-- signal bnormal:real:=0.0; -- bit decoding
signal bhigh:std_logic:= '1'; -- bit decoding
signal blow:std_logic:= '0'; -- bit decoding
signal bout1:std_logic;
signal clk_div:std_logic_vector(3 downto 0):="0000"; -- clock counter
signal trans:std_logic; -- transisition trigger
begin
-- bit decoding
proc1: process (reset,din,clk16x)
begin
if (reset = '1') then
bout1 <= 'X';
elsif (clk16x'event and clk16x = '1') then
if (din = bhigh) then
bout1 <= '1';
elsif (din = blow) then
bout1 <= '0';
else
bout1 <= 'X';
end if;
end if;
end process;
-- clock counter
proc2: process (reset, clk16x, clk_div)
begin
if (reset = '1') then
clk_div <= "0000";
elsif (clk16x'event and clk16x = '1') then
clk_div <= clk_div + "0001";
end if;
end process;
-- recovered clock
-- clk_out <= not clk_div(3);
clk_out <= clk_div(3);
-- transition trigger
trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or
(clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0)));
-- Manchester decoder
proc3: process (reset, trans, bout1, clk_out, clk16x)
begin
if (reset = '1') then
bout <= '0';
elsif (clk16x'event and clk16x = '1') then
if (trans = '1') then
bout <= bout1 XOR clk_out;
end if;
end if;
end process;
end architecture bhv;
architecture bhv_8 of mdec_rsc is
-- signal bhigh:real:= 1.0; -- bit decoding
-- signal blow:real:= -1.0; -- bit decoding
-- signal bnormal:real:=0.0; -- bit decoding
signal bhigh:std_logic:= '1'; -- bit decoding
signal blow:std_logic:= '0'; -- bit decoding
signal bout1:std_logic;
signal clk_div:std_logic_vector(2 downto 0):="000"; -- clock counter
signal trans:std_logic; -- transisition trigger
begin
-- bit decoding
proc1: process (reset,din,clk16x)
begin
if (reset = '1') then
bout1 <= 'X';
elsif (clk16x'event and clk16x = '1') then
if (din = bhigh) then
bout1 <= '1';
elsif (din = blow) then
bout1 <= '0';
else
bout1 <= 'X';
end if;
end if;
end process;
-- clock counter
proc2: process (reset, clk16x, clk_div)
begin
if (reset = '1') then
clk_div <= "000";
elsif (clk16x'event and clk16x = '1') then
clk_div <= clk_div + "001";
end if;
end process;
-- recovered clock
clk_out <= not clk_div(2);
-- transition trigger
trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0)));
-- Manchester decoder
proc3: process (reset, trans, bout1, clk_out, clk16x)
begin
if (reset = '1') then
bout <= '0';
elsif (clk16x'event and clk16x = '1') then
if (trans = '1') then
bout <= bout1 XOR clk_out;
end if;
end if;
end process;
end architecture bhv_8;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Decode_PW_Man is
port(
terminal power : electrical;
terminal ch1_pw : electrical;
terminal ch2_pw : electrical;
bit_stream_in : in std_logic
);
end Decode_PW_Man;
architecture Decode_PW_Man of Decode_PW_Man is
-- Component declarations
-- Signal declarations
signal bit_stream_in_mdec : std_logic;
signal clk16x : std_logic;
signal clk6k : std_logic;
signal clk_100k : std_logic;
signal cmp_bus : std_logic_vector(0 to 11);
signal cnt1 : std_logic_vector(0 to 11);
signal cnt2 : std_logic_vector(0 to 11);
signal mdec_clk : std_logic;
signal mdec_out : std_logic;
signal reset : std_logic;
signal reset_m : std_logic;
signal XSIG010228 : std_logic;
signal XSIG010229 : std_logic;
signal XSIG010256 : std_logic;
signal XSIG010263 : std_logic;
signal XSIG010264 : std_logic;
signal XSIG010266 : std_logic;
signal XSIG010267 : std_logic;
signal XSIG010268 : std_logic;
signal XSIG010320 : std_logic;
signal XSIG010330 : std_logic;
signal XSIG010334 : std_logic;
signal XSIG010339 : std_logic;
signal XSIG010349 : std_logic;
signal XSIG010357 : std_logic;
signal XSIG010371 : std_logic;
signal XSIG010372 : std_logic;
signal XSIG010373 : std_logic;
signal XSIG010383 : std_logic;
signal XSIG010384 : std_logic;
signal XSIG010385 : std_logic;
signal XSIG010386 : std_logic;
signal XSIG010390 : std_logic;
signal XSIG010433 : std_logic;
begin
-- Signal assignments
bit_stream_in_mdec <= bit_stream_in;
-- Component instances
cntr1 : entity work.counter_12
port map(
enable => XSIG010384,
cnt => cnt1,
reset => XSIG010357,
clk => XSIG010433
);
cntr2 : entity work.counter_12
port map(
enable => XSIG010349,
cnt => cnt2,
reset => XSIG010385,
clk => XSIG010320
);
cmp1 : entity work.dig_cmp(simple)
port map(
in1 => cnt1,
eq => XSIG010371,
clk => XSIG010433,
in2 => cmp_bus,
cmp => XSIG010384,
latch_in1 => XSIG010256,
latch_in2 => XSIG010383
);
cmp2 : entity work.dig_cmp(simple)
port map(
in1 => cnt2,
eq => XSIG010372,
clk => XSIG010320,
in2 => cmp_bus,
cmp => XSIG010349,
latch_in1 => XSIG010263,
latch_in2 => XSIG010264
);
XCMP109 : entity work.resistor(ideal)
generic map(
res => 1000000.0
)
port map(
p1 => power,
p2 => ELECTRICAL_REF
);
clk_1M2 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010320,
enable => XSIG010349
);
clk_1M1 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010433,
enable => XSIG010384
);
XCMP134 : entity work.d2a_bit(ideal)
port map(
D => XSIG010371,
A => ch1_pw
);
XCMP135 : entity work.d2a_bit(ideal)
port map(
D => XSIG010372,
A => ch2_pw
);
XCMP137 : entity work.SR_FF(simple)
port map(
S => XSIG010330,
R => XSIG010334,
Q => XSIG010349
);
XCMP138 : entity work.inverter(ideal)
port map(
input => XSIG010372,
output => XSIG010334
);
XCMP139 : entity work.SR_FF(simple)
port map(
S => XSIG010373,
R => XSIG010339,
Q => XSIG010384
);
XCMP140 : entity work.inverter(ideal)
port map(
input => XSIG010371,
output => XSIG010339
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => reset,
clk_6K => clk6k,
clk_100k => clk_100k
);
sm_rcvr1 : entity work.sm_cnt_rcvr
port map(
cnt1_en => XSIG010373,
cmp1_ltch1 => XSIG010256,
cnt2_rst => XSIG010385,
clk_100k => clk_100k,
cnt1_rst => XSIG010357,
cnt2_en => XSIG010330,
cmp2_ltch1 => XSIG010263,
frm_det => XSIG010229,
par_det => XSIG010228,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
clk_6k => mdec_clk,
clk_50 => reset,
da_latch => XSIG010268,
cmp1_ltch2 => XSIG010383,
cmp2_ltch2 => XSIG010264,
start_pulse => XSIG010390,
par_oe => XSIG010386
);
XCMP155 : entity work.level_set(ideal)
generic map(
logic_val => '0'
)
port map(
level => cmp_bus(11)
);
XCMP157 : entity work.TDM_Demux_dbg
port map(
data_bus => cmp_bus(0 to 9),
tdm_in => mdec_out,
clk_6k => mdec_clk,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
da_latch => XSIG010268,
frm_det => XSIG010229,
par_det => XSIG010228,
par_oe => XSIG010386,
start_bit => XSIG010390
);
XCMP172 : entity work.level_set(ideal)
generic map(
logic_val => '1'
)
port map(
level => cmp_bus(10)
);
clock1 : entity work.clock(ideal)
generic map(
period => 9.375us
)
port map(
CLK_OUT => clk16x
);
mdec_rsc7 : entity work.mdec_rsc(bhv)
port map(
din => bit_stream_in_mdec,
clk16x => clk16x,
reset => reset_m,
bout => mdec_out,
clk_out => mdec_clk
);
XCMP181 : entity work.clock_duty(ideal)
generic map(
off_time => 19.98 sec
)
port map(
CLOCK_OUT => reset_m
);
end Decode_PW_Man;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lpf_2_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (pole)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_2_e;
architecture simple of lpf_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
-- constant num : real := k;
constant num : real_vector := (0 => w1*w2*k); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (w1*w2, w1+w2, 1.0);
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- ideal one bit A/D converter
LIBRARY IEEE;
USE IEEE.math_real.ALL;
USE IEEE.std_logic_1164.ALL;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY a2d_bit IS
GENERIC (
thres : real := 2.5); -- Threshold to determine logic output
PORT (
TERMINAL a : electrical; -- analog input
SIGNAL d : OUT std_logic); -- digital (std_logic) output
END ENTITY a2d_bit;
ARCHITECTURE ideal OF a2d_bit IS
QUANTITY vin ACROSS a;
BEGIN -- threshold
-- Process needed to detect threshold crossing and assign output (d)
PROCESS (vin'ABOVE(thres)) IS
BEGIN -- PROCESS
IF vin'ABOVE(thres) THEN
d <= '1';
ELSE
d <= '0';
END IF;
END PROCESS;
END ideal;
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input OR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY or2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY or2;
ARCHITECTURE ideal OF or2 IS
BEGIN
output <= in1 OR in2 AFTER delay;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pw2ana is
port(
terminal ana_out : electrical;
terminal pw_in : electrical
);
end pw2ana;
architecture pw2ana of pw2ana is
-- Component declarations
-- Signal declarations
signal bus_servo : std_logic_vector(0 to 11);
signal XSIG010008 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010020 : std_logic;
signal XSIG010021 : std_logic;
signal XSIG010022 : std_logic;
begin
-- Signal assignments
-- Component instances
counter_rudder : entity work.counter_12
port map(
enable => XSIG010022,
cnt => bus_servo,
reset => XSIG010021,
clk => XSIG010008
);
XCMP3 : entity work.a2d_bit(ideal)
port map(
D => XSIG010022,
A => pw_in
);
clk_en_rudder : entity work.clock_en(ideal)
generic map(
pw => 500ns
)
port map(
CLOCK_OUT => XSIG010008,
enable => XSIG010022
);
XCMP5 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010022,
output => XSIG010013
);
XCMP8 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010020,
output => XSIG010021
);
XCMP9 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010022,
output => XSIG010019
);
or_rudder : entity work.or2(ideal)
port map(
in1 => XSIG010022,
in2 => XSIG010019,
output => XSIG010020
);
XCMP11 : entity work.d2a_nbit(behavioral)
generic map(
vmax => 4.8,
high_bit => 9,
low_bit => 0
)
port map(
bus_in => bus_servo,
ana_out => ana_out,
latch => XSIG010013
);
end pw2ana;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library ieee;
use ieee.math_real.all;
package pwl_functions is
-- This function returns the incremental value to the next element in a real vector
function next_increment(x : in real; xdata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real;
function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
return real;
end package pwl_functions;
package body pwl_functions is
function next_increment(x : in real; xdata : in real_vector)
return real is
variable i : integer;
begin
i := 0;
while i <= xdata'right loop
if x >= xdata(i) - 6.0e-15 then -- The value 6.0e-15 envelopes round-off error
-- of real-to-time conversion in calling model
i := i + 1;
else
return xdata(i) - xdata(i - 1);
end if;
end loop;
return 1.0; -- Returns a "large number" relative to expected High-Speed time scale
end function next_increment;
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "extrapolate: x1 cannot be equal to x2"
severity error;
assert (x <= x1) or (x >= x2)
report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
severity warning;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function extrapolate;
-- Created a new pwl_dim1_flat function that returns a constant
-- value of ydata(0) if x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right)
function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x >= xdata(xdata'right) then
yvalue := ydata(ydata'right);
return yvalue;
end if;
if x <= xdata(0) then
yvalue := ydata(0);
return yvalue;
end if;
start:=0;
fin:=xdata'right;
-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
-- so fin==n-1 in C terms (where n is the size of the array).
while start <=fin loop
mid:=(start+fin)/2;
if xdata(mid) < x
then start:=mid+1;
else fin:=mid-1;
end if;
end loop;
if xdata(mid) > x
then mid:=mid-1;
end if;
yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
return yvalue;
end function pwl_dim1_flat;
end package body pwl_functions;
-- Not sure the sync_tdata process is necessary. Requires the tdata set contain
-- a larger value than the actual simulation time.
-- Piece-wise linear voltage source model
library IEEE; use IEEE.std_logic_1164.all;
Library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
use work.pwl_functions.all;
entity v_pwl is
generic (
vdata : real_vector; -- v-pulse data
tdata : real_vector -- time-data for v-pulse
);
port (
terminal pos, neg : electrical
);
end entity v_pwl;
architecture ideal of v_pwl is
QUANTITY v across i through pos TO neg;
signal tick : std_logic := '0'; -- Sync signal for tdata "tracking"
begin
sync_tdata: process is
variable next_tick_delay : real := 0.0; -- Time increment to the next time-point in tdata
begin
wait until domain = time_domain;
loop
next_tick_delay := next_increment(NOW,tdata);
tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs);
wait on tick;
end loop;
end process sync_tdata;
break on tick; -- Forces analog solution point at all tdata time-points
v == pwl_dim1_flat(NOW, tdata, vdata);
end architecture ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity plane_pos_src is
port(
terminal plane_pos : electrical;
terminal rudder_fb : electrical
);
end plane_pos_src;
architecture plane_pos_src of plane_pos_src is
-- Component declarations
-- Signal declarations
terminal flight_deviation : electrical;
terminal plane_sum_out : electrical;
terminal wind : electrical;
terminal wind_neg : electrical;
terminal XSIG010020 : electrical;
begin
-- Signal assignments
-- Component instances
sum1 : entity work.sum2_e(simple)
generic map(
k1 => 1.0
)
port map(
in1 => wind,
in2 => rudder_fb,
output => plane_sum_out
);
dir_out : entity work.gain_e(simple)
generic map(
k => -1.0
)
port map(
input => plane_sum_out,
output => plane_pos
);
wind_neg_gain : entity work.gain_e(simple)
generic map(
k => -1.0
)
port map(
input => wind,
output => wind_neg
);
sum2 : entity work.sum2_e(simple)
generic map(
k2 => 1.89,
k1 => 1.0
)
port map(
in1 => wind,
in2 => rudder_fb,
output => flight_deviation
);
R2 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => XSIG010020
);
v3 : entity work.v_pulse(ideal)
generic map(
period => 3 sec,
width => 100 ms,
delay => 100 ms,
tp2i => 1 sec,
ti2p => 1 sec,
pulse => -4.8,
initial => 0.0
)
port map(
pos => XSIG010020,
neg => ELECTRICAL_REF
);
PWL_Wind : entity work.v_pwl(ideal)
generic map(
tdata => (0.0,100.0e-3,110.0e-3,500.0e-3,510.0e-3,800.0e-3, 810.0e-3),
vdata => (0.0,0.0,-2.4,-2.4,-4.7,-4.7,0.0)
)
port map(
pos => wind,
neg => ELECTRICAL_REF
);
end plane_pos_src;
--
-------------------------------------------------------------------------------
-- Integrator
--
-- Transfer Function:
--
-- k
-- H(s) = ---------
-- s
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity integ_1_e is
generic (
k: real := 1.0; -- Gain
-- init: real := real'low); -- Initial value of output
init: real := 0.0); -- Initial value of output
port (terminal input: electrical;
terminal output: electrical);
end entity integ_1_e;
architecture simple of integ_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
begin
vin_temp == vin;
-- IF domain = QUIESCENT_DOMAIN AND init /= real'low USE
IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
vout == init;
ELSE
vout == k*vin_temp'INTEG;
END USE;
end architecture simple;
--
-------------------------------------------------------------------------------
-- First Order Lowpass filter
--
-- Transfer Function:
--
-- w1
-- H(s) = k * -----------
-- s + w1
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lpf_1_e is
generic (
fp : real; -- pole freq in Hertz
gain : real := 1.0); -- filter gain
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_1_e;
architecture simple of lpf_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant wp : real := math_2_pi*fp;
constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (wp, 1.0);
quantity vin_temp : real;
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity hcl is
port(
terminal output : electrical;
terminal plane_pos : electrical
);
end hcl;
architecture hcl of hcl is
-- Component declarations
-- Signal declarations
terminal hcl_err_in : electrical;
terminal heading : electrical;
terminal XSIG010001 : electrical;
terminal XSIG010002 : electrical;
terminal XSIG010003 : electrical;
begin
-- Signal assignments
-- Component instances
prop_gain : entity work.gain_e(simple)
generic map(
k => 1.0
)
port map(
input => hcl_err_in,
output => XSIG010002
);
integ : entity work.integ_1_e(simple)
generic map(
init => 0.0,
k => 0.1
)
port map(
input => hcl_err_in,
output => XSIG010003
);
lowpass : entity work.lpf_1_e(simple)
generic map(
fp => 4.0
)
port map(
input => XSIG010001,
output => output
);
sum2 : entity work.sum2_e(simple)
port map(
in1 => XSIG010002,
in2 => XSIG010003,
output => XSIG010001
);
set_src : entity work.v_constant(ideal)
generic map(
level => 0.0
)
port map(
pos => heading,
neg => ELECTRICAL_REF
);
sum1 : entity work.sum2_e(simple)
port map(
in1 => heading,
in2 => plane_pos,
output => hcl_err_in
);
end hcl;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS5_HCL is
end tb_CS5_HCL;
architecture TB_CS5_HCL of tb_CS5_HCL is
-- Component declarations
-- Signal declarations
signal bitstream1 : std_logic;
signal bitstream2 : std_logic;
terminal ch1_in : electrical;
terminal ch1_pw_out : electrical;
terminal ch2_in : electrical;
terminal ch2_pw_out : electrical;
terminal gear_hrn_out : translational;
terminal gear_in : rotational_v;
terminal gear_out : rotational;
terminal mtr_in : electrical;
terminal plane_dir : electrical;
terminal prop_in : electrical;
terminal rot2v_out : electrical;
terminal rudder : rotational;
terminal rudder_fb : electrical;
terminal rudder_hrn_in : translational;
terminal servo_fltr_in : electrical;
terminal servo_in : electrical;
terminal XSIG010018 : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => mtr_in,
servo_in => servo_in,
pos_fb => rot2v_out
);
gear1 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => gear_in,
rot2 => gear_out
);
potentiometer1 : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => rot2v_out,
input => gear_out
);
gear_horn : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => gear_hrn_out
);
rudder_horn : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => rudder_hrn_in
);
motor1 : entity work.DC_Motor(basic)
generic map(
j => 168.0e-9,
d => 5.63e-6,
l => 2.03e-3,
kt => 3.43e-3,
r_wind => 2.2
)
port map(
p1 => mtr_in,
p2 => ELECTRICAL_REF,
shaft_rotv => gear_in
);
stop1 : entity work.stop_r(ideal)
generic map(
ang_min => -1.05,
ang_max => 1.05,
k_stop => 1.0e6,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
\linkage\ : entity work.tran_linkage(a1)
port map(
p2 => rudder_hrn_in,
p1 => gear_hrn_out
);
rudder_1 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
XCMP6 : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => XSIG010018,
neg => ELECTRICAL_REF
);
Throttle : entity work.stick(ideal)
generic map(
freq => 1.0,
amplitude => 2.397,
phase => 0.0,
offset => 2.397
)
port map(
v_out => ch1_in
);
rf_tx_rx : entity work.rf_xmtr_rcvr(behavioral)
port map(
tdm_in => bitstream1,
tdm_out => bitstream2
);
Digitize_Encode1 : entity work.Digitize_Encode_Man
port map(
ch2_in => ch2_in,
ch1_in => ch1_in,
tdm_out => bitstream1
);
Decode_PW_Man3 : entity work.Decode_PW_Man
port map(
bit_stream_in => bitstream2,
ch2_pw => ch2_pw_out,
ch1_pw => ch1_pw_out,
power => XSIG010018
);
lpf2 : entity work.lpf_2_e(simple)
generic map(
f1 => 10.0,
f2 => 10.0
)
port map(
input => servo_fltr_in,
output => servo_in
);
pw2ana_throttle : entity work.pw2ana
port map(
ana_out => prop_in,
pw_in => ch1_pw_out
);
pw2ana_rudder : entity work.pw2ana
port map(
ana_out => servo_fltr_in,
pw_in => ch2_pw_out
);
rot2v_rudder : entity work.rot2v(bhv)
generic map(
k => 4.57
)
port map(
output => rudder_fb,
input => rudder
);
plane11 : entity work.plane_pos_src
port map(
plane_pos => plane_dir,
rudder_fb => rudder_fb
);
hcl_1 : entity work.hcl
port map(
output => ch2_in,
plane_pos => plane_dir
);
end TB_CS5_HCL;
--
|
gpl-2.0
|
ced64f22b9d39d140b9affb11231077a
| 0.563229 | 3.645198 | false | false | false | false |
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