repo_name
stringlengths 6
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stringlengths 6
236
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int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
tgingold/ghdl
|
testsuite/synth/mem01/tb_sram02.vhdl
| 1 | 976 |
entity tb_sram02 is
end tb_sram02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram02 is
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: entity work.sram02
port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
wen_i => wen);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
addr <= "0000";
wdat <= x"02";
wen <= '1';
pulse;
assert rdat = x"02" severity failure;
addr <= "0100";
wdat <= x"03";
wait for 1 ns;
assert rdat = x"02" severity failure;
pulse;
assert rdat = x"03" severity failure;
addr <= "0000";
wen <= '0';
pulse;
assert rdat = x"02" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
8ac2f24b259020eac9b49b8fcc3493eb
| 0.578893 | 3.297297 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1650.vhd
| 4 | 2,260 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1650.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01650ent IS
END c08s13b00x00p03n01i01650ent;
ARCHITECTURE c08s13b00x00p03n01i01650arch OF c08s13b00x00p03n01i01650ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable LOCALI : INTEGER := 47;
variable LOCALR : REAL := 47.0;
variable LOCALB : BOOLEAN := TRUE;
BEGIN
-- Check for proper initialization.
assert (LOCALI = 47);
assert (LOCALR = 47.0);
assert (LOCALB = TRUE);
-- Execute the NULL statement.
null;
-- Verify that nothing has changed as a result.
assert NOT((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***PASSED TEST: c08s13b00x00p03n01i01650"
severity NOTE;
assert ((LOCALI = 47) and
(LOCALR = 47.0) and
(LOCALB = TRUE))
report "***FAILED TEST: c08s13b00x00p03n01i01650 - The execution of the null statement has no effect on any of the local variable within the process."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01650arch;
|
gpl-2.0
|
e941c995b57cef9a6e7ba11d62da5bb0
| 0.640265 | 3.772955 | false | true | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/sim/design_1_axi_timer_0_0.vhd
| 3 | 8,498 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0_10;
USE axi_timer_v2_0_10.axi_timer;
ENTITY design_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END design_1_axi_timer_0_0;
ARCHITECTURE design_1_axi_timer_0_0_arch OF design_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END design_1_axi_timer_0_0_arch;
|
gpl-3.0
|
0627c30094adb1b7d0112133815e2df4
| 0.684985 | 3.341722 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/fsm01/fsm_5s.vhdl
| 1 | 1,055 |
library ieee;
use ieee.std_logic_1164.all;
entity fsm_5s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_5s;
architecture behav of fsm_5s is
type state_t is (S0_1, S1_0, S2_0, S3_1, S4_0);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
s <= S2_0;
end if;
when S2_0 =>
if d = '0' then
s <= S3_1;
end if;
when S3_1 =>
if d = '1' then
s <= S4_0;
end if;
when S4_0 =>
if d = '0' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
|
gpl-2.0
|
bb34a631927db1ad72420d5eba2b6c10
| 0.396209 | 3.187311 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_18.vhd
| 3 | 2,530 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_18.vhd,v 1.5 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.5 $
--
-- ---------------------------------------------------------------------
entity fg_05_18 is
end entity fg_05_18;
library stimulus;
architecture test of fg_05_18 is
use stimulus.stimulus_generators.all;
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3;
-- end code from book
end block functional_mux;
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
else
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
stimulus_proc :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
gpl-2.0
|
a3033c7681ffeef66eb7c937ef732f9f
| 0.560474 | 3.682678 | false | false | false | false |
nickg/nvc
|
test/parse/homograph.vhd
| 1 | 583 |
package pack is
constant x : integer := 10;
end package;
entity e is
end entity;
architecture a of e is
procedure test1 is
constant x : integer := 5;
use work.pack.x; -- OK (work.pack.x is potentially visible and hidden
-- by local x above)
begin
assert x = 5; -- OK
end procedure;
procedure test2 is
use work.pack.x;
constant x : integer := 5;
begin
assert x = 5; -- OK
end procedure;
begin
end architecture;
|
gpl-3.0
|
c79db0f68d6a11410f4d121746e18865
| 0.504288 | 4.383459 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1903.vhd
| 4 | 3,476 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1903.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01903pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01903pkg;
use work.c07s01b00x00p08n01i01903pkg.all;
ENTITY c07s01b00x00p08n01i01903ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01903ent_a;
ARCHITECTURE c07s01b00x00p08n01i01903arch_a OF c07s01b00x00p08n01i01903ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01903arch_a;
use work.c07s01b00x00p08n01i01903pkg.all;
ENTITY c07s01b00x00p08n01i01903ent IS
END c07s01b00x00p08n01i01903ent;
ARCHITECTURE c07s01b00x00p08n01i01903arch OF c07s01b00x00p08n01i01903ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01903ent_a(c07s01b00x00p08n01i01903arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "process label accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
c : test port map ( ibus, p ); -- process label illegal here
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01903 - Process labels are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01903arch;
|
gpl-2.0
|
2994df182a02bb07bb1ac81b2a9e6edb
| 0.652474 | 3.361702 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/issue542/write.vhd
| 1 | 450 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity write is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end write;
architecture a of write is
begin
process (clk, reset) is
begin
if reset = '1' then
ack <= '0';
elsif rising_edge(clk) then
if write = '1' then
ack <= '1';
else
ack <= '0';
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
d1fd782ece17bf8d311e44faf1802e99
| 0.624444 | 2.631579 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffcode.vhd
| 2 | 1,519 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_ac_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_ac_huffcode;
architecture augh of huff_make_dhuff_tb_ac_huffcode is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
|
gpl-2.0
|
96cb8869893ad17815506a37fbfbf094
| 0.676103 | 2.893333 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue1269/ent93.vhdl
| 1 | 421 |
library ieee;
use ieee.std_logic_1164.all;
entity ent93 is
end ent93;
architecture arch of ent93 is
begin
process
variable color: bit_vector(2 downto 0);
variable lcol: std_logic_vector(31 downto 0);
begin
lcol := (
23 downto 16 => color(2),
15 downto 8 => color(1),
7 downto 0 => color(0),
others=> '0'
);
wait;
end process;
end architecture;
|
gpl-2.0
|
c32da887950e9e19302ca157782bb9a0
| 0.584323 | 3.508333 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue328/repro2.vhdl
| 1 | 632 |
entity repro2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Test case architecture
architecture func of repro2 is
signal s : std_logic := 'Z';
procedure write (signal s : inout std_logic) is
begin
null;
end write;
begin
b: block
port (s1 : out std_logic := '0');
port map (s1 => s);
begin
process
begin
s1 <= 'Z' after 2 ns;
wait;
end process;
end block;
process
begin
write(s);
wait for 1 ns;
assert s = '0' severity failure;
wait for 2 ns;
assert s = 'Z' severity failure;
wait;
end process;
end func;
|
gpl-2.0
|
b4b8b583e5d0146e2e4e738f82a6347c
| 0.609177 | 3.308901 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/synth109/ram2.vhdl
| 1 | 1,465 |
library ieee;
use ieee.std_logic_1164.all;
entity ram2 is
generic (
WIDTH : integer := 32;
SIZE : integer := 64;
ADDRWIDTH : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end ram2;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
architecture behavioral of ram2 is
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
doA <= ram(conv_integer(addrA));
end if;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
doB <= ram(conv_integer(addrB));
end if;
end if;
end process;
end behavioral;
|
gpl-2.0
|
167dd77971e720cb6c718276696cdfb6
| 0.575427 | 3.233996 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vh_rfs.vhd
| 5 | 40,066 |
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`protect end_protected
|
mit
|
64de2f20349903287f14f241ebba5733
| 0.949284 | 1.847296 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1240/tb_issue3.vhdl
| 1 | 527 |
entity tb_issue3 is
end tb_issue3;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_issue3 is
signal i : integer := 0;
signal o : signed (3 downto 0);
begin
dut: entity work.issue3
port map (i, o);
process
begin
i <= 0;
wait for 1 ns;
assert o = "0010" severity failure;
i <= 1;
wait for 1 ns;
assert o = "0011" severity failure;
i <= -1;
wait for 1 ns;
assert o = "0001" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
1baa1d3779a250462f2678419aaa3a63
| 0.618596 | 3.174699 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd
| 4 | 16,578 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1948.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01948pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01948pkg.all;
ENTITY c07s02b01x00p01n02i01948ent IS
END c07s02b01x00p01n02i01948ent;
ARCHITECTURE c07s02b01x00p01n02i01948arch OF c07s02b01x00p01n02i01948ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT NOR_C_csa1_1 : t_csa1_1 := ( '0', '0', '0', '1' );
CONSTANT NOR_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NOR_C_csa1_2 : t_csa1_2 := ( FALSE, FALSE, FALSE, TRUE );
CONSTANT NOR_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE, TRUE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT NOR_C_csa1_3 : t_csa1_3 := ( '0', '0', '0', '1' );
CONSTANT NOR_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NOR_C_csa1_4 : t_csa1_4 := ( FALSE, FALSE, FALSE, TRUE );
CONSTANT NOR_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE, TRUE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL NOR_S_csa1_1 : t_csa1_1 := ( '0', '0', '0', '1' );
SIGNAL NOR_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NOR_S_csa1_2 : t_csa1_2 := ( FALSE, FALSE, FALSE, TRUE );
SIGNAL NOR_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE, TRUE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL NOR_S_csa1_3 : t_csa1_3 := ( '0', '0', '0', '1' );
SIGNAL NOR_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NOR_S_csa1_4 : t_csa1_4 := ( FALSE, FALSE, FALSE, TRUE );
SIGNAL NOR_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE, TRUE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE NOR_V_csa1_1 : t_csa1_1 := ( '0', '0', '0', '1' );
VARIABLE NOR_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NOR_V_csa1_2 : t_csa1_2 := ( FALSE, FALSE, FALSE, TRUE );
VARIABLE NOR_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE, TRUE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE NOR_V_csa1_3 : t_csa1_3 := ( '0', '0', '0', '1' );
VARIABLE NOR_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NOR_V_csa1_4 : t_csa1_4 := ( FALSE, FALSE, FALSE, TRUE );
VARIABLE NOR_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE, TRUE );
BEGIN
--
-- Test NOR operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 NOR ARGB_C_csa1_1 ) = NOR_C_csa1_1
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 NOR ARGB_C_csa1_2 ) = NOR_C_csa1_2
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 NOR ARGB_C_csa1_3 ) = NOR_C_csa1_3
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 NOR ARGB_C_csa1_4 ) = NOR_C_csa1_4
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 NOR ARGB_C_usa1_1 ) = NOR_C_usa1_1
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 NOR ARGB_C_usa1_2 ) = NOR_C_usa1_2
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 NOR ARGB_C_usa1_3 ) = NOR_C_usa1_3
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 NOR ARGB_C_usa1_4 ) = NOR_C_usa1_4
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test NOR operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 NOR ARGB_S_csa1_1 ) = NOR_S_csa1_1
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 NOR ARGB_S_csa1_2 ) = NOR_S_csa1_2
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 NOR ARGB_S_csa1_3 ) = NOR_S_csa1_3
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 NOR ARGB_S_csa1_4 ) = NOR_S_csa1_4
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 NOR ARGB_S_usa1_1 ) = NOR_S_usa1_1
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 NOR ARGB_S_usa1_2 ) = NOR_S_usa1_2
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 NOR ARGB_S_usa1_3 ) = NOR_S_usa1_3
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 NOR ARGB_S_usa1_4 ) = NOR_S_usa1_4
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test NOR operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 NOR ARGB_V_csa1_1 ) = NOR_V_csa1_1
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 NOR ARGB_V_csa1_2 ) = NOR_V_csa1_2
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 NOR ARGB_V_csa1_3 ) = NOR_V_csa1_3
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 NOR ARGB_V_csa1_4 ) = NOR_V_csa1_4
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 NOR ARGB_V_usa1_1 ) = NOR_V_usa1_1
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 NOR ARGB_V_usa1_2 ) = NOR_V_usa1_2
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 NOR ARGB_V_usa1_3 ) = NOR_V_usa1_3
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 NOR ARGB_V_usa1_4 ) = NOR_V_usa1_4
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 NOR ARGB_C_csa1_1 ) = NOR_C_csa1_1 and
( ARGA_C_csa1_2 NOR ARGB_C_csa1_2 ) = NOR_C_csa1_2 and
( ARGA_C_csa1_3 NOR ARGB_C_csa1_3 ) = NOR_C_csa1_3 and
( ARGA_C_csa1_4 NOR ARGB_C_csa1_4 ) = NOR_C_csa1_4 and
( ARGA_C_usa1_1 NOR ARGB_C_usa1_1 ) = NOR_C_usa1_1 and
( ARGA_C_usa1_2 NOR ARGB_C_usa1_2 ) = NOR_C_usa1_2 and
( ARGA_C_usa1_3 NOR ARGB_C_usa1_3 ) = NOR_C_usa1_3 and
( ARGA_C_usa1_4 NOR ARGB_C_usa1_4 ) = NOR_C_usa1_4 and
( ARGA_S_csa1_1 NOR ARGB_S_csa1_1 ) = NOR_S_csa1_1 and
( ARGA_S_csa1_2 NOR ARGB_S_csa1_2 ) = NOR_S_csa1_2 and
( ARGA_S_csa1_3 NOR ARGB_S_csa1_3 ) = NOR_S_csa1_3 and
( ARGA_S_csa1_4 NOR ARGB_S_csa1_4 ) = NOR_S_csa1_4 and
( ARGA_S_usa1_1 NOR ARGB_S_usa1_1 ) = NOR_S_usa1_1 and
( ARGA_S_usa1_2 NOR ARGB_S_usa1_2 ) = NOR_S_usa1_2 and
( ARGA_S_usa1_3 NOR ARGB_S_usa1_3 ) = NOR_S_usa1_3 and
( ARGA_S_usa1_4 NOR ARGB_S_usa1_4 ) = NOR_S_usa1_4 and
( ARGA_V_csa1_1 NOR ARGB_V_csa1_1 ) = NOR_V_csa1_1 and
( ARGA_V_csa1_2 NOR ARGB_V_csa1_2 ) = NOR_V_csa1_2 and
( ARGA_V_csa1_3 NOR ARGB_V_csa1_3 ) = NOR_V_csa1_3 and
( ARGA_V_csa1_4 NOR ARGB_V_csa1_4 ) = NOR_V_csa1_4 and
( ARGA_V_usa1_1 NOR ARGB_V_usa1_1 ) = NOR_V_usa1_1 and
( ARGA_V_usa1_2 NOR ARGB_V_usa1_2 ) = NOR_V_usa1_2 and
( ARGA_V_usa1_3 NOR ARGB_V_usa1_3 ) = NOR_V_usa1_3 and
( ARGA_V_usa1_4 NOR ARGB_V_usa1_4 ) = NOR_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01948"
severity NOTE;
assert ( ( ARGA_C_csa1_1 NOR ARGB_C_csa1_1 ) = NOR_C_csa1_1 and
( ARGA_C_csa1_2 NOR ARGB_C_csa1_2 ) = NOR_C_csa1_2 and
( ARGA_C_csa1_3 NOR ARGB_C_csa1_3 ) = NOR_C_csa1_3 and
( ARGA_C_csa1_4 NOR ARGB_C_csa1_4 ) = NOR_C_csa1_4 and
( ARGA_C_usa1_1 NOR ARGB_C_usa1_1 ) = NOR_C_usa1_1 and
( ARGA_C_usa1_2 NOR ARGB_C_usa1_2 ) = NOR_C_usa1_2 and
( ARGA_C_usa1_3 NOR ARGB_C_usa1_3 ) = NOR_C_usa1_3 and
( ARGA_C_usa1_4 NOR ARGB_C_usa1_4 ) = NOR_C_usa1_4 and
( ARGA_S_csa1_1 NOR ARGB_S_csa1_1 ) = NOR_S_csa1_1 and
( ARGA_S_csa1_2 NOR ARGB_S_csa1_2 ) = NOR_S_csa1_2 and
( ARGA_S_csa1_3 NOR ARGB_S_csa1_3 ) = NOR_S_csa1_3 and
( ARGA_S_csa1_4 NOR ARGB_S_csa1_4 ) = NOR_S_csa1_4 and
( ARGA_S_usa1_1 NOR ARGB_S_usa1_1 ) = NOR_S_usa1_1 and
( ARGA_S_usa1_2 NOR ARGB_S_usa1_2 ) = NOR_S_usa1_2 and
( ARGA_S_usa1_3 NOR ARGB_S_usa1_3 ) = NOR_S_usa1_3 and
( ARGA_S_usa1_4 NOR ARGB_S_usa1_4 ) = NOR_S_usa1_4 and
( ARGA_V_csa1_1 NOR ARGB_V_csa1_1 ) = NOR_V_csa1_1 and
( ARGA_V_csa1_2 NOR ARGB_V_csa1_2 ) = NOR_V_csa1_2 and
( ARGA_V_csa1_3 NOR ARGB_V_csa1_3 ) = NOR_V_csa1_3 and
( ARGA_V_csa1_4 NOR ARGB_V_csa1_4 ) = NOR_V_csa1_4 and
( ARGA_V_usa1_1 NOR ARGB_V_usa1_1 ) = NOR_V_usa1_1 and
( ARGA_V_usa1_2 NOR ARGB_V_usa1_2 ) = NOR_V_usa1_2 and
( ARGA_V_usa1_3 NOR ARGB_V_usa1_3 ) = NOR_V_usa1_3 and
( ARGA_V_usa1_4 NOR ARGB_V_usa1_4 ) = NOR_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01948 - Logical operator NOR for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01948arch;
|
gpl-2.0
|
cb1d4eed5aa2bf14cd10a021bb6127e5
| 0.545301 | 2.61689 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dispout01/tb_rec01.vhdl
| 1 | 483 |
entity tb_rec01 is
end tb_rec01;
library ieee;
use ieee.std_logic_1164.all;
use work.rec01_pkg.all;
architecture behav of tb_rec01 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec01
port map (inp => inp, o => r);
process
begin
inp <= '0';
wait for 1 ns;
assert r = (a => '0', b => '1') severity failure;
inp <= '1';
wait for 1 ns;
assert r = (a => '1', b => '0') severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
ffb61061803ea90147f096ba8efd35b2
| 0.590062 | 2.96319 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue369/e.vhdl
| 1 | 685 |
entity e is end entity;
architecture a of e is
-- type type_t is range integer'low to integer'high; -- Unlimited range works fine
type type_t is range 0 to integer'high; -- Limited range triggers CONSTRAINT_ERROR
procedure p1(variable t :in type_t) is begin end procedure;
procedure p2(variable t : out type_t) is begin t := 1; end procedure;
procedure p3(variable t :inout type_t) is begin t := t + 1; end procedure;
begin
process
variable n :natural := 12;
begin
p1( t => type_t(n)); -- CONSTRAINT_ERROR
p2(integer(t) => n );
p3(integer(t) => type_t(n)); -- CONSTRAINT_ERROR
wait;
end process;
end architecture;
|
gpl-2.0
|
bf56b2558840ce117cd765b61d7f410f
| 0.642336 | 3.477157 | false | false | false | false |
nickg/nvc
|
test/regress/driver7.vhd
| 1 | 735 |
entity driver7 is
end entity;
architecture test of driver7 is
type int_vec is array (natural range <>) of integer;
function resolved (v : int_vec) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
subtype rint is resolved integer;
signal x : rint := 0;
begin
p1: process is
begin
x <= 1;
wait for 1 ns;
assert x = 3;
assert x'driving;
assert x'driving_value = 1;
wait;
end process;
p2: process is
begin
assert x'driving; -- Error
wait;
end process;
end architecture;
|
gpl-3.0
|
9367b5d3747475aa96732c3c0a3e3814
| 0.553741 | 4.176136 | false | false | false | false |
nickg/nvc
|
test/regress/proc11.vhd
| 5 | 627 |
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end function;
procedure proc(signal x : in bit_vector) is
begin
wait for 1 ns;
assert count_bits(x) = 0;
wait for 5 ns;
assert count_bits(x) = 4;
end procedure;
signal s : bit_vector(1 to 8);
begin
s <= X"aa" after 2 ns;
proc(s);
end architecture;
|
gpl-3.0
|
2d519ac5acf74973745ec3fece618a16
| 0.532695 | 3.603448 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc875.vhd
| 4 | 2,315 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc875.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b02x00p02n01i00875ent_a is
port ( ia, ib : bit;
oc, od : out bit) ;
end c01s03b02x00p02n01i00875ent_a;
architecture c01s03b02x00p02n01i00875arch_a of c01s03b02x00p02n01i00875ent_a is
begin
A1_BLK : block
signal S : INTEGER;
begin
S <= 1;
end block;
end c01s03b02x00p02n01i00875arch_a;
ENTITY c01s03b02x00p02n01i00875ent IS
port ( P3 : out bit;
P4 : out bit) ;
END c01s03b02x00p02n01i00875ent;
ARCHITECTURE c01s03b02x00p02n01i00875arch OF c01s03b02x00p02n01i00875ent IS
BEGIN
BB : block
signal S1 : bit;
signal S2 : bit;
component LOCAL port( CI, I2 : in BIT;
CO, RES :out BIT);
end component ;
for --- Failure_here
use entity work.c01s03b02x00p02n01i00875ent_a (c01s03b02x00p02n01i00875arch_a)
port map (ia => CI, ib => I2, oc => CO, od => RES);
begin
L : LOCAL port map (CI =>S1 , I2 =>S2 , CO=>P3 , RES =>P4 );
assert FALSE
report "***FAILED TEST: c01s03b02x00p02n01i00875 - Missing component specification."
severity ERROR;
end block BB;
END c01s03b02x00p02n01i00875arch;
|
gpl-2.0
|
e566b276a31d78f00c662e8b209a09b8
| 0.649244 | 3.283688 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug052/tb_simple2.vhdl
| 2 | 333 |
entity tb_simple2 is
generic (v : natural := 4);
package pkg1 is
constant c : natural := v + 1;
end pkg1;
constant c : natural := v - 1;
end;
architecture behav of tb_simple2 is
begin
assert pkg1.c = 5 and c = 3 severity failure;
assert not (pkg1.c = 5 and c = 3) report "value is correct" severity note;
end behav;
|
gpl-2.0
|
108aedae99690e9bc4a143bf28e1c8f7
| 0.657658 | 3.201923 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug0110/tb4.vhdl
| 1 | 559 |
package pkg4 is
type my_arr is array (1 to 2) of bit_vector (7 downto 0);
end pkg4;
use work.pkg4.all;
entity ent4 is
port (v : out my_arr;
b : in bit);
end ent4;
architecture behav of ent4 is
begin
v <= (others => (others => b));
end behav;
entity top4 is
end top4;
use work.pkg4.all;
architecture behav of top4 is
signal s : bit_vector (7 downto 0);
signal b : bit;
begin
dut : entity work.ent4
port map (
v(1)(3 downto 2) => s (3 downto 2),
v(2)(7 downto 6) => s (7 downto 6),
b => b);
b <= '0';
end behav;
|
gpl-2.0
|
07bf37b2eab1c599cff93683de59127a
| 0.597496 | 2.795 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1332/rom_constant.vhdl
| 1 | 549 |
library ieee;
use ieee.std_logic_1164.all;
entity rom_constant is
port (
clk : in std_logic;
a : out std_logic_vector(7 downto 0)
);
end rom_constant;
architecture rtl of rom_constant is
constant C_IEND : std_logic_vector(12*8-1 downto 0) := (others => '1');
signal index : integer := 0;
begin
process(clk)
begin
if rising_edge(clk) then
a <= C_IEND(index*8-1 downto (index-1)*8);
if index < 12 then
index <= index + 1;
else
index <= 0;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
e75cdd2f0d8ab9bf69c43dd1d7ce6298
| 0.59745 | 3.119318 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue963/tb_ent.vhdl
| 1 | 1,030 |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal dout : std_logic;
signal set : std_logic;
signal reset : std_logic;
begin
dut: entity work.ent
port map (
set => set,
reset => reset,
q => dout,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
set <= '1';
reset <= '0';
pulse;
assert dout = '1' severity failure;
set <= '0';
reset <= '0';
pulse;
assert dout = '0' severity failure;
set <= '0';
reset <= '0';
pulse;
assert dout = '1' severity failure;
set <= '0';
reset <= '1';
pulse;
assert dout = '0' severity failure;
set <= '1';
reset <= '1';
pulse;
assert dout = '1' severity failure;
set <= '0';
reset <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
ae72b321dcd3cfaeccfd42af7bd83fc8
| 0.527184 | 3.410596 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/synth58/repro1.vhdl
| 1 | 466 |
library ieee;
use ieee.std_logic_1164.all;
entity repro1 is
generic (
g : std_logic := '1'
);
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0)
);
end repro1;
architecture rtl of repro1 is
begin
process (i)
variable slv_out : std_logic_vector(7 downto 0);
begin
if g = '0' then
slv_out := i;
elsif g = '1' then
slv_out := not i;
end if;
o <= slv_out;
end process;
end rtl;
|
gpl-2.0
|
d5ada967b8dec5a4798d4dc9da35bf00
| 0.581545 | 2.949367 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd
| 4 | 3,691 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1375.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s05b00x00p03n01i01375pkg is
-- Type declarations.
subtype BV2 is BIT_VECTOR( 0 to 1 );
subtype CH2 is STRING( 1 to 2 );
-- Constant declarations.
constant BVC : BV2 := B"00";
constant CHC : CH2 := "bb";
-- Function returns BV2.
function returnBV2 return BV2;
-- Function returns CH2.
function returnCH2 return CH2;
end c08s05b00x00p03n01i01375pkg;
package body c08s05b00x00p03n01i01375pkg is
-- Function returns BV2.
function returnBV2 return BV2 is
begin
return ( BVC );
end returnBV2;
-- Function returns CH2.
function returnCH2 return CH2 is
begin
return( CHC );
end returnCH2;
end c08s05b00x00p03n01i01375pkg;
use work.c08s05b00x00p03n01i01375pkg.all;
ENTITY c08s05b00x00p03n01i01375ent IS
END c08s05b00x00p03n01i01375ent;
ARCHITECTURE c08s05b00x00p03n01i01375arch OF c08s05b00x00p03n01i01375ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable BITV : BV2 := B"11";
variable STRV : CH2 := "ab";
variable S, T : BIT;
variable S1, T1 : BIT;
variable S11, T11 : BIT;
variable C1, C2 : CHARACTER;
variable C11, C22 : CHARACTER;
variable C111, C222 : CHARACTER;
BEGIN
-- Assign with a variable as the expression.
( S, T ) := BITV;
( C1,C2 ) := STRV;
-- Assign with a function return value.
( S1, T1 ) := returnBV2;
( C11,C22 ) := returnCH2;
-- Assign with a qualified expression.
( S11, T11 ) := BV2'( '0', '1' );
( C111,C222 ) := CH2'( 'c', 'c' );
assert NOT(((S = BITV( 0 )) and (T = BITV( 1 )))
and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
and ((S11 = '0') and (T11 = '1'))
and ((C111 = 'c') and (C222 = 'c')))
report "***PASSED TEST: c08s05b00x00p03n01i01375"
severity NOTE;
assert (((S = BITV( 0 )) and (T = BITV( 1 )))
and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
and ((S11 = '0') and (T11 = '1'))
and ((C111 = 'c') and (C222 = 'c')))
report "***FAILED TEST: c08s05b00x00p03n01i01375 - Legal aggregate variable assignment fail."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01375arch;
|
gpl-2.0
|
d1059952be59cbc5e7dab17dde2b0a46
| 0.587375 | 3.358508 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd
| 4 | 32,019 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : capacitor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Electrical Capacitor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity capacitor is
generic (
cap : capacitance; -- Capacitance [F]
v_ic : real := real'low); -- Initial voltage (activated by
-- IF statement below)
port (
terminal p1, p2 : electrical);
end entity capacitor;
-------------------------------------------------------------------------------
-- Ideal Architecture (I = C * dV/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of capacitor is
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and v_ic /= real'low use
v == v_ic;
else
i == cap * v'dot; -- characteristic equation
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : resistor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Resistor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity resistor is
generic (
res : resistance); -- resistance (no initial value)
port (
terminal p1, p2 : electrical);
end entity resistor;
-------------------------------------------------------------------------------
-- Ideal Architecture (V = I*R)
-------------------------------------------------------------------------------
architecture ideal of resistor is
quantity v across i through p1 to p2;
begin
-- Characteristic equation
v == i*res;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : diode.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/11/07
-------------------------------------------------------------------------------
-- Description: Diode model with ideal architecture
-- Currently no Generics due to bug in DV
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/11/07 1.1 Mentor Graphics Added limit_exp function
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
use IEEE_proposed.energy_systems.all;
entity diode is
port (
terminal p, n : electrical);
end entity diode;
-------------------------------------------------------------------------------
-- Ideal Architecture: i = is*(exp(v/vt) - 1)
-------------------------------------------------------------------------------
architecture ideal of diode is
-- Declare internal quanties and constants
quantity v across i through p to n;
constant isat : current := 1.0e-14; -- Saturation current [Amps]
constant TempC : real := 27.0; -- Ambient Temperature [Degrees]
constant TempK : real := 273.0 + TempC; -- Temperaure [Kelvin]
constant vt : real := K*TempK/Q; -- Thermal Voltage
-- This function is to limit the exponential function to avoid convergence
-- problems due to numerical overflow. At x=100, it becomes a straight line
-- with slope matching that at the intercept.
function limit_exp( x : real ) return real is
variable abs_x : real := abs(x);
variable result : real;
begin
if abs_x < 100.0 then
result := exp(abs_x);
else
result := exp(100.0) * (abs_x - 99.0);
end if;
-- If exponent is negative, set exp(-x) = 1/exp(x)
if x < 0.0 then
result := 1.0 / result;
end if;
return result;
end function limit_exp;
begin -- ideal architecture
-- Characteristic equation
i == isat*(limit_exp(v/vt) - 1.0);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity EnvDetect is
port(
terminal input : electrical;
terminal output : electrical
);
end EnvDetect;
architecture EnvDetect of EnvDetect is
-- Component declarations
-- Signal declarations
terminal XSIG010001 : electrical;
begin
-- Signal assignments
-- Component instances
C1 : entity work.capacitor(ideal)
generic map(
cap => 0.1e-6
)
port map(
p1 => XSIG010001,
p2 => ELECTRICAL_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => XSIG010001,
p2 => ELECTRICAL_REF
);
D4 : entity work.diode(ideal)
port map(
p => input,
n => XSIG010001
);
C2 : entity work.capacitor(ideal)
generic map(
cap => 6.0e-6
)
port map(
p1 => XSIG010001,
p2 => output
);
R6 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => output,
p2 => ELECTRICAL_REF
);
end EnvDetect;
--
-- Model of Binary Frequency Shift Keying (BFSK) modulator
-- with digital input and analog output
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.MATH_REAL.all;
entity bfsk is
generic (
fc : real := 455.0e3; -- Mean carrier frequency
delta_f : real := 5.0e3; -- Difference between low and high carrier frequency
amp : voltage := 1.0; -- Amplitude of modulated signal
offset : voltage := 0.0 -- output offset voltage
);
port (
d_in : in std_logic; -- digital input
terminal a_out : electrical -- output terminal
);
end entity bfsk;
architecture behavioral of bfsk is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity for angle in radians
constant wc : real := math_2_pi*fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi*delta_f; -- convert delta_f to rad/s
begin
if (d_in = '0') use
phi'dot == wc; -- set to carrier frequency
elsif (d_in = '1') use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
vout == offset + amp*sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : vSum.vhd
-- Author : Mentor Graphics
-- Created : 2001/11/09
-- Last update: 2001/11/09
-------------------------------------------------------------------------------
-- Description: Summing junction with electrical connections
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/11/09 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity vSum is
generic (
K1 : real := 1.0;
K2 : real := -1.0);
port (
terminal in1, in2 : electrical;
terminal output : electrical);
end entity vSum;
architecture behavioral of vSum is
quantity vin1 across in1 to electrical_ref;
quantity vin2 across in2 to electrical_ref;
quantity vout across iout through output to electrical_ref;
begin
vout == K1*vin1 + K2*vin2;
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : vLPF_2nd.vhd
-- Author : Mentor Graphics
-- Created : 2001/11/27
-- Last update: 2001/11/27
-------------------------------------------------------------------------------
-- Description: 2nd order Lowpass Filter with Electrical connections
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/11/27 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity vLPF_2nd is
generic ( K : real := 1.0; -- Filter Gain
Fp : real; -- Double Pole Frequency [Hz]
Q : real := 0.707 -- Quality factor
);
port ( terminal input : electrical;
terminal output : electrical
);
end entity vLPF_2nd;
-------------------------------------------------------------------------------
-- Transfer Function:
--
-- wp^2
-- Vo(s) = K * --------------------- Vin(s)
-- S^2 + (wp/Q)*s + wp^2
-------------------------------------------------------------------------------
architecture behavioral of vLPF_2nd is
quantity vin across input;
quantity vout across iout through output;
constant wp : real := math_2_pi*Fp; -- Frequency in Radians
constant num : real_vector := (wp*wp, 0.0, 0.0); -- Numerator array
constant den : real_vector := (wp*wp, wp/Q, 1.0); -- Denominator array
begin
vout == K * vin'ltf(num, den); -- Laplace Transform of input
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : vBPF.vhd
-- Author : Mentor Graphics
-- Created : 2001/11/27
-- Last update: 2001/11/27
-------------------------------------------------------------------------------
-- Description: Bandpass Filter with Electrical connections
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/11/27 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity vBPF is
generic ( K : real := 1.0; -- Filter Gain
Fc : real; -- Center Frequency [Hz]
Q : real := 0.707 -- Quality factor
);
port ( terminal input : electrical;
terminal output : electrical
);
end entity vBPF;
-------------------------------------------------------------------------------
-- Transfer Function:
--
-- wc*s
-- Vo(s) = K * --------------------- Vin(s)
-- S^2 + (wc/Q)*s + wc^2
-------------------------------------------------------------------------------
architecture behavioral of vBPF is
quantity vin across input;
quantity vout across iout through output;
constant wc : real := math_2_pi*Fc; -- Frequency in Radians
constant num : real_vector := (0.0, wc); -- Numerator array
constant den : real_vector := (wc*wc, wc/Q, 1.0); -- Denominator array
begin
vout == K * vin'ltf(num, den); -- Laplace Transform of output
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
entity MeasFreq is
generic ( thres : real := 0.0 ); -- threshold crossing
port ( terminal input : electrical;
signal f_out : out real := 0.0);
end entity MeasFreq;
architecture ThresDetect of MeasFreq is
quantity vin across input;
-- signal freq : real := 0.0;
begin
-- f_out <= freq;
detect : process (vin'above(thres)) is
variable t_old : real := real'low;
begin
if vin'above(thres) then
f_out <= 1.0 / (now - t_old);
t_old := now;
end if;
end process detect;
end ThresDetect;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : a2d_bit.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Ideal one bit A/D converter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity a2d_bit is
generic (
thres : real := 2.5); -- Threshold to determine logic output
port (
terminal a : electrical; -- analog input
signal d : out std_logic); -- digital (std_logic) output
end entity a2d_bit;
-------------------------------------------------------------------------------
-- Ideal architecture
-- Uses 'above operator to detect threshold crossing
-------------------------------------------------------------------------------
architecture ideal of a2d_bit is
quantity vin across a;
begin
-- purpose: Detect threshold crossing and assign event on output (d)
-- type : combinational
-- inputs : vin'above(thres)
-- outputs: pulse_signal
process (vin'above(thres)) is
begin -- PROCESS
if vin'above(thres) then
d <= '1';
else
d <= '0';
end if;
end process;
end ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity tb_CS4_CommSys_det is
end tb_CS4_CommSys_det;
architecture TB_CS4_CommSys_det of tb_CS4_CommSys_det is
-- Component declarations
-- Signal declarations
signal baseband : std_logic;
signal bitstream : std_logic;
terminal bp1_out : electrical;
terminal bp2_out : electrical;
terminal ed1_out : electrical;
terminal ed2_out : electrical;
terminal fsk_out : electrical;
signal fsk_out_f : real;
terminal lna_in : electrical;
terminal lna_out : electrical;
begin
-- Signal assignments
-- Component instances
EnvDetect1 : entity work.EnvDetect
port map(
output => ed1_out,
input => bp1_out
);
EnvDetect2 : entity work.EnvDetect
port map(
output => ed2_out,
input => bp2_out
);
BFSK3 : entity work.bfsk(behavioral)
generic map(
amp => 5.0
)
port map(
d_in => bitstream,
a_out => fsk_out
);
vsum1 : entity work.vSum(behavioral)
port map(
in1 => ed1_out,
in2 => ed2_out,
output => lna_in
);
vLPF2 : entity work.vLPF_2nd(behavioral)
generic map(
Fp => 20.0e3,
K => 10000.0
)
port map(
input => lna_in,
output => lna_out
);
vBPF2 : entity work.vBPF(behavioral)
generic map(
Fc => 455.0e3
)
port map(
input => fsk_out,
output => bp2_out
);
vBPF3 : entity work.vBPF(behavioral)
generic map(
Fc => 460.0e3
)
port map(
input => fsk_out,
output => bp1_out
);
MeasFreq6 : entity work.MeasFreq(ThresDetect)
port map(
input => fsk_out,
f_out => fsk_out_f
);
a2 : entity work.a2d_bit(ideal)
generic map(
thres => 1.0
)
port map(
D => baseband,
A => lna_out
);
-- bitstream
P_bitstream :
process
begin
-- 0.000
wait for 0.000 ns; bitstream <= '0';
-- 50000.000
wait for 50000.000 ns; bitstream <= '1';
-- 100000.000
wait for 50000.000 ns; bitstream <= '0';
-- 150000.000
wait for 50000.000 ns; bitstream <= '1';
-- 200000.000
wait for 50000.000 ns; bitstream <= '0';
-- 300000.000
wait for 100000.000 ns; bitstream <= '1';
-- 501000.000
wait for 201000.000 ns; bitstream <= '0';
-- 550000.000
wait for 49000.000 ns; bitstream <= '1';
-- 600000.000
wait for 50000.000 ns; bitstream <= '0';
wait;
end process;
-- KillerProc :
-- process
-- begin
-- wait for 1 ns;
-- lclclkinitwire <= '1';
-- wait;
-- end process;
end TB_CS4_CommSys_det;
|
gpl-2.0
|
5da3d26c85e6a018717e15df6c5938f5
| 0.562073 | 4.775391 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dff03/tb_dff07.vhdl
| 1 | 1,063 |
entity tb_dff07 is
end tb_dff07;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff07 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff07
port map (
q1 => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
en2 <= '0';
din <= '1';
pulse;
assert dout = '0' severity failure;
en2 <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
3d6efdcb980a0da6cb827950238a3b7d
| 0.522107 | 3.201807 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd
| 4 | 2,158 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity comp_2p2z is
generic ( gain : real := 100.0; -- high DC gain for good load regulation
fp1 : real := 7.5e3; -- pole location to achieve crossover frequency
fp2 : real := 531.0e3; -- pole location to cancel effect of ESR
fz1 : real := 403.0; -- zero locations to cancel L-C filter poles
fz2 : real := 403.0 );
port ( terminal input, output, ref : electrical );
end entity comp_2p2z;
----------------------------------------------------------------
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi * fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi * fp2;
constant wz1 : real := math_2_pi * fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi * fz2;
constant num : real_vector := ( 1.0,
(wz1 + wz2) / (wz1 * wz2),
1.0 / (wz1 * wz2) );
constant den : real_vector := ( 1.0e-9, 1.0,
(wp1 + wp2) / (wp1 * wp2),
1.0 / (wp1 * wp2) );
begin
vout == -1.0 * gain * vin'ltf(num, den);
end architecture ltf;
|
gpl-2.0
|
52dee8477a41db574906a9fa438f1324
| 0.60519 | 3.746528 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue1152/ent.vhdl
| 1 | 499 |
entity ent is
end;
architecture arch of ent is
type range_t is array (integer range <>) of bit;
function get_range (constant code : string) return range_t is
constant ret_val : range_t(1 to 10) := (others => '0');
begin
return ret_val;
end function get_range;
signal ret_val : boolean_vector(get_range("HELLO")'range) := (others => false);
--constant ret_range : range_t := get_range("HELLO");
--signal ret_val : boolean_vector(ret_range) := (others => false);
begin
end;
|
gpl-2.0
|
3f64dbb6b29617d5dc56e83455334b50
| 0.657315 | 3.326667 | false | false | false | false |
nickg/nvc
|
test/regress/signal17.vhd
| 1 | 1,219 |
entity signal17 is
end entity;
architecture test of signal17 is
type rec1 is record
x : bit;
y : bit_vector(1 to 3);
z : integer;
end record;
type rec2 is record
x : rec1;
y : character;
end record;
type bv2d is array (natural range <>) of bit_vector(1 to 2);
signal a : bit;
signal b : bit_vector(1 to 3);
signal c : integer;
signal d : character;
signal p, q, r : bit;
begin
p1: process is
variable r1 : rec1;
variable r2 : rec2;
begin
r1 := ('1', "010", 42);
(a, b, c) <= r1;
wait for 1 ns;
assert a = '1';
assert b = "010";
assert c = 42;
r2 := (('0', "100", 72), 'Z');
((a, b, c), d) <= r2;
wait for 1 ns;
assert a = '0';
assert b = "100";
assert c = 72;
assert d = 'Z';
(a, (p, q, r), c) <= r1;
wait for 1 ns;
assert a = '1';
assert p = '0';
assert q = '1';
assert r = '0';
assert c = 42;
(b(1 to 2), (q, r)) <= bv2d'( "10", "01" );
wait for 1 ns;
assert b = "100";
wait;
end process;
end architecture;
|
gpl-3.0
|
ca97fad76228d850290134de060c3b72
| 0.442166 | 3.259358 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/syn/vhdl/doHistStretch_sitofp_32s_32_6.vhd
| 5 | 2,557 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity doHistStretch_sitofp_32s_32_6 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of doHistStretch_sitofp_32s_32_6 is
--------------------- Component ---------------------
component doHistStretch_ap_sitofp_4_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
doHistStretch_ap_sitofp_4_no_dsp_32_u : component doHistStretch_ap_sitofp_4_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
abed4fb5f6a53086f3205a88a904c0fd
| 0.472429 | 3.891933 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd
| 4 | 1,879 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_01_01 is
end entity test_bench_01_01;
architecture test_reg4_behav of test_bench_01_01 is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
stimulus : process is
begin
wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
clk <= '0'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
en <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
wait;
end process stimulus;
end architecture test_reg4_behav;
|
gpl-2.0
|
d0ed1431be4748978c1adefb31976f7d
| 0.584886 | 3.24525 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd
| 4 | 1,950 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_15 is
generic ( extended_reset : boolean := false );
end entity inline_15;
----------------------------------------------------------------
architecture test of inline_15 is
signal functional_reset, equivalent_reset : bit := '0';
begin
block_3_r : block is
port ( reset : out bit );
port map ( reset => functional_reset );
begin
-- code from book:
reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
'1', '0' after 50 ns;
-- end of code from book
end block block_3_r;
----------------
block_3_s : block is
port ( reset : out bit );
port map ( reset => equivalent_reset );
begin
-- code from book:
reset_gen : process is
begin
if extended_reset then
reset <= '1', '0' after 200 ns;
else
reset <= '1', '0' after 50 ns;
end if;
wait;
end process reset_gen;
-- end of code from book
end block block_3_s;
----------------
verifier :
assert functional_reset = equivalent_reset
report "Functional and equivalent models give different results";
end architecture test;
|
gpl-2.0
|
88ac258d084bbfba9b7768eaddb79cfa
| 0.625128 | 4.202586 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/synth104/case02.vhdl
| 1 | 528 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity case02 is
port (
sel : in unsigned(3 downto 0);
det : out std_logic_vector(1 downto 0)
);
end case02;
architecture behavior of case02 is
begin
tc: process(sel)
begin
case to_integer(sel) is
when 0 to 1 =>
det <= "00";
when 2 | 7 downto 4 =>
det <= "01";
when 3 | 12 downto 10 | 8 to 9 =>
det <= "10";
when others =>
det <= "11";
end case;
end process;
end behavior;
|
gpl-2.0
|
aec7e59718fe21043d7a53d6ad8b18a6
| 0.5625 | 3.3 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug24064/pp_fir_filter.vhd
| 2 | 14,621 |
--------------------------------------------------------------------------------
--! @file
--! @brief pp_fir_filter.
--! This implements a poly-phase fir filter that can be used for
--! rational resampling or rational sample delay.
--! The taps of the FIR filter are generated at compile time and start
--! as a Hann-windowed sinc function. 0-phase offset is then normalized
--! to be 0.98 amplitude.
--! The generics determine the resolution of the fir-filter, as well as
--! as the number of phases.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.er_pack.all;
entity pp_fir_filter is
generic (
--! The width of each tap in bits
taps_width_g : natural := 16;
--! The number of lobes. This is basically the number of taps per filter
num_lobes_g : natural := 8;
--! The number of parallel channels
num_channels_g : natural := 1;
--! The number of taps per lobe
taps_per_lobe_g : natural := 512;
--! The number of taps to skip to get to the next tap
step_size_g : natural := 512);
port (
-- standard ports
clk_i : in std_logic;
rst_i : in std_logic;
-- input data ports
--! Run the filter without taking another sample
run_i : in std_logic;
phase_i : in std_logic_vector(log2(taps_per_lobe_g) downto 0);
data_en_i : in std_logic;
data_i : in std_logic_vector(num_channels_g*taps_width_g-1 downto 0);
-- output data ports
data_o : out std_logic_vector(num_channels_g*taps_width_g-1 downto 0);
data_en_o : out std_logic);
end entity pp_fir_filter;
architecture behavior of pp_fir_filter is
----------------------------------------------------------------------------
-- Types, Subtypes, and Constants
----------------------------------------------------------------------------
subtype word_t is signed(1*taps_width_g-1 downto 0);
subtype dword_t is signed(2*taps_width_g-1 downto 0);
subtype save_range is natural range 2*taps_width_g-2 downto 1*taps_width_g-1;
type word_vector_t is array (integer range <>) of word_t;
type dword_vector_t is array (integer range <>) of dword_t;
type rom_t is array (integer range <>) of signed(data_i'range);
-- The state machine deals with the MACCs
type state_type is (
idle_state, -- Waiting for input signal
load_state, -- Load the sample into the input ram
mult_state, -- First multiply does not accumulate product
macc_state, -- P += A*B
save_state); -- Save the output
type dsp_opcode_type is (
clear, -- P = 0
mult, -- P = A*B
macc, -- P += A*B
hold); -- P = P
constant round_val : dword_t := shift_left(to_signed(1, dword_t'length), taps_width_g-2);
-- We want the phase offset to be in relation to the middle of the center
-- lobe. For this reason, we will need to determine the offset of the first
-- sample in relation to the step_size, taps_per_lobe, and the number of
-- lobes
constant phase_offset_c : natural :=
-- (num_lobes_g * (taps_per_lobe_g - step_size_g+1)) mod taps_per_lobe_g;
(num_lobes_g/2 * (taps_per_lobe_g - step_size_g));
constant num_regs_c : natural :=
-- (num_lobes_g * (taps_per_lobe_g / step_size_g));
(num_lobes_g);
----------------------------------------------------------------------------
-- functions
----------------------------------------------------------------------------
function load_sinc_rom (
taps_per_lobe : natural;
num_lobes : natural)
return word_vector_t is
-- The returned ram
variable rom : word_vector_t(0 to taps_per_lobe * num_lobes-1);
-- Stuff for the actual sinc calculation
variable real_rom : real_vector(rom'range);
variable half : real := real(rom'length/2);
variable nm1 : real := real(rom'length-1);
variable phase : real;
variable sinc : real;
variable hann : real;
-- for power calculation
variable power : real;
begin
------------------------------------------------------------------------
-- Tap generation
------------------------------------------------------------------------
for idx in real_rom'range loop
-- Determine the phase, but multiply it by PI to get the correct
-- phase shift
phase := math_pi * (real(idx) - half) / real(taps_per_lobe);
-- Don't divide by zero
if phase = 0.0 then
sinc := 1.0;
else
sinc := sin(phase) / phase;
end if;
-- Multiply it by a hann window
hann := 0.5 * (1.0 - cos(2.0*math_pi*real(idx)/nm1));
-- Put it in the rom
real_rom(idx) := sinc*hann;
end loop;
------------------------------------------------------------------------
-- Energy measurement
------------------------------------------------------------------------
-- Now that the ram is complete, we still need to make sure that we
-- scale everything to be a power of one. This is to make sure that we
-- don't overflow during the actual addition.
power := 0.0;
for idx in 0 to num_regs_c-1 loop
power := power + real_rom(phase_offset_c + idx*step_size_g);
end loop;
------------------------------------------------------------------------
-- Normalization
------------------------------------------------------------------------
-- Now put it in the actual ram
for idx in rom'range loop
real_rom(idx) := real_rom(idx) * (0.98 / power);
rom (idx) := signed(to_slv(real_rom(idx), word_t'length));
end loop;
-- return it
return rom;
end function load_sinc_rom;
-----------------------------------------------------------------------------
constant taps_rom : word_vector_t := load_sinc_rom(taps_per_lobe_g, num_lobes_g);
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
signal phase_reg : natural;
signal data_reg : std_logic_vector(data_i'range);
signal state : state_type;
signal dsp_opcode : dsp_opcode_type;
-- DSP Signals
signal a : word_vector_t (0 to num_channels_g-1);
signal b : word_t;
signal p : dword_vector_t(0 to num_channels_g-1);
signal r : word_vector_t (0 to num_channels_g-1);
-- RAM/ROM Signals
signal taps_addr : natural;
signal next_taps_addr : natural;
signal z_addr : natural;
signal z_ram : rom_t(0 to num_regs_c-1);
signal z_ram_en : std_logic;
-- Quantization signals
signal q : dword_vector_t(0 to num_channels_g-1);
-- for internal testing
signal rom_data_test : word_t;
signal rom_addr_test : natural;
--------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- The actual fir filter part
-----------------------------------------------------------------------------
-- Direct signal assignments
-----------------------------------------------------------------------------
a_gen : for idx in 0 to num_channels_g-1 generate
-- Get the input for the multiplication
a(idx) <= z_ram(z_addr)((idx+1)*taps_width_g-1 downto idx*taps_width_g);
-- Since the rounding is combinational, we can sum it up here
q(idx) <= p(idx) + round_val;
-- Now the data out
data_o((idx+1)*taps_width_g-1 downto idx*taps_width_g) <=
std_logic_vector(r(idx));
end generate a_gen;
-- This one is easy
b <= taps_rom(taps_addr); -- Select MUX
-----------------------------------------------------------------------------
-- FIR process controls the main state machine behind the serial FIR
-----------------------------------------------------------------------------
fsm_proc : process(clk_i)
variable idx_hi : natural;
variable idx_lo : natural;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
state <= idle_state;
dsp_opcode <= clear;
z_ram_en <= '0';
z_addr <= 0 ;
taps_addr <= 0 ;
next_taps_addr <= 0 ;
data_en_o <= '0';
-- data_o <= (others => '0');
else
-- Default cases
z_ram_en <= '0';
data_en_o <= '0';
next_taps_addr <= next_taps_addr + step_size_g;
-- Other cases
case state is
-----------------------------------------------------------------
when idle_state =>
dsp_opcode <= clear;
z_addr <= 0 ;
taps_addr <= 0 ;
if data_en_i = '1' or run_i = '1' then
z_ram_en <= data_en_i;
state <= load_state;
phase_reg <= phase_offset_c + to_integer(unsigned(phase_i));
data_reg <= data_i;
end if;
-----------------------------------------------------------------
when load_state =>
dsp_opcode <= clear;
z_addr <= 0 ;
taps_addr <= phase_reg;
next_taps_addr <= phase_reg;
state <= mult_state;
-----------------------------------------------------------------
when mult_state =>
dsp_opcode <= mult;
z_addr <= 0 ;
taps_addr <= phase_reg;
state <= macc_state;
-----------------------------------------------------------------
when macc_state =>
dsp_opcode <= macc;
-- The delayed version of the incoming signal
-- if next_taps_addr >= taps_rom'length then
if z_addr = z_ram'high then
state <= save_state;
else
z_addr <= z_addr + 1;
taps_addr <= next_taps_addr;
end if;
-----------------------------------------------------------------
when save_state =>
dsp_opcode <= macc;
z_addr <= 0 ;
data_en_o <= '1';
state <= idle_state;
for idx in q'range loop
r(idx) <= q(idx)(save_range);
end loop;
-----------------------------------------------------------------
end case;
end if;
end if;
end process fsm_proc;
-----------------------------------------------------------------------------
-- DSP48 process emulates a DSP48 (partially)
-----------------------------------------------------------------------------
alu_proc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
p <= (others => (others => '0'));
else
case dsp_opcode is
------------------------------------------------------------
when clear =>
p <= (others => (others => '0'));
------------------------------------------------------------
when mult =>
for idx in p'range loop
p(idx) <= a(idx) * b;
end loop;
------------------------------------------------------------
when macc =>
for idx in p'range loop
p(idx) <= p(idx) + a(idx) * b;
end loop;
------------------------------------------------------------
when hold =>
null;
------------------------------------------------------------
end case;
end if;
end if;
end process alu_proc;
-----------------------------------------------------------------------------
-- Shift RAM
-----------------------------------------------------------------------------
-- I'm calling it the z ram, since it is the z delay of the incoming signal
shift_ram_proc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
z_ram <= (others => (others => '0'));
elsif z_ram_en = '1' then
z_ram <= signed(data_reg) & z_ram(0 to z_ram'length-2);
end if;
end if;
end process shift_ram_proc;
----------------------------------------------------------------------------
-- tests
----------------------------------------------------------------------------
-- synthesis off
-- Test the rom by iterating through the rom
rom_test_proc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
rom_addr_test <= 0;
else
if rom_addr_test >= taps_rom'length-1 then
rom_addr_test <= 0;
else
rom_addr_test <= rom_addr_test + 1;
end if;
end if;
end if;
end process rom_test_proc;
-- combinational read
rom_data_test <= taps_rom(rom_addr_test);
-- synthesis on
end architecture behavior;
|
gpl-2.0
|
71f10bb9b3745cbb0ef5fe4c2ab58f8e
| 0.385405 | 4.842994 | false | false | false | false |
tgingold/ghdl
|
libraries/synopsys/std_logic_misc-body.vhdl
| 2 | 27,741 |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
--START-!V08
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--END-!V08
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
--START-!V08
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
--END-!V08
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
--START-!V08
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
--END-!V08
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
--START-!V08
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
--END-!V08
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
gpl-2.0
|
e9bcadd650719607f93059839aefff21
| 0.383404 | 3.257133 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dff01/tb_dff06.vhdl
| 1 | 897 |
entity tb_dff06 is
end tb_dff06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff06 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff06
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
pulse;
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '0' severity failure;
pulse;
assert dout = '0' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
eadc82b797e13b72c54c67406eb88605
| 0.571906 | 3.476744 | false | false | false | false |
nickg/nvc
|
test/regress/ename3.vhd
| 1 | 868 |
entity bot is
generic ( N : integer );
end entity;
architecture test of bot is
constant k : integer := N;
signal x, y : natural;
begin
p1: process (y) is
begin
x <= y + 5;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ename3 is
end entity;
architecture test of ename3 is
begin
g: for i in 1 to 3 generate
uut: entity work.bot generic map (N => i);
end generate;
p1: process is
begin
assert << constant g(1).uut.k : integer >> = 1;
assert << constant g(2).uut.k : integer >> = 2;
assert << constant g(3).uut.k : integer >> = 3;
<< signal g(1).uut.x : integer >> <= force 1;
wait for 1 ns;
assert << signal g(1).uut.x : integer >> = 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
36be408c1a6125746aee933a1ee83d06
| 0.509217 | 3.790393 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sm.vhd
| 3 | 28,280 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
gpl-3.0
|
a96ad4ff009722b9554a3a3e8431c94e
| 0.399611 | 4.602865 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd
| 4 | 4,822 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_ch_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity buf is
port ( a : in std_logic; y : out std_logic );
end buf;
architecture basic of buf is
begin
y <= a;
end basic;
library ieee; use ieee.std_logic_1164.all;
entity fanout_tree is
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end fanout_tree;
--------------------------------------------------
architecture recursive of fanout_tree is
component buf
port ( a : in std_logic; y : out std_logic );
end component;
component fanout_tree
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end component;
signal buffered_input_0, buffered_input_1 : std_logic;
begin
degenerate_tree : if height = 0 generate
output(0) <= input;
end generate degenerate_tree;
compound_tree : if height > 0 generate
buf_0 : buf
port map ( a => input, y => buffered_input_0 );
-- code from book
block_0 : block
for subtree_0 : fanout_tree
use entity work.fanout_tree(recursive);
begin
subtree_0 : fanout_tree
generic map ( height => height - 1 )
port map ( input => buffered_input_0,
output => output(0 to 2**(height - 1) - 1) );
end block block_0;
-- end code from book
buf_1 : buf
port map ( a => input, y => buffered_input_1 );
block_1 : block
for subtree_1 : fanout_tree
use entity work.fanout_tree(recursive);
begin
subtree_1 : fanout_tree
generic map ( height => height - 1 )
port map ( input => buffered_input_1,
output => output(2**(height - 1) to 2**height - 1) );
end block block_1;
end generate compound_tree;
end recursive;
library ieee; use ieee.std_logic_1164.all;
entity ch_14_01 is
end ch_14_01;
architecture test of ch_14_01 is
component fanout_tree
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end component;
for clock_buffer_tree : fanout_tree
use entity work.fanout_tree(recursive);
signal unbuffered_clock : std_logic;
signal buffered_clock_array : std_logic_vector(0 to 7);
begin
clock_buffer_tree : fanout_tree
generic map ( height => 3 )
port map ( input => unbuffered_clock,
output => buffered_clock_array );
clock_gen : process
begin
unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
end process clock_gen;
end test;
|
gpl-2.0
|
8a5d92220c672d921b4ad4750f959bb7
| 0.459768 | 5.033403 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd
| 4 | 1,773 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1963.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01963ent IS
END c07s02b01x00p02n02i01963ent;
ARCHITECTURE c07s02b01x00p02n02i01963arch OF c07s02b01x00p02n02i01963ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01963"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01963 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01963arch;
|
gpl-2.0
|
5730e7b2e63cf3d5ca42069cb681c1ff
| 0.664975 | 3.678423 | false | true | false | false |
nickg/nvc
|
test/regress/elab31.vhd
| 1 | 1,561 |
package pack is
type rec is record
x : integer;
end record;
type pt is protected
impure function next_id return integer;
end protected;
impure function get_rec return rec;
function get_id (r : rec) return integer;
end package;
package body pack is
type pt is protected body
variable ctr : integer := 0;
impure function next_id return integer is
begin
ctr := ctr + 1;
return ctr;
end function;
end protected body;
shared variable p : pt;
impure function get_rec return rec is
begin
return (x => p.next_id);
end function;
function get_id (r : rec) return integer is
begin
return r.x;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( r1, r2 : rec );
port ( s1 : in bit_vector(1 to get_id(r1));
s2 : in bit_vector(1 to get_id(r2)) );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert s1 = "0";
assert s2 = "00";
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity elab31 is
end entity;
architecture test of elab31 is
constant r1, r2 : rec := get_rec;
signal s1 : bit_vector(1 to 1);
signal s2 : bit_vector(1 to 2);
begin
u: entity work.sub generic map ( r1, r2 ) port map ( s1, s2 );
end architecture;
|
gpl-3.0
|
6ca830811aac68314e931853769f346b
| 0.537476 | 3.951899 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc281.vhd
| 4 | 2,044 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc281.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p08n02i00281ent IS
END c03s01b03x00p08n02i00281ent;
ARCHITECTURE c03s01b03x00p08n02i00281arch OF c03s01b03x00p08n02i00281ent IS
type UPLE is range 1 to 8
units
single;
duple = 2 single;
triple = 3 single;
quadruple = 2 duple;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
variable k : UPLE := 1 duple;
BEGIN
assert NOT(k = 2 single)
report "***PASSED TEST: c03s01b03x00p08n02i00281"
severity NOTE;
assert (k = 2 single)
report "***FAILED TEST: c03s01b03x00p08n02i00281 - The relative order of secondary unit declarations is not fixed as long as units are not used before they are declared."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p08n02i00281arch;
|
gpl-2.0
|
2c68b86a43acca801663e86aa3909690
| 0.661937 | 3.729927 | false | true | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_afifo_autord.vhd
| 3 | 17,964 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0_2;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_EN_SAFETY_CKT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF,
C_USE_EMBEDDED_REG => 0 -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
gpl-3.0
|
afab96d4f35cfb16f51ef3dce860b757
| 0.475618 | 4.068856 | false | false | false | false |
nickg/nvc
|
test/regress/assign4.vhd
| 1 | 490 |
entity assign4 is
end entity;
architecture test of assign4 is
type int_vec is array (natural range <>) of integer;
begin
check: process is
variable v : int_vec(1 to 2);
variable a, b : integer;
begin
v := (1, 2);
wait for 1 ns;
(a, b) := v;
wait for 1 ns;
assert a = 1;
assert b = 2;
(a, b) := int_vec'(5, 7);
assert a = 5;
assert b = 7;
wait;
end process;
end architecture;
|
gpl-3.0
|
da444dc6d00ec43a0eb3fb3257c45af5
| 0.502041 | 3.5 | false | false | false | false |
nickg/nvc
|
test/regress/protected3.vhd
| 5 | 1,073 |
entity protected3 is
end entity;
architecture test of protected3 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
procedure do_inc(p : inout SharedCounter) is
begin
p.increment;
end procedure;
shared variable x : SharedCounter;
begin
process is
begin
do_inc(x);
assert x.value = 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
087c5c94c69eea79f1701fb2efa0cc17
| 0.607642 | 5.061321 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_03.vhd
| 4 | 1,416 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
|
gpl-2.0
|
8e011b44b771e0861239b7204409be62
| 0.601695 | 3.94429 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/pkg01/tb_mixer.vhdl
| 2 | 561 |
library ieee;
use ieee.std_logic_1164.all;
entity tb_mixer is
end tb_mixer;
architecture behav of tb_mixer is
signal h, l, o : std_logic_vector (7 downto 0);
begin
dut : entity work.mixer
port map (h => h, l => l, o => o);
process
begin
h <= x"00";
l <= x"ab";
wait for 1 ns;
assert o = x"0b" severity failure;
h <= x"50";
l <= x"a6";
wait for 1 ns;
assert o = x"56" severity failure;
h <= x"a3";
l <= x"5c";
wait for 1 ns;
assert o = x"af" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
c11905391e75c3c554e10fa56f89f8f1
| 0.56328 | 2.906736 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd
| 4 | 1,430 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_srff-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of synch_sr_ff is
begin
behavior : process (clk) is
constant Tpd_clk_out : time := 3 ns;
begin
if rising_edge(clk) then
if To_X01(clr) = '1' then
q <= '0' after Tpd_clk_out;
elsif To_X01(set) = '1' then
q <= '1' after Tpd_clk_out;
end if;
end if;
end process behavior;
end architecture behavioral;
|
gpl-2.0
|
2fdd238c47d552912071797b5d741358
| 0.604196 | 4.016854 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_realign.vhd
| 3 | 59,969 |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_fifo;
use axi_datamover_v5_1_10.axi_datamover_s2mm_dre;
use axi_datamover_v5_1_10.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1_10.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
gpl-3.0
|
6dcab4f1e67dbcd877945eb205893c3f
| 0.427438 | 4.893831 | false | false | false | false |
nickg/nvc
|
test/regress/conv8.vhd
| 1 | 1,865 |
package pack is
type rec is record
x, y : natural;
end record;
type rec_array is array (natural range <>) of rec;
function rec_array_to_int (r : rec_array) return natural;
function int_to_rec_array (x : natural) return rec_array;
end package;
package body pack is
function rec_array_to_int (r : rec_array) return natural is
variable sum : natural;
begin
for i in r'range loop
sum := sum + r(i).x + r(i).y;
end loop;
return sum;
end function;
function int_to_rec_array (x : natural) return rec_array is
variable r : rec_array(1 to 3);
begin
for i in 1 to 3 loop
r(i).x := x / i;
r(i).y := x * i;
end loop;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
i1 : in rec_array(1 to 3);
i2 : in natural );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert i1 = (1 to 3 => (0, 0));
assert i2 = 0;
wait for 0 ns;
assert i1 = ((10, 10), (5, 20), (3, 30));
assert i2 = 21;
wait for 2 ns;
assert i2 = 22;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity conv8 is
end entity;
architecture test of conv8 is
signal s1 : natural;
signal s2 : rec_array(1 to 3);
begin
uut: entity work.sub
port map (
i1 => int_to_rec_array(s1),
i2 => rec_array_to_int(s2) );
main: process is
begin
s2 <= ((1, 2), (3, 4), (5, 6));
s1 <= 10;
wait for 1 ns;
s2(2).y <= 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
6c598a1acef7e1d61d38bccedcf18812
| 0.484182 | 3.579655 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/i2c_ctrl.vhd
| 1 | 5,379 |
-- Controller for the I2C master.
-- This is mostly a state machine used to control
-- the various muxes and registers used for the I2C
-- device.
-- Author: Kevin Johnson. Last modified: 18 June 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_ctrl is
port(
resetn : in std_logic;
clk : in std_logic;
IO_DATA : in std_logic_vector(15 downto 0);
wr_rdy : in std_logic;
wr_cmd : in std_logic;
wr_data : in std_logic;
rx_byte : in std_logic_vector(7 downto 0);
i2c_busy : in std_logic;
tx_addr : out std_logic_vector(7 downto 0);
tx_byte : out std_logic_vector(7 downto 0);
comm_en : out std_logic;
rnw : out std_logic;
data_out : out std_logic_vector(15 downto 0);
busy : out std_logic
);
end entity;
architecture main of i2c_ctrl is
-- Build an enumerated type for the state machine
type state_type is (idle, Tx2, Tx1p, Tx1, Rx2, Rx1p, Rx1);
-- Register used to hold the current state
signal state : state_type;
signal go : std_logic; -- tells state machine when to leave idle
signal running : std_logic; -- flag that communication is in progress
signal prev_busy : std_logic; -- previous value of i2c_busy
signal cmd_in : std_logic_vector(7 downto 0);
signal addr_in : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(15 downto 0);
begin
-- latches for the cmd/data from SCOMP:
latch_cmd_data : process (wr_cmd, wr_data, resetn)
begin
if (resetn = '0') then
cmd_in <= x"00";
elsif rising_edge(wr_cmd) then
cmd_in <= IO_DATA(15 downto 8);
addr_in <= IO_DATA(7 downto 0);
end if;
if (resetn = '0') then
data_in <= x"0000";
elsif rising_edge(wr_data) then
data_in <= IO_DATA;
end if;
end process;
-- This process handles the START signal, which
-- is basically a DFF that gets set by wr_rdy, and reset
-- by a signal from the other state machine. The other
-- state machine checks this to determine if it should start,
-- and resets this once it has started.
latch_rdy : process (wr_rdy, running, resetn)
begin
if (resetn = '0') OR (running = '1') then
go <= '0';
elsif rising_edge(wr_rdy) then
go <= '1';
end if;
end process;
busy <= running OR go;
-- The main state machine
state_machine : process (clk, resetn)
begin
if resetn = '0' then
state <= idle;
comm_en <= '0';
running <= '0';
elsif (rising_edge(clk)) then
prev_busy <= i2c_busy; -- used to detect transitions
case state is
when idle =>
if go = '1' then -- this is the signal to start
running <= '1';
tx_addr <= addr_in; -- set the I2C controller's address
data_out(15 downto 0) <= x"0000"; -- clear data
-- transition to the correct state according to cmd
if cmd_in(5 downto 4) = "10" then -- two to send
state <= Tx2;
tx_byte <= data_in(15 downto 8);
rnw <= '0';
elsif cmd_in(5 downto 4) = "01" then -- one to send
state <= Tx1p;
tx_byte <= data_in(7 downto 0);
rnw <= '0';
elsif cmd_in(1 downto 0) = "10" then -- two to rx
state <= Rx2;
rnw <= '1';
elsif cmd_in(1 downto 0) = "01" then -- one to rx
state <= Rx1p;
rnw <= '1';
else -- invalid command
state <= idle;
end if;
else -- not starting
state <= idle;
running <= '0'; -- no longer running
end if;
when Tx2 =>
comm_en <= '1'; -- safe to start transaction
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
tx_byte <= data_in(7 downto 0); -- prepare next byte
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= Tx1;
end if;
when Tx1p =>
comm_en <= '1'; -- begin communication
state <= Tx1;
when Tx1 =>
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
rnw <= '1'; -- prepare to read
if cmd_in(1) = cmd_in(0) then -- probably 00 read, but also handles 11
comm_en <= '0'; -- end communication
end if;
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
if cmd_in(1 downto 0) = "10" then
state <= Rx2;
elsif cmd_in(1 downto 0) = "01" then
state <= Rx1;
else
state <= idle;
end if;
end if;
when Rx2 =>
comm_en <= '1'; -- safe to start transaction
if (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= Rx1;
data_out(15 downto 8) <= rx_byte; -- store the rx'd byte
end if;
when Rx1p =>
comm_en <= '1'; -- begin communication
state <= Rx1;
when Rx1 =>
if (prev_busy = '0') and (i2c_busy = '1') then -- busy just went high
comm_en <= '0'; -- end communication
elsif (prev_busy = '1') and (i2c_busy = '0') then -- just went low
state <= idle;
data_out(7 downto 0) <= rx_byte; -- store the rx'd byte
end if;
when others =>
state <= idle;
end case;
end if;
end process;
end main;
|
mit
|
727180189e9d20cda8d32b5a9c7073a3
| 0.549916 | 3.123693 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/memmux01/tb_memmux03.vhdl
| 1 | 1,221 |
entity tb_memmux03 is
end tb_memmux03;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux03 is
signal wen : std_logic;
signal addr : std_logic_vector (3 downto 0);
signal rdat : std_logic;
signal wdat : std_logic_vector (12 downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
dut : entity work.memmux03
port map (
wen => wen,
addr => addr,
rdat => rdat,
wdat => wdat,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
constant c : std_logic_vector (12 downto 0) := b"1_0101_1100_1001";
begin
rst <= '1';
wen <= '0';
wdat <= c;
addr <= x"0";
pulse;
rst <= '0';
pulse;
assert rdat = '0' severity failure;
addr <= x"3";
wen <= '1';
pulse;
assert rdat = '0' severity failure;
wen <= '0';
pulse;
assert rdat = '1' severity failure;
for i in c'range loop
addr <= std_logic_vector (to_unsigned (i, 4));
pulse;
assert rdat = c(i) severity failure;
end loop;
wait;
end process;
end behav;
|
gpl-2.0
|
9dbdac92c5d8ef9a133a9ed8809aebce
| 0.55774 | 3.308943 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/sip_check_data/async_fifo_align_64in_out/synth/async_fifo_align_64in_out.vhd
| 1 | 38,656 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY async_fifo_align_64in_out IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END async_fifo_align_64in_out;
ARCHITECTURE async_fifo_align_64in_out_arch OF async_fifo_align_64in_out IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF async_fifo_align_64in_out_arch : ARCHITECTURE IS "async_fifo_align_64in_out,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "async_fifo_align_64in_out,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=510,C_PROG_FULL_THRESH_NEGATE_VAL=509,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 9,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 510,
C_PROG_FULL_THRESH_NEGATE_VAL => 509,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 9,
C_RD_DEPTH => 512,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 9,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 9,
C_WR_DEPTH => 512,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 9,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END async_fifo_align_64in_out_arch;
|
mit
|
1eaff4bbe06463a566993c589819ad80
| 0.628466 | 2.914794 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/fsm01/tb_fsm_3s.vhdl
| 1 | 887 |
entity tb_fsm_3s is
end tb_fsm_3s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_3s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_3s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"101_101_1100";
constant res : std_logic_vector := b"001_001_0000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
|
gpl-2.0
|
78aab01446f979f8d73e220dc039c333
| 0.564825 | 3.261029 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/lpm_dff_oe0.vhd
| 1 | 4,264 |
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff_oe0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff_oe0 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_dff_oe0;
ARCHITECTURE SYN OF lpm_dff_oe0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 32
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff_oe0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
fa78949be0abd6763edeb3abc3b56ab1
| 0.620075 | 3.518152 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue731/tbadder.vhdl
| 1 | 529 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.env.all;
entity tbAdder is
end entity tbAdder;
architecture Bhv of tbAdder is
constant cWidth : natural := 8;
signal iA, iB : std_ulogic_vector(cWidth-1 downto 0) := (others => '0');
signal oRes : std_ulogic_vector(cWidth-1 downto 0);
signal oCarry : std_ulogic;
begin
UUT: entity work.Adder
generic map(
gWidth => cWidth
)
port map(
iA => iA,
iB => iB,
oCarry => oCarry,
oRes => oRes
);
end architecture Bhv;
|
gpl-2.0
|
be5f0a3eedf420a0e68a218f7e256dd5
| 0.657845 | 2.81383 | false | false | false | false |
nickg/nvc
|
test/regress/vests32.vhd
| 1 | 5,724 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1785.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n07i01785pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n07i01785pkg;
use work.c09s06b00x00p04n07i01785pkg.all;
entity c09s06b00x00p04n07i01785ent_a is
port (
port_0 : in Boolean ;
port_1 : in Bit ;
port_2 : in Character ;
port_3 : in SEVERITY_LEVEL ;
port_4 : in Integer ;
port_5 : in Real ;
port_6 : in TIME ;
port_7 : in Natural ;
port_8 : in Positive ;
port_9 : in String ;
port_A : in Bit_vector ;
port_B : in stuff
);
end c09s06b00x00p04n07i01785ent_a;
use work.c09s06b00x00p04n07i01785pkg.all;
architecture c09s06b00x00p04n07i01785arch_a of c09s06b00x00p04n07i01785ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS(port_0,port_1,port_2,port_3,port_4,port_5,port_6,port_7,port_8)
BEGIN
assert NOT( port_0 = True and
port_1 = '0' and
port_2 = '@' and
port_3 = NOTE and
port_4 = 123456789 and
port_5 = 987654321.5 and
port_6 = 110 ns and
port_7 = 12312 and
port_8 = 3423 and
port_9 = "16 characters OK" and
port_A = B"01010010100101010010101001010100" and
port_B = ((123, 456.7), (890, 135.7))
)
report "***PASSED TEST: c09s06b00x00p04n07i01785"
severity NOTE;
assert ( port_0 = True and
port_1 = '0' and
port_2 = '@' and
port_3 = NOTE and
port_4 = 123456789 and
port_5 = 987654321.5 and
port_6 = 110 ns and
port_7 = 12312 and
port_8 = 3423 and
port_9 = "16 characters OK" and
port_A = B"01010010100101010010101001010100" and
port_B = ((123, 456.7), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n07i01785 - Port map aspect associates a single actual with each local port in the corresponding component declaration test failed."
severity ERROR;
END PROCESS TESTING;
end c09s06b00x00p04n07i01785arch_a;
-----------------------------------------------------------------------
ENTITY vests32 IS
END vests32;
use work.c09s06b00x00p04n07i01785pkg.all;
ARCHITECTURE c09s06b00x00p04n07i01785arch OF vests32 IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
signal sig_0 : Boolean := TRUE;
signal sig_1 : Bit := '0';
signal sig_2 : Character := '@';
signal sig_3 : SEVERITY_LEVEL := NOTE;
signal sig_4 : Integer := 123456789;
signal sig_5 : Real := 987654321.5;
signal sig_6 : TIME := 110 NS;
signal sig_7 : Natural := 12312;
signal sig_8 : Positive := 3423;
signal sig_9 : String16 := "16 characters OK";
signal sig_A : REG32 := B"0101_0010_1001_0101_0010_1010_0101_0100";
signal sig_B : stuff := (( 123, 456.7 ), ( 890, 135.7 ));
component MultiType
port (
port_0 : in Boolean ;
port_1 : in Bit ;
port_2 : in Character ;
port_3 : in SEVERITY_LEVEL ;
port_4 : in Integer ;
port_5 : in Real ;
port_6 : in TIME ;
port_7 : in Natural ;
port_8 : in Positive ;
port_9 : in String ;
port_A : in Bit_vector ;
port_B : in stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n07i01785ent_a (c09s06b00x00p04n07i01785arch_a);
BEGIN
u1 : MultiType
port map (
port_0 => sig_0,
port_1 => sig_1,
port_2 => sig_2,
port_3 => sig_3,
port_4 => sig_4,
port_5 => sig_5,
port_6 => sig_6,
port_7 => sig_7,
port_8 => sig_8,
port_9 => sig_9,
port_A => sig_A,
port_B => sig_B
);
END c09s06b00x00p04n07i01785arch;
|
gpl-3.0
|
d324b94dfb5e721d9b6d2a4518ffd49e
| 0.51782 | 3.606805 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_cmd_status.vhd
| 3 | 20,361 |
-------------------------------------------------------------------------------
-- axi_datamover_cmd_status.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
Use axi_datamover_v5_1_10.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_cmd_status;
architecture implementation of axi_datamover_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
CACHE_ENABLE : if C_ENABLE_CACHE_USER = 1 generate
begin
I_CACHE_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
end generate;
CACHE_DISABLE : if C_ENABLE_CACHE_USER = 0 generate
begin
cache2mstr_command <= (others => '0');
end generate CACHE_DISABLE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
gpl-3.0
|
b21b1297aadfc5f45da2ebd2097cec6a
| 0.424341 | 4.939592 | false | false | false | false |
snow4life/PipelinedDLX
|
alu/carry_select_adder/carry_select_block.vhd
| 1 | 1,074 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity CARRY_SELECT_BLOCK is
generic (N: integer);
port ( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
Ci:in std_logic;
S: out std_logic_vector(N-1 downto 0);
Co: out std_logic);
end CARRY_SELECT_BLOCK;
architecture STRUCTURAL of CARRY_SELECT_BLOCK is
signal S0: std_logic_vector(N-1 downto 0);
signal S1: std_logic_vector(N-1 downto 0);
signal C0: std_logic;
signal C1: std_logic;
component RCA_GENERIC
generic (N: integer);
port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
begin
RCA0 : RCA_GENERIC
generic map (N=>N)
port map (A=>A, B=>B, Ci=>'0', S=>S0, Co=>C0);
RCA1 : RCA_GENERIC
generic map (N=>N)
port map (A=>A, B=>B, Ci=>'1', S=>S1, Co=>C1);
S <= S0 when Ci='0' else S1;
Co <= C0 when Ci='0' else C1;
end architecture STRUCTURAL;
|
lgpl-2.1
|
7ab6bed19236980b9bc0f271943e1ec7
| 0.647114 | 2.486111 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue955/tb_ent1.vhdl
| 1 | 979 |
entity tb_ent1 is
end tb_ent1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent1 is
signal clk : std_logic;
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.ent1
port map (clk => clk, o => dout);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = x"10" severity failure;
pulse;
assert dout = x"11" severity failure;
pulse;
assert dout = x"12" severity failure;
pulse;
assert dout = x"13" severity failure;
pulse;
assert dout = x"14" severity failure;
pulse;
assert dout = x"15" severity failure;
pulse;
assert dout = x"16" severity failure;
pulse;
assert dout = x"17" severity failure;
pulse;
assert dout = x"00" severity failure;
pulse;
assert dout = x"00" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
c6935ec9176e99823a6cf487382f8a94
| 0.610827 | 3.534296 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1987.vhd
| 4 | 3,896 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1987.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01987ent IS
END c07s02b02x00p02n01i01987ent;
ARCHITECTURE c07s02b02x00p02n01i01987arch OF c07s02b02x00p02n01i01987ent IS
BEGIN
TESTING: PROCESS
variable r1, r2, r3, r4 : real;
BEGIN
r1 := 69.0;
r2 := 50.0;
r3 := (-69.0);
r4 := (-50.0);
assert NOT( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***PASSED TEST: c07s02b02x00p02n01i01987"
severity NOTE;
assert ( real'high > real'low and
real'high >= real'low and
real'high > 0.0 and
real'high >= 0.0 and
real'low < 0.0 and
real'low <= 0.0 and
real'high /= real'low and
r1 > r2 and
r1 >= r2 and
r1 > 0.0 and
r1 /= r2 and
r2 < r1 and
r2 <= r1 and
r4 > r3 and
r4 >= r3 and
r4 < 0.0 and
r4 /= r3 and
r3 < r4 and
r3 <= r4 and
r1 > r3 and
r2 >= r4 and
r4 < r1 and
r1 /= r3 and
r2 /= r4 and
r3 < r1 and
r4 <= r2 and
3.14E1 > 3.10E1 and
5.7E-9 < 5.7E+9 )
report "***FAILED TEST: c07s02b02x00p02n01i01987 - Relational operators truth table test for data type of Real failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01987arch;
|
gpl-2.0
|
67bcf67ea0b86adcce03756a3f72d834
| 0.434805 | 3.868918 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/dff01/tb_dff13.vhdl
| 1 | 722 |
entity tb_dff13 is
end tb_dff13;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff13 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff13
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
0a8e7bfbab4d0db79448d2c6968b7795
| 0.567867 | 3.389671 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1069/tdp_ram_single2.vhdl
| 1 | 2,517 |
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH_A : positive := 10;
WIDTH_A : positive := 32;
ADDRWIDTH_B : positive := 10;
WIDTH_B : positive := 32;
COL_WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
byteen_a : in std_logic_vector(WIDTH_A/COL_WIDTH - 1 downto 0);
addr_a : in std_logic_vector(ADDRWIDTH_A - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH_A - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH_A - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
function log2(val : INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
res := i;
exit;
end if;
end loop;
return res;
end function log2;
function eq_assert(x : integer; y : integer) return integer is
begin
assert x = y;
return x;
end function eq_assert;
constant COLS_A : positive := WIDTH_A / COL_WIDTH;
constant TOTAL_COLS : positive := COLS_A * 2 ** ADDRWIDTH_A;
constant EXTRA_ADDR_BITS_A : positive := log2(COLS_A);
type ram_t is array(0 to TOTAL_COLS - 1) of std_logic_vector(COL_WIDTH - 1 downto 0);
shared variable store : ram_t := (others => (others => '0'));
signal reg_a : std_logic_vector(WIDTH_A - 1 downto 0);
begin
assert WIDTH_A mod COL_WIDTH = 0 and
2 ** (ADDRWIDTH_A + EXTRA_ADDR_BITS_A) = TOTAL_COLS
report "WIDTH_A have to be a power-of-two multiple of COL_WIDTH"
severity failure;
process(clk_a)
begin
if rising_edge(clk_a) then
for i in 0 to COLS_A - 1 loop
if write_a = '1' and byteen_a(i) = '1' then
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A))) :=
data_write_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_a = '1' then
reg_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A)));
end if;
end loop;
data_read_a <= reg_a;
end if;
end process;
end behavioral;
|
gpl-2.0
|
b245a2efd490cdbb00a2bce212ffa0a8
| 0.52801 | 3.51046 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue406/queuep.vhdl
| 1 | 2,098 |
library ieee;
use ieee.std_logic_1164.all;
package QueueP is
generic (
type QUEUE_TYPE;
function to_string(d : in QUEUE_TYPE) return string
);
-- simple queue interface
type t_simple_queue is protected
procedure push (data : in QUEUE_TYPE);
procedure pop (data : out QUEUE_TYPE);
impure function is_empty return boolean;
impure function is_full return boolean;
end protected t_simple_queue;
end package QueueP;
package body QueueP is
-- simple queue implementation
-- inspired by noasic article http://noasic.com/blog/a-simple-fifo-using-vhdl-protected-types/
type t_simple_queue is protected body
constant C_QUEUE_DEPTH : natural := 64;
type t_queue_array is array (0 to C_QUEUE_DEPTH-1) of QUEUE_TYPE;
variable v_queue : t_queue_array;
variable v_count : natural range 0 to t_queue_array'length := 0;
variable v_head : natural range 0 to t_queue_array'high := 0;
variable v_tail : natural range 0 to t_queue_array'high := 0;
-- write one entry into queue
procedure push (data : in QUEUE_TYPE) is
begin
assert not(is_full)
report "push into full queue -> discarded"
severity failure;
v_queue(v_head) := data;
v_head := (v_head + 1) mod t_queue_array'length;
v_count := v_count + 1;
end procedure push;
-- read one entry from queue
procedure pop (data : out QUEUE_TYPE) is
begin
assert not(is_empty)
report "pop from empty queue -> discarded"
severity failure;
data := v_queue(v_tail);
v_tail := (v_tail + 1) mod t_queue_array'length;
v_count := v_count - 1;
end procedure pop;
-- returns true if queue is empty, false otherwise
impure function is_empty return boolean is
begin
return v_count = 0;
end function is_empty;
-- returns true if queue is full, false otherwise
impure function is_full return boolean is
begin
return v_count = t_queue_array'length;
end function is_full;
end protected body t_simple_queue;
end package body QueueP;
|
gpl-2.0
|
52b330cafbcc5d01b2574fa6f9bb7d4b
| 0.654433 | 3.674256 | false | false | false | false |
nickg/nvc
|
test/sem/textio.vhd
| 1 | 1,664 |
package textio is
type line is access string;
type text is file of string;
type side is (RIGHT, LEFT);
subtype width is natural;
file input : text open READ_MODE is "STD_INPUT";
file output : text open WRITE_MODE is "STD_OUTPUT";
end package;
package body textio is
procedure grow (l : inout line;
extra : in natural;
old_size : out natural ) is
variable tmp : line;
begin
if l = null then
l := new string(1 to extra);
old_size := 0;
elsif extra > 0 then
old_size := l'length;
tmp := new string(1 to l'length + extra); -- OK
tmp(1 to l'length) := l.all;
deallocate(l);
l := tmp;
end if;
end procedure;
procedure shrink (l : inout line; size : in natural) is
variable tmp : line;
begin
assert l /= null;
if size < l'length then
tmp := new string(1 to size);
tmp.all := l.all(1 to size);
deallocate(l);
l := tmp;
end if;
end procedure;
procedure consume (l : inout line; nchars : in natural) is
variable tmp : line;
begin
if nchars = 0 then
return;
end if;
assert l /= null;
if nchars = l'length then
tmp := new string'("");
else
assert nchars <= l'length;
tmp := new string(1 to l'length - nchars); -- OK
tmp.all := l.all(1 + nchars to l'length);
end if;
deallocate(l);
l := tmp;
end procedure;
end package body;
|
gpl-3.0
|
8549911382d76ac5ed34650aadc122f9
| 0.499399 | 4.180905 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/func01/func04.vhdl
| 1 | 576 |
library ieee;
use ieee.std_logic_1164.all;
entity func04 is
port (a : std_logic_vector (7 downto 0);
b : std_logic_vector (7 downto 0);
r : out std_logic_vector (7 downto 0));
end func04;
architecture behav of func04 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (len - 1 downto 0);
begin
res := (0 | 1 => '0', others => '1');
return res;
end gen_mask;
constant mask : std_logic_vector(7 downto 0) := not gen_mask (8);
begin
r <= (a and mask) or (b and gen_mask (8));
end behav;
|
gpl-2.0
|
fb2669178975e7caedc3f04a36fe8844
| 0.625 | 3.130435 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug040/rgb_buf.vhd
| 2 | 1,395 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity rgb_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end rgb_buf;
architecture augh of rgb_buf is
-- Embedded RAM
type ram_type is array (0 to 1023) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
gpl-2.0
|
6ab9b6289a098be2a66579eda7ed1e9e
| 0.670251 | 2.882231 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug22868/works.vhdl
| 3 | 511 |
library ieee;
use ieee.std_logic_1164.all;
entity works is
generic (
width : integer := 8
);
port(
x : in std_logic;
y : out std_logic_vector(width-1 downto 0);
z : out std_logic
);
end works;
architecture a of works is
component subcomponent is
generic (
w : integer
);
port(
x : in std_logic;
y : out std_logic_vector(w-1 downto 0)
);
end component;
begin
s : subcomponent
generic map(
w => width+1
)
port map(
x => x,
y(8 downto 1) => y,
y(0) => z
);
end a;
|
gpl-2.0
|
db9ee1ca5fd6b199e20f33664f536f54
| 0.600783 | 2.504902 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd
| 4 | 2,123 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p12n01i03165ent IS
END c14s01b00x00p12n01i03165ent;
ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
subtype abc is real range 0.0 to 20.0;
subtype cba is real range 20.0 downto 0.0;
subtype xyz is real range 20.0 to 0.0;
subtype zyx is real range 0.0 downto 20.0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***PASSED TEST: c14s01b00x00p12n01i03165"
severity NOTE;
assert ( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p12n01i03165arch;
|
gpl-2.0
|
56641583f39baada085edfd65371049a
| 0.635422 | 3.616695 | false | true | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/syn/vhdl/doHistStretch_fmul_32ns_32ns_32_4_max_dsp.vhd
| 5 | 3,113 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity doHistStretch_fmul_32ns_32ns_32_4_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 4;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of doHistStretch_fmul_32ns_32ns_32_4_max_dsp is
--------------------- Component ---------------------
component doHistStretch_ap_fmul_2_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
doHistStretch_ap_fmul_2_max_dsp_32_u : component doHistStretch_ap_fmul_2_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
60a57b52c70ec0a08dad925a2d17732d
| 0.484099 | 3.662353 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/fsm01/tb_fsm_5s.vhdl
| 1 | 897 |
entity tb_fsm_5s is
end tb_fsm_5s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_5s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_5s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"10010_10010_11000";
constant res : std_logic_vector := b"00001_00001_00000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
|
gpl-2.0
|
7d6641f0aa2248cb9d9e69bfbf0e3f73
| 0.569677 | 3.297794 | false | false | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_mm_bridge_0/pr_region_alternate_mm_bridge_0_inst.vhd
| 1 | 4,672 |
component pr_region_alternate_mm_bridge_0 is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_logic := 'X'; -- clk
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
m0_write : out std_logic; -- write
m0_read : out std_logic; -- read
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
reset : in std_logic := 'X'; -- reset
s0_waitrequest : out std_logic; -- waitrequest
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
s0_readdatavalid : out std_logic; -- readdatavalid
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
s0_write : in std_logic := 'X'; -- write
s0_read : in std_logic := 'X'; -- read
s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
s0_debugaccess : in std_logic := 'X' -- debugaccess
);
end component pr_region_alternate_mm_bridge_0;
u0 : component pr_region_alternate_mm_bridge_0
generic map (
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE
)
port map (
clk => CONNECTED_TO_clk, -- clk.clk
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
m0_address => CONNECTED_TO_m0_address, -- .address
m0_write => CONNECTED_TO_m0_write, -- .write
m0_read => CONNECTED_TO_m0_read, -- .read
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess
reset => CONNECTED_TO_reset, -- reset.reset
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
s0_address => CONNECTED_TO_s0_address, -- .address
s0_write => CONNECTED_TO_s0_write, -- .write
s0_read => CONNECTED_TO_s0_read, -- .read
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess
);
|
mit
|
d3cef47a27d5fc217f01ebf09c2b604a
| 0.494435 | 3.786062 | false | false | false | false |
nickg/nvc
|
test/regress/assign5.vhd
| 1 | 1,247 |
entity assign5 is
end entity;
architecture test of assign5 is
type rec1 is record
x : bit;
y : bit_vector(1 to 3);
z : integer;
end record;
type rec2 is record
x : rec1;
y : character;
end record;
type bv2d is array (natural range <>) of bit_vector(1 to 2);
begin
p1: process is
variable a : bit;
variable b : bit_vector(1 to 3);
variable c : integer;
variable d : character;
variable p, q, r : bit;
variable r1 : rec1;
variable r2 : rec2;
begin
r1 := ('1', "010", 42);
(a, b, c) := r1;
wait for 1 ns;
assert a = '1';
assert b = "010";
assert c = 42;
r2 := (('0', "100", 72), 'Z');
((a, b, c), d) := r2;
wait for 1 ns;
assert a = '0';
assert b = "100";
assert c = 72;
assert d = 'Z';
(a, (p, q, r), c) := r1;
wait for 1 ns;
assert a = '1';
assert p = '0';
assert q = '1';
assert r = '0';
assert c = 42;
(b(1 to 2), (q, r)) := bv2d'( "10", "01" );
wait for 1 ns;
assert b = "100";
wait;
end process;
end architecture;
|
gpl-3.0
|
5813ab82c7b6c86f74411d48858cf738
| 0.438653 | 3.334225 | false | false | false | false |
nickg/nvc
|
test/regress/func2.vhd
| 1 | 1,247 |
entity func2 is
end entity;
architecture rtl of func2 is
type int_array is array (integer range <>) of integer;
function len(x : int_array) return integer is
begin
return x'length;
end function;
function sum(x : int_array) return integer is
variable tmp : integer := 0;
begin
for i in x'range loop
tmp := tmp + x(i);
end loop;
return tmp;
end function;
function asc(x : int_array) return boolean is
begin
return x'ascending;
end function;
function get_low(x : int_array) return integer is
begin
return x'low;
end function;
function get_high(x : int_array) return integer is
begin
return x'high;
end function;
begin
process is
variable u : int_array(5 downto 1) := (6, 3, 1, 1, 2);
variable v : int_array(1 to 5) := (3, 5, 6, 1, 2);
begin
assert len(v) = 5;
assert sum(v) = 17;
assert len(u) = 5;
assert sum(u) = 13;
assert asc(v);
assert get_low(u) = 1;
assert get_low(v) = 1;
assert get_high(u) = 5;
assert get_high(v) = 5;
assert not asc(u);
wait;
end process;
end architecture;
|
gpl-3.0
|
af65896f95c7d2435c97ce824429bdc0
| 0.551724 | 3.583333 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/oper01/uns01.vhdl
| 1 | 426 |
entity uns01 is
port (ok : out boolean);
end uns01;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of uns01 is
-- add uns uns
constant a : unsigned (7 downto 0) := x"1e";
constant b : unsigned (3 downto 0) := x"2";
constant r1 : unsigned (7 downto 0) := a - b;
signal er1 : unsigned (7 downto 0);
begin
er1 <= x"1c";
-- ok <= r1 = x"20";
ok <= r1 = er1;
end behav;
|
gpl-2.0
|
4794fdfed68aed3c458ed98a81281da3
| 0.624413 | 2.784314 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1295/issue.vhdl
| 1 | 1,648 |
library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b, c : std_logic;
begin
-- 012345678901234
SEQ_A : sequencer generic map ("_-______________-____") port map (clk, a);
SEQ_B : sequencer generic map ("--___--__----________") port map (clk, b);
SEQ_C : sequencer generic map ("_____-___---_____----") port map (clk, c);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
assert_NEXT_EVENT_a : assert always ((a and b) -> next_event_a(c)[1 to 4](b));
end architecture psl;
|
gpl-2.0
|
fa774c0df80f63fe2814747100450ea3
| 0.559466 | 3.544086 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/sip_check_data/data_check.vhd
| 1 | 7,212 |
-------------------------------------------------------------------------------------
-- FILE NAME : data_check.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity data_check is
port (
clk_in : in std_logic;
rst_in : in std_logic;
data_in : in std_logic_vector(63 downto 0);
valid_in : in std_logic;
check_en_in : in std_logic;
status_out : out std_logic_vector(7 downto 0)
);
end data_check;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of data_check is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type state_machine is (HOLD_CMD, BYTE0_CMD, BYTE1_CMD, BYTE2_CMD);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal recv_sm_reg : state_machine;
signal byte_in : bus008(7 downto 0);
signal byte_check : bus008(7 downto 0);
signal byte_error : std_logic_vector(7 downto 0);
signal run_test : std_logic;
signal valid_reg : std_logic;
signal data_reg : std_logic_vector(63 downto 0);
signal samples8bit : bus008(7 downto 0) := (others=>(others=>'0'));
signal base_cnt : std_logic_vector(7 downto 0);
signal generate_data : std_logic_vector(63 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
run_test <= check_en_in;
status_out(7 downto 0) <= byte_error(7 downto 0);
-------------------------------------------------------------------------------------
-- Counter process
-------------------------------------------------------------------------------------
process(clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
for I in 0 to 7 loop
byte_in(I) <= (others=>'0');
byte_check(I) <= (others=>'0');
end loop;
valid_reg <= '0';
base_cnt <= (others=>'0');
data_reg <= (others=>'0');
byte_error <= (others=>'0');
else
base_cnt <= data_in(7 downto 0);
data_reg <= data_in;
valid_reg <= valid_in;
byte_in(0) <= data_reg(7 downto 0);
byte_in(1) <= data_reg(15 downto 8);
byte_in(2) <= data_reg(23 downto 16);
byte_in(3) <= data_reg(31 downto 24);
byte_in(4) <= data_reg(39 downto 32);
byte_in(5) <= data_reg(47 downto 40);
byte_in(6) <= data_reg(55 downto 48);
byte_in(7) <= data_reg(63 downto 56);
if run_test = '1' and valid_reg = '1' then
base_cnt <= base_cnt + 2;
byte_check(0) <= base_cnt + 0;
byte_check(1) <= base_cnt + 0;
byte_check(2) <= base_cnt + 0;
byte_check(3) <= base_cnt + 0;
byte_check(4) <= base_cnt + 1;
byte_check(5) <= base_cnt + 1;
byte_check(6) <= base_cnt + 1;
byte_check(7) <= base_cnt + 1;
else
byte_check(0) <= data_reg(7 downto 0);
byte_check(1) <= data_reg(15 downto 8);
byte_check(2) <= data_reg(23 downto 16);
byte_check(3) <= data_reg(31 downto 24);
byte_check(4) <= data_reg(39 downto 32);
byte_check(5) <= data_reg(47 downto 40);
byte_check(6) <= data_reg(55 downto 48);
byte_check(7) <= data_reg(63 downto 56);
end if;
for I in 0 to 7 loop
if byte_in(I) /= byte_check(I) and run_test = '1' and valid_reg = '1' then
byte_error(I) <= '1';
end if;
end loop;
end if;
end if;
end process;
--process(clk_in, rst_in)
--begin
-- if rising_edge(clk_in) then
-- if rst_in = '1' then
-- base_cnt <= (others =>'0');
-- else
-- base_cnt <= base_cnt + 2;
-- end if;
-- end if;
--end process;
--samples8bit(0) <= base_cnt + 0;
--samples8bit(1) <= base_cnt + 0;
--samples8bit(2) <= base_cnt + 0;
--samples8bit(3) <= base_cnt + 0;
--samples8bit(4) <= base_cnt + 1;
--samples8bit(5) <= base_cnt + 1;
--samples8bit(6) <= base_cnt + 1;
--samples8bit(7) <= base_cnt + 1;
-------------------------------------------------------------------------------------
-- Component Instance
-------------------------------------------------------------------------------------
--inst0_vp680_nnn_lx130t:
--entity work.vp680_nnn_lx130t
--generic map (
-- DEBUG => FALSE,
-- ADDRESS => "00010111111"
--)
--port map (
-- gpio_led_8 => ,
-- sys_clk_p_8 => ,
-- sys_clk_n_8 => ,
-- sys_reset_n_8 => ,
-- pci_exp_rxn_8 => ,
-- pci_exp_rxp_8 => ,
-- pci_exp_txn_8 => ,
-- pci_exp_txp_8 => ,
-- fp_cp_8 => ,
-- host_if_i2c_scl_8 =>
--);
-------------------------------------------------------------------------------------
-- Debug
-------------------------------------------------------------------------------------
--generate_debug:
--if (DEBUG_ENABLE = TRUE) generate
--begin
--
--end generate;
--generate_add_loop:
--for I in 0 to 7 generate
-- SUM(I) <= A(I) xor B(I) xor C(I);
-- C(I+1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
--end generate;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
2b9247d7eab7c15783309ef18e6cd415
| 0.354548 | 4.12822 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1109/ent.vhdl
| 1 | 2,980 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic (
INT : integer := -42;
NAT : natural := 21
);
port (
slv_a : in std_logic_vector(7 downto 0);
slv_b : in std_logic_vector(7 downto 0);
slv_eq : out std_logic;
slv_ne : out std_logic;
sl_a : in std_logic;
sl_b : in std_logic;
sl_lt : out std_logic;
sl_le : out std_logic;
sl_eq : out std_logic;
sl_ne : out std_logic;
sl_ge : out std_logic;
sl_gt : out std_logic;
uns_a : in unsigned(7 downto 0);
uns_b : in unsigned(7 downto 0);
uns_lt : out std_logic;
uns_le : out std_logic;
uns_eq : out std_logic;
uns_ne : out std_logic;
uns_ge : out std_logic;
uns_gt : out std_logic;
uns_int_lt : out std_logic;
uns_int_le : out std_logic;
uns_int_eq : out std_logic;
uns_int_ne : out std_logic;
uns_int_ge : out std_logic;
uns_int_gt : out std_logic;
int_uns_lt : out std_logic;
int_uns_le : out std_logic;
int_uns_eq : out std_logic;
int_uns_ne : out std_logic;
int_uns_ge : out std_logic;
int_uns_gt : out std_logic;
sgn_a : in signed(7 downto 0);
sgn_b : in signed(7 downto 0);
sgn_lt : out std_logic;
sgn_le : out std_logic;
sgn_eq : out std_logic;
sgn_ne : out std_logic;
sgn_ge : out std_logic;
sgn_gt : out std_logic;
sgn_nat_lt : out std_logic;
sgn_nat_le : out std_logic;
sgn_nat_eq : out std_logic;
sgn_nat_ne : out std_logic;
sgn_nat_ge : out std_logic;
sgn_nat_gt : out std_logic;
nat_sgn_lt : out std_logic;
nat_sgn_le : out std_logic;
nat_sgn_eq : out std_logic;
nat_sgn_ne : out std_logic;
nat_sgn_ge : out std_logic;
nat_sgn_gt : out std_logic
);
end;
architecture a of ent is
begin
slv_eq <= slv_a ?= slv_b;
slv_ne <= slv_a ?/= slv_b;
sl_lt <= sl_a ?< sl_b;
sl_le <= sl_a ?<= sl_b;
sl_eq <= sl_a ?= sl_b;
sl_ne <= sl_a ?/= sl_b;
sl_ge <= sl_a ?>= sl_b;
sl_gt <= sl_a ?> sl_b;
uns_lt <= uns_a ?< uns_b;
uns_le <= uns_a ?<= uns_b;
uns_eq <= uns_a ?= uns_b;
uns_ne <= uns_a ?/= uns_b;
uns_ge <= uns_a ?>= uns_b;
uns_gt <= uns_a ?> uns_b;
uns_int_lt <= uns_a ?< NAT;
uns_int_le <= uns_a ?<= NAT;
uns_int_eq <= uns_a ?= NAT;
uns_int_ne <= uns_a ?/= NAT;
uns_int_ge <= uns_a ?>= NAT;
uns_int_gt <= uns_a ?> NAT;
int_uns_lt <= NAT ?< uns_b;
int_uns_le <= NAT ?<= uns_b;
int_uns_eq <= NAT ?= uns_b;
int_uns_ne <= NAT ?/= uns_b;
int_uns_ge <= NAT ?>= uns_b;
int_uns_gt <= NAT ?> uns_b;
sgn_lt <= sgn_a ?< sgn_b;
sgn_le <= sgn_a ?<= sgn_b;
sgn_eq <= sgn_a ?= sgn_b;
sgn_ne <= sgn_a ?/= sgn_b;
sgn_ge <= sgn_a ?>= sgn_b;
sgn_gt <= sgn_a ?> sgn_b;
sgn_nat_lt <= sgn_a ?< INT;
sgn_nat_le <= sgn_a ?<= INT;
sgn_nat_eq <= sgn_a ?= INT;
sgn_nat_ne <= sgn_a ?/= INT;
sgn_nat_ge <= sgn_a ?>= INT;
sgn_nat_gt <= sgn_a ?> INT;
nat_sgn_lt <= INT ?< sgn_b;
nat_sgn_le <= INT ?<= sgn_b;
nat_sgn_eq <= INT ?= sgn_b;
nat_sgn_ne <= INT ?/= sgn_b;
nat_sgn_ge <= INT ?>= sgn_b;
nat_sgn_gt <= INT ?> sgn_b;
end;
|
gpl-2.0
|
406887b83107f18884d8f5166ffec8fa
| 0.559732 | 2.202513 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1076/ent3.vhdl
| 1 | 964 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ext_comp.all;
entity ent is
-- This case works.
-- generic ( CONFIG_C1: boolean := false );
port (
i : in std_logic;
o : out std_logic;
q : out std_logic
);
constant CONFIG_C1 : boolean := false;
end;
architecture a of ent is
begin
gen: if false generate
o <= '1';
else generate
o <= '0';
end generate;
maybe_c1:
if CONFIG_C1 generate
c1_inst: c1 port map (i => i, o=> q);
end generate;
maybe_c2:
if not CONFIG_C1 generate
c2_inst: c2 port map (i => i, o=> q);
end generate;
end;
-- Added entities to satisfy simulation:
library ieee;
use ieee.std_logic_1164.all;
entity c1 is
port (i: in std_logic; o : out std_logic);
end entity;
architecture a of c1 is
begin
o <= i;
end a;
library ieee;
use ieee.std_logic_1164.all;
entity c2 is
port (i: in std_logic; o : out std_logic);
end entity;
architecture a of c2 is
begin
o <= i;
end a;
|
gpl-2.0
|
7db0f99c29caddd09b9077aeb74494cb
| 0.641079 | 2.57754 | false | true | false | false |
tgingold/ghdl
|
libraries/ieee2008/math_complex.vhdl
| 3 | 34,106 |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_COMPLEX package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common COMPLEX
-- : constants and common COMPLEX mathematical functions and
-- : operators.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use WORK.MATH_REAL.all;
package MATH_COMPLEX is
constant CopyRightNotice : STRING
:= "Copyright IEEE P1076 WG. Licensed Apache 2.0";
--
-- Type Definitions
--
type COMPLEX is
record
RE : REAL; -- Real part
IM : REAL; -- Imaginary part
end record;
subtype POSITIVE_REAL is REAL range 0.0 to REAL'high;
subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI;
type COMPLEX_POLAR is
record
MAG : POSITIVE_REAL; -- Magnitude
ARG : PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal
end record;
--
-- Constant Definitions
--
constant MATH_CBASE_1 : COMPLEX := COMPLEX'(1.0, 0.0);
constant MATH_CBASE_J : COMPLEX := COMPLEX'(0.0, 1.0);
constant MATH_CZERO : COMPLEX := COMPLEX'(0.0, 0.0);
--
-- Overloaded equality and inequality operators for COMPLEX_POLAR
-- (equality and inequality operators for COMPLEX are predefined)
--
function "=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is equal to R and returns FALSE otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE
-- regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "="(L,R) is either TRUE or FALSE
-- Notes:
-- None
function "/=" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is not equal to R and returns FALSE
-- otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns
-- FALSE regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "/="(L,R) is either TRUE or FALSE
-- Notes:
-- None
--
-- Function Declarations
--
function CMPLX(X : in REAL; Y : in REAL := 0.0) return COMPLEX;
-- Purpose:
-- Returns COMPLEX number X + iY
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- CMPLX(X,Y) is mathematically unbounded
-- Notes:
-- None
function GET_PRINCIPAL_VALUE(X : in REAL) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns principal value of angle X; X in radians
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI
-- Notes:
-- None
function COMPLEX_TO_POLAR(Z : in COMPLEX) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value COMPLEX_POLAR of Z
-- Special values:
-- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0)
-- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM),
-- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function POLAR_TO_COMPLEX(Z : in COMPLEX_POLAR) return COMPLEX;
-- Purpose:
-- Returns COMPLEX value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- POLAR_TO_COMPLEX(Z) is mathematically unbounded
-- Notes:
-- None
function "ABS"(Z : in COMPLEX) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(Z) is mathematically unbounded
-- Notes:
-- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
function "ABS"(Z : in COMPLEX_POLAR) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- ABS(Z) >= 0.0
-- Notes:
-- ABS(Z) = Z.MAG
function ARG(Z : in COMPLEX) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0
-- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0
-- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = ARCTAN(Z.IM, Z.RE)
function ARG(Z : in COMPLEX_POLAR) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = Z.ARG
function "-" (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns unary minus of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- Returns -x -jy for Z= x + jy
function "-" (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of unary minus of Z
-- Special values:
-- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if
-- Z.ARG /= 0.0
function CONJ (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns complex conjugate of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- CONJ(Z) is mathematically unbounded
-- Notes:
-- Returns x -jy for Z= x + jy
function CONJ (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of complex conjugate of Z
-- Special values:
-- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI
function SQRT(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(MATH_CZERO) = MATH_CZERO
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- SQRT(Z) is mathematically unbounded
-- Notes:
-- None
function SQRT(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function EXP(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns exponential of Z
-- Special values:
-- EXP(MATH_CZERO) = MATH_CBASE_1
-- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI
-- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and
-- ABS(Z.IM) = MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- EXP(Z) is mathematically unbounded
-- Notes:
-- None
function EXP(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of exponential of Z
-- Special values:
-- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and
-- Z.ARG = 0.0
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- ABS(Z.ARG) = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns natural logarithm of Z
-- Special values:
-- LOG(MATH_CBASE_1) = MATH_CZERO
-- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI)
-- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2)
-- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2)
-- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG(Z) is mathematically unbounded
-- Notes:
-- None
function LOG2(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns logarithm base 2 of Z
-- Special values:
-- LOG2(MATH_CBASE_1) = MATH_CZERO
-- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG2(Z) is mathematically unbounded
-- Notes:
-- None
function LOG10(Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns logarithm base 10 of Z
-- Special values:
-- LOG10(MATH_CBASE_1) = MATH_CZERO
-- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG10(Z) is mathematically unbounded
-- Notes:
-- None
function LOG(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of natural logarithm of Z
-- Special values:
-- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG2(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 2 of Z
-- Special values:
-- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG10(Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 10 of Z
-- Special values:
-- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z : in COMPLEX; BASE : in REAL) return COMPLEX;
-- Purpose:
-- Returns logarithm base BASE of Z
-- Special values:
-- LOG(MATH_CBASE_1, BASE) = MATH_CZERO
-- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(Z,BASE) is mathematically unbounded
-- Notes:
-- None
function LOG(Z : in COMPLEX_POLAR; BASE : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base BASE of Z
-- Special values:
-- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SIN (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns sine of Z
-- Special values:
-- SIN(MATH_CZERO) = MATH_CZERO
-- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function SIN (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of sine of Z
-- Special values:
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COS (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns cosine of Z
-- Special values:
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0)
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function COS (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of cosine of Z
-- Special values:
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = 0.0
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SINH (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns hyperbolic sine of Z
-- Special values:
-- SINH(MATH_CZERO) = MATH_CZERO
-- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI
-- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = MATH_PI_OVER_2
-- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- SIN(Z.IM)*SIN(Z.IM))
-- Notes:
-- None
function SINH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic sine of Z
-- Special values:
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COSH (Z : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns hyperbolic cosine of Z
-- Special values:
-- COSH(MATH_CZERO) = MATH_CBASE_1
-- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- COS(Z.IM)*COS(Z.IM))
-- Notes:
-- None
function COSH (Z : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic cosine of Z
-- Special values:
-- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
--
-- Arithmetic Operators
--
function "+" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" (L : in COMPLEX; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" (L : in REAL; R : in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" (L : in COMPLEX; R : in REAL) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL and R /= 0.0
-- Error conditions:
-- Error if R = 0.0
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" (L : in COMPLEX_POLAR; R : in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" (L : in REAL; R : in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" (L : in COMPLEX_POLAR; R : in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R /= 0.0
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
end package MATH_COMPLEX;
|
gpl-2.0
|
2b5331a0901b426939eae61cd4df614d
| 0.493667 | 3.596162 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue301/src/acs.vhd
| 7 | 4,334 |
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Add-compare-select unit for trellis processing.
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
--! @details The ACS decides which path is the the surviving trellis path.
--! In the design there are 2^{K-1} ACS instances.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
use dec_viterbi.pkg_helper.all;
entity acs is
generic(
-- Reset value
INITIALIZE_VALUE : in signed(BW_MAX_PROBABILITY - 1 downto 0)
);
port(
clk : in std_logic;
rst : in std_logic;
--
-- Values from branch distance, signed values in std_logic_vector
-- high is located in the upper half.
--
s_axis_inbranch_tvalid : in std_logic;
s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
s_axis_inbranch_tlast : in std_logic;
s_axis_inbranch_tready : out std_logic;
--
-- Probabilities from previous nodes, signed values in std_logic_vector
-- high is located in the upper half.
--
s_axis_inprev_tvalid : in std_logic;
s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
s_axis_inprev_tready : out std_logic;
-- probability result of the add compare and select
m_axis_outprob_tvalid : out std_logic;
m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
m_axis_outprob_tready : in std_logic;
-- decision result of the add compare and select
m_axis_outdec_tvalid : out std_logic;
m_axis_outdec_tdata : out std_logic;
m_axis_outdec_tlast : out std_logic;
m_axis_outdec_tready : in std_logic
);
end entity acs;
architecture rtl of acs is
signal s_axis_inbranch_tlast_d : std_logic;
signal m_axis_outdec_tvalid_int : std_logic;
signal s_axis_inbranch_tready_int : std_logic;
begin
s_axis_inbranch_tready_int <= '1' when m_axis_outdec_tready = '1' or m_axis_outdec_tvalid_int = '0' else
'0';
s_axis_inbranch_tready <= s_axis_inbranch_tready_int;
m_axis_outdec_tvalid <= m_axis_outdec_tvalid_int;
-- Add branch to previous, compare both paths and select survivor.
pr_add_compare : process(clk) is
variable v_diff, v_high, v_low : signed(BW_MAX_PROBABILITY - 1 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
m_axis_outdec_tvalid_int <= '0';
m_axis_outdec_tdata <= '0';
m_axis_outdec_tlast <= '0';
m_axis_outprob_tvalid <= '0';
s_axis_inprev_tready <= '0';
s_axis_inbranch_tlast_d <= '0';
m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
else
-- If this is the last value, prepare for processing of next incoming value.
if s_axis_inbranch_tlast_d = '1' then
m_axis_outprob_tdata <= std_logic_vector(INITIALIZE_VALUE);
s_axis_inbranch_tlast_d <= '0';
m_axis_outdec_tvalid_int <= '0';
end if;
if m_axis_outdec_tvalid_int = '1' and m_axis_outdec_tready = '1' then
m_axis_outdec_tvalid_int <= '0';
end if;
-- Process only if we receive valid data.
if s_axis_inbranch_tvalid = '1' and s_axis_inbranch_tready_int = '1' then
s_axis_inbranch_tlast_d <= s_axis_inbranch_tlast;
-- Add.
v_low := signed(s_axis_inbranch_tdata_low) + signed(s_axis_inprev_tdata_low);
v_high := signed(s_axis_inbranch_tdata_high) + signed(s_axis_inprev_tdata_high);
-- Use modulo normalization, do not extend the sign here!
v_diff := v_low - v_high;
-- Compare, select the correct path.
if v_diff < 0 then
m_axis_outdec_tdata <= '1';
m_axis_outprob_tdata <= std_logic_vector(v_high);
else
m_axis_outdec_tdata <= '0';
m_axis_outprob_tdata <= std_logic_vector(v_low);
end if;
m_axis_outdec_tvalid_int <= '1';
end if;
m_axis_outdec_tlast <= s_axis_inbranch_tlast;
end if;
end if;
end process pr_add_compare;
end architecture rtl;
|
gpl-2.0
|
2546aeba97f87c5b1a2794ce44f4dc81
| 0.659898 | 2.916555 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1253/repro1.vhdl
| 1 | 506 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity repro1 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end repro1;
architecture archi of repro1 is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= std_logic_vector'(1 + signed(tmp));
end if;
end process;
Q <= tmp;
end archi;
|
gpl-2.0
|
cec8f08a399d36dcf9e8571f9ce74435
| 0.579051 | 3.22293 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1243/DSPn.vhdl
| 1 | 21,099 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
entity DSPn is
port(
CLK : in std_logic;
CE : in std_logic;
RST_N : in std_logic;
ENABLE : in std_logic;
A0 : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_N : in std_logic;
RD_N : in std_logic;
WR_N : in std_logic;
DP_ADDR : in std_logic_vector(11 downto 0);
DP_SEL : in std_logic;
VER : in std_logic_vector(2 downto 0);--00-DSP1B, 01-DSP2, 10-DSP3, 11-DSP4
BRK_OUT : out std_logic;
DBG_REG : in std_logic_vector(7 downto 0);
DBG_DAT_IN : in std_logic_vector(7 downto 0);
DBG_DAT_OUT : out std_logic_vector(7 downto 0);
DBG_DAT_WR : in std_logic
);
end DSPn;
architecture rtl of DSPn is
constant ACC_A : integer range 0 to 1 := 0;
constant ACC_B : integer range 0 to 1 := 1;
constant FLAG_OV0 : integer range 0 to 5 := 0;
constant FLAG_OV1 : integer range 0 to 5 := 1;
constant FLAG_Z : integer range 0 to 5 := 2;
constant FLAG_C : integer range 0 to 5 := 3;
constant FLAG_S0 : integer range 0 to 5 := 4;
constant FLAG_S1 : integer range 0 to 5 := 5;
constant INSTR_OP: std_logic_vector(1 downto 0) := "00";
constant INSTR_RT: std_logic_vector(1 downto 0) := "01";
constant INSTR_JP: std_logic_vector(1 downto 0) := "10";
constant INSTR_LD: std_logic_vector(1 downto 0) := "11";
-- IO Registers
signal DR : std_logic_vector(15 downto 0);
signal SR : std_logic_vector(15 downto 0);
signal DP : std_logic_vector(10 downto 0);
signal RP : std_logic_vector(10 downto 0);
signal PC : std_logic_vector(10 downto 0);
type StackRam_t is array (0 to 7) of std_logic_vector(10 downto 0);
signal STACK_RAM : StackRam_t;
signal SP : unsigned(2 downto 0);
signal K, L, M, N : std_logic_vector(15 downto 0);
signal P, Q : std_logic_vector(15 downto 0);
type Acc_t is array (0 to 1) of std_logic_vector(15 downto 0);
signal ACC : Acc_t;
type Flags_t is array (0 to 1) of std_logic_vector(5 downto 0);
signal FLAGS : Flags_t;
signal TR, TRB : std_logic_vector(15 downto 0);
signal SI, SO : std_logic_vector(15 downto 0);
signal SGN : std_logic_vector(15 downto 0);
signal RQM : std_logic;
signal DRS, DRC : std_logic;
signal USF0, USF1 : std_logic;
signal P0, P1 : std_logic;
signal EI, DMA : std_logic;
signal OP_DST : std_logic_vector(3 downto 0);
signal OP_SRC : std_logic_vector(3 downto 0);
signal OP_RP : std_logic;
signal OP_DPH : std_logic_vector(3 downto 0);
signal OP_DPL : std_logic_vector(1 downto 0);
signal OP_A : unsigned(0 downto 0);
signal OP_ALU : std_logic_vector(3 downto 0);
signal OP_P : std_logic_vector(1 downto 0);
signal OP_ID : std_logic_vector(15 downto 0);
signal OP_NA : std_logic_vector(10 downto 0);
signal OP_BRCH : std_logic_vector(8 downto 0);
signal OP_INSTR : std_logic_vector(1 downto 0);
signal IDB : std_logic_vector(15 downto 0);
signal ALU_R : std_logic_vector(15 downto 0);
signal PROG_ROM_ADDR : std_logic_vector(12 downto 0);
signal PROG_ROM_Q : std_logic_vector(23 downto 0);
signal DATA_ROM_ADDR : std_logic_vector(12 downto 0);
signal DATA_ROM_Q : std_logic_vector(15 downto 0);
signal DATA_RAM_ADDR_A, DATA_RAM_ADDR_B : std_logic_vector(10 downto 0);
signal DATA_RAM_Q_A, DATA_RAM_Q_B : std_logic_vector(15 downto 0);
signal DATA_RAM_WE : std_logic;
signal EN : std_logic;
signal RD_Nr, WR_Nr : std_logic_vector(2 downto 0);
signal PORT_ACTIVE : std_logic;
--debug
signal DBG_RUN_LAST : std_logic;
signal DBG_DAT_WRr : std_logic;
signal DBG_BRK_ADDR : std_logic_vector(10 downto 0) := (others => '1');
signal DBG_CTRL : std_logic_vector(7 downto 0) := (others => '0');
component dp16k_wrapper_8bit
generic (
addr_width : natural := 11
);
port (
clock : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data_a : in STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
enable_a : in STD_LOGIC := '1';
wren_a : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (7 DOWNTO 0);
cs_a : in std_logic := '1';
address_b : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0) := (others => '0');
data_b : in STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
enable_b : in STD_LOGIC := '1';
wren_b : in STD_LOGIC := '0';
q_b : out STD_LOGIC_VECTOR (7 DOWNTO 0);
cs_b : in std_logic := '1'
);
end component;
component sprom_verilog is
generic (
addr_width : integer := 8;
data_width : integer := 8;
length : integer := 8;
hex_file : string := ""
);
port
(
clock : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0)
);
end component;
begin
EN <= ENABLE and CE;
OP_INSTR <= PROG_ROM_Q(23 downto 22);
OP_P <= PROG_ROM_Q(21 downto 20);
OP_ALU <= PROG_ROM_Q(19 downto 16);
OP_A <= unsigned(PROG_ROM_Q(15 downto 15));
OP_DPL <= PROG_ROM_Q(14 downto 13);
OP_DPH <= PROG_ROM_Q(12 downto 9);
OP_RP <= PROG_ROM_Q(8);
OP_SRC <= PROG_ROM_Q(7 downto 4);
OP_DST <= PROG_ROM_Q(3 downto 0);
OP_ID <= PROG_ROM_Q(21 downto 6) when OP_INSTR = INSTR_LD else IDB;
OP_NA <= PROG_ROM_Q(12 downto 2);
OP_BRCH <= PROG_ROM_Q(21 downto 13);
SGN <= x"8000" xor (0 to 15 => FLAGS(ACC_A)(FLAG_S1));
SR <= RQM & USF1 & USF0 & DRS & DMA & DRC & "00" & EI & "00000" & P1 & P0;
SI <= (others => '0');
IDB <= TRB when OP_SRC = x"0" else
ACC(ACC_A) when OP_SRC = x"1" else
ACC(ACC_B) when OP_SRC = x"2" else
TR when OP_SRC = x"3" else
"00000" & DP when OP_SRC = x"4" and VER(2) = '1' else
"00000" & RP when OP_SRC = x"5" and VER(2) = '1' else
x"00" & DP(7 downto 0) when OP_SRC = x"4" else
"000000" & RP(9 downto 0) when OP_SRC = x"5" else
DATA_ROM_Q when OP_SRC = x"6" else
SGN when OP_SRC = x"7" else
DR when OP_SRC = x"8" else
DR when OP_SRC = x"9" else
SR when OP_SRC = x"A" else
SI when OP_SRC = x"B" else
SI when OP_SRC = x"C" else
K when OP_SRC = x"D" else
L when OP_SRC = x"E" else
DATA_RAM_Q_A when OP_SRC = x"F" else
x"0000";
--ALU
Q <= ACC(to_integer(OP_A));
P <= x"0001" when OP_ALU(3 downto 1) = "100" else
DATA_RAM_Q_A when OP_P = "00" else
IDB when OP_P = "01" else
M when OP_P = "10" else
N;
process( OP_ALU, P, Q, ALU_R, FLAGS, OP_A)
variable FC : std_logic;
variable CARRY : unsigned(15 downto 0);
begin
FC := FLAGS(to_integer(not OP_A))(FLAG_C);
CARRY := (0 => FC, others => '0');
case OP_ALU is
when x"1" =>
ALU_R <= Q or P;
when x"2" =>
ALU_R <= Q and P;
when x"3" =>
ALU_R <= Q xor P;
when x"4" =>
ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P));
when x"5" =>
ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P));
when x"6" =>
ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P) - CARRY);
when x"7" =>
ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P) + CARRY);
when x"8" =>
ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P));
when x"9" =>
ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P));
when x"A" =>
ALU_R <= not Q;
when x"B" =>
ALU_R <= Q(15) & Q(15 downto 1);
when x"C" =>
ALU_R <= Q(14 downto 0) & FC;
when x"D" =>
ALU_R <= Q(13 downto 0) & "11";
when x"E" =>
ALU_R <= Q(11 downto 0) & "1111";
when x"F" =>
ALU_R <= Q(7 downto 0) & Q(15 downto 8);
when others =>
ALU_R <= Q;
end case;
end process;
--Flags
process(CLK, RST_N)
variable OV0 : std_logic;
begin
if RST_N = '0' then
FLAGS <= (others => (others => '0'));
elsif rising_edge(CLK) then
if EN = '1' then
if (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) and OP_ALU /= x"0" then
FLAGS(to_integer(OP_A))(FLAG_S0) <= ALU_R(15);
if ALU_R = x"0000" then
FLAGS(to_integer(OP_A))(FLAG_Z) <= '1';
else
FLAGS(to_integer(OP_A))(FLAG_Z) <= '0';
end if;
case OP_ALU is
when x"1" | x"2" | x"3" | x"A" | x"D" | x"E" | x"F" =>
FLAGS(to_integer(OP_A))(FLAG_C) <= '0';
when x"4" | x"6" | x"8" =>
if ALU_R > Q then
FLAGS(to_integer(OP_A))(FLAG_C) <= '1';
else
FLAGS(to_integer(OP_A))(FLAG_C) <= '0';
end if;
when x"5" | x"7" | x"9" =>
if ALU_R < Q then
FLAGS(to_integer(OP_A))(FLAG_C) <= '1';
else
FLAGS(to_integer(OP_A))(FLAG_C) <= '0';
end if;
when x"B" =>
FLAGS(to_integer(OP_A))(FLAG_C) <= Q(0);
when x"C" =>
FLAGS(to_integer(OP_A))(FLAG_C) <= Q(15);
when others => null;
end case;
OV0 := (Q(15) xor ALU_R(15)) and ((Q(15) xor P(15)) xor OP_ALU(0));
case OP_ALU is
when x"1" | x"2" | x"3" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" =>
FLAGS(to_integer(OP_A))(FLAG_OV0) <= '0';
FLAGS(to_integer(OP_A))(FLAG_OV1) <= '0';
when x"4" | x"5" | x"6" | x"7" | x"8" | x"9" =>
FLAGS(to_integer(OP_A))(FLAG_OV0) <= OV0;
if OV0 = '1' then
FLAGS(to_integer(OP_A))(FLAG_S1) <= FLAGS(to_integer(OP_A))(FLAG_OV1) xor (not ALU_R(15));
FLAGS(to_integer(OP_A))(FLAG_OV1) <= not FLAGS(to_integer(OP_A))(FLAG_OV1);
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
--Multiplier
process(K, L)
variable TEMP : signed(30 downto 0);
begin
TEMP := resize((signed(K) * signed(L)),TEMP'length);
M <= std_logic_vector(TEMP(30 downto 15));
N <= std_logic_vector(TEMP(14 downto 0)) & "0";
end process;
--Registers
process(CLK, RST_N)
variable DAT : std_logic_vector(15 downto 0);
begin
if RST_N = '0' then
ACC <= (others => (others => '0'));
TR <= (others => '0');
DP <= (others => '0');
RP <= (others => '1');
DRC <= '0';
USF1 <= '0';
USF0 <= '0';
DMA <= '0';
EI <= '0';
P1 <= '0';
P0 <= '0';
TRB <= (others => '0');
SO <= (others => '0');
K <= (others => '0');
L <= (others => '0');
elsif rising_edge(CLK) then
if EN = '1' then
if (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) then
if OP_ALU /= x"0" then
ACC(to_integer(OP_A)) <= ALU_R;
end if;
case OP_DPL is
when "01" =>
DP(3 downto 0) <= std_logic_vector(unsigned(DP(3 downto 0)) + 1);
when "10" =>
DP(3 downto 0) <= std_logic_vector(unsigned(DP(3 downto 0)) - 1);
when "11" =>
DP(3 downto 0) <= (others => '0');
when others => null;
end case;
DP(7 downto 4) <= DP(7 downto 4) xor OP_DPH;
if OP_RP = '1' then
RP <= std_logic_vector(unsigned(RP) - 1);
end if;
end if;
if OP_INSTR /= INSTR_JP then
case OP_DST is
when x"1" =>
ACC(ACC_A) <= OP_ID;
when x"2" =>
ACC(ACC_B) <= OP_ID;
when x"3" =>
TR <= OP_ID;
when x"4" =>
DP <= OP_ID(10 downto 0);
when x"5" =>
RP <= OP_ID(10 downto 0);
when x"7" =>
USF1 <= OP_ID(14);
USF0 <= OP_ID(13);
DMA <= OP_ID(11);
DRC <= OP_ID(10);
EI <= OP_ID(7);
P1 <= OP_ID(1);
P0 <= OP_ID(0);
when x"8" =>
SO <= OP_ID;
when x"9" =>
SO <= OP_ID;
when x"A" =>
K <= OP_ID;
when x"B" =>
K <= OP_ID;
L <= DATA_ROM_Q;
when x"C" =>
K <= DATA_RAM_Q_B;
L <= OP_ID;
when x"D" =>
L <= OP_ID;
when x"E" =>
TRB <= OP_ID;
when others => null;
end case;
end if;
end if;
end if;
end process;
process(CLK, RST_N)
variable NEXT_SP : unsigned(2 downto 0);
variable NEXT_PC : std_logic_vector(10 downto 0);
variable COND : std_logic;
begin
if RST_N = '0' then
STACK_RAM <= (others => (others => '0'));
SP <= (others => '0');
PC <= (others => '0');
elsif rising_edge(CLK) then
if EN = '1' then
NEXT_PC := std_logic_vector(unsigned(PC) + 1);
if OP_INSTR = INSTR_RT then
NEXT_SP := SP - 1;
PC <= STACK_RAM(to_integer((NEXT_SP(2) and VER(2))&NEXT_SP(1 downto 0)));
SP <= NEXT_SP;
elsif OP_INSTR = INSTR_JP then
case OP_BRCH(5 downto 2) is
when "0000" =>
COND := FLAGS(ACC_A)(FLAG_C) xor (not OP_BRCH(1));
when "0001" =>
COND := FLAGS(ACC_B)(FLAG_C) xor (not OP_BRCH(1));
when "0010" =>
COND := FLAGS(ACC_A)(FLAG_Z) xor (not OP_BRCH(1));
when "0011" =>
COND := FLAGS(ACC_B)(FLAG_Z) xor (not OP_BRCH(1));
when "0100" =>
COND := FLAGS(ACC_A)(FLAG_OV0) xor (not OP_BRCH(1));
when "0101" =>
COND := FLAGS(ACC_B)(FLAG_OV0) xor (not OP_BRCH(1));
when "0110" =>
COND := FLAGS(ACC_A)(FLAG_OV1) xor (not OP_BRCH(1));
when "0111" =>
COND := FLAGS(ACC_B)(FLAG_OV1) xor (not OP_BRCH(1));
when "1000" =>
COND := FLAGS(ACC_A)(FLAG_S0) xor (not OP_BRCH(1));
when "1001" =>
COND := FLAGS(ACC_B)(FLAG_S0) xor (not OP_BRCH(1));
when "1010" =>
COND := FLAGS(ACC_A)(FLAG_S1) xor (not OP_BRCH(1));
when "1011" =>
COND := FLAGS(ACC_B)(FLAG_S1) xor (not OP_BRCH(1));
when "1100" =>
if (DP(3 downto 0) = (0 to 3 => OP_BRCH(1)) and OP_BRCH(0) = '0') or
(DP(3 downto 0) /= (0 to 3 => OP_BRCH(1)) and OP_BRCH(0) = '1') then
COND := '1';
else
COND := '0';
end if;
when "1111" =>
COND := RQM xor (not OP_BRCH(1));
when others =>
COND := '0';
end case;
if OP_BRCH = "000000000" then
PC <= SO(10 downto 0);
elsif OP_BRCH(8 downto 6) = "010" and COND = '1' then
PC <= OP_NA;
elsif OP_BRCH(8 downto 7) = "10" and OP_BRCH(5 downto 0) = "000000" then
PC <= OP_NA;
if OP_BRCH(6) = '1' then
STACK_RAM(to_integer((SP(2) and VER(2))&SP(1 downto 0))) <= NEXT_PC;
SP <= SP + 1;
end if;
else
PC <= NEXT_PC;
end if;
else
PC <= NEXT_PC;
end if;
end if;
end if;
end process;
PROG_ROM_ADDR <= std_logic_vector(unsigned(PC) + ("0"&x"000")) when VER="000" else
std_logic_vector(unsigned(PC) + ("0"&x"500")) when VER="001" else
std_logic_vector(unsigned(PC) + ("0"&x"C00")) when VER="010" else
std_logic_vector(unsigned(PC) + ("1"&x"254")) when VER="011" else
std_logic_vector(unsigned(PC) + ("1"&x"954"));
PROG_ROM : sprom_verilog generic map(13, 24, 7018, "../src/chip/DSP/dsp1b23410_p.hex")
port map(
clock => CLK,
address => PROG_ROM_ADDR,
q => PROG_ROM_Q
);
DATA_ROM_ADDR <= VER(2 downto 1) & (VER(0) or (RP(10) and VER(2))) & RP(9 downto 0);
DATA_ROM : sprom_verilog generic map(13, 16, 6144, "../src/chip/DSP/dsp1b23410_d.hex")
port map(
clock => CLK,
address => DATA_ROM_ADDR,
q => DATA_ROM_Q
);
DATA_RAM_ADDR_A <= "000" & DP(7 downto 0) when VER(2)='0' else DP;
DATA_RAM_ADDR_B <= DP_ADDR(11 downto 1) when DP_SEL = '1' and (WR_N = '0' or RD_N = '0') else DATA_RAM_ADDR_A or x"40";
DATA_RAM_WE <= '1' when OP_INSTR /= INSTR_JP and OP_DST = x"F" and EN = '1' else '0';
DATA_RAML : dp16k_wrapper_8bit generic map(11)
port map(
clock => CLK,
address_a => DATA_RAM_ADDR_A,
data_a => OP_ID(7 downto 0),
wren_a => DATA_RAM_WE,
q_a => DATA_RAM_Q_A(7 downto 0),
address_b => DATA_RAM_ADDR_B,
data_b => DI,
wren_b => not WR_N and DP_SEL and not DP_ADDR(0),
q_b => DATA_RAM_Q_B(7 downto 0)
);
DATA_RAMH : dp16k_wrapper_8bit generic map(11)
port map(
clock => CLK,
address_a => DATA_RAM_ADDR_A,
data_a => OP_ID(15 downto 8),
wren_a => DATA_RAM_WE,
q_a => DATA_RAM_Q_A(15 downto 8),
address_b => DATA_RAM_ADDR_B,
data_b => DI,
wren_b => not WR_N and DP_SEL and DP_ADDR(0),
q_b => DATA_RAM_Q_B(15 downto 8)
);
--I/O Ports
process(CLK, RST_N)
begin
if RST_N = '0' then
DRS <= '0';
RQM <= '0';
DR <= (others => '0');
WR_Nr <= (others => '1');
RD_Nr <= (others => '1');
PORT_ACTIVE <= '0';
elsif rising_edge(CLK) then
if ENABLE = '1' then
WR_Nr <= WR_Nr(1 downto 0) & WR_N;
RD_Nr <= RD_Nr(1 downto 0) & RD_N;
if WR_Nr = "110" and CS_N = '0' and A0 = '0' then
if DRC = '0' then
if DRS = '0' then
DR(7 downto 0) <= DI;
else
DR(15 downto 8) <= DI;
end if;
else
DR(7 downto 0) <= DI;
end if;
PORT_ACTIVE <= '1';
elsif RD_Nr = "110" and CS_N = '0' and A0 = '0' then
PORT_ACTIVE <= '1';
end if;
if (WR_Nr = "001" or RD_Nr = "001") and PORT_ACTIVE = '1' then
if DRC = '0' then
if DRS = '0' then
DRS <= '1';
else
RQM <= '0';
DRS <= '0';
end if;
else
RQM <= '0';
end if;
PORT_ACTIVE <= '0';
elsif EN = '1' then
if OP_INSTR /= INSTR_JP and OP_DST = x"6" then
DR <= OP_ID;
RQM <= '1';
elsif (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) and OP_SRC = x"8" then
RQM <= '1';
end if;
end if;
end if;
end if;
end process;
process( A0, SR, DR, DRC, DRS, DP_SEL, DP_ADDR, DATA_RAM_Q_B )
begin
if DP_SEL = '1' then
if DP_ADDR(0) = '0' then
DO <= DATA_RAM_Q_B(7 downto 0);
else
DO <= DATA_RAM_Q_B(15 downto 8);
end if;
elsif A0 = '1' then
DO <= SR(15 downto 8);
else
if DRC = '0' then
if DRS = '0' then
DO <= DR(7 downto 0);
else
DO <= DR(15 downto 8);
end if;
else
DO <= DR(7 downto 0);
end if;
end if;
end process;
--Debug
process(CLK, RST_N)
begin
if RST_N = '0' then
BRK_OUT <= '0';
DBG_RUN_LAST <= '0';
elsif rising_edge(CLK) then
if EN = '1' then
BRK_OUT <= '0';
if DBG_CTRL(0) = '1' then --step
BRK_OUT <= '1';
elsif DBG_CTRL(2) = '1' and DBG_BRK_ADDR = PC then --opcode address break
BRK_OUT <= '1';
end if;
end if;
DBG_RUN_LAST <= DBG_CTRL(7);
if DBG_CTRL(7) = '1' and DBG_RUN_LAST = '0' then
BRK_OUT <= '0';
end if;
end if;
end process;
process( RST_N, CLK, DBG_REG, ACC, FLAGS, PC, RP, DP, TR, TRB, K, L, M, N, DR, SR, SP, IDB )
begin
case DBG_REG is
when x"00" => DBG_DAT_OUT <= ACC(ACC_A)(7 downto 0);
when x"01" => DBG_DAT_OUT <= ACC(ACC_A)(15 downto 8);
when x"02" => DBG_DAT_OUT <= ACC(ACC_B)(7 downto 0);
when x"03" => DBG_DAT_OUT <= ACC(ACC_B)(15 downto 8);
when x"04" => DBG_DAT_OUT <= "00"&FLAGS(ACC_A);
when x"05" => DBG_DAT_OUT <= "00"&FLAGS(ACC_B);
when x"06" => DBG_DAT_OUT <= PC(7 downto 0);
when x"07" => DBG_DAT_OUT <= "00000"&PC(10 downto 8);
when x"08" => DBG_DAT_OUT <= RP(7 downto 0);
when x"09" => DBG_DAT_OUT <= "000000"&RP(9 downto 8);
when x"0A" => DBG_DAT_OUT <= DP(7 downto 0);
when x"0B" => DBG_DAT_OUT <= TR(7 downto 0);
when x"0C" => DBG_DAT_OUT <= TR(15 downto 8);
when x"0D" => DBG_DAT_OUT <= TRB(7 downto 0);
when x"0E" => DBG_DAT_OUT <= TRB(15 downto 8);
when x"0F" => DBG_DAT_OUT <= K(7 downto 0);
when x"10" => DBG_DAT_OUT <= K(15 downto 8);
when x"11" => DBG_DAT_OUT <= L(7 downto 0);
when x"12" => DBG_DAT_OUT <= L(15 downto 8);
when x"13" => DBG_DAT_OUT <= M(7 downto 0);
when x"14" => DBG_DAT_OUT <= M(15 downto 8);
when x"15" => DBG_DAT_OUT <= N(7 downto 0);
when x"16" => DBG_DAT_OUT <= N(15 downto 8);
when x"17" => DBG_DAT_OUT <= DR(7 downto 0);
when x"18" => DBG_DAT_OUT <= DR(15 downto 8);
when x"19" => DBG_DAT_OUT <= SR(7 downto 0);
when x"1A" => DBG_DAT_OUT <= SR(15 downto 8);
when x"1B" => DBG_DAT_OUT <= "00000" & std_logic_vector(SP);
when x"1C" => DBG_DAT_OUT <= IDB(7 downto 0);
when x"1D" => DBG_DAT_OUT <= IDB(15 downto 8);
when others => DBG_DAT_OUT <= x"00";
end case;
if RST_N = '0' then
DBG_DAT_WRr <= '0';
elsif rising_edge(CLK) then
DBG_DAT_WRr <= DBG_DAT_WR;
if DBG_DAT_WR = '1' and DBG_DAT_WRr = '0' then
case DBG_REG is
when x"80" => DBG_BRK_ADDR(7 downto 0) <= DBG_DAT_IN;
when x"81" => DBG_BRK_ADDR(10 downto 8) <= DBG_DAT_IN(2 downto 0);
when x"82" => null;
when x"83" => DBG_CTRL <= DBG_DAT_IN;
when others => null;
end case;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
b9bf5f915d0ea3b51bd053442196c6a7
| 0.515522 | 2.581865 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug18810/DMEM.vhd
| 3 | 6,721 |
-- NOTE: http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
library ieee;
use ieee.std_logic_1164.all;
package DMEM_PRIM_PKG is
component DMEM_PRIM is
generic (
log2A : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iWCLK : in std_logic;
iWE : in std_logic;
iWA : in integer range 0 to 2**log2A-1;
iWD : in std_logic_vector(DW-1 downto 0);
iRA0 : in integer range 0 to 2**log2A-1;
iRA1 : in integer range 0 to 2**log2A-1;
iRA2 : in integer range 0 to 2**log2A-1;
oRD0 : out std_logic_vector(DW-1 downto 0);
oRD1 : out std_logic_vector(DW-1 downto 0);
oRD2 : out std_logic_vector(DW-1 downto 0)
);
end component DMEM_PRIM;
constant cDMEM_PRIM_W_LATENCY : integer := 1;
constant cDMEM_PRIM_R0_LATENCY : integer := 0;
constant cDMEM_PRIM_R1_LATENCY : integer := 0;
constant cDMEM_PRIM_R2_LATENCY : integer := 0;
end package DMEM_PRIM_PKG;
package body DMEM_PRIM_PKG is
-- NOTE: This body should keep to be empty to stub.
end package body DMEM_PRIM_PKG;
library ieee;
use ieee.std_logic_1164.all;
entity DMEM_PRIM is
generic (
log2A : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iWCLK : in std_logic;
iWE : in std_logic;
iWA : in integer range 0 to 2**log2A-1;
iWD : in std_logic_vector(DW-1 downto 0);
iRA0 : in integer range 0 to 2**log2A-1;
iRA1 : in integer range 0 to 2**log2A-1;
iRA2 : in integer range 0 to 2**log2A-1;
oRD0 : out std_logic_vector(DW-1 downto 0);
oRD1 : out std_logic_vector(DW-1 downto 0);
oRD2 : out std_logic_vector(DW-1 downto 0)
);
begin
end entity DMEM_PRIM;
architecture RTL of DMEM_PRIM is
type tDMEM_PRIM is array (0 to 2**log2A-1) of std_logic_vector(DW-1 downto 0);
signal aDMEM_PRIM0 : tDMEM_PRIM := (0 to 2**log2A-1 => (DW-1 downto 0 => '0'));
signal aDMEM_PRIM1 : tDMEM_PRIM := (0 to 2**log2A-1 => (DW-1 downto 0 => '0'));
signal aDMEM_PRIM2 : tDMEM_PRIM := (0 to 2**log2A-1 => (DW-1 downto 0 => '0'));
begin
P_DMEM_PRIM : process (iWCLK)
begin
if (rising_edge(iWCLK)) then
if (iWE = '1') then
aDMEM_PRIM0(iWA) <= iWD;
aDMEM_PRIM1(iWA) <= iWD;
aDMEM_PRIM2(iWA) <= iWD;
end if;
end if;
end process P_DMEM_PRIM;
oRD0 <= (DW-1 downto 0 => '0') when (ZERO = true and iRA0 = 0) else aDMEM_PRIM0(iRA0);
oRD1 <= (DW-1 downto 0 => '0') when (ZERO = true and iRA1 = 0) else aDMEM_PRIM1(iRA1);
oRD2 <= (DW-1 downto 0 => '0') when (ZERO = true and iRA2 = 0) else aDMEM_PRIM2(iRA2);
end architecture RTL;
library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PRIM_PKG.all;
package DMEM_PKG is
component DMEM is
generic (
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLK : in std_logic;
iAADDR : in integer range 0 to 2**log2DADDR-1;
oADATA : out std_logic_vector(DW-1 downto 0);
iBWE : in std_logic;
iBADDR : in integer range 0 to 2**log2DADDR-1;
iBDATA : in std_logic_vector(DW-1 downto 0);
oBDATA : out std_logic_vector(DW-1 downto 0)
);
end component DMEM;
constant cDMEM_DW_LATENCY : integer := cDMEM_PRIM_W_LATENCY;
constant cDMEM_DR_LATENCY : integer := cDMEM_PRIM_R0_LATENCY;
constant cDMEM_AR_LATENCY : integer := cDMEM_PRIM_R1_LATENCY;
constant cDMEM_BW_LATENCY : integer := cDMEM_PRIM_W_LATENCY;
constant cDMEM_BR_LATENCY : integer := cDMEM_PRIM_R2_LATENCY;
end package DMEM_PKG;
package body DMEM_PKG is
-- NOTE: This body should keep to be empty to stub.
end package body DMEM_PKG;
library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PRIM_PKG.all;
entity DMEM is
generic (
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLK : in std_logic;
iAADDR : in integer range 0 to 2**log2DADDR-1;
oADATA : out std_logic_vector(DW-1 downto 0);
iBWE : in std_logic;
iBADDR : in integer range 0 to 2**log2DADDR-1;
iBDATA : in std_logic_vector(DW-1 downto 0);
oBDATA : out std_logic_vector(DW-1 downto 0)
);
begin
end entity DMEM;
architecture RTL of DMEM is
-- FIXME: ISE 13.2 does not support "protected"... :(
type tBANK is (BANK_D, BANK_B);
type tLVT is array (0 to 2**log2DADDR-1) of tBANK;
shared variable aLVT : tLVT := (0 to 2**log2DADDR-1 => BANK_D);
signal sDMEM_PRIM_D_oDDATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_D_oADATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_D_oBDATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_B_oDDATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_B_oADATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_B_oBDATA : std_logic_vector(DW-1 downto 0);
begin
P_LVT_D : process (iDCLK)
begin
if (rising_edge(iDCLK)) then
if (iDWE = '1') then
aLVT(iDADDR) := BANK_D;
end if;
end if;
end process P_LVT_D;
P_LVT_B : process (iCLK)
begin
if (rising_edge(iCLK)) then
if (iBWE = '1') then
aLVT(iBADDR) := BANK_B;
end if;
end if;
end process P_LVT_B;
U_DMEM_PRIM_D : DMEM_PRIM
generic map (
log2A => log2DADDR,
DW => DW,
ZERO => ZERO
)
port map (
iWCLK => iDCLK,
iWE => iDWE,
iWA => iDADDR,
iWD => iDDATA,
iRA0 => iDADDR,
iRA1 => iAADDR,
iRA2 => iBADDR,
oRD0 => sDMEM_PRIM_D_oDDATA,
oRD1 => sDMEM_PRIM_D_oADATA,
oRD2 => sDMEM_PRIM_D_oBDATA
);
U_DMEM_PRIM_B : DMEM_PRIM
generic map (
log2A => log2DADDR,
DW => DW,
ZERO => ZERO
)
port map (
iWCLK => iCLK,
iWE => iBWE,
iWA => iBADDR,
iWD => iBDATA,
iRA0 => iDADDR,
iRA1 => iAADDR,
iRA2 => iBADDR,
oRD0 => sDMEM_PRIM_B_oDDATA,
oRD1 => sDMEM_PRIM_B_oADATA,
oRD2 => sDMEM_PRIM_B_oBDATA
);
oDDATA <= sDMEM_PRIM_D_oDDATA when (aLVT(iDADDR) = BANK_D) else sDMEM_PRIM_B_oDDATA;
oADATA <= sDMEM_PRIM_D_oADATA when (aLVT(iAADDR) = BANK_D) else sDMEM_PRIM_B_oADATA;
oBDATA <= sDMEM_PRIM_D_oBDATA when (aLVT(iBADDR) = BANK_D) else sDMEM_PRIM_B_oBDATA;
end architecture RTL;
|
gpl-2.0
|
980e7d92f8c7fe5e7b8065c704f125b5
| 0.629371 | 2.668122 | false | false | false | false |
nickg/nvc
|
test/regress/vests47.vhd
| 1 | 2,102 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc133.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests47 IS
END vests47;
ARCHITECTURE c04s03b02x02p08n01i00133arch OF vests47 IS
type RT1 is record
a : INTEGER;
b : INTEGER;
end record;
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout RT1; ref : in RT1; set : in RT1) is
begin
if (P = ref) then
P := set;
end if;
end;
variable V : RT1 := (1, 2);
BEGIN
V := (1, 2);
Proc1(P.a => V.b, P.b => V.a, ref => (2, 1), set => (2, 3));
-- test here
assert V = (3, 2) report "FAIL: P didn't get set right";
assert NOT( V = (3,2) )
report "***PASSED TEST: c04s03b02x02p08n01i00133"
severity NOTE;
assert ( V = (3,2) )
report "***FAILED TEST: c04s03b02x02p08n01i00133 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00133arch;
|
gpl-3.0
|
99c7ff8af491c0f52e7d929657f91399
| 0.602284 | 3.740214 | false | true | false | false |
nickg/nvc
|
test/regress/protected5.vhd
| 1 | 1,524 |
-- The order of design units in the file is significant
package pack1 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
-------------------------------------------------------------------------------
use work.pack1.all;
package pack2 is
shared variable sv : SharedCounter;
end package;
-------------------------------------------------------------------------------
entity protected5 is
end entity;
use work.pack2.all;
architecture test of protected5 is
begin
p1: process is
begin
sv.increment;
sv.increment;
wait for 0 ns;
assert sv.value = 3;
wait;
end process;
p2: process is
begin
sv.increment;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
package body pack1 is
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
|
gpl-3.0
|
3b6329f9c7bc394f507f36ff0ba6cc7c
| 0.520997 | 5.237113 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/prog.vhd
| 2 | 2,944 |
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity prog is
port(
clock : in std_logic;
reset : in std_logic;
step : in std_logic;
instr_next : out instruction
);
end prog;
architecture rtl of prog is
signal instr_n : instruction := instr_rst;
--Table describing fsm behavior
constant fsm_behavior : table_behavior := (
--##PROGRAM_GOES_DOWN_HERE##--
0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(2,ARG_WIDTH)),
4 => (state => Running, context_uut => "01", arg => to_unsigned(5,ARG_WIDTH)),
5 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
6 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
7 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
8 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
9 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
10 => (state => Ack_data, context_uut => "10", arg => to_unsigned(2,ARG_WIDTH)),
11 => (state => Running, context_uut => "10", arg => to_unsigned(6,ARG_WIDTH)),
12 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
13 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
14 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
15 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
16 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
17 => (state => Waitfor, context_uut => "01", arg => to_unsigned(1,ARG_WIDTH)),
18 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
19 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
20 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
21 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
22 => (state => Waitfor, context_uut => "10", arg => to_unsigned(1,ARG_WIDTH)),
23 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
--##PROGRAM_GOES_OVER_HERE##--
others => instr_rst);
signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0');
begin
drive_state : process (reset,clock) is
begin
if reset = '1' then
instr_n <= instr_rst;
pc <= (others => '0');
elsif rising_edge(clock) then
if (step = '1') then
pc <= pc + 1;
end if;
instr_n <= fsm_behavior(to_integer(pc));
end if;
end process drive_state;
--instr_next <= instr_n;
instr_next <= fsm_behavior(to_integer(pc));
end rtl;
|
gpl-2.0
|
16eb0bfd9196de90c0b96df570701e90
| 0.592052 | 2.82805 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/axi_lite_ipif.vhd
| 8 | 14,526 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_3.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
gpl-3.0
|
60127bc0a98d4b7a6f0dbd04166c43ec
| 0.489261 | 4.181347 | false | false | false | false |
nickg/nvc
|
lib/ieee.08/numeric_bit-body.vhdl
| 1 | 94,005 |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library nvc;
use nvc.sim_pkg.ieee_warnings;
package body NUMERIC_BIT is
-- null range array constants
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := not ieee_warnings;
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNSIGNED; C : BIT) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNSIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : SIGNED; C : BIT) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(L_LEFT downto 0) is R;
variable RESULT : SIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNSIGNED; XQUOT, XREMAIN : out UNSIGNED) is
variable TEMP : UNSIGNED(NUM'length downto 0);
variable QUOT : UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0);
alias DENOM : UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_BIT.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_BIT.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
---------------- Local Subprograms - Relational Operators --------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- ====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT : SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : SIGNED(ARG_LEFT downto 0);
variable CBIT : BIT := '1';
begin
if ARG'length < 1 then return NAS;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.3R
function "+" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.4R
function "+" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.9R
function "-" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.10R
function "-" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable RESULT : UNSIGNED((L'length+R'length-1) downto 0) := (others => '0');
variable ADVAL : UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable RESULT : SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL : SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
QNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
RNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
RNEG := true;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function ">";
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function ">";
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function "<";
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function "<";
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function "<=";
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "<=";
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function ">=";
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function ">=";
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'length), R);
end function "=";
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "=";
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'length), R));
end function "/=";
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length)));
end function "/=";
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.53
function "?>" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.54
function "?>" (L : SIGNED; R : INTEGER) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.59
function "?<" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.60
function "?<" (L : SIGNED; R : INTEGER) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.66
function "?<=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.72
function "?>=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.77
function "?=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.78
function "?=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.84
function "?/=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER is
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
if ARG(ARG'left) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED is
variable RESULT : UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER;
SIZE : NATURAL) return SIGNED is
variable RESULT : SIGNED(SIZE-1 downto 0);
variable B_VAL : BIT := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED is
alias INVEC : SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : SIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNSIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : SIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNSIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : SIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNSIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : SIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNSIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : SIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNSIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : SIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNSIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function TO_OSTRING (value : UNSIGNED) return STRING is
begin
return TO_OSTRING(BIT_VECTOR (value));
end function TO_OSTRING;
function TO_OSTRING (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(1 to (result_length*3 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return TO_OSTRING(pad & BIT_VECTOR (value));
end function TO_OSTRING;
function to_hstring (value : UNSIGNED) return STRING is
begin
return to_hstring(BIT_VECTOR (value));
end function to_hstring;
function to_hstring (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(1 to (result_length*4 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & BIT_VECTOR (value));
end function to_hstring;
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
GOOD := true;
else
GOOD := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
GOOD := true;
else
GOOD := false;
end if;
end if;
else
GOOD := true;
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
if not ok then
GOOD := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
end if;
else
GOOD := true;
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - VALUE'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_BIT;
|
gpl-3.0
|
0b8a4d9a3c7e9ddc0d829509b0c10e5e
| 0.545269 | 3.952447 | false | false | false | false |
snow4life/PipelinedDLX
|
register_file_mips.vhd
| 1 | 1,929 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity register_file_mips is
-- MODULE is the logarithm in base 2 of the number of registers
generic(MODULE: integer := 5;
N_BIT: integer := 32);
port( CK: in std_logic;
RESET: in std_logic;
ENABLE: in std_logic;
RD1: in std_logic;
RD2: in std_logic;
WR: in std_logic;
ADD_WR: in std_logic_vector(MODULE-1 downto 0);
ADD_RD1: in std_logic_vector(MODULE-1 downto 0);
ADD_RD2: in std_logic_vector(MODULE-1 downto 0);
DATAIN: in std_logic_vector(N_BIT-1 downto 0);
OUT1: out std_logic_vector(N_BIT-1 downto 0);
OUT2: out std_logic_vector(N_BIT-1 downto 0));
end register_file_mips;
architecture BEHAVIORAL of register_file_mips is
subtype REG_ADDR is natural range 0 to (2**MODULE)-1;
type REG_ARRAY is array(REG_ADDR) of std_logic_vector(N_BIT-1 downto 0);
signal REGISTERS : REG_ARRAY;
begin
REGISTER_FILE_PROCESS: process(CK, RESET)
begin
if CK'event and CK='1' then -- positive edge triggered:
if RESET='1' then -- active high reset
REGISTERS_RESET_LOOP: for i in (2**MODULE)-1 downto 0 loop
-- all register file is reset
REGISTERS(i) <= (others => '0');
end loop REGISTERS_RESET_LOOP;
OUT1 <= (others => '0');
OUT2 <= (others => '0');
else
if WR = '1' and ENABLE = '1' and conv_integer(ADD_WR) /= 0 then
REGISTERS(conv_integer(ADD_WR)) <= DATAIN;
end if;
if RD1 = '1' and ENABLE = '1' then
if conv_integer(ADD_RD1) = 0 then
OUT1 <= (others => '0');
else
OUT1 <= REGISTERS(conv_integer(ADD_RD1));
end if;
end if;
if RD2 = '1' and ENABLE = '1' then
if conv_integer(ADD_RD2) = 0 then
OUT2 <= (others => '0');
else
OUT2 <= REGISTERS(conv_integer(ADD_RD2));
end if;
end if;
end if;
end if;
end process;
end BEHAVIORAL;
|
lgpl-2.1
|
961f95d5e331fcb6d4bbcd891a69293f
| 0.618974 | 2.73617 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/arr01/arr04.vhdl
| 1 | 781 |
library ieee;
use ieee.std_logic_1164.all;
entity arr04 is
port (clk : in std_logic;
rst : std_logic;
sel_i : std_logic;
sel_o : std_logic;
v : std_logic;
res : out std_logic);
end arr04;
architecture behav of arr04 is
signal reg : std_logic_vector (0 to 1);
begin
-- Reader
process(clk)
begin
if rising_edge (clk) then
if sel_o = '0' then
res <= reg (0);
else
res <= reg (1);
end if;
end if;
end process;
-- Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg <= "00";
else
if sel_i = '0' then
reg (0) <= v;
else
reg (1) <= v;
end if;
end if;
end if;
end process;
end behav;
|
gpl-2.0
|
4bdff57095914ad8dae9026d8ebc22af
| 0.503201 | 3.227273 | false | false | false | false |
nickg/nvc
|
test/regress/ieee10.vhd
| 1 | 1,383 |
-- file numeric_std_tb1.vhd is a simulation testbench for
-- IEEE 1076.3 numeric_std package.
-- This is the first in a series of testbenches.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ieee10 is
generic (
quiet : boolean := false); -- make the simulation quiet
end entity ieee10;
architecture t1 of ieee10 is
begin
process
-- required A15_38
variable res4,sgn4: signed(3 downto 0);
variable sgn6: signed(5 downto 0);
variable res8: signed(7 downto 0);
variable sgn10,res10:signed(9 downto 0);
variable ures4,uns4: unsigned(1 to 4);
variable uns6: unsigned(2 to 7);
variable uns8: unsigned(0 to 7);
variable uns10,ures10:unsigned(1 to 10);
begin
-- Id: A.21, A.23, and A.24
for i in 0 to 1023 loop
uns10:=to_unsigned(i,10);
for j in 1 to 15 loop
uns4:=to_unsigned(j,4);
ures10:=uns10/uns4;
assert to_integer(ures10)=i/j report "A.21 fails"
severity FAILURE;
ures10:=uns10/j;
assert to_integer(ures10)=i/j report "A.23 fails"
severity FAILURE;
ures10:=i/("000000"&uns4);
assert to_integer(ures10)=i/j report "A.24 fails"
severity FAILURE;
end loop;
end loop;
if now < 2 ns then
wait for 1 ns;
else
wait;
end if;
end process;
end architecture t1;
|
gpl-3.0
|
67c9e900b140efafca241e274fa66f94
| 0.627621 | 3.292857 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug029/fft.vhdl
| 2 | 808 |
package fft_package is
TYPE complex IS ARRAY(0 TO 1) OF INTEGER;
CONSTANT w0 : complex := (1, 0); --Pre-computed constants
CONSTANT w1 : complex := (0, -1); --Pre-computed constants
function butterfly(X1, X2 , W : complex )return complex;
END fft_package;
package body fft_package is
function butterfly ( X1, X2 , W : complex )return complex is
VARIABLE Y1, Y2 : complex;
BEGIN
-- G1 = X1 + W*X2
G1:Y1(0) := X1(0) + ((W(0)*X2(0)) - W(1)*X2(1)); -- G1 real
Y1(1) := X1(1) + ((W(0)*X2(1)) + W(1)*X2(0)); -- G1 imaginary
-- G2 = X1 - W*X2
Y2(0) := X1(0) - ((W(0)*X2(0)) - W(1)*X2(1)); -- G2 real
Y2(1) := X1(1) - ((W(0)*X2(1)) + W(1)*X2(0)); -- G2 imaginary
return Y1;
return Y2;
END butterfly;
end fft_package;
|
gpl-2.0
|
744a58cd84c3f22541bf6d54e826d0ad
| 0.530941 | 2.598071 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/fsm02/tb_recv.vhdl
| 1 | 1,360 |
library ieee;
use ieee.std_logic_1164.all;
entity tb_recv is
end tb_recv;
architecture behav of tb_recv is
signal clk : std_logic;
signal rst : std_logic := '1';
signal tx : std_logic;
signal data : std_logic_vector (7 downto 0);
signal valid : std_logic;
signal err : std_logic;
begin
dut: entity work.recv
port map (clk => clk,
rst => rst,
rx => tx,
byte => data,
b_err => err,
b_en => valid);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
variable txdata : std_logic_vector (7 downto 0);
begin
rst <= '1';
tx <= '1';
pulse;
rst <= '0';
-- Transmit 1 byte.
tx <= '0';
pulse;
assert err = '0' and valid = '0' severity error;
txdata := x"6e";
for i in txdata'reverse_range loop
tx <= txdata(i);
pulse;
assert err = '0' and valid = '0' severity error;
end loop;
tx <= '1'; -- parity
pulse;
tx <= '1'; -- stop
pulse;
assert valid = '1' severity error;
assert err = '0' severity error;
assert data = txdata;
wait;
end process;
end behav;
|
gpl-2.0
|
d1da895a33d47b5df020fd7d4d232f6e
| 0.475 | 3.830986 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd
| 4 | 2,166 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_04 is
end entity fg_05_04;
architecture test of fg_05_04 is
constant prop_delay : time := 5 ns;
signal a, b, sel, z : bit;
begin
-- code from book
mux : process (a, b, sel) is
begin
case sel is
when '0' =>
z <= a after prop_delay;
when '1' =>
z <= b after prop_delay;
end case;
end process mux;
-- end code from book
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0010",
"0100",
"0111",
"1001",
"1010",
"1101",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
e69d460886fbb04a9b1a50c0bccb0dd3
| 0.534626 | 4.17341 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_06.vhd
| 4 | 1,982 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_06.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_06 is
end entity ch_03_06;
architecture test of ch_03_06 is
-- code from book:
type alu_func is (pass1, pass2, add, subtract);
-- end of code from book
signal func : alu_func := pass1;
signal operand1 : integer := 10;
signal operand2 : integer := 3;
begin
process_03_2_a : process (func, operand1, operand2) is
variable result : integer := 0;
begin
-- code from book:
case func is
when pass1 =>
result := operand1;
when pass2 =>
result := operand2;
when add =>
result := operand1 + operand2;
when subtract =>
result := operand1 - operand2;
end case;
-- end of code from book
end process process_03_2_a;
stimulus : process is
begin
func <= pass2 after 10 ns,
add after 20 ns,
subtract after 30 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
ced1b7982af46c2d3c007588155d1ada
| 0.596367 | 4.10352 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue467/testbench2.vhdl
| 1 | 1,724 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AbstractMmPkg.all;
entity testbench is
end entity testbench;
architecture TB of testbench is
signal AWADDR : std_logic_vector(6 downto 0);
signal AWPROT : std_logic_vector(2 downto 0);
signal AWVALID : std_logic;
signal AWREADY : std_logic;
signal WDATA : std_logic_vector(31 downto 0);
signal WSTRB : std_logic_vector(3 downto 0);
signal WVALID : std_logic;
signal WREADY : std_logic;
signal BRESP : std_logic_vector(1 downto 0);
signal BVALID : std_logic;
signal BREADY : std_logic;
signal ARADDR : std_logic_vector(6 downto 0);
signal ARPROT : std_logic_vector(2 downto 0);
signal ARVALID : std_logic;
signal ARREADY : std_logic;
signal RDATA : std_logic_vector(31 downto 0);
signal RRESP : std_logic_vector(1 downto 0);
signal RVALID : std_logic;
signal RREADY : std_logic;
signal ACLK : std_logic;
signal ARESETn : std_logic;
signal rec : AbstractMmRecType(
writedata(31 downto 0),
readdata(31 downto 0),
address(4 downto 0),
byteen(3 downto 0)
);
begin
BFM: entity work.axi_master
generic map (
DATAWIDTH => 32,
ADDRWIDTH => AWADDR'length
) port map(
-- AXI interface,
AWADDR => AWADDR,
AWPROT => AWPROT,
AWVALID => AWVALID,
AWREADY => AWREADY,
WDATA => WDATA,
WSTRB => WSTRB,
WVALID => WVALID,
WREADY => WREADY,
BRESP => BRESP,
BVALID => BVALID,
BREADY => BREADY,
ARADDR => ARADDR,
ARPROT => ARPROT,
ARVALID => ARVALID,
ARREADY => ARREADY,
RDATA => RDATA,
RRESP => RRESP,
RVALID => RVALID,
RREADY => RREADY,
ACLK => ACLK,
ARESETn => ARESETn,
-- AMR interface
amr => rec
);
end architecture TB;
|
gpl-2.0
|
fe0a1e5cf493d0184cd5c8604719e1d8
| 0.664153 | 3.029877 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug061/dictp.vhdl
| 2 | 5,814 |
library ieee;
use ieee.std_logic_1164.all;
package corelib_Dict is
-- generic (
-- type KEY_TYPE;
-- type VALUE_TYPE;
-- function to_hash(d : in KEY_TYPE, size : positive) return natural;
-- INIT_SIZE : natural := 128
-- );
-- REMOVE when using package generics
constant INIT_SIZE : positive := 128;
alias to_hash is "mod" [integer, integer return integer];
subtype KEY_TYPE is integer;
subtype VALUE_TYPE is std_logic_vector;
type PT_DICT is protected
procedure Set (constant key : in KEY_TYPE; constant data : in VALUE_TYPE);
procedure Get (constant key : in KEY_TYPE; data : out VALUE_TYPE);
impure function Get (constant key : KEY_TYPE) return VALUE_TYPE;
procedure Del (constant key : in KEY_TYPE);
procedure Clear;
impure function HasKey (constant key : KEY_TYPE) return boolean;
impure function Count return natural;
end protected PT_DICT;
procedure Merge(d0 : inout PT_DICT; d1 : inout PT_DICT; dout : inout PT_DICT);
end package corelib_Dict;
package body corelib_Dict is
type t_key_ptr is access KEY_TYPE;
type t_data_ptr is access VALUE_TYPE;
type PT_DICT is protected body
type t_entry;
type t_entry_ptr is access t_entry;
type t_entry is record
key : t_key_ptr;
data : t_data_ptr;
last_entry : t_entry_ptr;
next_entry : t_entry_ptr;
end record t_entry;
type t_entry_array is array (0 to INIT_SIZE-1) of t_entry_ptr;
variable head : t_entry_array := (others => null);
variable entry_count : integer_vector(0 to INIT_SIZE-1) := (others => 0);
-- Private method to find entry stored in dictionary
impure function Find (constant key : KEY_TYPE) return t_entry_ptr;
impure function Find (constant key : KEY_TYPE) return t_entry_ptr is
variable entry : t_entry_ptr := head(to_hash(key, INIT_SIZE));
begin
while (entry /= null) loop
if (entry.key.all = key) then
return entry;
end if;
entry := entry.last_entry;
end loop;
return null;
end function Find;
procedure Set (constant key : in KEY_TYPE; constant data : in VALUE_TYPE) is
variable addr : natural := 0;
variable entry : t_entry_ptr := Find(key);
begin
if (entry = null) then
addr := to_hash(key, INIT_SIZE);
if (head(addr) /= null) then
entry := new t_entry;
entry.key := new KEY_TYPE'(key);
entry.data := new VALUE_TYPE'(data);
entry.last_entry := head(addr);
entry.next_entry := null;
head(addr) := entry;
head(addr).last_entry.next_entry := head(addr);
else
head(addr) := new t_entry;
head(addr).key := new KEY_TYPE'(key);
head(addr).data := new VALUE_TYPE'(data);
head(addr).last_entry := null;
head(addr).next_entry := null;
end if;
entry_count(addr) := entry_count(addr) + 1;
else
entry.data.all := data;
end if;
end procedure Set;
procedure Get (constant key : in KEY_TYPE; data : out VALUE_TYPE) is
variable entry : t_entry_ptr := Find(key);
begin
assert entry /= null
report PT_DICT'instance_name & ": ERROR: key " & to_string(key) & " not found"
severity failure;
data := entry.data.all;
end procedure Get;
impure function Get (constant key : KEY_TYPE) return VALUE_TYPE is
variable entry : t_entry_ptr := Find(key);
begin
assert entry /= null
report PT_DICT'instance_name & ": ERROR: key " & to_string(key) & " not found"
severity failure;
return entry.data.all;
end function Get;
procedure Del (constant key : in KEY_TYPE) is
variable entry : t_entry_ptr := Find(key);
variable addr : natural := 0;
begin
if (entry /= null) then
addr := to_hash(key, INIT_SIZE);
-- remove head entry
if(entry.next_entry = null and entry.last_entry /= null) then
entry.last_entry.next_entry := null;
head(addr) := entry.last_entry;
-- remove start entry
elsif(entry.next_entry /= null and entry.last_entry = null) then
entry.next_entry.last_entry := null;
-- remove from between
elsif(entry.next_entry /= null and entry.last_entry /= null) then
entry.last_entry.next_entry := entry.next_entry;
entry.next_entry.last_entry := entry.last_entry;
else
head(addr) := null;
end if;
deallocate(entry.key);
deallocate(entry.data);
deallocate(entry);
entry_count(addr) := entry_count(addr) - 1;
end if;
end procedure Del;
procedure Clear is
variable entry : t_entry_ptr;
variable entry_d : t_entry_ptr;
begin
for i in t_entry_array'range loop
entry := head(i);
while (entry /= null) loop
entry_d := entry;
Del(entry_d.key.all);
entry := entry.last_entry;
end loop;
end loop;
end procedure Clear;
impure function HasKey (constant key : KEY_TYPE) return boolean is
begin
return Find(key) /= null;
end function HasKey;
impure function Count return natural is
variable value : natural := 0;
begin
for i in entry_count'range loop
value := value + entry_count(i);
end loop;
return value;
end function Count;
end protected body PT_DICT;
procedure Merge(d0 : inout PT_DICT; d1 : inout PT_DICT; dout : inout PT_DICT) is
begin
end procedure Merge;
end package body corelib_Dict;
|
gpl-2.0
|
bb8f43b1d6f569057e8ddf60dd1b8b4f
| 0.584279 | 3.819974 | false | false | false | false |
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