repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
unhold/hdl
|
vhdl/ddr_serdes/ddr_ser.vhd
| 1 | 2,495 |
library ieee;
use ieee.std_logic_1164.all;
--- DDR serializer.
entity ddr_ser is
generic (
data_width_g : positive;
delay_g : time);
port (
clk_i,
reset_ni : in std_ulogic;
data_i : in std_ulogic_vector(data_width_g-1 downto 0);
start_stb_i : in std_ulogic;
busy_o : out std_ulogic;
ddr_data_o,
bit_clk_o,
frame_clk_o : out std_ulogic);
end;
architecture bhv of ddr_ser is
type state_t is record
shift_reg : std_ulogic_vector(data_width_g-1 downto 0);
count_down : integer range 0 to data_width_g;
busy,
frame_clk : std_ulogic;
end record;
constant state_reset_c : state_t := (
shift_reg => (others => '0'),
count_down => 0,
busy => '0',
frame_clk => '0');
signal s, n : state_t;
signal data_even,
data_odd,
data_mux,
clk_delay,
clk_trans : std_ulogic;
begin
sync : process(clk_i, reset_ni)
begin
if reset_ni = '0' then
s <= state_reset_c;
elsif rising_edge(clk_i) then
s <= n;
end if;
end process;
comb : process(data_i, start_stb_i, s)
begin
n <= s;
if s.count_down /= 0 then
n.shift_reg <= "00" & s.shift_reg(s.shift_reg'left downto 2);
n.count_down <= s.count_down - 2;
end if;
if s.count_down = data_width_g/2 + 2 then
n.frame_clk <= '1';
end if;
if s.count_down <= 2 then
n.busy <= '0';
n.frame_clk <= '0';
end if;
if start_stb_i = '1' then
n.shift_reg <= data_i;
n.count_down <= data_width_g;
n.busy <= '1';
end if;
busy_o <= s.busy;
end process;
odd_ff : process(clk_i, reset_ni)
begin
if reset_ni = '0' then
data_odd <= '0';
elsif rising_edge(clk_i) then
if s.busy = '1' then
data_odd <= s.shift_reg(1);
else
data_odd <= '0';
end if;
end if;
end process;
even_ff : process(clk_i, reset_ni)
begin
if reset_ni = '0' then
data_even <= '0';
elsif falling_edge(clk_i) then
if s.busy = '1' then
data_even <= s.shift_reg(0);
else
data_even <= '0';
end if;
end if;
end process;
mux : with clk_i select data_mux <=
s.shift_reg(1) when '0',
s.shift_reg(0) when '1',
'X' when others;
-- replace with delay element(s) or tuned delay line
clk_delay <= clk_i after delay_g;
clk_trans <= clk_i xor clk_delay;
bit_clk_o <= not clk_i and s.busy;
latch_with_reset : process(reset_ni, clk_trans, data_mux, s)
begin
if reset_ni = '0' then
ddr_data_o <= '0';
frame_clk_o <= '0';
elsif clk_trans = '0' then
ddr_data_o <= data_mux;
frame_clk_o <= s.frame_clk;
end if;
end process;
end;
|
gpl-3.0
|
debbc71f0a253ec2367013e889bb1089
| 0.596794 | 2.394434 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_uart_autobaud.vhd
| 2 | 6,460 |
-- $Id: serport_uart_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_autobaud - syn
-- Description: serial port UART - autobauder
--
-- Dependencies: -
-- Test bench: tb/tb_serport_autobaud
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0.4 now numeric_std clean
-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_autobaud is -- serial port uart: autobauder
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
ACT : out slbit; -- active; if 1 clkdiv is invalid
DONE : out slbit -- resync done
);
end serport_uart_autobaud;
architecture syn of serport_uart_autobaud is
type state_type is (
s_idle,
s_break,
s_wait,
s_sync
);
type regs_type is record
ccnt : slv(CDWIDTH-1+3 downto 0); -- clock divider counter
mcnt : slv7; -- msec counter
seen1 : slbit; -- seen a '1' in this msec
state : state_type; -- state
end record regs_type;
-- Note on initialization of ccnt:
-- - in the current logic ccnt is incremented n-1 times when n is number
-- clock cycles with a RXD of '0'. When running at 50 MBaud, ccnt will
-- be incremented 7 (not 8!) times.
-- - the three LSBs of ccnt should be at 100 under perfect conditions, this
-- gives the best rounded estimate of CLKDIV.
-- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
-- --> ccntinit = -3
constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
slv(to_unsigned(2**(CDWIDTH+3)-3, CDWIDTH+3));
constant mcntzero : slv7 := (others=>'0');
constant mcntlast : slv7 := (others=>'1');
constant regs_init : regs_type := (
slv(to_unsigned(CDINIT,CDWIDTH))&"000",
(others=>'0'),
'0',
s_idle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CDINIT <= 2**CDWIDTH-1
report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, RESET, RXSD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iact : slbit := '0';
variable idone : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
iact := '1';
idone := '0';
case r.state is
when s_idle => -- s_idle: idle, detect break --------
iact := '0';
if CE_MSEC = '1' then -- if end of msec
if r.seen1 = '0' then -- if no '1' seen on RXD
n.mcnt := slv(unsigned(r.mcnt) + 1); -- up break timer counter
if r.mcnt = mcntlast then -- after 127 msec
n.state := s_break; -- break detected !
end if;
else -- otherwise if '1' seen
n.mcnt := mcntzero; -- clear break timer again
end if;
n.seen1 := RXSD; -- latch current RXD value
else -- otherwise if not at end-of-msec
n.seen1 := r.seen1 or RXSD; -- remember whether RXS=1 seen
end if;
when s_break => -- s_break: detect end of break ------
if RXSD = '1' then -- if end of break seen
n.state := s_wait; -- to s_wait to wait for sync char
n.ccnt := ccntinit; -- and initialize ccnt
end if; -- otherwise stay in s_break
when s_wait => -- s_wait: wait for sync char --------
if RXSD = '0' then -- if start bit if sync char seen
n.state := s_sync; -- to s_sync to wait for end of '0'
end if; -- otherwise stay in s_wait
when s_sync => -- s_sync: wait for end of '0' bits --
if RXSD = '1' then -- if end of '0' bits seen
n.state := s_idle; -- to s_idle, autobauding done
idone := '1'; -- emit done pulse
else -- otherwise still in '0' of sync
n.ccnt := slv(unsigned(n.ccnt) + 1); -- increment ccnt
end if;
when others => null; -- -----------------------------------
end case;
N_REGS <= n;
CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3);
ACT <= iact or RESET;
DONE <= idone;
end process proc_next;
end syn;
|
gpl-2.0
|
e82348ea11dc2c1284c84f7e73e3d964
| 0.521362 | 3.982737 | false | false | false | false |
freecores/w11
|
rtl/vlib/genlib/genlib.vhd
| 1 | 7,060 |
-- $Id: genlib.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2007-2012 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: genlib
-- Description: some general purpose components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 13.3; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0.9 add led_pulse_stretch
-- 2011-11-09 421 1.0.8 add cdc_pulse
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
-- 2007-12-25 105 1.0.3 RESET:='0' defaults
-- 2007-06-17 58 1.0.2 added debounce_gen
-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package genlib is
component clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end component;
component cnt_array_dram is -- counter array, dram based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : out slv(AWIDTH-1 downto 0); -- counter address
DATA : out slv(DWIDTH-1 downto 0); -- counter data
ACT : out slbit -- active (not reseting)
);
end component;
component cnt_array_regs is -- counter array, register based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : in slv(AWIDTH-1 downto 0); -- address
DATA : out slv(DWIDTH-1 downto 0) -- counter data
);
end component;
component debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end component;
component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
component gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end component;
component timer is -- retriggerable timer
generic (
TWIDTH : positive := 4; -- timer counter width
RETRIG : boolean := true); -- re-triggerable true/false
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
START : in slbit; -- start timer
STOP : in slbit := '0'; -- stop timer
DONE : out slbit; -- mark last delay cycle
BUSY : out slbit -- timer running
);
end component;
component cdc_pulse is -- clock domain cross for pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false); -- if true: busy waits for ack
port (
CLKM : in slbit; -- clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end component;
component led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end component;
end package genlib;
|
gpl-2.0
|
e83ff20db903cdca1b5eafcedefb0202
| 0.51728 | 4.057471 | false | false | false | false |
freecores/w11
|
rtl/ibus/ibdr_dl11.vhd
| 2 | 13,865 |
-- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11 - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK
-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change)
-- 2008-01-27 115 1.0.3 bugfix: set ilam when rbuf read by cpu;
-- add xdone and rrdy bits to rri xbuf read
-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now)
-- 2008-01-20 112 1.0.1 use BRESET
-- 2008-01-05 108 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11;
architecture syn of ibdr_dl11 is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xmaint: integer := 2;
constant xbuf_ibf_xval : integer := 8;
constant xbuf_ibf_rrdy : integer := 9;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rbuf : slv8; -- rbuf:
rval : slbit; -- rx rbuf valid
rintreq : slbit; -- rx interrupt request
rdlybsy : slbit; -- rx delay busy
rdlycnt : slv10; -- rx delay counter
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xmaint : slbit; -- xcsr: maintenance mode
xbuf : slv8; -- xbuf:
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- rrlim
'0','0', -- rdone, rie
(others=>'0'), -- rbuf
'0','0','0', -- rval,rintreq,rdlybsy
(others=>'0'), -- rdlycnt
'1', -- xrdy !! is set !!
'0','0', -- xie,xmaint
(others=>'0'), -- xbuf
'0' -- xintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- don't reset rx rate limit
R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable rdlystart : slbit := '0';
variable rdlyinit : slv10 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
rdlystart := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then
if r.rdone='1' and r.rie='0' then -- ie set while done=1
n.rintreq := '1'; -- request interrupt
end if;
else
n.rintreq := '0';
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibrd = '1' then
n.rdone := '0'; -- clear DONE
n.rval := '0'; -- clear rbuf valid
n.rintreq := '0'; -- clear pending interrupts
rdlystart := '1'; -- start rx delay counter
if r.xmaint = '0' then -- if not in loop-back
ilam := '1'; -- request rb attention
end if;
end if;
else -- rri ---------------------
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rval := '1'; -- set rbuf valid
if r.rdlybsy = '0' then -- if rdly timer not running
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
idout(xcsr_ibf_xmaint):= r.xmaint;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then
if r.xrdy='1' and r.xie='0' then -- ie set while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else
n.xintreq := '0';
end if;
n.xmaint := IB_MREQ.din(xcsr_ibf_xmaint);
end if;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xbuf := IB_MREQ.din(n.xbuf'range);
n.xrdy := '0';
n.xintreq := '0';
if r.xmaint = '0' then
ilam := '1';
end if;
end if;
else -- rri ---------------------
idout(r.xbuf'range) := r.xbuf;
if r.xmaint = '0' then -- if not in maintenace mode
idout(xbuf_ibf_xval) := not r.xrdy;
idout(xbuf_ibf_rrdy) := not r.rval;
end if;
if ibrd = '1' then
n.xrdy := '1';
if r.xie = '1' then
n.xintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
else -- if unselected handle loop-back
if r.xmaint = '1' and -- if in maintenace mode
r.xrdy='0' and -- and transmit pending
r.rdone='0' and -- and receive buffer empty
r.rdlybsy='0' then -- and rdly timer not running
n.rbuf := r.xbuf; -- copy transmit to receive buffer
n.xrdy := '1'; -- mark transmit done
n.rdone := '1'; -- make receive done
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request it
end if;
if r.xie = '1' then -- if tx interrupt enabled
n.xintreq := '1'; -- request it
end if;
end if;
end if;
-- other state changes
rdlyinit := (others=>'0');
case r.rrlim is
when "000" => rdlyinit := "0000000000"; -- rlim=0 -> disabled
when "001" => rdlyinit := "0000000011"; -- rlim=1 -> delay by 3+ usec
when "010" => rdlyinit := "0000001111"; -- rlim=2 -> delay by 15+ usec
when "011" => rdlyinit := "0000111111"; -- rlim=3 -> delay by 63+ usec
when "100" => rdlyinit := "0001111111"; -- rlim=4 -> delay by 127+ usec
when "101" => rdlyinit := "0011111111"; -- rlim=5 -> delay by 255+ usec
when "110" => rdlyinit := "0111111111"; -- rlim=6 -> delay by 511+ usec
when "111" => rdlyinit := "1111111111"; -- rlim=7 -> delay by 1023+ usec
when others => null;
end case;
if rdlystart = '1' then -- if rdly timer start requested
n.rdlycnt := rdlyinit; -- init counter
if r.rrlim /= "000" then -- rate limiter enabled ?
n.rdlybsy := '1'; -- set busy
end if;
elsif CE_USEC = '1' then -- if end-of-usec
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement
if r.rdlybsy='1' and -- if delay busy
unsigned(r.rdlycnt) = 0 then -- and counter at zero
n.rdlybsy := '0'; -- clear busy
if n.rval = '1' then -- if rbuf is valid or is set
-- valid this cycle (use n.!!)
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
|
gpl-2.0
|
53c8e86236c03cbdeed4cc31161acc86
| 0.460151 | 3.868583 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/control/input_rom_pkg.vhd
| 1 | 2,414 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : input_rom_pkg.vhd
-- PROJECT : FPGA_NEURAL-Network
-- PACKAGE : INPUT_ROM_pkg
--=============================================================================
-- AUTORS(s) : Agostini, N
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 14, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.NN_TYPES_pkg.all;
--=============================================================================
-- Package declaration for INPUT_ROM_pkg
--=============================================================================
package INPUT_ROM_pkg is
constant SAMPLE_SIZE : natural := 178;
subtype INPUT_SFIXED is sfixed(1 downto L_SIZE);
type INPUT_ARRAY is array (natural range <>) of INPUT_SFIXED;
subtype INPUT_LOOKUP_ARRAY is INPUT_ARRAY(0 to (PERCEPTRONS_INPUT-1+PERCEPTRONS_OUTPUT));
type INPUT_TABLE is array (natural range <>) of INPUT_ARRAY;
subtype INPUT_CONSTRAINED_SFIXED_ARRAY is ARRAY_OF_SFIXED(0 to (PERCEPTRONS_INPUT-1+PERCEPTRONS_OUTPUT));
end;
--=============================================================================
-- package body declaration
--=============================================================================
package body INPUT_ROM_pkg is
end package body;
|
gpl-3.0
|
f91abd17399c8f9e9eeb2b8ee0035373
| 0.493372 | 4.818363 | false | false | false | false |
unhold/hdl
|
vhdl/dual_port_ram.vhd
| 1 | 3,000 |
library ieee;
use ieee.std_logic_1164.all;
-- True dual-port, dual-clock RAM. Inference of Intel and Xilinx RAM blocks.
-- Can also be used as single-port, single-clock, with a read-only and a write-only port.
entity dual_port_ram is
generic (
address_width_g : positive;
data_width_g : positive);
port (
a_clock_i : in std_ulogic;
a_address_i : in std_ulogic_vector(address_width_g-1 downto 0);
a_write_i : in std_ulogic;
a_data_i : in std_ulogic_vector(data_width_g-1 downto 0);
a_read_i : in std_ulogic := '0';
a_data_o : out std_ulogic_vector(data_width_g-1 downto 0);
b_clock_i : in std_ulogic := '0';
b_address_i : in std_ulogic_vector(address_width_g-1 downto 0) := (others => 'X');
b_write_i : in std_ulogic := '0';
b_data_i : in std_ulogic_vector(data_width_g-1 downto 0) := (others => 'X');
b_read_i : in std_ulogic := '0';
b_data_o : out std_ulogic_vector(data_width_g-1 downto 0));
end;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dual_port_ram is
function to_index(slv : std_ulogic_vector) return natural is
begin
return to_integer(unsigned(slv));
end;
subtype data_t is std_ulogic_vector(data_width_g-1 downto 0);
type ram_t is array(0 to 2**address_width_g-1) of data_t;
shared variable ram_v : ram_t;
begin
a_port : process(a_clock_i)
begin
if rising_edge(a_clock_i) then
if a_read_i = '1' and not is_x(a_address_i) then
a_data_o <= ram_v(to_index(a_address_i));
else
a_data_o <= (others => 'X');
end if;
if a_write_i = '1' then
if not is_x(a_address_i) then
ram_v(to_index(a_address_i)) := a_data_i;
else
ram_v := (others => (others => 'X'));
end if;
end if;
end if;
end process;
b_port : process(b_clock_i)
begin
if rising_edge(b_clock_i) then
if b_read_i = '1' and not is_x(b_address_i) then
b_data_o <= ram_v(to_index(b_address_i));
else
b_data_o <= (others => 'X');
end if;
if b_write_i = '1' then
if not is_x(b_address_i) then
ram_v(to_index(b_address_i)) := b_data_i;
else
ram_v := (others => (others => 'X'));
end if;
end if;
end if;
end process;
write_contention : block is
signal a_write_r, b_write_r : std_ulogic;
begin
a_write_contention : process(a_clock_i)
begin
if rising_edge(a_clock_i) then
a_write_r <= a_write_i;
if (a_write_i = '1' and a_address_i = b_address_i and
(b_write_r = '1' or
(rising_edge(b_clock_i) and b_write_i = '1'))) then
report "dual_port_ram: write contention" severity warning;
ram_v(to_index(a_address_i)) := (others => 'X');
end if;
end if;
end process;
b_write_contention : process(b_clock_i)
begin
if rising_edge(b_clock_i) then
b_write_r <= b_write_i;
if b_write_i = '1' and a_write_r = '1' and b_address_i = a_address_i then
report "dual_port_ram: write contention" severity warning;
ram_v(to_index(b_address_i)) := (others => 'X');
end if;
end if;
end process;
end block;
end;
|
gpl-3.0
|
baa801648f1cb83f4f14028f13a87d62
| 0.619 | 2.493766 | false | false | false | false |
freecores/w11
|
rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd
| 1 | 15,415 |
-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_xfirst_gen_unisim;
architecture syn of ram_2swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => O"000000000000",
INIT_B => O"000000000000",
SRVAL_A => O"000000000000",
SRVAL_B => O"000000000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(36*i+31 downto 36*i),
DOB => L_DOB(36*i+31 downto 36*i),
DOPA => L_DOA(36*i+35 downto 36*i+32),
DOPB => L_DOB(36*i+35 downto 36*i+32),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(36*i+31 downto 36*i),
DIB => L_DIB(36*i+31 downto 36*i),
DIPA => L_DIA(36*i+35 downto 36*i+32),
DIPB => L_DIB(36*i+35 downto 36*i+32),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => X"00000000",
INIT_B => X"00000000",
SRVAL_A => X"00000000",
SRVAL_B => X"00000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(32*i+31 downto 32*i),
DOB => DOB(32*i+31 downto 32*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(32*i+31 downto 32*i),
DIB => DIB(32*i+31 downto 32*i),
DIPA => "0000",
DIPB => "0000",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => O"000000",
INIT_B => O"000000",
SRVAL_A => O"000000",
SRVAL_B => O"000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(18*i+15 downto 18*i),
DOB => L_DOB(18*i+15 downto 18*i),
DOPA => L_DOA(18*i+17 downto 18*i+16),
DOPB => L_DOB(18*i+17 downto 18*i+16),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(18*i+15 downto 18*i),
DIB => L_DIB(18*i+15 downto 18*i),
DIPA => L_DIA(18*i+17 downto 18*i+16),
DIPB => L_DIB(18*i+17 downto 18*i+16),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => X"0000",
INIT_B => X"0000",
SRVAL_A => X"0000",
SRVAL_B => X"0000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(16*i+15 downto 16*i),
DOB => DOB(16*i+15 downto 16*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(16*i+15 downto 16*i),
DIB => DIB(16*i+15 downto 16*i),
DIPA => "00",
DIPB => "00",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => O"000",
INIT_B => O"000",
SRVAL_A => O"000",
SRVAL_B => O"000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(9*i+7 downto 9*i),
DOB => L_DOB(9*i+7 downto 9*i),
DOPA => L_DOA(9*i+8 downto 9*i+8),
DOPB => L_DOB(9*i+8 downto 9*i+8),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(9*i+7 downto 9*i),
DIB => L_DIB(9*i+7 downto 9*i),
DIPA => L_DIA(9*i+8 downto 9*i+8),
DIPB => L_DIB(9*i+8 downto 9*i+8),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => X"00",
INIT_B => X"00",
SRVAL_A => X"00",
SRVAL_B => X"00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(8*i+7 downto 8*i),
DOB => DOB(8*i+7 downto 8*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(8*i+7 downto 8*i),
DIB => DIB(8*i+7 downto 8*i),
DIPA => "0",
DIPB => "0",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4_S4
generic map (
INIT_A => X"0",
INIT_B => X"0",
SRVAL_A => X"0",
SRVAL_B => X"0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(4*i+3 downto 4*i),
DOB => L_DOB(4*i+3 downto 4*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(4*i+3 downto 4*i),
DIB => L_DIB(4*i+3 downto 4*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2_S2
generic map (
INIT_A => "00",
INIT_B => "00",
SRVAL_A => "00",
SRVAL_B => "00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(2*i+1 downto 2*i),
DOB => L_DOB(2*i+1 downto 2*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(2*i+1 downto 2*i),
DIB => L_DIB(2*i+1 downto 2*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(i downto i),
DOB => DOB(i downto i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_14_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
|
gpl-2.0
|
53d24439f890e7f3b3a76968e249a6ae
| 0.459033 | 3.348175 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/rlink_core.vhd
| 2 | 40,169 |
-- $Id: rlink_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_core - syn
-- Description: rlink core with 9bit interface
--
-- Dependencies: comlib/crc8
--
-- Test bench: tb/tb_rlink_direct
-- tb/tb_rlink_serport
-- tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-04 343 12.1 M53d xc3s1000-4 155 322 0 199 s 8.9
-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now;
-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
-- ioerr->rberr; '111' cmd now aborts via s_txnak and
-- sets cerr flag; set [cd]err on eop/nak aborts;
-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now
-- aval,re,we; add new states: s_rstart, s_wstart
-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
-- now nak on reserved cmd 111; use do_comma_abort();
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH output
-- 2009-07-12 233 2.0.1 remove snoopers
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-02 121 1.1.1 comment out snoopers
-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-15 82 1.0 Initial version, fully functional
-- 2007-06-17 58 0.5 First preliminary version
------------------------------------------------------------------------------
--
-- Overall protocol:
-- _idle : expect
-- sop -> _txsop (echo sop, , to _txsop, _rxcmd)
-- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (silently ignore nak)
-- attn -> _txito (send ito , to _idle)
-- data -> _idle (silently ignore data)
-- _error: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (silently ignore data)
-- _rxcmd: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode command)
-- _rx...: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode data)
--
-- 7 supported commands:
--
-- 000 read reg (rreg):
-- rx: cmd addr ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
-- _rstart _rreg _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 001 read blk (rblk):
-- rx: cmd addr cnt ccrc
-- tx: cmd cnt dl dh ... stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
-- {_rstart _rreg _txdatl _txdath _blk}*
-- _txstat _txcrc -> _rxcmd
--
-- 010 write reg (wreg):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _wstart _wreg _txstat _txcrc -> _rxcmd
--
-- 011 write blk (wblk):
-- rx: cmd addr cnt ccrc dl dh ... dcrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
-- {_rxdatl _rxdath _wstart _wreg _blk}*
-- _rxdcrc _txstat _txcrc -> (_rxcmd|_txnak)
--
-- 100 read stat (stat):
-- rx: cmd ccrc
-- tx: cmd ccmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _txccmd _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 101 read attn (attn):
-- rx: cmd ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _attn _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 110 write init (init):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _txstat _txcrc -> _rxcmd
-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
--
-- 111 is currently not a legal command and causes a nak
-- seq: _txnak
--
-- The state bits nakcerr and nakderr determine whether cerr/derr is set
-- when s_txnak is entered. cerr is '1' during command receive, derr is '1'
-- during data wblk data receive phase:
-- nakcerr set in s_rxcmd (when command received, unless it's stat)
-- clr in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
-- nakderr set in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
--
-- The different rbus cycle types are encoded as:
--
-- init aval re we
-- 0 0 0 0 idle
-- 0 0 1 0 not allowed
-- 0 0 0 1 not allowed
-- 0 1 1 0 read
-- 0 1 0 1 write
-- 1 0 0 0 internal init
-- 1 0 0 1 external init
-- 1 0 1 0 not allowed
-- * * 1 1 not allowed
-- 1 1 * * not allowed
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core is -- rlink core with 9bit interface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6); -- idle timeout counter width
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end entity rlink_core;
architecture syn of rlink_core is
type state_type is (
s_idle, -- s_idle: wait for sop
s_txito, -- s_txito: send timeout symbol
s_txsop, -- s_txsop: send sop
s_txnak, -- s_txnak: send nak
s_txeop, -- s_txeop: send eop
s_error, -- s_error: wait for eop
s_rxcmd, -- s_rxcmd: wait for cmd
s_rxaddr, -- s_rxaddr: wait for addr
s_rxdatl, -- s_rxdatl: wait for data low
s_rxdath, -- s_rxdath: wait for data high
s_rxcnt, -- s_rxcnt: wait for count
s_rxccrc, -- s_rxccrc: wait for command crc
s_txcmd, -- s_txcmd: send cmd
s_txcnt, -- s_txcnt: send cnt
s_rstart, -- s_rstart: start reg or blk read
s_rreg, -- s_rreg: do reg or blk read
s_txdatl, -- s_txdatl: send data low
s_txdath, -- s_txdath: send data high
s_wstart, -- s_wstart: start reg or blk write
s_wreg, -- s_wreg: do reg or blk write
s_blk, -- s_blk: block count handling
s_rxdcrc, -- s_rxdcrc: wait for data crc
s_attn, -- s_attn: handle attention flags
s_txccmd, -- s_txccmd: send last command
s_txstat, -- s_txstat: send status
s_txcrc -- s_txcrc: send crc
);
type regs_type is record
state : state_type; -- state
rcmd : slv8; -- received command
ccmd : slv8; -- current command
addr : slv8; -- register address
dil : slv8; -- input data, lsb
dih : slv8; -- input data, msb
dol : slv8; -- output data, lsb
doh : slv8; -- output data, msb
cnt : slv8; -- block transfer count
attn : slv16; -- attn mask
atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter
itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
itoena : slbit; -- idle timeout enable flag
anena : slbit; -- attn notification enable flag
andone : slbit; -- attn notification done
cerr : slbit; -- stat: command error
derr : slbit; -- stat: data error
rbnak: slbit; -- stat: rbus no ack or timeout
rberr : slbit; -- stat: rbus err bit set
nakeop : slbit; -- send eop after nak
nakcerr : slbit; -- set cerr after nak
nakderr : slbit; -- set derr after nak
rbinit : slbit; -- rbus init signal
rbaval : slbit; -- rbus aval signal
rbre : slbit; -- rbus re signal
rbwe : slbit; -- rbus we signal
moneop : slbit; -- rl_moni: eop send pulse
monattn : slbit; -- rl_moni: attn send pulse
monlamp : slbit; -- rl_moni: attn pending state
stat : slv3; -- external status flags
end record regs_type;
constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
constant c_idle : slv4 := "0000";
constant c_sop : slv4 := "0001";
constant c_eop : slv4 := "0010";
constant c_nak : slv4 := "0011";
constant c_attn : slv4 := "0100";
constant regs_init : regs_type := (
s_idle, --
(others=>'0'), -- rcmd
(others=>'0'), -- ccmd
(others=>'0'), -- addr
(others=>'0'), -- dil
(others=>'0'), -- dih
(others=>'0'), -- dol
(others=>'0'), -- doh
(others=>'0'), -- cnt
(others=>'0'), -- attn
atocnt_init, -- atocnt
itocnt_init, -- itocnt
itocnt_init, -- itoval
'0', -- itoena
'0','0', -- anena, andone
'0','0','0','0', -- stat flags
'0','0','0', -- nakeop,nakcerr,nakderr
'0','0','0','0', -- rbinit,rbaval,rbre,rbwe
'0','0','0', -- moneop,monattn,monlamp
(others=>'0') -- stat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CRC_RESET : slbit := '0';
signal ICRC_ENA : slbit := '0';
signal OCRC_ENA : slbit := '0';
signal ICRC_OUT : slv8 := (others=>'0');
signal OCRC_OUT : slv8 := (others=>'0');
signal OCRC_IN : slv8 := (others=>'0');
begin
assert ITOWIDTH<=8
report "assert(ITOWIDTH<=8): max byte size ITO counter supported"
severity failure;
ICRC : crc8 -- crc generator for input data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => ICRC_ENA,
DI => RL_DI(7 downto 0),
CRC => ICRC_OUT
);
OCRC : crc8 -- crc generator for output data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => OCRC_ENA,
DI => OCRC_IN,
CRC => OCRC_OUT
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable ido : slv9 := (others=>'0');
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable ito_go : slbit := '0';
variable ito_end : slbit := '0';
variable crcreset : slbit := '0';
variable icrcena : slbit := '0';
variable ocrcena : slbit := '0';
variable has_attn : slbit := '0';
variable snd_attn : slbit := '0';
variable idi8 : slv8 := (others=>'0');
variable is_comma : slbit := '0';
variable comma_typ : slv4 := "0000";
procedure do_comma_abort(nstate : inout state_type;
nnakeop : inout slbit;
comma_typ : in slv4) is
begin
if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then
if comma_typ = c_eop then
nnakeop := '1';
end if;
nstate := s_txnak; -- next: send nak
end if;
end procedure do_comma_abort;
begin
r := R_REGS;
n := R_REGS;
idi8 := RL_DI(7 downto 0); -- get data part of RL_DI
is_comma := RL_DI(8); -- get comma marker
comma_typ := RL_DI(3 downto 0); -- get comma type
n.rbinit := '0'; -- clear rb(init|aval|re|we) by default
n.rbaval := '0'; -- they must always be set by the
n.rbre := '0'; -- 'previous state'
n.rbwe := '0'; --
n.moneop := '0'; -- default '0', only set by states
n.monattn := '0'; -- "
n.monlamp := '0'; --
ibusy := '1'; -- default is to hold input
ival := '0';
ido := (others=>'0');
crcreset := '0';
icrcena := '0';
ocrcena := '0';
for i in RB_LAM'range loop -- handle attention "LAM's"
if RB_LAM(i) = '1' then -- if LAM bit set
n.attn(i) := '1'; -- set attention bit
end if;
end loop;
has_attn := '0';
snd_attn := '0';
if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
has_attn := '1';
if r.anena='1' and r.andone='0' then -- is attn notification to be send ?
snd_attn := '1';
n.monlamp := '1'; -- set lamp flag in rl_moni
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
ito_go := '0'; -- default: keep idle timeout in reset
ito_end := '0';
if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero
ito_end := '1'; -- signal expiration
end if;
case r.state is
when s_idle => -- s_idle: wait for sop --------------
ito_go := '1'; -- idle timeout active
if snd_attn = '1' then -- if attn notification to be send
n.state := s_txito; -- next: send ito byte
else
ibusy := '0'; -- accept input
if RL_ENA = '1' then -- if input
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop
crcreset := '1'; -- reset crc generators
n.state := s_txsop; -- next: echo it
when c_eop => -- if eop (unexpected)
n.nakeop := '1'; -- send nak,eop
n.state := s_txnak; -- next: send nak
when c_attn => -- if attn
n.state := s_txito; -- next: send ito byte
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_idle; -- silently dropped
end if;
elsif (r.itoena='1' and -- if ito enable, expired and XSEC
ito_end='1' and CE_INT='1') then
n.state := s_txito; -- next: send ito byte
end if;
end if;
when s_txito => -- s_txito: send timeout symbol ------
if has_attn = '1' then
ido := c_rlink_dat_attn; -- if attn pending: send attn symbol
n.andone := '1';
else
ido := c_rlink_dat_idle; -- otherwise: send idle symbol
end if;
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.monattn := has_attn; -- signal on rl_moni
n.state := s_idle; -- next: wait for sop
end if;
when s_txsop => -- s_txsop: send sop -----------------
ido := c_rlink_dat_sop; -- send sop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.state := s_rxcmd; -- next: read first command
end if;
when s_txnak => -- s_txnak: send nak -----------------
ido := c_rlink_dat_nak; -- send nak character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.nakeop := '0'; -- clear all 'do on nak' state flags
n.nakcerr := '0';
n.nakderr := '0';
if r.nakcerr = '1' then -- if setting cerr requested
n.cerr := '1'; -- do it
end if;
if r.nakderr = '1' then -- if settung derr requested
n.derr := '1'; -- do it
end if;
if r.nakeop = '1' then -- if eop after nak requested
n.state := s_txeop; -- next: send eop
else
n.state := s_error; -- next: error state, wait for eop
end if;
end if;
when s_txeop => -- s_txeop: send eop -----------------
ido := c_rlink_dat_eop; -- send eop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.moneop := '1'; -- signal on rl_moni
n.state := s_idle; -- next: idle state, wait for sop
end if;
when s_error => -- s_error: wait for eop -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_error; -- silently dropped
end if;
end if;
when s_rxcmd => -- s_rxcmd: wait for cmd -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; --other commas: silently ignore
end case;
else -- if not comma
icrcena := '1'; -- update input crc
n.rcmd := idi8; -- latch received command code
-- unless the command is stat
if RL_DI(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.nakcerr := '1'; -- set cerr on eop/nak abort
end if;
case RL_DI(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg |
c_rlink_cmd_rblk |
c_rlink_cmd_wreg |
c_rlink_cmd_wblk |
c_rlink_cmd_init => -- for commands needing addr(data)
n.state := s_rxaddr; -- next: read address
when c_rlink_cmd_stat |
c_rlink_cmd_attn => -- stat and attn commands
n.state := s_rxccrc; -- next: read command crc
when others =>
n.state := s_txnak; -- next: send nak
end case; -- rcmd,ccmd always hold good cmd
end if;
end if;
when s_rxaddr => -- s_rxaddr: wait for addr -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.addr := idi8; -- latch read address
case r.rcmd(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg => -- for rreg command
n.state := s_rxccrc; -- next: read command crc
when c_rlink_cmd_wreg |
c_rlink_cmd_init => -- for wreg, init command
n.state := s_rxdatl; -- next: read data lsb
when others => -- for rblk or wblk
n.state := s_rxcnt; -- next: read count
end case;
end if;
end if;
when s_rxdatl => -- s_rxdatl: wait for data low -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dil := idi8; -- latch data lsb part
n.state := s_rxdath; -- next: read data msb
end if;
end if;
when s_rxdath => -- s_rxdath: wait for data high ------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dih := idi8; -- latch data msb part
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
else -- otherwise
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
end if;
when s_rxcnt => -- s_rxcnt: wait for count -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.cnt := idi8; -- latch count
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
when s_rxccrc => -- s_rxccrc: wait for command crc ----
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
-- unless the command is stat
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.cerr := '1'; -- set command error flag
end if;
n.state := s_txnak; -- next: send nak
else -- if crc ok
n.state := s_txcmd; -- next: echo command
end if;
end if;
end if;
when s_txcmd => -- s_txcmd: send cmd -----------------
ido := '0' & r.rcmd; -- send read command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then --unless stat
n.ccmd := r.rcmd; -- latch current command in ccmd
n.stat := RB_STAT; -- latch external status bits
n.cerr := '0';
n.derr := '0';
n.rbnak := '0';
n.rberr := '0';
end if;
n.nakcerr := '0'; -- all command rx done up to here
case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
when c_rlink_cmd_rreg => -- rreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read reg
when c_rlink_cmd_rblk => -- rblk ----------------
n.state := s_txcnt;
when c_rlink_cmd_wreg => -- wreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
when c_rlink_cmd_wblk => -- wblk ----------------
n.nakderr := '1'; -- set derr on eop/nak abort
n.state := s_rxdatl;
when c_rlink_cmd_stat => -- stat ----------------
n.state := s_txccmd;
when c_rlink_cmd_attn => -- attn ----------------
n.state := s_attn;
when c_rlink_cmd_init => -- init ----------------
n.rbinit := '1'; -- send init pulse
if r.addr(7 downto 3) = "11111" then -- is internal init
if r.addr(2 downto 0) = "111" then -- is rri init
n.anena := r.dih(c_rlink_iint_rbf_anena - 8);
n.itoena := r.dih(c_rlink_iint_rbf_itoena - 8);
n.itoval := r.dil(ITOWIDTH-1 downto 0);
-- note: itocnt will load in next
-- cycle because ito_go=0, so no
-- action required here
end if;
else -- is external init
n.rbwe := '1'; -- send init with we
end if;
n.state := s_txstat;
when others => -- '111' ---------------
n.state := s_txnak; -- send NAK on reserved command
end case;
end if;
when s_txcnt => -- s_txcnt: send cnt -----------------
ido := '0' & r.cnt; -- send cnt
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start first read reg
end if;
when s_rstart => -- s_rstart: start reg or blk read ---
n.rbaval := '1'; -- start actual read cycle
n.rbre := '1';
n.state := s_rreg; -- next: reg read
when s_rreg => -- s_rreg: do reg or blk read --------
-- this state handles all rbus reads
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.doh := RB_SRES.dout(15 downto 8); -- latch data
n.dol := RB_SRES.dout( 7 downto 0);
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack = '0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
n.state := s_txdatl; -- next: send data lsb
else -- otherwise rbus read continues
n.rbaval := '1'; -- extend cycle
n.rbre := '1';
end if;
when s_txdatl => -- s_txdatl: send data low -----------
ido := '0' & r.dol; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdath; -- next: send data msb
end if;
when s_txdath => -- s_txdath: send data high
ido := '0' & r.doh; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
end if;
when s_wstart => -- s_wstart: start reg or blk write --
n.rbaval := '1'; -- start actual write cycle
n.rbwe := '1';
n.state := s_wreg; -- next: reg write
when s_wreg => -- s_wreg: do reg or blk write -------
-- this state handles all rbus writes
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack='0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
else -- otherwise rbus write continues
n.rbaval := '1'; -- extend cycle
n.rbwe := '1';
end if;
when s_blk => -- s_blk: block count handling -------
n.cnt := slv(unsigned(r.cnt) - 1);-- decrement transfer count
if unsigned(r.cnt) = 0 then -- if last transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_txstat; -- next: send stat
else -- otherwise
n.state := s_rxdcrc; -- next: read data crc
end if;
else -- otherwise more to transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read blk
else -- otherwise
n.state := s_rxdatl; -- next: read data
end if;
end if;
when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
n.derr := '1'; -- set data error flag
end if;
n.state := s_txstat; -- next: echo command
end if;
end if;
when s_attn => -- s_attn: handle attention flags ----
n.dol := r.attn(7 downto 0); -- move attention flags to do buffer
n.doh := r.attn(15 downto 8);
n.attn := RB_LAM; -- LAM in current cycle send next time
n.andone := '0'; -- reenable attn nofification
n.state := s_txdatl; -- next: send data lsb
when s_txccmd => -- s_txccmd: send last command
ido := '0' & r.ccmd; -- send last accepted command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdatl; -- next: send last data lsb
end if;
when s_txstat => -- s_txstat: send status -------------
ido := (others=>'0');
ido(c_rlink_stat_rbf_stat) := r.stat;
ido(c_rlink_stat_rbf_attn) := has_attn;
ido(c_rlink_stat_rbf_cerr) := r.cerr;
ido(c_rlink_stat_rbf_derr) := r.derr;
ido(c_rlink_stat_rbf_rbnak) := r.rbnak;
ido(c_rlink_stat_rbf_rberr) := r.rberr;
ival := '1';
if RL_HOLD ='0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txcrc; -- next: send crc
end if;
when s_txcrc => -- s_txcrc: send crc -----------------
ido := "0" & OCRC_OUT; -- send crc code
ival := '1';
if RL_HOLD = '0' then -- wait for accept
-- if dcrc seen in wblk
if r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_wblk and r.derr='1' then
n.state := s_txnak; -- next: send nak
else -- otherwise
n.nakcerr := '0'; -- clear 'set on nak' requests
n.nakderr := '0';
n.state := s_rxcmd; -- next: read command or eop
end if;
end if;
when others => null; -- <> --------------------------------
end case;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
if ito_go = '0' then -- handle idle timeout counter
n.itocnt := r.itoval; -- if ito_go=0, keep at start value
else
if CE_INT = '1' then
n.itocnt := slv(unsigned(r.itocnt) - 1);-- otherwise cnt dn every CE_INT
end if;
end if;
N_REGS <= n;
RL_BUSY <= ibusy;
RL_DO <= ido;
RL_VAL <= ival;
RL_MONI.eop <= r.moneop;
RL_MONI.attn <= r.monattn;
RL_MONI.lamp <= r.monlamp;
RB_MREQ <= rb_mreq_init;
RB_MREQ.aval <= r.rbaval;
RB_MREQ.re <= r.rbre;
RB_MREQ.we <= r.rbwe;
RB_MREQ.init <= r.rbinit;
RB_MREQ.addr <= r.addr;
RB_MREQ.din <= r.dih & r.dil;
CRC_RESET <= crcreset;
ICRC_ENA <= icrcena;
OCRC_ENA <= ocrcena;
OCRC_IN <= ido(7 downto 0);
end process proc_next;
end syn;
|
gpl-2.0
|
a674334f9ca3bb113348cab7da670180
| 0.430033 | 4.009282 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
libraries/numeric_std_additions.vhdl
| 2 | 95,104 |
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.numeric_std_additions.all;
-- (this package is independant of "std_logic_1164_additions")
-- Last Modified: $Date: 2007/09/27 14:46:32 $
-- RCS ID: $Id: numeric_std_additions.vhdl,v 1.9 2007/09/27 14:46:32 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package numeric_std_additions is
-- Make these a subtype of "signed" and "unsigned" for compatability
-- type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
-- type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
subtype UNRESOLVED_UNSIGNED is UNSIGNED;
subtype UNRESOLVED_SIGNED is SIGNED;
-- alias U_UNSIGNED is UNRESOLVED_UNSIGNED;
-- alias U_SIGNED is UNRESOLVED_SIGNED;
subtype U_UNSIGNED is UNSIGNED;
subtype U_SIGNED is SIGNED;
-- Id: A.3R
function "+"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.3 where R is a one bit UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.4R
function "+"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.4 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.4 where L is bit 0 of a non-negative
-- SIGNED
-- Id: A.9R
function "-"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.10R
function "-"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: M.2B
-- %%% function "?=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic;
function \?=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- Id: M.3B
-- %%% function "?=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic;
function \?=\ (L, R : SIGNED) return STD_ULOGIC;
function \?/=\ (L, R : SIGNED) return STD_ULOGIC;
function \?>\ (L, R : SIGNED) return STD_ULOGIC;
function \?>=\ (L, R : SIGNED) return STD_ULOGIC;
function \?<\ (L, R : SIGNED) return STD_ULOGIC;
function \?<=\ (L, R : SIGNED) return STD_ULOGIC;
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
-- Result subtype: std_ulogic
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Overloaded functions from "std_logic_1164"
function To_X01 (s : UNSIGNED) return UNSIGNED;
function To_X01 (s : SIGNED) return SIGNED;
function To_X01Z (s : UNSIGNED) return UNSIGNED;
function To_X01Z (s : SIGNED) return SIGNED;
function To_UX01 (s : UNSIGNED) return UNSIGNED;
function To_UX01 (s : SIGNED) return SIGNED;
function Is_X (s : UNSIGNED) return BOOLEAN;
function Is_X (s : SIGNED) return BOOLEAN;
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit funcitons, using the local ">" operator
function maximum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l, r : SIGNED) -- inputs
return SIGNED;
function minimum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l, r : SIGNED) -- inputs
return SIGNED;
function maximum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function maximum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function minimum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function minimum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function maximum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
function minimum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
-- Finds the first "Y" in the input string. Returns an integer index
-- into that string. If "Y" does not exist in the string, then the
-- "find_rightmost" returns arg'low -1, and "find_leftmost" returns -1
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
alias TO_U_UNSIGNED is
TO_UNRESOLVED_UNSIGNED[NATURAL, NATURAL return UNRESOLVED_UNSIGNED];
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
alias TO_U_SIGNED is
TO_UNRESOLVED_SIGNED[NATURAL, NATURAL return UNRESOLVED_SIGNED];
-- L.15
function "and" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.16
function "and" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.17
function "or" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.18
function "or" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.19
function "nand" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.20
function "nand" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.21
function "nor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.22
function "nor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.23
function "xor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.24
function "xor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.25
function "xnor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.26
function "xnor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.27
function "and" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.28
function "and" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.29
function "or" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.30
function "or" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.31
function "nand" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.32
function "nand" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.33
function "nor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.34
function "nor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.35
function "xor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.36
function "xor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.37
function "xnor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.38
function "xnor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- %%% remove 12 functions (old syntax)
function and_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
function and_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( l : SIGNED ) RETURN std_ulogic;
-- function "nand" ( l : SIGNED ) RETURN std_ulogic;
-- function "or" ( l : SIGNED ) RETURN std_ulogic;
-- function "nor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : SIGNED ) RETURN std_ulogic;
-- function "and" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nand" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "or" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : UNSIGNED ) RETURN std_ulogic;
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- string functions
-------------------------------------------------------------------
function to_string (value : UNSIGNED) return STRING;
function to_string (value : SIGNED) return STRING;
-- explicitly defined operations
alias to_bstring is to_string [UNSIGNED return STRING];
alias to_bstring is to_string [SIGNED return STRING];
alias to_binary_string is to_string [UNSIGNED return STRING];
alias to_binary_string is to_string [SIGNED return STRING];
function to_ostring (value : UNSIGNED) return STRING;
function to_ostring (value : SIGNED) return STRING;
alias to_octal_string is to_ostring [UNSIGNED return STRING];
alias to_octal_string is to_ostring [SIGNED return STRING];
function to_hstring (value : UNSIGNED) return STRING;
function to_hstring (value : SIGNED) return STRING;
alias to_hex_string is to_hstring [UNSIGNED return STRING];
alias to_hex_string is to_hstring [SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNSIGNED);
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNSIGNED];
alias BREAD is READ [LINE, SIGNED];
alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNSIGNED];
alias BINARY_READ is READ [LINE, SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out SIGNED);
alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNSIGNED];
alias OCTAL_READ is OREAD [LINE, SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out SIGNED);
alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNSIGNED];
alias HEX_READ is HREAD [LINE, SIGNED];
alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
end package numeric_std_additions;
package body numeric_std_additions is
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
function MAX (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end function MAX;
-- Id: A.3R
function "+"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4R
function "+"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.9R
function "-"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10R
function "-"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ ( l, r : STD_ULOGIC ) return STD_ULOGIC is
variable value : STD_ULOGIC;
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: UNSIGNED) return std_ulogic is
-- end function "?=";
-- Id: M.3B
function \?=\ (L, R: SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: signed) return std_ulogic is
-- end function "?=";
-- Id: C.75
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_UNSIGNED(L, R'length), R);
end function \?=\;
-- Id: C.76
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_SIGNED(L, R'length), R);
end function \?=\;
-- Id: C.77
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?=\ (L, TO_UNSIGNED(R, L'length));
end function \?=\;
-- Id: C.78
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?=\ (L, TO_SIGNED(R, L'length));
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?/=";
function \?/=\ (L, R : SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?/=";
-- Id: C.75
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_UNSIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.76
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_SIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.77
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?/=\ (L, TO_UNSIGNED(R, L'length));
end function \?/=\;
-- Id: C.78
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?/=\ (L, TO_SIGNED(R, L'length));
end function \?/=\;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>";
-- Id: C.57
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_UNSIGNED(L, R'length), R);
end function \?>\;
-- Id: C.58
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_SIGNED(L, R'length),R);
end function \?>\;
-- Id: C.59
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>\ (L, TO_UNSIGNED(R, L'length));
end function \?>\;
-- Id: C.60
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>\ (L, TO_SIGNED(R, L'length));
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_UNSIGNED(L, R'length), R);
end function \?>=\;
-- Id: C.64
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_SIGNED(L, R'length),R);
end function \?>=\;
-- Id: C.65
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>=\ (L, TO_UNSIGNED(R, L'length));
end function \?>=\;
-- Id: C.66
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>=\ (L, TO_SIGNED(R, L'length));
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<";
-- Id: C.57
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_UNSIGNED(L, R'length), R);
end function \?<\;
-- Id: C.58
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_SIGNED(L, R'length),R);
end function \?<\;
-- Id: C.59
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<\ (L, TO_UNSIGNED(R, L'length));
end function \?<\;
-- Id: C.60
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<\ (L, TO_SIGNED(R, L'length));
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<=";
-- Id: C.63
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_UNSIGNED(L, R'length), R);
end function \?<=\;
-- Id: C.64
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_SIGNED(L, R'length),R);
end function \?<=\;
-- Id: C.65
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<=\ (L, TO_UNSIGNED(R, L'length));
end function \?<=\;
-- Id: C.66
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<=\ (L, TO_SIGNED(R, L'length));
end function \?<=\;
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
-- begin LCS-2006-120
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- These functions are in std_logic_1164 and are defined for
-- std_logic_vector. They are overloaded here.
function To_X01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01Z ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_X01Z ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_UX01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function To_UX01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-----------------------------------------------------------------------------
-- New/updated functions for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit functions, using the local ">" operator
-- UNSIGNED output
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- signed output
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- UNSIGNED output
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- signed output
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(to_unsigned (arg, size));
end function TO_UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(to_signed (arg, size));
end function TO_UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
-- Performs the boolean operation on every bit in the vector
-- L.15
function "and" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.16
function "and" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.17
function "or" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.18
function "or" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.19
function "nand" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.20
function "nand" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.21
function "nor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.22
function "nor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.23
function "xor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.24
function "xor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.25
function "xnor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.26
function "xnor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-- L.27
function "and" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.28
function "and" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.29
function "or" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.30
function "or" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.31
function "nand" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.32
function "nand" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.33
function "nor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.34
function "nor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.35
function "xor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.36
function "xor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.37
function "xnor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.38
function "xnor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
--------------------------------------------------------------------------
-- Reduction operations
--------------------------------------------------------------------------
-- %%% Remove the following 12 funcitons (old syntax)
function and_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return and_reduce (UNSIGNED ( l ));
end function and_reduce;
function and_reduce ( l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '1'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "and" (BUS_int(BUS_int'right),BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "and" (Upper, Lower);
end if;
end if;
return Result;
end function and_reduce;
function nand_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce ( l ));
end function nand_reduce;
function nand_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce (l ));
end function nand_reduce;
function or_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return or_reduce (UNSIGNED ( l ));
end function or_reduce;
function or_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "or" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "or" (Upper, Lower);
end if;
end if;
return Result;
end function or_reduce;
function nor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function nor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function xor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return xor_reduce (UNSIGNED ( l ));
end function xor_reduce;
function xor_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "xor" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "xor" (Upper, Lower);
end if;
end if;
return Result;
end function xor_reduce;
function xnor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
function xnor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% Replace the above with the following 12 functions (New syntax)
-- function "and" ( l : SIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "and" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "nand" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "nand" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "or" ( l : SIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "or" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "nor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "nor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "xor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xnor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- function "xnor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- TO_STRING
-------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
function to_string (value : UNSIGNED) return STRING is
alias ivalue : UNSIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_string (value : SIGNED) return STRING is
alias ivalue : SIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_hstring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value(value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value (value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_hstring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-----------------------------------------------------------------------------
-- Read and Write routines
-----------------------------------------------------------------------------
-- Routines copied from the "std_logic_1164_additions" package
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
good := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
-- purpose: or reduction
function or_reduce (
arg : STD_ULOGIC_VECTOR)
return STD_ULOGIC is
variable uarg : UNSIGNED (arg'range);
begin
uarg := unsigned(arg);
return or_reduce (uarg);
end function or_reduce;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
-- End copied code.
procedure READ (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- rtl_synthesis on
-- pragma synthesis_on
end package body numeric_std_additions;
|
gpl-3.0
|
b3ae383a1670a584d9851fa703b3b726
| 0.54003 | 3.704004 | false | false | false | false |
superboy0712/MIPS
|
MIPSProcessor_with_PC_inside.vhd
| 1 | 8,806 |
-- Part of TDT4255 Computer Design laboratory exercises
-- Group for Computer Architecture and Design
-- Department of Computer and Information Science
-- Norwegian University of Science and Technology
-- MIPSProcessor.vhd
-- The MIPS processor component to be used in Exercise 1 and 2.
-- TODO replace the architecture DummyArch with a working Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MIPSProcessor is
generic (
ADDR_WIDTH : integer := 8;
DATA_WIDTH : integer := 32
);
port (
clk, reset : in std_logic;
processor_enable : in std_logic;
imem_data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); -- instruction memory in
imem_address : out std_logic_vector(ADDR_WIDTH-1 downto 0);-- instruction memory address
dmem_data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data memory in
dmem_address : out std_logic_vector(ADDR_WIDTH-1 downto 0);-- data memory address
dmem_data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);-- data memory out
dmem_write_enable : out std_logic
);
end MIPSProcessor;
architecture behavioral of MIPSProcessor is
-- component declaration
COMPONENT MIPS_main_controller
PORT(
proc_en : IN std_logic;
clk : IN std_logic;
Opcode : IN std_logic_vector(31 downto 26);
PC_en : OUT std_logic;
IF_en : OUT std_logic;
ALUOp : OUT std_logic_vector(1 downto 0);
RegDst : OUT std_logic;
ALUSrc : OUT std_logic;
MemtoReg : OUT std_logic;
RegWrite : OUT std_logic;
MemRead : OUT std_logic;
MemWrite : OUT std_logic;
Branch : OUT std_logic;
Jump : OUT std_logic;
RF_WriteSrc : OUT std_logic
);
END COMPONENT;
COMPONENT reg_file
PORT(
clk : IN std_logic;
wr_en : IN std_logic;
rd_reg_num1 : IN std_logic_vector(4 downto 0);
rd_reg_num2 : IN std_logic_vector(4 downto 0);
wr_reg_num : IN std_logic_vector(4 downto 0);
wr_data : IN std_logic_vector(31 downto 0);
rd_data1 : OUT std_logic_vector(31 downto 0);
rd_data2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT alu
PORT(
alu_ctrl : IN std_logic_vector(3 downto 0);
alu_src1 : IN std_logic_vector(31 downto 0);
alu_src2 : IN std_logic_vector(31 downto 0);
alu_zero : OUT std_logic;
alu_result : OUT std_logic_vector(31 downto 0);
alu_carry : OUT std_logic
);
END COMPONENT;
-- COMPONENT MIPS_PC_with_src_select
-- PORT(
-- reset : IN std_logic;
-- PC_en : IN std_logic;
-- clk : IN std_logic;
-- PCSrc : IN std_logic;
-- offeset_address : IN std_logic_vector(31 downto 0);
-- PC : OUT std_logic_vector(31 downto 0)
-- );
-- END COMPONENT;
COMPONENT MIPS_ALU_ctrl
PORT(
funct_code : IN std_logic_vector(5 downto 0);
ALU_op : IN std_logic_vector(1 downto 0);
ALU_ctrl : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
-- signals declaration
-- instruction register, for stable fetch instruction
signal instr_reg : std_logic_vector (31 downto 0);
-- for stable processor_enable signal, delays half cycle
signal inside_clk : std_logic;
-- for address length compatible
signal dmem_address_32bit : std_logic_vector (31 downto 0);
signal imem_address_32bit : std_logic_vector (31 downto 0);
-- for reg_file
signal reg_file_WrReg : std_logic_vector (4 downto 0);
signal mem_to_reg_mux_output : std_logic_vector (31 downto 0);
signal reg_file_wrDat_Mux_output : std_logic_vector(31 downto 0);
signal reg_file_Rd1_to_ALUSrc1 : std_logic_vector(31 downto 0);
signal reg_file_Rd2 : std_logic_vector(31 downto 0); -- actually connected to dmem_data_out
signal upper_immediate : std_logic_vector(31 downto 0);
-- for ALU
signal ALU_Src2 : std_logic_vector(31 downto 0);
signal ALU_to_ALUCtrl : std_logic_vector(3 downto 0);
signal ALU_result : std_logic_vector(31 downto 0);
signal ALU_zero : std_logic;
signal ALU_carry : std_logic; -- not connected yet!! not implemented
-- for PC_with_MUX_and_shifter
signal PC : std_logic_vector (31 downto 0);
signal PC_output : std_logic_vector (31 downto 0);
signal PC_add_1 : std_logic_vector (31 downto 0);
signal PCSrc : std_logic;
signal PC_offeset_address : std_logic_vector (31 downto 0);
signal PC_branch_address : std_logic_vector (31 downto 0);
signal branch_tmp : std_logic_vector (31 downto 0);
signal Jump_address : std_logic_vector(31 downto 0);
-- for Main Controller
signal PC_en, IF_en, RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump, RF_WriteSrc: std_logic;
signal ALUOp : std_logic_vector(1 downto 0);
begin
-- component instantiation
Inst_MIPS_main_controller: MIPS_main_controller PORT MAP(
proc_en => processor_enable,
clk => inside_clk,
Opcode => instr_reg(31 downto 26),
PC_en => PC_en,
IF_en => IF_en,
ALUOp => ALUOp,
RegDst => RegDst,
ALUSrc => ALUSrc,
MemtoReg => MemtoReg,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
Branch => Branch,
Jump => Jump,
RF_WriteSrc => RF_WriteSrc
);
dmem_write_enable <= MemWrite;-- AND (NOT MemRead); -- no read_enable port from dmem
Inst_reg_file: reg_file PORT MAP(
clk => inside_clk,
wr_en => RegWrite,
rd_reg_num1 => instr_reg(25 downto 21),
rd_reg_num2 => instr_reg(20 downto 16),
wr_reg_num => reg_file_WrReg,
wr_data => reg_file_wrDat_Mux_output,
rd_data1 => reg_file_Rd1_to_ALUSrc1,
rd_data2 => reg_file_Rd2
);
Inst_alu: alu PORT MAP(
alu_ctrl => ALU_to_ALUCtrl,
alu_src1 => reg_file_Rd1_to_ALUSrc1,
alu_src2 => ALU_Src2,
alu_zero => ALU_zero,
alu_result => ALU_result,
alu_carry => ALU_carry
);
dmem_address_32bit <= ALU_result;
-- Inst_MIPS_PC_with_src_select: MIPS_PC_with_src_select PORT MAP(
-- reset => reset,
-- PC_en => PC_en,
-- clk => inside_clk,
-- PCSrc => PCSrc,
-- offeset_address => PC_offeset_address,
-- PC => imem_address_32bit
-- );
-- FOR PC
imem_address_32bit <= PC;
PC_add_1 <= std_logic_vector(unsigned(PC) + X"00000001");
Jump_address <= PC_add_1(31 downto 28) & "00" & instr_reg(25 downto 0); -- not shifting, becoz the actual mem_in is word address/ not byte address
PC_branch_address <= std_logic_vector(signed(PC_add_1) + signed(PC_offeset_address));
branch_tmp <= PC_add_1 when PCSrc = '0' else
PC_branch_address;
PC_output <= branch_tmp when Jump = '0' else
Jump_address;
PC_update : process(inside_clk)
begin
if rising_edge(inside_clk) then
if reset = '1' then PC <= X"00000000";
elsif reset = '0' then
if PC_en = '1' then PC <= PC_output;
end if;
end if;
end if;
end process;
--
PCSrc <= Branch AND ALU_zero;
inside_clk_generator : process(clk) -- change to delay 0.5 cycle after PC_CLK
begin
inside_clk <= NOT clk;
end process;
Inst_MIPS_ALU_ctrl: MIPS_ALU_ctrl PORT MAP(
funct_code => instr_reg(5 downto 0),
ALU_op => ALUOp,
ALU_ctrl => ALU_to_ALUCtrl
);
--
Instru_reg_fetch: process(inside_clk)
begin
if rising_edge(inside_clk) then
if IF_en = '1' then instr_reg <= imem_data_in;
end if;
end if;
end process;
MUX_RegDst : process(instr_reg(20 downto 16),instr_reg(15 downto 11),RegDst)
begin
if RegDst = '1' then reg_file_WrReg <= instr_reg(15 downto 11);
else reg_file_WrReg <= instr_reg(20 downto 16);
end if;
end process;
MUX_MemtoReg : process(MemtoReg, ALU_result, dmem_data_in)
begin
if MemtoReg = '1' then mem_to_reg_mux_output <= dmem_data_in;
else mem_to_reg_mux_output <= ALU_result;
end if;
end process;
-- for LUI upper immediate covert
upper_immediate <= instr_reg(15 downto 0) & X"0000";
MUX_regfile_WriteDat : reg_file_wrDat_Mux_output <= upper_immediate when RF_WriteSrc = '1' else
mem_to_reg_mux_output;
MUX_ALUSrc : process(ALUSrc, PC_offeset_address, reg_file_Rd2)
begin
if ALUSrc = '1' then ALU_Src2 <= PC_offeset_address;
else ALU_Src2 <= reg_file_Rd2;
end if;
end process;
Sign_extend : process(instr_reg(15 downto 0))
begin
PC_offeset_address <= std_logic_vector(resize(signed(instr_reg(15 downto 0)), PC_offeset_address'length));
end process;
dmem_data_out <= reg_file_Rd2;
-- use a register to delay half a cycle
--dmem_address <= std_logic_vector(resize(unsigned(dmem_address_32bit), dmem_address'length));
--imem_address <= std_logic_vector(resize(unsigned(imem_address_32bit), imem_address'length));
dmem_address <= dmem_address_32bit(7 downto 0); -- only use 8 least significant bits
imem_address <= imem_address_32bit(7 downto 0);
--ALU_carry <= '0'; -- not used
end architecture;
|
mit
|
beadf2db06fec1a4202b535ee0e6556c
| 0.656484 | 3.01989 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_gpr.vhd
| 2 | 5,517 |
-- $Id: pdp11_gpr.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_gpr - syn
-- Description: pdp11: general purpose registers
--
-- Dependencies: memlib/ram_1swar_1ar_gen
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.4 now numeric_std clean
-- 2008-08-22 161 1.0.3 rename ubf_ -> ibf_; use iblib
-- 2007-12-30 108 1.0.2 use ubf_byte[01]
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_gpr is -- general purpose registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end pdp11_gpr;
architecture syn of pdp11_gpr is
-- --------------------------------------
-- the register map determines the internal register file storage address
-- of a register. The mapping is
-- ADDR RNUM SET MODE
-- 0000 000 0 -- R0 set 0
-- 0001 001 0 -- R1 set 0
-- 0010 010 0 -- R2 set 0
-- 0011 011 0 -- R3 set 0
-- 0100 100 0 -- R4 set 0
-- 0101 101 0 -- R5 set 0
-- 0110 110 - 00 SP kernel mode
-- 0111 110 - 01 SP supervisor mode
-- 1000 000 1 -- R0 set 1
-- 1001 001 1 -- R1 set 1
-- 1010 010 1 -- R2 set 1
-- 1011 011 1 -- R3 set 1
-- 1100 100 1 -- R4 set 1
-- 1101 101 1 -- R5 set 1
-- 1110 111 - -- PC
-- 1111 110 - 11 SP user mode
procedure do_regmap (
signal RNUM : in slv3; -- register number
signal MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
signal RSET : in slbit; -- register set
signal ADDR : out slv4 -- internal address in regfile
) is
begin
if RNUM = c_gpr_pc then
ADDR <= "1110";
elsif RNUM = c_gpr_sp then
ADDR <= MODE(1) & "11" & MODE(0);
else
ADDR <= RSET & RNUM;
end if;
end procedure do_regmap;
-- --------------------------------------
signal MASRC : slv4 := (others=>'0'); -- mapped source register address
signal MADST : slv4 := (others=>'0'); -- mapped destination register address
signal WE1 : slbit := '0'; -- write enable high byte
signal MEMSRC : slv16 := (others=>'0');-- source reg data from memory
signal MEMDST : slv16 := (others=>'0');-- destination reg data from memory
signal R_PC : slv16 := (others=>'0'); -- PC register
begin
do_regmap(RNUM => ASRC, MODE => MODE, RSET => RSET, ADDR => MASRC);
do_regmap(RNUM => ADST, MODE => MODE, RSET => RSET, ADDR => MADST);
WE1 <= WE and not BYTOP;
GPR_LOW : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => WE,
ADDRA => MADST,
ADDRB => MASRC,
DI => DIN(ibf_byte0),
DOA => MEMDST(ibf_byte0),
DOB => MEMSRC(ibf_byte0));
GPR_HIGH : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => WE1,
ADDRA => MADST,
ADDRB => MASRC,
DI => DIN(ibf_byte1),
DOA => MEMDST(ibf_byte1),
DOB => MEMSRC(ibf_byte1));
proc_pc : process (CLK)
alias R_PC15 : slv15 is R_PC(15 downto 1); -- upper 15 bit of PC
begin
if rising_edge(CLK) then
if WE='1' and ADST=c_gpr_pc then
R_PC(ibf_byte0) <= DIN(ibf_byte0);
if BYTOP = '0' then
R_PC(ibf_byte1) <= DIN(ibf_byte1);
end if;
elsif PCINC = '1' then
R_PC15 <= slv(unsigned(R_PC15) + 1);
end if;
end if;
end process proc_pc;
DSRC <= R_PC when ASRC=c_gpr_pc else MEMSRC;
DDST <= R_PC when ADST=c_gpr_pc else MEMDST;
PC <= R_PC;
end syn;
|
gpl-2.0
|
e8b421ad0bf14b0722c7f3c8b26e2311
| 0.520754 | 3.491772 | false | false | false | false |
freecores/w11
|
rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd
| 2 | 3,239 |
-- $Id: s3board_fusp_dummy.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s3board_fusp_dummy - syn
-- Description: s3board minimal target (base+fusp; serport loopback)
--
-- Dependencies: -
-- To test: tb_s3board_fusp
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.2 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.1 rename s3board_usp_dummy->s3board_fusp_dummy
-- 2010-05-01 286 1.0 Initial version (derived from s3board_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.s3boardlib.all;
entity s3board_fusp_dummy is -- S3BOARD dummy (base+fusp; loopback)
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end s3board_fusp_dummy;
architecture syn of s3board_fusp_dummy is
begin
O_TXD <= I_RXD;
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
|
gpl-2.0
|
e9107cf1c44472da924b79f8cc78786a
| 0.544304 | 3.346074 | false | false | false | false |
unhold/hdl
|
vhdl/state_pack.vhd
| 1 | 2,908 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.rtl_pack.all;
-- Proposal for a generic state encoding/decoding and error injection package,
-- using only VHDL-93.
package state_pack is
-- Generic natural encoding/decoding, e.g. for states.
-- Use the attributes t'val and t'pos to use it with enumeration types.
-- TODO: Add correctable encodings, e.g. Hamming code.
type encoding_t is (binary, onehot);
subtype code_t is std_ulogic_vector;
function code_length(length : natural; encoding : encoding_t) return natural;
function encode(value, length : natural; encoding : encoding_t) return code_t;
function decode(code : code_t; encoding : encoding_t) return natural;
function error(code : code_t; encoding : encoding_t) return boolean;
-- Generic value injection into codes, e.g. for error injection into states.
-- In this implementation it can handle only single bit errors,
-- but the record and function could be changed without impacting user code.
type inject_t is record
index : natural;
write : boolean;
end record;
constant inject_off_c : inject_t := (
index => 0,
write => false);
function handle_inject(code : code_t; inject : inject_t) return code_t;
end;
package body state_pack is
function code_length(length : natural; encoding : encoding_t) return natural is
begin
case encoding is
when binary => return log_ceil(length);
when onehot => return length;
end case;
end;
function encode_onehot(value, length : natural) return code_t is
variable code : code_t(length-1 downto 0);
begin
code := (others => '0');
code(value) := '1';
return code;
end;
function encode(value, length : natural; encoding : encoding_t) return code_t is
begin
case encoding is
when binary =>
return std_ulogic_vector(to_unsigned(value, code_length(length, encoding)));
when onehot =>
return encode_onehot(value, length);
end case;
end;
function decode(code : code_t; encoding : encoding_t) return integer is
begin
if is_x(code) then
return -1;
else
case encoding is
when binary =>
return to_integer(unsigned(code));
when onehot =>
if one_count(code) /= 1 then
return -1;
else
return log_ceil(to_integer(unsigned(code)));
end if;
end case;
end if;
end;
function error(code : code_t; encoding : encoding_t) return boolean is
begin
return decode(code, encoding) = -1;
end;
function handle_inject(code : code_t; inject : inject_t) return code_t is
variable result : code_t(code'high downto code'low);
begin
if inject.write and inject.index >= code'low and inject.index <= code'high then
result := code;
result(inject.index) := not result(inject.index);
return result;
else
return code;
end if;
end;
end;
|
gpl-3.0
|
efb264347ca5e8e7ba74fcd7454ec403
| 0.674003 | 3.389277 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/bram_fifo.vhd
| 1 | 4,245 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Bram_FIFO is
generic (
width : integer := 32;
dept : integer := 256;
set_prog_full_value : std_logic := '0';
prog_full_value : integer := 0;
set_empty_value : std_logic := '0';
empty_value : std_logic_vector := x"abcdefab"
);
port (
clk : in std_logic;
din : in std_logic_vector(width-1 downto 0);
rd_en : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
data_count : OUT std_logic_VECTOR(10 downto 0);
dout : out std_logic_vector(width-1 downto 0);
empty : out std_logic;
full : out std_logic;
prog_full : out std_logic
);
end Bram_FIFO;
architecture Behavioral of Bram_FIFO is
type bram_type is array (0 to dept-1) of std_logic_vector (width-1 downto 0);
signal bram : bram_type; -- := (others => x"CDCDCDCD"); -- default value only for debug purpose
signal read_ptr : integer range 0 to dept-1;
signal write_ptr : integer range 0 to dept-1;
signal counter : integer range 0 to dept-1;
signal read_data : std_logic_vector(width-1 downto 0);
signal cache_data : std_logic_vector(width-1 downto 0);
signal read_cache_data : std_logic;
signal push : std_logic;
signal pop : std_logic;
signal sfull, sempty : std_logic;
begin
data_count <= conv_std_logic_vector(counter, data_count'length);
sempty <= '1' when counter = 0 else '0';
sfull <= '1' when counter = dept else '0';
empty <= sempty;
full <= sfull;
--IF PROG_FULL IS SET SET prog_full TO 1 WHEN MORE THAN prog_full_value VALUES ARE IN THE FIFO
WITH_PROG_FULL_VALUE : if (set_prog_full_value = '1') generate
prog_full <= '1' when counter >= prog_full_value else '0';
end generate;
--ENABLE WRITE REQEUST IF WRITE_EN IS SET AND EITHER THE FIFO IS NOT FULL (COUNTER = 1024) OR A READ IS PROCESSED IN THE SAME CLOCK
push <= wr_en and (not sfull or rd_en);
--ENABLE READ REQEUST IF READ_EN IS SET AND THE FIFO IS NOT EMPTY
pop <= rd_en and not sempty;
--BRAM READ WRITE LOGIC
fifo_read_write: process (CLK) is
begin
if rising_edge(CLK) then
if (push = '1') then
bram(conv_integer(write_ptr)) <= din;
end if;
--if pop is selected read next value (read_ptr is raised with one clock delay and bram read operation needs one clock thus its required to read ahead)
if (pop = '1') then
read_data <= bram(conv_integer((read_ptr+1) mod dept));
--otherwise read data at current read-pointer
else
read_data <= bram(conv_integer(read_ptr));
end if;
end if;
end process;
--BRAM READ WRITE LOGIC
fifo_fwft: process (CLK) is
begin
if rising_edge(CLK) then
read_cache_data <= '0';
if( pop = '1' and push = '1' and counter = 1 ) then
cache_data <= din;
read_cache_data <= '1';
--allow fwft one clock cycle after data is written when the fifo is empty
elsif ( pop = '0' and sempty = '1' and push = '1' ) then
cache_data <= din;
read_cache_data <= '1';
end if;
end if;
end process;
--IF EMPTY_VALUE IS SET ENABLE OUTPUT OF THIS VALUE WHEN THE FIFO IS EMPTY
WITH_EMPTY_VALUE : if (set_empty_value = '1') generate
dout <= empty_value when sempty = '1' else cache_data when read_cache_data = '1' else read_data;
end generate;
WITHOUT_EMPTY_VALUE : if (set_empty_value = '0') generate
dout <= cache_data when read_cache_data = '1' else read_data;
end generate;
--WIRTE/READ POINTER AND COUNTER LOGIC
fifo_logic_proc : process(clk)
begin
if (clk'event AND clk='1') then
if (rst = '1') then
read_ptr <= 0;
write_ptr <= 0;
counter <= 0;
else
if(pop = '1') then
--INCREASE READ POINTER
read_ptr <= (read_ptr+1) mod dept;
end if;
if(push = '1') then
--INCREASE WRITE POINTER ((write_ptr + 1) % 1024)
write_ptr <= (write_ptr+1) mod dept;
end if;
--DECREASE FIFO FILL COUNTER WHEN ONLY POP INCREASE WHEN ONLY PUSH LEAVE OTHERWISE
counter <= counter + conv_integer(push) - conv_integer(pop);
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
0ea27330cb31a7931d6fd230b424d609
| 0.625677 | 3.165548 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/decryption_mem/example_design/decryption_mem_exdes.vhd
| 1 | 5,306 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: decryption_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY decryption_mem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
RSTB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END decryption_mem_exdes;
ARCHITECTURE xilinx OF decryption_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT decryption_mem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
RSTB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : decryption_mem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
RSTB => RSTB,
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
gpl-3.0
|
36bcd704312f60f6d54ce455d60f660c
| 0.538447 | 4.489002 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rbd_tester.vhd
| 2 | 11,109 |
-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_tester - syn
-- Description: rbus dev: rbus tester
--
-- Dependencies: memlib/fifo_1c_dram_raw
--
-- Test bench: rlink/tb/tb_rlink (used as test target)
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.4 now numeric_std clean
-- 2010-12-31 352 1.0.3 simplify irb_ack logic
-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
-- 2010-12-04 343 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register
-- 15 nofifo r/w/- a 1 disables fifo, to test delayed aborts
-- 14:12 stat r/w/- echo'ed on RB_STAT
-- 11:00 nbusy r/w/- busy cycles (for data and fifo access)
-- bbbbbb01 15:00 data r/w/- Data register (just w/r reg, no function)
-- bbbbbb10 15:00 fifo r/w/- Fifo interface register
-- bbbbbb11 attn r/w/- Attn/Length register
-- 15:00 w: ping RB_LAM lines
-- 9:00 r: return cycle length of last access
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_tester is -- rbus dev: rbus tester
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#11110000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end entity rbd_tester;
architecture syn of rbd_tester is
constant awidth : positive := 4; -- fifo address width
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_data : slv2 := "01"; -- data address offset
constant rbaddr_fifo : slv2 := "10"; -- fifo address offset
constant rbaddr_attn : slv2 := "11"; -- attn address offset
constant cntl_rbf_nofifo : integer := 15;
subtype cntl_rbf_stat is integer range 14 downto 12;
subtype cntl_rbf_nbusy is integer range 9 downto 0;
constant init_rbf_cntl : integer := 0;
constant init_rbf_data : integer := 1;
constant init_rbf_fifo : integer := 2;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
nofifo : slbit; -- disable fifo flag
stat : slv3; -- stat setting
nbusy : slv10; -- nbusy setting
data : slv16; -- data register
act_1 : slbit; -- rbsel and (re or we) in last cycle
ncyc : slv10; -- cycle length of last access
cntbusy : slv10; -- busy timer
cntcyc : slv10; -- cycle length counter
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
'0', -- nofifo
(others=>'0'), -- stat
(others=>'0'), -- nbusy
(others=>'0'), -- data
'0', -- act_1
(others=>'0'), -- ncyc
(others=>'0'), -- cntbusy
(others=>'0') -- cntcyc
);
constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_RESET : slbit := '0';
signal FIFO_RE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_1c_dram_raw
generic map (
AWIDTH => awidth,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
RE => FIFO_RE,
WE => FIFO_WE,
DI => RB_MREQ.din,
DO => FIFO_DO,
SIZE => FIFO_SIZE,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irblam : slv16 := (others=>'0');
variable ififo_re : slbit := '0';
variable ififo_we : slbit := '0';
variable ififo_reset : slbit := '0';
variable isbusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irblam := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ififo_re := '0';
ififo_we := '0';
ififo_reset := '0';
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
n.cntcyc := (others=>'0'); -- clear cycle length counter
end if;
end if;
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
if r.cntcyc /= cntcyc_max then -- if cycle counter < max
n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
end if;
end if;
irb_ack := irbena; -- ack all (some rejects later)
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we='1' then
n.nofifo := RB_MREQ.din(cntl_rbf_nofifo);
n.stat := RB_MREQ.din(cntl_rbf_stat);
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
if r.nofifo='1' and RB_MREQ.din(cntl_rbf_nofifo)='0' then
ififo_reset := '1';
end if;
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if RB_MREQ.we='1' and isbusy='0' then
n.data := RB_MREQ.din;
end if;
when rbaddr_fifo =>
if r.nofifo = '0' then -- if fifo enabled
irb_busy := irbena and isbusy;
if RB_MREQ.re='1' and isbusy='0' then
if FIFO_EMPTY = '1' then
irb_err := '1';
else
ififo_re := '1';
end if;
end if;
if RB_MREQ.we='1' and isbusy='0' then
if FIFO_FULL = '1' then
irb_err := '1';
else
ififo_we := '1';
end if;
end if;
else -- else: if fifo disabled
irb_ack := '0'; -- nak it
if isbusy = '1' then -- or do a delayed nak
irb_ack := irbena;
irb_busy := irbena;
end if;
end if;
when rbaddr_attn =>
if RB_MREQ.we = '1' then
irblam := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
-- rbus output driver
-- send a '0101...' pattern when selected and busy or err
-- send data only when busy=0 and err=0
-- this extra logic allows to debug rlink state machine
if r.rbsel = '1' then
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_stat) := r.stat;
irb_dout(cntl_rbf_nofifo) := r.nofifo;
irb_dout(cntl_rbf_nbusy) := r.nbusy;
when rbaddr_data =>
irb_dout := r.data;
when rbaddr_fifo =>
if r.nofifo='0' and FIFO_EMPTY = '0' then
irb_dout := FIFO_DO;
end if;
when rbaddr_attn =>
irb_dout(r.cntcyc'range) := r.ncyc;
when others => null;
end case;
else
irb_dout := "0101010101010101";
end if;
end if;
-- init transactions
if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR then
if RB_MREQ.din(init_rbf_cntl) = '1' then
n.nofifo := '0';
n.stat := (others=>'0');
n.nbusy := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_data) = '1' then
n.data := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_fifo) = '1' then
ififo_reset := '1';
end if;
end if;
-- other transactions
if irbena='0' and r.act_1='1' then
n.ncyc := r.cntcyc;
end if;
n.act_1 := irbena;
N_REGS <= n;
FIFO_RE <= ififo_re;
FIFO_WE <= ififo_we;
FIFO_RESET <= ififo_reset;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_LAM <= irblam;
RB_STAT <= r.stat;
end process proc_next;
end syn;
|
gpl-2.0
|
19f669e7a548350c653773fd124a0659
| 0.499865 | 3.642295 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rbd_rbmon.vhd
| 2 | 14,310 |
-- $Id: rbd_rbmon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_rbmon - syn
-- Description: rbus dev: rbus monitor
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/f Control register
-- 00 go r/w/f writing 1 clears add
-- bbbbbb01 alim r/w/- Address limit register
-- 15:08 hilim r/w/- upper address limit (def: ff)
-- 07:00 lolim r/w/- lower address limit (def: 00)
-- bbbbbb10 addr r/w/- Address register
-- 15 wrap r/0/- line address wrapped (cleared on write)
-- *:02 laddr r/w/- line address
-- 01:00 waddr r/w/- word address
-- bbbbbb11 data r/w/- Data register
--
-- data format:
-- word 3 15 : ack
-- 14 : busy
-- 13 : err
-- 12 : nak
-- 11 : tout
-- 09 : init
-- 08 : we
-- 07:00 : addr
-- word 2 data
-- word 1 15:00 : delay to prev (lsb's)
-- word 0 15:12 : delay to prev (msb's)
-- 11:00 : number of busy cycles
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#11111100#,8));
AWIDTH : positive := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor)
);
end entity rbd_rbmon;
architecture syn of rbd_rbmon is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_alim : slv2 := "01"; -- alim address offset
constant rbaddr_addr : slv2 := "10"; -- addr address offset
constant rbaddr_data : slv2 := "11"; -- data address offset
constant cntl_rbf_go : integer := 0;
subtype alim_rbf_hilim is integer range 15 downto 8;
subtype alim_rbf_lolim is integer range 7 downto 0;
constant addr_rbf_wrap : integer := 15;
subtype addr_rbf_laddr is integer range 2+AWIDTH-1 downto 2;
subtype addr_rbf_waddr is integer range 1 downto 0;
constant dat3_rbf_ack : integer := 15;
constant dat3_rbf_busy : integer := 14;
constant dat3_rbf_err : integer := 13;
constant dat3_rbf_nak : integer := 12;
constant dat3_rbf_tout : integer := 11;
constant dat3_rbf_init : integer := 9;
constant dat3_rbf_we : integer := 8;
subtype dat3_rbf_addr is integer range 7 downto 0;
subtype dat0_rbf_ndlymsb is integer range 15 downto 12;
subtype dat0_rbf_nbusy is integer range 11 downto 0;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
go : slbit; -- go flag
hilim : slv8; -- upper address limit
lolim : slv8; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
rbtake_1 : slbit; -- rb capture active in last cycle
rbaddr : slv8; -- rbus trace: addr
rbinit : slbit; -- rbus trace: init
rbwe : slbit; -- rbus trace: we
rback : slbit; -- rbus trace: ack seen
rbbusy : slbit; -- rbus trace: busy seen
rberr : slbit; -- rbus trace: err seen
rbnak : slbit; -- rbus trace: nak detected
rbtout : slbit; -- rbus trace: tout detected
rbdata : slv16; -- rbus trace: data
rbnbusy : slv12; -- rbus number of busy cycles
rbndly : slv20; -- rbus delay to prev. access
end record regs_type;
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
'0', -- rbsel
'0', -- go (default is off)
(others=>'1'), -- hilim (def: ff)
(others=>'0'), -- lolim (def: 00)
'0', -- wrap
laddrzero, -- laddr
"00", -- waddr
'0', -- rbtake_1
(others=>'0'), -- rbaddr
'0','0','0','0','0', -- rbinit,rbwe,rback,rbbusy,rberr
'0','0', -- rbnak,rbtout
(others=>'0'), -- rbdata
(others=>'0'), -- rbnbusy
(others=>'0') -- rbndly
);
constant rbnbusylast : slv12 := (others=>'1');
constant rbndlylast : slv20 := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM0_DI : slv32 := (others=>'0');
signal BRAM1_DI : slv32 := (others=>'0');
signal BRAM0_DO : slv32 := (others=>'0');
signal BRAM1_DO : slv32 := (others=>'0');
begin
assert AWIDTH<=13
report "assert(AWIDTH<=13): max address width supported"
severity failure;
BRAM1 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.laddr,
DI => BRAM1_DI,
DO => BRAM1_DO
);
BRAM0 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.laddr,
DI => BRAM0_DI,
DO => BRAM0_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, RB_SRES_SUM, BRAM0_DO, BRAM1_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0';
variable ibramwe : slbit := '0';
variable rbtake : slbit := '0';
variable laddr_inc : slbit := '0';
variable idat0 : slv16 := (others=>'0');
variable idat1 : slv16 := (others=>'0');
variable idat2 : slv16 := (others=>'0');
variable idat3 : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
ibramwe := '0';
laddr_inc := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
ibramen := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
n.go := RB_MREQ.din(cntl_rbf_go);
if RB_MREQ.din(cntl_rbf_go)='1' then
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
end if;
end if;
when rbaddr_alim =>
if RB_MREQ.we = '1' then
n.hilim := RB_MREQ.din(alim_rbf_hilim);
n.lolim := RB_MREQ.din(alim_rbf_lolim);
end if;
when rbaddr_addr =>
if RB_MREQ.we = '1' then
n.go := '0';
n.wrap := '0';
n.laddr := RB_MREQ.din(addr_rbf_laddr);
n.waddr := RB_MREQ.din(addr_rbf_waddr);
end if;
when rbaddr_data =>
if r.go='1' or RB_MREQ.we='1' then
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
n.waddr := slv(unsigned(r.waddr) + 1);
if r.waddr = "11" then
laddr_inc := '1';
end if;
end if;
when others => null;
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_go) := r.go;
when rbaddr_alim =>
irb_dout(alim_rbf_hilim) := r.hilim;
irb_dout(alim_rbf_lolim) := r.lolim;
when rbaddr_addr =>
irb_dout(addr_rbf_wrap) := r.wrap;
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data =>
case r.waddr is
when "11" => irb_dout := BRAM1_DO(31 downto 16);
when "10" => irb_dout := BRAM1_DO(15 downto 0);
when "01" => irb_dout := BRAM0_DO(31 downto 16);
when "00" => irb_dout := BRAM0_DO(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- rbus monitor
-- a rbus transaction are captured if the address is in alim window
-- and the access is not refering to rbd_rbmon itself
rbtake := '0';
if RB_MREQ.aval='1' and irbena='1' then -- aval and (re or we)
if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(RB_MREQ.addr)<=unsigned(r.hilim) and
r.rbsel='0' then -- and not self
rbtake := '1';
end if;
end if;
if RB_MREQ.init = '1' then -- also take init's
rbtake := '1';
end if;
if rbtake = '1' then -- if capture active
n.rbaddr := RB_MREQ.addr; -- keep track of some state
n.rbinit := RB_MREQ.init;
n.rbwe := RB_MREQ.we;
if RB_MREQ.init='1' or RB_MREQ.we='1' then -- for write/init of din
n.rbdata := RB_MREQ.din;
else -- for read of dout
n.rbdata := RB_SRES_SUM.dout;
end if;
if r.rbtake_1 = '0' then -- if initial cycle of a transaction
n.rback := RB_SRES_SUM.ack;
n.rbbusy := RB_SRES_SUM.busy;
n.rberr := RB_SRES_SUM.err;
n.rbnbusy := (others=>'0');
else -- if non-initial cycles
if RB_SRES_SUM.err = '1' then -- keep track of err flags
n.rberr := '1';
end if;
if r.rbnbusy /= rbnbusylast then -- and count
n.rbnbusy := slv(unsigned(r.rbnbusy) + 1);
end if;
end if;
n.rbnak := not RB_SRES_SUM.ack;
n.rbtout := RB_SRES_SUM.busy;
else -- if capture not active
if r.go='1' and r.rbtake_1='1' then -- active and transaction just ended
ibramen := '1';
ibramwe := '1';
laddr_inc := '1';
end if;
if r.rbtake_1 = '1' then -- rbus transaction just ended
n.rbndly := (others=>'0'); -- clear delay counter
else -- just idle
if r.rbndly /= rbndlylast then -- count cycles
n.rbndly := slv(unsigned(r.rbndly) + 1);
end if;
end if;
end if;
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
end if;
end if;
idat3 := (others=>'0');
idat3(dat3_rbf_ack) := r.rback;
idat3(dat3_rbf_busy) := r.rbbusy;
idat3(dat3_rbf_err) := r.rberr;
idat3(dat3_rbf_nak) := r.rbnak;
idat3(dat3_rbf_tout) := r.rbtout;
idat3(dat3_rbf_init) := r.rbinit;
idat3(dat3_rbf_we) := r.rbwe;
idat3(dat3_rbf_addr) := r.rbaddr;
idat2 := r.rbdata;
idat1 := r.rbndly(15 downto 0);
idat0(dat0_rbf_ndlymsb) := r.rbndly(19 downto 16);
idat0(dat0_rbf_nbusy) := r.rbnbusy;
n.rbtake_1 := rbtake;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
|
gpl-2.0
|
a29230154afbf21d9ea57cca29592ad5
| 0.495318 | 3.560587 | false | false | false | false |
freecores/w11
|
rtl/vlib/comlib/byte2cdata.vhd
| 2 | 3,996 |
-- $Id: byte2cdata.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: byte2cdata - syn
-- Description: Byte stream to 9 bit comma,data converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity byte2cdata is -- byte stream -> 9bit comma,data
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv9; -- output data; bit 8 = comma flag
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end byte2cdata;
architecture syn of byte2cdata is
type state_type is (
s_idle,
s_data,
s_escape
);
type regs_type is record
data : slv9; -- current data
state : state_type; -- state
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),
s_idle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert NCOMM <= 14
report "assert(NCOMM <= 14)"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, HOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ival := '0';
ibusy := '1';
case r.state is
when s_idle =>
ibusy := '0';
if ENA = '1' then
n.data := "0" & DI;
n.state := s_data;
if DI(7 downto 4) = CPREF then
if DI(3 downto 0) = "1111" then
n.state := s_escape;
elsif unsigned(DI(3 downto 0)) <= NCOMM then
n.data := "10000" & DI(3 downto 0);
n.state := s_data;
end if;
end if;
end if;
when s_data =>
ival := '1';
if HOLD = '0' then
n.state := s_idle;
end if;
when s_escape =>
ibusy := '0';
if ENA = '1' then
n.data := "0" & CPREF & DI(3 downto 0);
n.state := s_data;
end if;
when others => null;
end case;
N_REGS <= n;
DO <= r.data;
VAL <= ival;
BUSY <= ibusy;
end process proc_next;
end syn;
|
gpl-2.0
|
d781c7c31c2622466157e9b570970d39
| 0.511762 | 3.759172 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_tmu.vhd
| 1 | 8,752 |
-- $Id: pdp11_tmu.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
-- Description: pdp11: trace and monitor unit
--
-- Dependencies: -
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use local clkcycle count instead of simbus global
-- 2011-11-18 427 1.0.7 now numeric_std clean
-- 2010-10-17 333 1.0.6 use ibus V2 interface
-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
-- 2008-04-19 137 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end pdp11_tmu;
architecture sim of pdp11_tmu is
signal R_FIRST : slbit := '1';
begin
proc_tm: process (CLK)
variable oline : line;
variable clkcycle : integer := 0;
variable ipsw : slv16 := (others=>'0');
variable ibaddr : slv16 := (others=>'0');
variable emaddr : slv22 := (others=>'0');
variable dp_ireg_we_last : slbit := '0';
variable vm_ibsres_busy_last : slbit := '0';
variable vm_ibsres_ack_last : slbit := '0';
variable wcycle : boolean := false;
file ofile : text open write_mode is "tmu_ofile";
begin
if rising_edge(CLK) then
clkcycle := clkcycle + 1;
if R_FIRST = '1' then
R_FIRST <= '0';
write(oline, string'("#"));
write(oline, string'(" clkcycle:d"));
write(oline, string'(" cpu:o"));
write(oline, string'(" dp.pc:o"));
write(oline, string'(" dp.psw:o"));
write(oline, string'(" dp.ireg:o"));
write(oline, string'(" dp.ireg_we:b"));
write(oline, string'(" dp.ireg_we_last:b")); -- is ireg_we last cycle
write(oline, string'(" dp.dsrc:o"));
write(oline, string'(" dp.ddst:o"));
write(oline, string'(" dp.dtmp:o"));
write(oline, string'(" dp.dres:o"));
write(oline, string'(" dp.gpr_adst:o"));
write(oline, string'(" dp.gpr_mode:o"));
write(oline, string'(" dp.gpr_bytop:b"));
write(oline, string'(" dp.gpr_we:b"));
write(oline, string'(" vm.ibmreq.aval:b"));
write(oline, string'(" vm.ibmreq.re:b"));
write(oline, string'(" vm.ibmreq.we:b"));
write(oline, string'(" vm.ibmreq.rmw:b"));
write(oline, string'(" vm.ibmreq.be0:b"));
write(oline, string'(" vm.ibmreq.be1:b"));
write(oline, string'(" vm.ibmreq.cacc:b"));
write(oline, string'(" vm.ibmreq.racc:b"));
write(oline, string'(" vm.ibmreq.addr:o"));
write(oline, string'(" vm.ibmreq.din:o"));
write(oline, string'(" vm.ibsres.ack:b"));
write(oline, string'(" vm.ibsres.busy:b"));
write(oline, string'(" vm.ibsres.dout:o"));
write(oline, string'(" co.cpugo:b"));
write(oline, string'(" co.cpuhalt:b"));
write(oline, string'(" sy.emmreq.req:b"));
write(oline, string'(" sy.emmreq.we:b"));
write(oline, string'(" sy.emmreq.be:b"));
write(oline, string'(" sy.emmreq.cancel:b"));
write(oline, string'(" sy.emmreq.addr:o"));
write(oline, string'(" sy.emmreq.din:o"));
write(oline, string'(" sy.emsres.ack_r:b"));
write(oline, string'(" sy.emsres.ack_w:b"));
write(oline, string'(" sy.emsres.dout:o"));
write(oline, string'(" sy.chit:b"));
writeline(ofile, oline);
end if;
ipsw := (others=>'0');
ipsw(psw_ibf_cmode) := DM_STAT_DP.psw.cmode;
ipsw(psw_ibf_pmode) := DM_STAT_DP.psw.pmode;
ipsw(psw_ibf_rset) := DM_STAT_DP.psw.rset;
ipsw(psw_ibf_pri) := DM_STAT_DP.psw.pri;
ipsw(psw_ibf_tflag) := DM_STAT_DP.psw.tflag;
ipsw(psw_ibf_cc) := DM_STAT_DP.psw.cc;
ibaddr := "1110000000000000";
ibaddr(DM_STAT_VM.ibmreq.addr'range) := DM_STAT_VM.ibmreq.addr;
emaddr := (others=>'0');
emaddr(DM_STAT_SY.emmreq.addr'range) := DM_STAT_SY.emmreq.addr;
wcycle := false;
if dp_ireg_we_last='1' or
DM_STAT_DP.gpr_we='1' or
DM_STAT_SY.emmreq.req='1' or
DM_STAT_SY.emsres.ack_r='1' or
DM_STAT_SY.emsres.ack_w='1' or
DM_STAT_SY.emmreq.cancel='1' or
DM_STAT_VM.ibmreq.re='1' or
DM_STAT_VM.ibmreq.we='1' or
DM_STAT_VM.ibsres.ack='1'
then
wcycle := true;
end if;
if DM_STAT_VM.ibsres.busy='0' and
(vm_ibsres_busy_last='1' and vm_ibsres_ack_last='0')
then
wcycle := true;
end if;
if ENA = '0' then -- if not enabled
wcycle := false; -- force to not logged...
end if;
if wcycle then
write(oline, clkcycle, right, 9);
write(oline, string'(" 0"));
writeoct(oline, DM_STAT_DP.pc, right, 7);
writeoct(oline, ipsw, right, 7);
writeoct(oline, DM_STAT_DP.ireg, right, 7);
write(oline, DM_STAT_DP.ireg_we, right, 2);
write(oline, dp_ireg_we_last, right, 2);
writeoct(oline, DM_STAT_DP.dsrc, right, 7);
writeoct(oline, DM_STAT_DP.ddst, right, 7);
writeoct(oline, DM_STAT_DP.dtmp, right, 7);
writeoct(oline, DM_STAT_DP.dres, right, 7);
writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
write(oline, DM_STAT_DP.gpr_bytop, right, 2);
write(oline, DM_STAT_DP.gpr_we, right, 2);
write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
write(oline, DM_STAT_VM.ibmreq.re, right, 2);
write(oline, DM_STAT_VM.ibmreq.we, right, 2);
write(oline, DM_STAT_VM.ibmreq.rmw, right, 2);
write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
writeoct(oline, ibaddr, right, 7);
writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
write(oline, DM_STAT_VM.ibsres.ack, right, 2);
write(oline, DM_STAT_VM.ibsres.busy, right, 2);
writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7);
write(oline, DM_STAT_CO.cpugo, right, 2);
write(oline, DM_STAT_CO.cpuhalt, right, 2);
write(oline, DM_STAT_SY.emmreq.req, right, 2);
write(oline, DM_STAT_SY.emmreq.we, right, 2);
write(oline, DM_STAT_SY.emmreq.be, right, 3);
write(oline, DM_STAT_SY.emmreq.cancel, right, 2);
writeoct(oline, emaddr, right, 9);
writeoct(oline, DM_STAT_SY.emmreq.din, right, 7);
write(oline, DM_STAT_SY.emsres.ack_r, right, 2);
write(oline, DM_STAT_SY.emsres.ack_w, right, 2);
writeoct(oline, DM_STAT_SY.emsres.dout, right, 7);
write(oline, DM_STAT_SY.chit, right, 2);
writeline(ofile, oline);
end if;
dp_ireg_we_last := DM_STAT_DP.ireg_we;
vm_ibsres_busy_last := DM_STAT_VM.ibsres.busy;
vm_ibsres_ack_last := DM_STAT_VM.ibsres.ack;
end if;
end process proc_tm;
end sim;
|
gpl-2.0
|
b361dbcabe15fbf1b4f87fed4f04ed01
| 0.561357 | 3.234294 | false | false | false | false |
freecores/w11
|
rtl/vlib/genlib/debounce_gen.vhd
| 2 | 3,823 |
-- $Id: debounce_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: debounce_gen - syn
-- Description: Generic signal debouncer
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2007-12-26 105 1.0.2 add default for RESET
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-29 61 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end entity debounce_gen;
architecture syn of debounce_gen is
constant cntzero : slv(CWIDTH-1 downto 0) := (others=>'0');
constant datazero : slv(dWIDTH-1 downto 0) := (others=>'0');
type regs_type is record
cecnt : slv(CWIDTH-1 downto 0); -- clock interval counter
dref : slv(DWIDTH-1 downto 0); -- data reference
dchange : slv(DWIDTH-1 downto 0); -- data change flag
dout : slv(DWIDTH-1 downto 0); -- data output
end record regs_type;
constant regs_init : regs_type := (
cntzero,
datazero,
datazero,
datazero
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CEDIV<=2**CWIDTH report "assert(CEDIV<=2**CWIDTH)" severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS.cecnt <= cntzero;
R_REGS.dref <= DI;
R_REGS.dchange <= datazero;
R_REGS.dout <= DI;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, DI)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
for i in DI'range loop
if DI(i) /= r.dref(i) then
n.dchange(i) := '1';
end if;
end loop;
if CE_INT = '1' then
if unsigned(r.cecnt) = 0 then
n.cecnt := slv(to_unsigned(CEDIV-1,CWIDTH));
n.dref := DI;
n.dchange := datazero;
for i in DI'range loop
if r.dchange(i) = '0' then
n.dout(i) := r.dref(i);
end if;
end loop;
else
n.cecnt := slv(unsigned(r.cecnt) - 1);
end if;
end if;
N_REGS <= n;
DO <= r.dout;
end process proc_next;
end syn;
|
gpl-2.0
|
6c141ecca011650cbf5c6061ea1a9502
| 0.569448 | 3.599812 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/142c74a63b21c0be/fifo_generator_0_sim_netlist.vhdl
| 1 | 308,097 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 09:52:04 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_sim_netlist.vhdl
-- Design : fifo_generator_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
\gic0.gc0.count_d1_reg[1]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC;
comp2 : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gic0.gc0.count_d1_reg[7]\,
S(2) => \gic0.gc0.count_d1_reg[5]\,
S(1) => \gic0.gc0.count_d1_reg[3]\,
S(0) => \gic0.gc0.count_d1_reg[1]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_d1_reg[9]\
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AEAA"
)
port map (
I0 => comp1,
I1 => comp2,
I2 => \out\,
I3 => wr_en,
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp2 : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : in STD_LOGIC;
\gic0.gc0.count_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_reg[9]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gic0.gc0.count_reg[7]\,
S(2) => \gic0.gc0.count_reg[5]\,
S(1) => \gic0.gc0.count_reg[3]\,
S(0) => \gic0.gc0.count_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_reg[9]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair8";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => \plusOp__0\(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
begin
\rd_dc_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0),
Q => rd_data_count(0)
);
\rd_dc_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1),
Q => rd_data_count(1)
);
\rd_dc_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2),
Q => rd_data_count(2)
);
\rd_dc_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3),
Q => rd_data_count(3)
);
\rd_dc_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4),
Q => rd_data_count(4)
);
\rd_dc_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5),
Q => rd_data_count(5)
);
\rd_dc_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6),
Q => rd_data_count(6)
);
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7),
Q => rd_data_count(7)
);
\rd_dc_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8),
Q => rd_data_count(8)
);
\rd_dc_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9),
Q => rd_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
port (
prog_empty : out STD_LOGIC;
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
signal \gdiff.diff_pntr_pad_reg_n_0_[10]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[1]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[2]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[3]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[4]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[5]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[6]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[7]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[8]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[9]\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
begin
prog_empty <= \^prog_empty\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => \gdiff.diff_pntr_pad_reg_n_0_[10]\
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => \gdiff.diff_pntr_pad_reg_n_0_[1]\
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => \gdiff.diff_pntr_pad_reg_n_0_[2]\
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => \gdiff.diff_pntr_pad_reg_n_0_[3]\
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => \gdiff.diff_pntr_pad_reg_n_0_[4]\
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => \gdiff.diff_pntr_pad_reg_n_0_[5]\
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => \gdiff.diff_pntr_pad_reg_n_0_[6]\
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => \gdiff.diff_pntr_pad_reg_n_0_[7]\
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => \gdiff.diff_pntr_pad_reg_n_0_[8]\
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => \gdiff.diff_pntr_pad_reg_n_0_[9]\
);
\gpe1.prog_empty_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \^prog_empty\,
I1 => \out\,
I2 => \gpe1.prog_empty_i_i_2_n_0\,
I3 => \gpe1.prog_empty_i_i_3_n_0\,
O => \gpe1.prog_empty_i_i_1_n_0\
);
\gpe1.prog_empty_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[9]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[10]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[8]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[7]\,
O => \gpe1.prog_empty_i_i_2_n_0\
);
\gpe1.prog_empty_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFEA"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[4]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[1]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[2]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[3]\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[6]\,
I5 => \gdiff.diff_pntr_pad_reg_n_0_[5]\,
O => \gpe1.prog_empty_i_i_3_n_0\
);
\gpe1.prog_empty_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gpe1.prog_empty_i_i_1_n_0\,
PRE => AR(0),
Q => \^prog_empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
\gdiff.diff_pntr_pad_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
\gdiff.diff_pntr_pad_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_0 : out STD_LOGIC;
ram_full_fb_i_reg_1 : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_2 : out STD_LOGIC;
ram_full_fb_i_reg_3 : out STD_LOGIC;
ram_full_fb_i_reg_4 : out STD_LOGIC;
ram_full_fb_i_reg_5 : out STD_LOGIC;
ram_full_fb_i_reg_6 : out STD_LOGIC;
ram_full_fb_i_reg_7 : out STD_LOGIC;
ram_full_fb_i_reg_8 : out STD_LOGIC;
\wr_data_count_i_reg[9]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_data_count_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair12";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(2),
I4 => wr_pntr_plus2(4),
O => \plusOp__1\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => wr_pntr_plus2(2),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(1),
I4 => wr_pntr_plus2(3),
I5 => wr_pntr_plus2(5),
O => \plusOp__1\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
O => \plusOp__1\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => wr_pntr_plus2(7),
O => \plusOp__1\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
I2 => wr_pntr_plus2(7),
I3 => wr_pntr_plus2(8),
O => \plusOp__1\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(8),
I2 => wr_pntr_plus2(7),
I3 => wr_pntr_plus2(6),
I4 => wr_pntr_plus2(9),
O => \plusOp__1\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => wr_pntr_plus2(2),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(1),
I4 => wr_pntr_plus2(3),
I5 => wr_pntr_plus2(5),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(4),
Q => \^q\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(5),
Q => \^q\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(6),
Q => \^q\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(7),
Q => \^q\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(8),
Q => \^q\(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(9),
Q => p_13_out(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(5),
Q => wr_pntr_plus2(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(6),
Q => wr_pntr_plus2(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(7),
Q => wr_pntr_plus2(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(8),
Q => wr_pntr_plus2(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(9),
Q => wr_pntr_plus2(9)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
I2 => \^q\(0),
I3 => RD_PNTR_WR(0),
O => ram_full_fb_i_reg_3
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus2(1),
I3 => RD_PNTR_WR(1),
O => ram_full_fb_i_reg_8
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
I2 => \^q\(2),
I3 => RD_PNTR_WR(2),
O => ram_full_fb_i_reg_2
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => RD_PNTR_WR(3),
I2 => wr_pntr_plus2(2),
I3 => RD_PNTR_WR(2),
O => ram_full_fb_i_reg_7
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
I2 => \^q\(4),
I3 => RD_PNTR_WR(4),
O => ram_full_fb_i_reg_1
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(5),
I1 => RD_PNTR_WR(5),
I2 => wr_pntr_plus2(4),
I3 => RD_PNTR_WR(4),
O => ram_full_fb_i_reg_6
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
I2 => \^q\(6),
I3 => RD_PNTR_WR(6),
O => ram_full_fb_i_reg_0
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(7),
I1 => RD_PNTR_WR(7),
I2 => wr_pntr_plus2(6),
I3 => RD_PNTR_WR(6),
O => ram_full_fb_i_reg_5
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
I2 => \^q\(8),
I3 => RD_PNTR_WR(8),
O => ram_full_fb_i_reg
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(9),
I1 => RD_PNTR_WR(9),
I2 => wr_pntr_plus2(8),
I3 => RD_PNTR_WR(8),
O => ram_full_fb_i_reg_4
);
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[7]\(3)
);
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[7]\(2)
);
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[7]\(1)
);
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[7]\(0)
);
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I1 => RD_PNTR_WR(9),
O => \wr_data_count_i_reg[9]\(1)
);
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => RD_PNTR_WR(8),
O => \wr_data_count_i_reg[9]\(0)
);
minusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I1 => RD_PNTR_WR(3),
O => \wr_data_count_i_reg[3]\(3)
);
minusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => RD_PNTR_WR(2),
O => \wr_data_count_i_reg[3]\(2)
);
minusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => RD_PNTR_WR(1),
O => \wr_data_count_i_reg[3]\(1)
);
minusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => RD_PNTR_WR(0),
O => \wr_data_count_i_reg[3]\(0)
);
\plusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
O => \gdiff.diff_pntr_pad_reg[8]\(3)
);
\plusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => RD_PNTR_WR(6),
O => \gdiff.diff_pntr_pad_reg[8]\(2)
);
\plusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
O => \gdiff.diff_pntr_pad_reg[8]\(1)
);
\plusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => RD_PNTR_WR(4),
O => \gdiff.diff_pntr_pad_reg[8]\(0)
);
\plusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
O => \gdiff.diff_pntr_pad_reg[10]\(1)
);
\plusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => RD_PNTR_WR(8),
O => \gdiff.diff_pntr_pad_reg[10]\(0)
);
plusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
plusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
plusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
plusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
signal \minusOp_carry__0_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_1\ : STD_LOGIC;
signal \minusOp_carry__0_n_2\ : STD_LOGIC;
signal \minusOp_carry__0_n_3\ : STD_LOGIC;
signal \minusOp_carry__0_n_4\ : STD_LOGIC;
signal \minusOp_carry__0_n_5\ : STD_LOGIC;
signal \minusOp_carry__0_n_6\ : STD_LOGIC;
signal \minusOp_carry__0_n_7\ : STD_LOGIC;
signal \minusOp_carry__1_n_3\ : STD_LOGIC;
signal \minusOp_carry__1_n_6\ : STD_LOGIC;
signal \minusOp_carry__1_n_7\ : STD_LOGIC;
signal minusOp_carry_n_0 : STD_LOGIC;
signal minusOp_carry_n_1 : STD_LOGIC;
signal minusOp_carry_n_2 : STD_LOGIC;
signal minusOp_carry_n_3 : STD_LOGIC;
signal minusOp_carry_n_4 : STD_LOGIC;
signal minusOp_carry_n_5 : STD_LOGIC;
signal minusOp_carry_n_6 : STD_LOGIC;
signal minusOp_carry_n_7 : STD_LOGIC;
signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_minusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
minusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => minusOp_carry_n_0,
CO(2) => minusOp_carry_n_1,
CO(1) => minusOp_carry_n_2,
CO(0) => minusOp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3) => minusOp_carry_n_4,
O(2) => minusOp_carry_n_5,
O(1) => minusOp_carry_n_6,
O(0) => minusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\minusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => minusOp_carry_n_0,
CO(3) => \minusOp_carry__0_n_0\,
CO(2) => \minusOp_carry__0_n_1\,
CO(1) => \minusOp_carry__0_n_2\,
CO(0) => \minusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \minusOp_carry__0_n_4\,
O(2) => \minusOp_carry__0_n_5\,
O(1) => \minusOp_carry__0_n_6\,
O(0) => \minusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(3 downto 0)
);
\minusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \minusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \minusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_minusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \minusOp_carry__1_n_6\,
O(0) => \minusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d2_reg[9]\(1 downto 0)
);
\wr_data_count_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_7,
Q => wr_data_count(0)
);
\wr_data_count_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_6,
Q => wr_data_count(1)
);
\wr_data_count_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_5,
Q => wr_data_count(2)
);
\wr_data_count_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_4,
Q => wr_data_count(3)
);
\wr_data_count_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_7\,
Q => wr_data_count(4)
);
\wr_data_count_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_6\,
Q => wr_data_count(5)
);
\wr_data_count_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_5\,
Q => wr_data_count(6)
);
\wr_data_count_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_4\,
Q => wr_data_count(7)
);
\wr_data_count_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_7\,
Q => wr_data_count(8)
);
\wr_data_count_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_6\,
Q => wr_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_2_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_3_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_1\ : STD_LOGIC;
signal \plusOp_carry__0_n_2\ : STD_LOGIC;
signal \plusOp_carry__0_n_3\ : STD_LOGIC;
signal \plusOp_carry__0_n_4\ : STD_LOGIC;
signal \plusOp_carry__0_n_5\ : STD_LOGIC;
signal \plusOp_carry__0_n_6\ : STD_LOGIC;
signal \plusOp_carry__0_n_7\ : STD_LOGIC;
signal \plusOp_carry__1_n_3\ : STD_LOGIC;
signal \plusOp_carry__1_n_6\ : STD_LOGIC;
signal \plusOp_carry__1_n_7\ : STD_LOGIC;
signal plusOp_carry_n_0 : STD_LOGIC;
signal plusOp_carry_n_1 : STD_LOGIC;
signal plusOp_carry_n_2 : STD_LOGIC;
signal plusOp_carry_n_3 : STD_LOGIC;
signal plusOp_carry_n_4 : STD_LOGIC;
signal plusOp_carry_n_5 : STD_LOGIC;
signal plusOp_carry_n_6 : STD_LOGIC;
signal plusOp_carry_n_7 : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal \NLW_plusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_6\,
Q => diff_pntr(9)
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_7,
Q => diff_pntr(0)
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_6,
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_5,
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_4,
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_7\,
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_6\,
Q => diff_pntr(5)
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_5\,
Q => diff_pntr(6)
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_4\,
Q => diff_pntr(7)
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_7\,
Q => diff_pntr(8)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8F888088"
)
port map (
I0 => \gpf1.prog_full_i_i_2_n_0\,
I1 => \gpf1.prog_full_i_i_3_n_0\,
I2 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I3 => ram_full_fb_i_reg,
I4 => \^prog_full\,
O => \gpf1.prog_full_i_i_1_n_0\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80808000"
)
port map (
I0 => diff_pntr(2),
I1 => diff_pntr(3),
I2 => diff_pntr(4),
I3 => diff_pntr(1),
I4 => diff_pntr(0),
O => \gpf1.prog_full_i_i_2_n_0\
);
\gpf1.prog_full_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => diff_pntr(7),
I1 => diff_pntr(8),
I2 => diff_pntr(5),
I3 => diff_pntr(6),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => diff_pntr(9),
O => \gpf1.prog_full_i_i_3_n_0\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gpf1.prog_full_i_i_1_n_0\,
PRE => \out\,
Q => \^prog_full\
);
plusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => plusOp_carry_n_0,
CO(2) => plusOp_carry_n_1,
CO(1) => plusOp_carry_n_2,
CO(0) => plusOp_carry_n_3,
CYINIT => E(0),
DI(3 downto 0) => Q(3 downto 0),
O(3) => plusOp_carry_n_4,
O(2) => plusOp_carry_n_5,
O(1) => plusOp_carry_n_6,
O(0) => plusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\plusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => plusOp_carry_n_0,
CO(3) => \plusOp_carry__0_n_0\,
CO(2) => \plusOp_carry__0_n_1\,
CO(1) => \plusOp_carry__0_n_2\,
CO(0) => \plusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \plusOp_carry__0_n_4\,
O(2) => \plusOp_carry__0_n_5\,
O(1) => \plusOp_carry__0_n_6\,
O(0) => \plusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d1_reg[7]\(3 downto 0)
);
\plusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_plusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_carry__1_n_6\,
O(0) => \plusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d1_reg[9]\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\rd_dc_i_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : in STD_LOGIC;
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gdiff.diff_pntr_pad[10]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[10]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_6_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out_0 : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \rd_dc_i[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[9]_i_1_n_3\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
\gdiff.diff_pntr_pad[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \gdiff.diff_pntr_pad[10]_i_2_n_0\
);
\gdiff.diff_pntr_pad[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \gdiff.diff_pntr_pad[4]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \gdiff.diff_pntr_pad[4]_i_4_n_0\
);
\gdiff.diff_pntr_pad[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \gdiff.diff_pntr_pad[4]_i_5_n_0\
);
\gdiff.diff_pntr_pad[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \gdiff.diff_pntr_pad[8]_i_2_n_0\
);
\gdiff.diff_pntr_pad[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \gdiff.diff_pntr_pad[8]_i_3_n_0\
);
\gdiff.diff_pntr_pad[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \gdiff.diff_pntr_pad[8]_i_4_n_0\
);
\gdiff.diff_pntr_pad[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gdiff.diff_pntr_pad_reg[10]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => D(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \gdiff.diff_pntr_pad[10]_i_2_n_0\,
S(0) => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\,
CYINIT => p_0_out,
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => D(3 downto 0),
S(3) => \gdiff.diff_pntr_pad[4]_i_3_n_0\,
S(2) => \gdiff.diff_pntr_pad[4]_i_4_n_0\,
S(1) => \gdiff.diff_pntr_pad[4]_i_5_n_0\,
S(0) => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(3) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => D(7 downto 4),
S(3) => \gdiff.diff_pntr_pad[8]_i_2_n_0\,
S(2) => \gdiff.diff_pntr_pad[8]_i_3_n_0\,
S(1) => \gdiff.diff_pntr_pad[8]_i_4_n_0\,
S(0) => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
I2 => p_22_out(1),
I3 => Q(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc0.count_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
I2 => p_22_out(3),
I3 => Q(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
I2 => p_22_out(5),
I3 => Q(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc0.count_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
I2 => p_22_out(7),
I3 => Q(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc0.count_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
I2 => p_22_out(9),
I3 => Q(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc0.count_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg_0(4)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out_0,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[8]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(9),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => RD_PNTR_WR(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => RD_PNTR_WR(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => RD_PNTR_WR(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => RD_PNTR_WR(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => RD_PNTR_WR(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => RD_PNTR_WR(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => RD_PNTR_WR(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => RD_PNTR_WR(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => RD_PNTR_WR(8)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(9),
Q => RD_PNTR_WR(9)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out_0,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => p_22_out(9)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
\rd_dc_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \rd_dc_i[3]_i_2_n_0\
);
\rd_dc_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \rd_dc_i[3]_i_3_n_0\
);
\rd_dc_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \rd_dc_i[3]_i_4_n_0\
);
\rd_dc_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \rd_dc_i[7]_i_2_n_0\
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \rd_dc_i[7]_i_3_n_0\
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \rd_dc_i[7]_i_4_n_0\
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \rd_dc_i[9]_i_2_n_0\
);
\rd_dc_i[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \rd_dc_i[9]_i_3_n_0\
);
\rd_dc_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[3]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[3]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[3]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => \rd_dc_i_reg[9]\(3 downto 0),
S(3) => \rd_dc_i[3]_i_2_n_0\,
S(2) => \rd_dc_i[3]_i_3_n_0\,
S(1) => \rd_dc_i[3]_i_4_n_0\,
S(0) => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[3]_i_1_n_0\,
CO(3) => \rd_dc_i_reg[7]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => \rd_dc_i_reg[9]\(7 downto 4),
S(3) => \rd_dc_i[7]_i_2_n_0\,
S(2) => \rd_dc_i[7]_i_3_n_0\,
S(1) => \rd_dc_i[7]_i_4_n_0\,
S(0) => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i_reg[9]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \rd_dc_i_reg[9]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \rd_dc_i_reg[9]\(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \rd_dc_i[9]_i_2_n_0\,
S(0) => \rd_dc_i[9]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\out\ => ram_empty_fb_i,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => p_0_out
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
WR_RST_BUSY : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
WR_RST_BUSY <= rst_d3;
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
port (
full : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d1_reg[1]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC;
\gic0.gc0.count_reg[0]\ : in STD_LOGIC;
\gic0.gc0.count_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_reg[9]\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
signal c1_n_0 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp2 => comp2,
\gic0.gc0.count_d1_reg[1]\ => \gic0.gc0.count_d1_reg[1]\,
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gic0.gc0.count_d1_reg[5]\ => \gic0.gc0.count_d1_reg[5]\,
\gic0.gc0.count_d1_reg[7]\ => \gic0.gc0.count_d1_reg[7]\,
\gic0.gc0.count_d1_reg[9]\ => \gic0.gc0.count_d1_reg[9]\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => ram_full_fb_i,
ram_full_fb_i_reg => c1_n_0,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp2 => comp2,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\gic0.gc0.count_reg[3]\ => \gic0.gc0.count_reg[3]\,
\gic0.gc0.count_reg[5]\ => \gic0.gc0.count_reg[5]\,
\gic0.gc0.count_reg[7]\ => \gic0.gc0.count_reg[7]\,
\gic0.gc0.count_reg[9]\ => \gic0.gc0.count_reg[9]\
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c1_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c1_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
prog_empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \gras.rsts_n_2\ : STD_LOGIC;
signal \^out\ : STD_LOGIC;
begin
\out\ <= \^out\;
\gras.gpe.rdpe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
port map (
AR(0) => AR(0),
D(9 downto 0) => D(9 downto 0),
\out\ => \^out\,
prog_empty => prog_empty,
rd_clk => rd_clk
);
\gras.grdc1.rdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
port map (
AR(0) => AR(0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0),
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0)
);
\gras.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_2\,
empty => empty,
\out\ => \^out\,
p_0_out => p_0_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \gras.rsts_n_2\,
Q(9 downto 0) => Q(9 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_11 : STD_LOGIC;
signal wpntr_n_12 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_14 : STD_LOGIC;
signal wpntr_n_15 : STD_LOGIC;
signal wpntr_n_16 : STD_LOGIC;
signal wpntr_n_17 : STD_LOGIC;
signal wpntr_n_18 : STD_LOGIC;
signal wpntr_n_19 : STD_LOGIC;
signal wpntr_n_20 : STD_LOGIC;
signal wpntr_n_21 : STD_LOGIC;
signal wpntr_n_22 : STD_LOGIC;
signal wpntr_n_23 : STD_LOGIC;
signal wpntr_n_24 : STD_LOGIC;
signal wpntr_n_25 : STD_LOGIC;
signal wpntr_n_26 : STD_LOGIC;
signal wpntr_n_27 : STD_LOGIC;
signal wpntr_n_28 : STD_LOGIC;
signal wpntr_n_29 : STD_LOGIC;
signal wpntr_n_30 : STD_LOGIC;
signal wpntr_n_41 : STD_LOGIC;
signal wpntr_n_42 : STD_LOGIC;
signal wpntr_n_43 : STD_LOGIC;
signal wpntr_n_44 : STD_LOGIC;
signal wpntr_n_45 : STD_LOGIC;
signal wpntr_n_46 : STD_LOGIC;
signal wpntr_n_47 : STD_LOGIC;
signal wpntr_n_48 : STD_LOGIC;
begin
E(0) <= \^e\(0);
Q(9 downto 0) <= \^q\(9 downto 0);
\gwas.gpf.wrpf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(8 downto 0) => p_13_out(8 downto 0),
S(3) => wpntr_n_18,
S(2) => wpntr_n_19,
S(1) => wpntr_n_20,
S(0) => wpntr_n_21,
\gic0.gc0.count_d1_reg[7]\(3) => wpntr_n_12,
\gic0.gc0.count_d1_reg[7]\(2) => wpntr_n_13,
\gic0.gc0.count_d1_reg[7]\(1) => wpntr_n_14,
\gic0.gc0.count_d1_reg[7]\(0) => wpntr_n_15,
\gic0.gc0.count_d1_reg[9]\(1) => wpntr_n_0,
\gic0.gc0.count_d1_reg[9]\(0) => wpntr_n_1,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \out\,
prog_full => prog_full,
ram_full_fb_i_reg => \gwas.wsts_n_1\,
wr_clk => wr_clk
);
\gwas.gwdc0.wdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
port map (
AR(0) => AR(0),
Q(8 downto 0) => \^q\(8 downto 0),
S(3) => wpntr_n_45,
S(2) => wpntr_n_46,
S(1) => wpntr_n_47,
S(0) => wpntr_n_48,
\gic0.gc0.count_d2_reg[7]\(3) => wpntr_n_41,
\gic0.gc0.count_d2_reg[7]\(2) => wpntr_n_42,
\gic0.gc0.count_d2_reg[7]\(1) => wpntr_n_43,
\gic0.gc0.count_d2_reg[7]\(0) => wpntr_n_44,
\gic0.gc0.count_d2_reg[9]\(1) => wpntr_n_29,
\gic0.gc0.count_d2_reg[9]\(0) => wpntr_n_30,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0)
);
\gwas.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
\gic0.gc0.count_d1_reg[1]\ => wpntr_n_23,
\gic0.gc0.count_d1_reg[3]\ => wpntr_n_22,
\gic0.gc0.count_d1_reg[5]\ => wpntr_n_17,
\gic0.gc0.count_d1_reg[7]\ => wpntr_n_16,
\gic0.gc0.count_d1_reg[9]\ => wpntr_n_11,
\gic0.gc0.count_reg[0]\ => wpntr_n_28,
\gic0.gc0.count_reg[3]\ => wpntr_n_27,
\gic0.gc0.count_reg[5]\ => wpntr_n_26,
\gic0.gc0.count_reg[7]\ => wpntr_n_25,
\gic0.gc0.count_reg[9]\ => wpntr_n_24,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \gwas.wsts_n_1\,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \^q\(9 downto 0),
E(0) => \^e\(0),
Q(8 downto 0) => p_13_out(8 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
S(3) => wpntr_n_18,
S(2) => wpntr_n_19,
S(1) => wpntr_n_20,
S(0) => wpntr_n_21,
\gdiff.diff_pntr_pad_reg[10]\(1) => wpntr_n_0,
\gdiff.diff_pntr_pad_reg[10]\(0) => wpntr_n_1,
\gdiff.diff_pntr_pad_reg[8]\(3) => wpntr_n_12,
\gdiff.diff_pntr_pad_reg[8]\(2) => wpntr_n_13,
\gdiff.diff_pntr_pad_reg[8]\(1) => wpntr_n_14,
\gdiff.diff_pntr_pad_reg[8]\(0) => wpntr_n_15,
ram_full_fb_i_reg => wpntr_n_11,
ram_full_fb_i_reg_0 => wpntr_n_16,
ram_full_fb_i_reg_1 => wpntr_n_17,
ram_full_fb_i_reg_2 => wpntr_n_22,
ram_full_fb_i_reg_3 => wpntr_n_23,
ram_full_fb_i_reg_4 => wpntr_n_24,
ram_full_fb_i_reg_5 => wpntr_n_25,
ram_full_fb_i_reg_6 => wpntr_n_26,
ram_full_fb_i_reg_7 => wpntr_n_27,
ram_full_fb_i_reg_8 => wpntr_n_28,
wr_clk => wr_clk,
\wr_data_count_i_reg[3]\(3) => wpntr_n_45,
\wr_data_count_i_reg[3]\(2) => wpntr_n_46,
\wr_data_count_i_reg[3]\(1) => wpntr_n_47,
\wr_data_count_i_reg[3]\(0) => wpntr_n_48,
\wr_data_count_i_reg[7]\(3) => wpntr_n_41,
\wr_data_count_i_reg[7]\(2) => wpntr_n_42,
\wr_data_count_i_reg[7]\(1) => wpntr_n_43,
\wr_data_count_i_reg[7]\(0) => wpntr_n_44,
\wr_data_count_i_reg[9]\(1) => wpntr_n_29,
\wr_data_count_i_reg[9]\(0) => wpntr_n_30
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \^wr_rst_busy\ : STD_LOGIC;
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 1 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
WR_RST_BUSY <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(9 downto 0) => plusOp(10 downto 1),
Q(9 downto 0) => p_0_out_0(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
p_0_out => p_0_out,
rd_clk => rd_clk,
\rd_dc_i_reg[9]\(9 downto 0) => minusOp(9 downto 0),
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(9 downto 0) => plusOp(10 downto 1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out_0(9 downto 0),
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
empty => empty,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => minusOp(9 downto 0),
\out\ => p_2_out,
p_0_out => p_0_out,
prog_empty => prog_empty,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(9 downto 0) => p_12_out(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
full => full,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \^wr_rst_busy\,
\out\ => rst_full_ff_i,
prog_full => prog_full,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
E(0) => p_18_out,
Q(9 downto 0) => p_12_out(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out_0(9 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
WR_RST_BUSY => \^wr_rst_busy\,
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
WR_RST_BUSY => WR_RST_BUSY,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
WR_RST_BUSY => WR_RST_BUSY,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
WR_RST_BUSY => wr_rst_busy,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_0,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => prog_empty,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => prog_full,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
f43d2acdb631226dd5b04d533264c75d
| 0.615874 | 2.920821 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd
| 1 | 5,317 |
-- $Id: sys_tst_snhumanio_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n2 - syn
-- Description: snhumanio tester design for nexys2
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_snhumanio_n2;
architecture syn of sys_tst_snhumanio_n2 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
gpl-2.0
|
02ccfa59e7b84a69c59d0c6a7c2248cc
| 0.493699 | 3.425902 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd
| 1 | 4,146 |
-- $Id: tb_tst_serloop_s3.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop_s3 - sim
-- Description: Test bench for sys_tst_serloop_s3
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop_s3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop_s3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop_s3 is
end tb_tst_serloop_s3;
architecture sim of tb_tst_serloop_s3 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKS : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop_s3
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKS,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
dcb44a0246caa3d0be5f46651343a729
| 0.529908 | 3.150456 | false | false | false | false |
superboy0712/MIPS
|
MIPS_ALU.vhd
| 1 | 1,327 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity alu is
port (
alu_ctrl : in std_logic_vector(3 downto 0);
alu_src1, alu_src2 : in std_logic_vector(31 downto 0);
alu_zero : out std_logic;
alu_result : out std_logic_vector(31 downto 0);
alu_carry : out std_logic
);
end alu;
architecture behavioral of alu is
begin
process(alu_src1, alu_src2, alu_ctrl)
variable src1, src2, result : signed(31 downto 0 );
variable zero : std_logic;
begin
--
src1 := signed(alu_src1);
src2 := signed(alu_src2);
result := (others => '0');
zero := '0';
--
case alu_ctrl is
--AND
when "0000" =>
result := src1 and src2;
--OR
when "0001" =>
result := src1 or src2;
--ADD
when "0010" =>
result := src1 + src2;
--SUB
when "0110" =>
result := src1 - src2;
--SLT
when "0111" =>
if src1 < src2 then result(0) := '1';
else result(0) := '0';
end if;
--NOR
when "1100" =>
result := src1 nor src2;
--error
when others =>
result := (others => '0');
end case;
if to_integer(result) = 0 then zero := '1';
else zero := '0';
end if;
alu_result <= std_logic_vector(result);
alu_zero <= zero;
end process;
end behavioral;
|
mit
|
1fe92ff1b5c5ce61a5b037b94a2eaf24
| 0.547099 | 2.781971 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
libraries/fixed_pkg_c.vhdl
| 1 | 302,708 |
-- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007/09/26 18:08:53 $
-- Version : $Revision: 2.0 $
-- Date : $Date: 2011/01/26 15:55:27 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--=====
-- Arithmetic Operators:
--=====
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--=====
-- Comparison Operators
--=====
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--=====
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--=====
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--=====
-- RESIZE Functions
--=====
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--=====
-- Conversion Functions
--=====
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--=====
-- Translation Functions
--=====
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--=====
-- string and textio Functions
--=====
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007/09/26 18:08:53 $
-- Version : $Revision: 2.0 $
-- Date : $Date: 2011/01/26 15:55:27 $
--
-- Created for VHDL-200X-ft, David Bishop ([email protected])
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
result := 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
c_out := result_slv(left_index-right_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
c_out := result_slv(left_index-right_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
|
gpl-3.0
|
96530f7716f3885169bb6962ed32865c
| 0.569988 | 3.963184 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/vector_dff.vhd
| 1 | 578 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vector_dff_block is
Generic (
WIDTH : positive := 8
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
end vector_dff_block;
architecture Behavioral of vector_dff_block is
begin
process (RST, CLK)
begin
if RST = '1' then
Q <= (others => '0');
elsif (CLK'event AND CLK = '1') then
Q <= D;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9ae10b369e1e97676b911a8660f136cf
| 0.586505 | 3.284091 | false | false | false | false |
Vadman97/ImageAES
|
des/DES/ipcore_dir/constants_mem/example_design/constants_mem_exdes.vhd
| 1 | 4,511 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: constants_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY constants_mem_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END constants_mem_exdes;
ARCHITECTURE xilinx OF constants_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT constants_mem IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : constants_mem
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
e5fbafcc2ea3510e7490455a9150c183
| 0.557748 | 4.626667 | false | false | false | false |
freecores/w11
|
rtl/vlib/comlib/misc/gen_crc8_tbl.vhd
| 2 | 1,986 |
-- $Id: gen_crc8_tbl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to print crc8 transition table
--
-- Dependencies: comlib/crc8_update (function)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.slvtypes.all;
use work.comlib.all;
entity gen_crc8_tbl is
end gen_crc8_tbl;
architecture sim of gen_crc8_tbl is
begin
process
variable crc : slv8 := (others=>'0');
variable dat : slv8 := (others=>'0');
variable nxt : slv8 := (others=>'0');
variable oline : line;
begin
for i in 0 to 255 loop
crc := (others=>'0');
dat := slv(to_unsigned(i,8));
nxt := crc8_update(crc, dat);
write(oline, to_integer(unsigned(nxt)), right, 4);
if i /= 255 then
write(oline, string'(","));
end if;
if (i mod 8) = 7 then
writeline(output, oline);
end if;
end loop; -- i
wait;
end process;
end sim;
|
gpl-2.0
|
2d5e0644b1e7053704ab30ae71495fad
| 0.604733 | 3.650735 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd
| 1 | 2,580 |
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-2.0
|
63a4cceba1124134de0f361bc2ec06ff
| 0.655039 | 3.73913 | false | false | false | false |
quicky2000/top_test_image_controler_640_480_1b
|
top_test_image_controler_640_480_1b.vhd
| 1 | 4,146 |
--
-- This file is part of top_test_image_controler_640_480_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_test_image_controler_640_480_1b is
Port ( clk : in STD_LOGIC;
w1a : inout STD_LOGIC_VECTOR (15 downto 0);
w1b : inout STD_LOGIC_VECTOR (15 downto 0);
w2c : inout STD_LOGIC_VECTOR (15 downto 0);
rx : in STD_LOGIC;
tx : inout STD_LOGIC);
end top_test_image_controler_640_480_1b;
architecture Behavioral of top_test_image_controler_640_480_1b is
COMPONENT clock_25mhz
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
signal clk_25mhz : std_logic;
signal reset : std_logic;
signal vsync : std_logic;
signal hsync : std_logic;
signal enable : std_logic;
signal screen_right_left : std_logic;
signal screen_up_down : std_logic;
signal r : std_logic_vector ( 5 downto 0);
signal g : std_logic_vector ( 5 downto 0);
signal b : std_logic_vector ( 5 downto 0);
signal audio_right : std_logic;
signal audio_left : std_logic;
signal x_out : std_logic_vector( 9 downto 0);
signal y_out : std_logic_vector( 8 downto 0);
signal vsync_ok : std_logic;
signal hsync_ok : std_logic;
signal enable_ok : std_logic;
-- Signals to write in screen memory
signal addr : std_logic_vector(18 downto 0) := (others => '0');
signal data_in : std_logic;
signal write_enable : std_logic;
begin
Inst_clock_25mhz: clock_25mhz PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => clk_25mhz,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
Inst_giovanni_card : entity work.giovanni_card PORT MAP(
w1a => w1a,
w1b => w1b,
scr_red => r,
scr_green => g,
scr_blue => b,
scr_clk => clk_25mhz,
scr_hsync => hsync_ok,
scr_vsync => vsync_ok,
scr_enable => enable_ok,
scr_right_left => screen_right_left,
scr_up_down => screen_up_down,
audio_right => audio_right,
audio_left => audio_left,
audio_stereo_ok => open,
audio_plugged => open,
io => open
);
Inst_driver_sharp : entity work.driver_sharp PORT MAP(
clk => clk_25mhz,
rst => reset,
vsync => vsync,
hsync => hsync,
enable => enable,
x_out => x_out,
y_out => y_out
);
inst_image_controler : entity work.image_controler PORT MAP(
clk => clk_25mhz,
rst => reset,
r => r,
g => g,
b => b,
x => x_out,
y => y_out,
hsync_in => hsync,
vsync_in => vsync,
enable_in => enable,
write_enable => write_enable,
write_addr => addr,
data_in => data_in,
hsync_out => hsync_ok,
vsync_out => vsync_ok,
enable_out => enable_ok
);
inst_image_generator : entity work.image_generator
port map (
clk => clk_25mhz,
rst => reset,
write_enable => write_enable,
data => data_in,
addr => addr);
reset <= '0';
screen_right_left <= '1';
screen_up_down <= '1';
audio_right <= '0';
audio_left <= '0';
end Behavioral;
|
gpl-3.0
|
d3d5f8eba09eed0a454f27c7b45cf833
| 0.62904 | 3.370732 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/7328ecd7be110fa2/fifo_generator_rx_inst_sim_netlist.vhdl
| 1 | 199,238 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 09:34:25 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => Q(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => din(31 downto 0),
DIBDI(31 downto 0) => din(63 downto 32),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => dout(31 downto 0),
DOBDO(31 downto 0) => dout(63 downto 32),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => \out\(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => WEBWE(0),
WEBWE(6) => WEBWE(0),
WEBWE(5) => WEBWE(0),
WEBWE(4) => WEBWE(0),
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_comb : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0055000000FFC0C0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => wr_rst_busy,
I4 => \out\,
I5 => ram_empty_fb_i_reg(0),
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
\gc0.count_d1_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \^gc0.count_d1_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair1";
begin
Q(8 downto 0) <= \^q\(8 downto 0);
\gc0.count_d1_reg[7]_0\(7 downto 0) <= \^gc0.count_d1_reg[7]_0\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(0),
I1 => \^gc0.count_d1_reg[7]_0\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(0),
I1 => \^gc0.count_d1_reg[7]_0\(1),
I2 => \^gc0.count_d1_reg[7]_0\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(1),
I1 => \^gc0.count_d1_reg[7]_0\(0),
I2 => \^gc0.count_d1_reg[7]_0\(2),
I3 => \^gc0.count_d1_reg[7]_0\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(2),
I1 => \^gc0.count_d1_reg[7]_0\(0),
I2 => \^gc0.count_d1_reg[7]_0\(1),
I3 => \^gc0.count_d1_reg[7]_0\(3),
I4 => \^gc0.count_d1_reg[7]_0\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(3),
I1 => \^gc0.count_d1_reg[7]_0\(1),
I2 => \^gc0.count_d1_reg[7]_0\(0),
I3 => \^gc0.count_d1_reg[7]_0\(2),
I4 => \^gc0.count_d1_reg[7]_0\(4),
I5 => \^gc0.count_d1_reg[7]_0\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[8]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[7]_0\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[8]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[7]_0\(6),
I2 => \^gc0.count_d1_reg[7]_0\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(6),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^gc0.count_d1_reg[7]_0\(7),
I3 => rd_pntr_plus1(8),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^gc0.count_d1_reg[7]_0\(5),
I1 => \^gc0.count_d1_reg[7]_0\(3),
I2 => \^gc0.count_d1_reg[7]_0\(1),
I3 => \^gc0.count_d1_reg[7]_0\(0),
I4 => \^gc0.count_d1_reg[7]_0\(2),
I5 => \^gc0.count_d1_reg[7]_0\(4),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(0),
Q => \^q\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(1),
Q => \^q\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(2),
Q => \^q\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(3),
Q => \^q\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(4),
Q => \^q\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(5),
Q => \^q\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(6),
Q => \^q\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[7]_0\(7),
Q => \^q\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(8),
Q => \^q\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^gc0.count_d1_reg[7]_0\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^gc0.count_d1_reg[7]_0\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^gc0.count_d1_reg[7]_0\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^gc0.count_d1_reg[7]_0\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => \^gc0.count_d1_reg[7]_0\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(5),
Q => \^gc0.count_d1_reg[7]_0\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(6),
Q => \^gc0.count_d1_reg[7]_0\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(7),
Q => \^gc0.count_d1_reg[7]_0\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_full_i_reg
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_empty_i_reg
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gcc0.gc0.count_reg[8]\(0),
O => ram_full_i_reg_0
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_empty_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8 downto 0);
Q(0) <= \^q\(0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[8]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[8]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => p_12_out(7),
I3 => \^q\(0),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => p_12_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(0)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gc0.count_d1_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gc0.count_d1_reg[7]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gc0.count_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gc0.count_reg[7]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[7]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[7]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gc0.count_d1_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gc0.count_d1_reg[7]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gc0.count_d1_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gc0.count_d1_reg[7]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gc0.count_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gc0.count_reg[7]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[7]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[7]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gc0.count_d1_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gc0.count_d1_reg[7]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gc0.count_d1_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gc0.count_d1_reg[7]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gc0.count_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gc0.count_reg[7]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[7]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[7]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gc0.count_d1_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gc0.count_d1_reg[7]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gc0.count_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gc0.count_reg[7]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gc0.count_d1_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gc0.count_d1_reg[7]\(7),
O => ram_empty_i_reg_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
\gc0.count_reg[8]\ => \gc0.count_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_comb : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0),
ram_full_comb => ram_full_comb,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]_0\,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i_reg_0 : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal rpntr_n_10 : STD_LOGIC;
signal rpntr_n_12 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[8]\ => rpntr_n_12,
\gc0.count_reg[8]\ => rpntr_n_10,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(8 downto 0) => Q(8 downto 0),
clk => clk,
\gc0.count_d1_reg[7]_0\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gcc0.gc0.count_d1_reg[8]\(0) => \gcc0.gc0.count_d1_reg[8]\(0),
\gcc0.gc0.count_reg[8]\(0) => \gcc0.gc0.count_reg[8]\(0),
ram_empty_i_reg => rpntr_n_10,
ram_empty_i_reg_0 => rpntr_n_12,
ram_full_i_reg => ram_full_i_reg,
ram_full_i_reg_0 => ram_full_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gc0.count_d1_reg[8]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
WEBWE(0) <= \^webwe\(0);
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^webwe\(0),
clk => clk,
full => full,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
\gc0.count_d1_reg[8]_0\ => \gc0.count_d1_reg[8]_0\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\,
\out\ => \out\,
ram_empty_fb_i_reg(0) => E(0),
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0),
v1_reg_0(3 downto 0) => \c1/v1_reg\(3 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \^webwe\(0),
Q(0) => Q(0),
clk => clk,
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gc0.count_reg[7]\(7 downto 0) => \gc0.count_reg[7]\(7 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0),
v1_reg_1(3 downto 0) => \c1/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(8 downto 0) => Q(8 downto 0),
WEBWE(0) => WEBWE(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
\out\(0) => \out\(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_17\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(8 downto 0) => p_0_out(8 downto 0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_17\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[8]\(0) => p_11_out(8),
\gcc0.gc0.count_reg[8]\(0) => p_12_out(8),
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_full_i_reg => \gntv_or_sync_fifo.gl0.rd_n_3\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.rd_n_21\,
rd_en => rd_en,
v1_reg(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_11_out(8 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(0) => p_12_out(8),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0),
\gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.rd_n_3\,
\gc0.count_d1_reg[8]_0\ => \gntv_or_sync_fifo.gl0.rd_n_21\,
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_17\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_20\,
v1_reg(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(8 downto 0) => p_0_out(8 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => p_11_out(8 downto 0),
\out\(0) => rd_rst_i(0),
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 510;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 509;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 510;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 509;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8 downto 0) => B"000000000",
prog_empty_thresh_assert(8 downto 0) => B"000000000",
prog_empty_thresh_negate(8 downto 0) => B"000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8 downto 0) => B"000000000",
prog_full_thresh_assert(8 downto 0) => B"000000000",
prog_full_thresh_negate(8 downto 0) => B"000000000",
rd_clk => '0',
rd_data_count(8 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(8 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(8 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(8 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
9297b0f1adb4bd84934f58a09ecd39d8
| 0.646383 | 2.907396 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd
| 2 | 7,536 |
-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_snhumanio - syn
-- Description: simple stand-alone tester for sn_humanio
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-15 416 1.0.2 fix sensitivity list of proc_next
-- 2011-10-08 412 1.0.1 use better rndm init (so that swi=0 is non-const)
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
-- ----------------------------------------------------------------------------
entity tst_snhumanio is -- tester for rlink
generic (
BWIDTH : positive := 4); -- BTN port width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
SWI : in slv8; -- switch settings
BTN : in slv(BWIDTH-1 downto 0); -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_snhumanio;
architecture syn of tst_snhumanio is
constant c_mode_rndm : slv2 := "00";
constant c_mode_cnt : slv2 := "01";
constant c_mode_swi : slv2 := "10";
constant c_mode_btst : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
allon : slbit; -- all LEDs on if set
cnt : slv16; -- counter
tcnt : slv16; -- swi/btn toggle counter
rndm : slv8; -- random number
swi_1 : slv8; -- last SWI state
btn_1 : slv(BWIDTH-1 downto 0); -- last BTN state
led : slv8; -- LED output state
dsp : slv16; -- display data
dp : slv4; -- display decimal points
end record regs_type;
-- the rndm start value is /= 0 because a seed of 0 with a SWI setting of 0
-- will result in a 0-0-0 sequence. The 01010101 start will get trapped in a
-- constant sequence with a 01100011 switch setting, which is rather unlikely.
constant rndminit : slv8 := "01010101";
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
c_mode_rndm, -- mode
'0', -- allon
(others=>'0'), -- cnt
(others=>'0'), -- tcnt
rndminit, -- rndm
(others=>'0'), -- swi_1
btnzero, -- btn_1
(others=>'0'), -- led
(others=>'0'), -- dsp
(others=>'0') -- dp
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN4 : slbit := '0';
begin
assert BWIDTH>=4
report "assert(BWIDTH>=4): at least 4 BTNs available"
severity failure;
B4YES: if BWIDTH > 4 generate
BTN4 <= BTN(4);
end generate B4YES;
B4NO: if BWIDTH = 4 generate
BTN4 <= '0';
end generate B4NO;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, SWI, BTN, BTN4)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable btn03 : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
n.swi_1 := SWI;
n.btn_1 := BTN;
if SWI/=r.swi_1 or BTN/=r.btn_1 then
n.tcnt := slv(unsigned(r.tcnt) + 1);
end if;
btn03 := BTN(3 downto 0);
n.allon := BTN4;
if unsigned(BTN) /= 0 then -- is a button being pressed ?
if r.mode /= c_mode_btst then -- not in btst mode
case btn03 is
when "0001" => -- 0001 single button -> rndm mode
n.mode := c_mode_rndm;
n.rndm := rndminit;
when "0010" => -- 0010 single button -> cnt mode
n.mode := c_mode_cnt;
when "0100" => -- 0100 single button -> swi mode
n.mode := c_mode_swi;
when "1000" => -- 1001 single button -> btst mode
n.mode := c_mode_btst;
n.tcnt := (others=>'0');
when others => -- any 2+ button combo -> led test
n.allon := '1';
end case;
else -- button press in btst mode
case btn03 is
when "1001" => -- 1001 double btn -> rndm mode
n.mode := c_mode_rndm;
when "1010" => -- 1010 double btn -> rndm cnt
n.mode := c_mode_cnt;
when "1100" => -- 1100 double btn -> rndm swi
n.mode := c_mode_swi;
when others => null;
end case;
end if;
else -- no button being pressed
if CE_MSEC = '1' then -- on every usec
n.cnt := slv(unsigned(r.cnt) + 1); -- inc counter
if unsigned(r.cnt(8 downto 0)) = 0 then -- every 1/2 sec (approx.)
n.rndm := crc8_update(r.rndm, SWI); -- update rndm state
end if;
end if;
end if;
if r.allon = '1' then -- if led test selected
n.led := (others=>'1'); -- all led,dsp,dp on
n.dsp := (others=>'1');
n.dp := (others=>'1');
else -- no led test, normal output
case r.mode is
when c_mode_rndm =>
n.led := r.rndm;
n.dsp(7 downto 0) := r.rndm;
n.dsp(15 downto 8) := not r.rndm;
when c_mode_cnt =>
n.led := r.cnt(14 downto 7);
n.dsp := r.cnt;
when c_mode_swi =>
n.led := SWI;
n.dsp(7 downto 0) := SWI;
n.dsp(15 downto 8) := not SWI;
when c_mode_btst =>
n.led := SWI;
n.dsp := r.tcnt;
when others => null;
end case;
n.dp := BTN(3 downto 0);
end if;
N_REGS <= n;
LED <= r.led;
DSP_DAT <= r.dsp;
DSP_DP <= r.dp;
end process proc_next;
end syn;
|
gpl-2.0
|
9877e062fbaab291dcbf9691eb7249ca
| 0.468949 | 3.966316 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
| 1 | 20,124 |
-- $Id: sys_w11a_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n3 - syn
-- Description: w11a test design for nexys3
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2rlink/rlink_sp1c_fx2
-- bplib/fx2rlink/ioleds_sp1c_fx2
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_bram
-- vlib/nxcramlib/nx_cram_dummy
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- bplib/nxcramlib/nx_cram_memctl_as
-- ibus/ib_sres_or_2
-- ibus/ibdr_minisys
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_sys_w11a_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.4 added fx2 (cuff) support
-- 2011-12-18 440 1.0.4 use rlink_sp1c
-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.0.1 fixup PPCM handling
-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
------------------------------------------------------------------------------
--
-- w11a test design for nexys3
-- w11a + rlink + serport
--
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:3): no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3:0) shows IO activity
-- if SWI(2)=0 (serport)
-- (3): not SER_MONI.txok (shows tx back preasure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back preasure)
-- (0): SER_MONI.rxact (shows rx activity)
-- if SWI(2)=1 (fx2-usb)
-- (3): RB_SRES.busy (shows rbus back preasure)
-- (2): RLB_TXBUSY (shows tx back preasure)
-- (1): RLB_TXENA (shows tx activity)
-- (0): RLB_RXVAL (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.fx2lib.all;
use work.fx2rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n3 is -- top level
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_w11a_n3;
architecture syn of sys_w11a_n3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal RLB_MONI : rlb_moni_type := rlb_moni_init;
signal SER_MONI : serport_moni_type := serport_moni_init;
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CPU_RESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal CACHE_CHIT : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
signal DISPREG : slv16 := (others=>'0');
constant rbaddr_core0 : slv8 := "00000000";
constant rbaddr_ibus : slv8 := "10000000";
constant rbaddr_hio : slv8 := "11000000";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c_fx2
generic map (
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
ENAFX2 => SWI(2),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
FX2_MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RB_SRES_OR : rb_sres_or_3
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_3 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
CORE : pdp11_core
port map (
CLK => CLK,
RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM_BRAM: if sys_conf_bram > 0 generate
signal HM_VAL_BRAM : slbit := '0';
begin
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => EM_MREQ.req,
HM_VAL => HM_VAL_BRAM,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end generate MEM_BRAM;
MEM_SRAM: if sys_conf_bram = 0 generate
CACHE: pdp11_cache
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
CHIT => CACHE_CHIT,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => HM_ENA,
HM_VAL => CACHE_CHIT,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
SRAM_CTL: nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => CPU_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end generate MEM_SRAM;
IB_SRES_OR : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES_IBDR,
IB_SRES_OR => IB_SRES
);
IBD_MINI : if false generate
begin
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MINI;
IBD_MAXI : if true generate
begin
IBDR_SYS : ibdr_maxisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MAXI;
IOLEDS : ioleds_sp1c_fx2
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => CPU_RESET,
ENAFX2 => SWI(2),
RB_SRES => RB_SRES,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
DSP_DAT(15 downto 0) <= DISPREG;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= CACHE_CHIT;
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
d7d5f07aeef957de079da22ea18a324b
| 0.488273 | 3.129218 | false | false | false | false |
freecores/w11
|
rtl/bplib/fx2rlink/fx2rlinklib.vhd
| 1 | 4,673 |
-- $Id: fx2rlinklib.vhd 525 2013-07-06 12:19:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: fx2rlinklib
-- Description: Definitions for rlink + fx2 interface combos
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
package fx2rlinklib is
--
-- core + fx2 interface combo
--
component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component ioleds_sp1c_fx2 -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end component;
end package fx2rlinklib;
|
gpl-2.0
|
d3ece60ff1d953a0fa2f25300c0a5e01
| 0.551252 | 3.768548 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serportlib.vhd
| 1 | 11,527 |
-- $Id: serportlib.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: serportlib
-- Description: serial port interface components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-26 476 1.2.6 renamed package to serportlib
-- 2011-12-09 437 1.2.5 rename stat->moni port
-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts;
-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs
-- 2011-10-14 416 1.2.2 add c_serport defs
-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab
-- 2010-04-10 276 1.2 add clock divider constant defs
-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package serportlib is
constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13
constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B
component serport_uart_rxtx is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end component;
component serport_uart_rx is -- serial port uart: receive part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end component;
component serport_uart_tx is -- serial port uart: transmit part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end component;
component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
);
end component;
component serport_uart_autobaud is -- serial port uart: autobauder
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
ACT : out slbit; -- active; if 1 clkdiv is invalid
DONE : out slbit -- resync done
);
end component;
component serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end component;
component serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end component;
type serport_moni_type is record -- serport monitor port
rxerr : slbit; -- receiver data error (frame error)
rxovr : slbit; -- receiver data overrun
rxact : slbit; -- receiver active
txact : slbit; -- transceiver active
abact : slbit; -- autobauder active;if 1 clkdiv invalid
abdone : slbit; -- autobauder resync done
abclkdiv : slv16; -- autobauder clock divider
rxok : slbit; -- rx channel ok
txok : slbit; -- tx channel ok
end record serport_moni_type;
constant serport_moni_init : serport_moni_type := (
'0','0', -- rxerr,rxovr
'0','0', -- rxact,txact
'0','0', -- abact,abdone
(others=>'0'), -- abclkdiv
'0','0' -- rxok,txok
);
component serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end component;
component serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end component;
end package serportlib;
|
gpl-2.0
|
b758ef67aea9035277733483091e5df7
| 0.510714 | 4.552528 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd
| 1 | 2,929 |
-- $Id: dcm_sfs_unisim_s3e.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - syn
-- Description: DCM for simple frequency synthesis; SPARTAN-3E version
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E; Spartan-6
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.3 rename dcm_sp_sfs -> dcm_sfs, SPARTAN-3E version
-- 2011-11-10 423 1.0.2 add FAMILY generic, SPARTAN-3 support
-- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM
-- 2010-11-07 337 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture syn of dcm_sfs is
begin
assert (CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1) or CLKFX_MULTIPLY>=2
report "assert((FX_DIV=1 and FX_MULT)=1 or FX_MULT>=2"
severity failure;
DCM0: if CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate DCM0;
DCM1: if CLKFX_MULTIPLY>=2 generate
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE")
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end generate DCM1;
end syn;
|
gpl-2.0
|
6eacc361efb4d0bee8556923ff3c8f78
| 0.585865 | 3.798962 | false | false | false | false |
freecores/w11
|
rtl/w11a/tb/tb_pdp11core.vhd
| 1 | 23,879 |
-- $Id: tb_pdp11core.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_pdp11core - sim
-- Description: Test bench for pdp11_core
--
-- Dependencies: simlib/simclk
-- tbd_pdp11core [UUT]
-- pdp11_intmap
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.29; ISim 11.3
--
-- Verified (with tb_pdp11core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-30 351 - 0.29 - - u:ok
-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
-- 2010-06-20 308 - 0.29 - - u:ok
-- 2009-11-22 252 - 0.26 - - u:ok
-- 2007-12-30 107 - 0.25 - - u:ok
-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
-- 2007-10-07 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-18 427 1.3.2 now numeric_std clean
-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
-- 'sta' behaviour with new 'stapc' command; rename
-- lal,lah -> wal,wah and implement locally; new
-- output format with cpfunc name
-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
-- command completion, wtgo waits for CPU to halt.
-- added .cerr,.merr directive, check cmd(m)err state
-- added .sdef as ignored directive
-- 2008-02-24 119 1.1.4 added lah,rps,wps command
-- 2008-01-26 114 1.1.3 add handling of d=val,msk
-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-02 79 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11_sim.all;
use work.pdp11.all;
entity tb_pdp11core is
end tb_pdp11core;
architecture sim of tb_pdp11core is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
signal CP_CNTL_req : slbit := '0';
signal CP_CNTL_func : slv5 := (others=>'0');
signal CP_CNTL_rnum : slv3 := (others=>'0');
signal CP_ADDR_addr : slv22_1 := (others=>'0');
signal CP_ADDR_racc : slbit := '0';
signal CP_ADDR_be : slv2 := "11";
signal CP_ADDR_ena_22bit : slbit := '0';
signal CP_ADDR_ena_ubmap : slbit := '0';
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT_cmdbusy : slbit := '0';
signal CP_STAT_cmdack : slbit := '0';
signal CP_STAT_cmderr : slbit := '0';
signal CP_STAT_cmdmerr : slbit := '0';
signal CP_STAT_cpugo : slbit := '0';
signal CP_STAT_cpustep : slbit := '0';
signal CP_STAT_cpuhalt : slbit := '0';
signal CP_STAT_cpurust : slv4 := (others=>'0');
signal CP_DOUT : slv16 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal R_CHKDAT : slv16 := (others=>'0');
signal R_CHKMSK : slv16 := (others=>'0');
signal R_CHKREQ : slbit := '0';
signal R_WAITCMD : slbit := '0';
signal R_WAITSTEP : slbit := '0';
signal R_WAITGO : slbit := '0';
signal R_WAITOK : slbit := '0';
signal R_CP_STAT : cp_stat_type := cp_stat_init;
signal R_CP_DOUT : slv16 := (others=>'0');
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT: entity work.tbd_pdp11core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL_req => CP_CNTL_req,
CP_CNTL_func => CP_CNTL_func,
CP_CNTL_rnum => CP_CNTL_rnum,
CP_ADDR_addr => CP_ADDR_addr,
CP_ADDR_racc => CP_ADDR_racc,
CP_ADDR_be => CP_ADDR_be,
CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
CP_DIN => CP_DIN,
CP_STAT_cmdbusy => CP_STAT_cmdbusy,
CP_STAT_cmdack => CP_STAT_cmdack,
CP_STAT_cmderr => CP_STAT_cmderr,
CP_STAT_cmdmerr => CP_STAT_cmdmerr,
CP_STAT_cpugo => CP_STAT_cpugo,
CP_STAT_cpustep => CP_STAT_cpustep,
CP_STAT_cpuhalt => CP_STAT_cpuhalt,
CP_STAT_cpurust => CP_STAT_cpurust,
CP_DOUT => CP_DOUT
);
proc_stim: process
file ifile : text open read_mode is "tb_pdp11core_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable idummy : integer := 0;
variable dcycle : integer := 0;
variable irqline : integer := 0;
variable ireq : boolean := false;
variable ifunc : slv5 := (others=>'0');
variable irnum : slv3 := (others=>'0');
variable idin : slv16 := (others=>'0');
variable imsk : slv16 := (others=>'1');
variable ichk : boolean := false;
variable idosta: slbit := '0';
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable rind : integer := 0;
variable nblk : integer := 0;
variable xmicmd : string(1 to 3) := (others=>' ');
variable iwtstp : boolean := false;
variable iwtgo : boolean := false;
variable icerr : integer := 0;
variable imerr : integer := 0;
variable to_cmd : integer := 50;
variable to_stp : integer := 100;
variable to_go : integer := 5000;
variable ien : slbit := '0';
variable ibit : integer := 0;
variable imemi : boolean := false;
variable ioff : slv6 := (others=>'0');
variable idoibr : boolean := false;
variable r_addr : slv22_1 := (others=>'0');
variable r_ena_22bit : slbit := '0';
variable r_ena_ubmap : slbit := '0';
variable r_ibrbase : slv(c_ibrb_ibf_base) := (others=>'0');
variable r_ibrbe : slv2 := (others=>'0');
begin
SB_CNTL <= (others=>'L');
wait for clock_offset - setup_time;
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
file_loop: while not endfile(ifile) loop
-- this logic is a quick hack to implement the 'stapc' command
if idosta = '0' then
readline (ifile, iline);
iwtstp := false;
iwtgo := false;
if nblk>0 and -- outstanding [rw]mi lines ?
iline'length>=3 and -- and 3 leading blanks
iline(iline'left to iline'left+2)=" " then
nblk := nblk - 1; -- than fill [rw]mi command in again
iline(iline'left to iline'left+2) := xmicmd;
end if;
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
else
idosta := '0';
dname := "sta ";
ok := true;
end if;
if ok then
case dname is
when "rsp " => dname := "rr6 "; -- rsp -> rr6
when "rpc " => dname := "rr7 "; -- rpc -> rr7
when "wsp " => dname := "wr6 "; -- wsp -> wr6
when "wpc " => dname := "wr7 "; -- wpc -> wr7
when others => null;
end case;
rind := character'pos(dname(3)) - character'pos('0');
if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
dname(2)='r' and
(rind>=0 and rind<=7) then
dname(3) := '|'; -- replace with [rw]r|
end if;
if dname(1) = '.' then
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="pdpcp "
report "assert .mode == pdpcp" severity failure;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".tocmd" => -- .tocmd
read_ea(iline, idelta);
to_cmd := idelta;
when ".tostp" => -- .tostp
read_ea(iline, idelta);
to_stp := idelta;
when ".togo " => -- .togo
read_ea(iline, idelta);
to_go := idelta;
when ".sdef " => -- .sdef (ignore it)
readempty(iline);
when ".cerr " => -- .cerr
read_ea(iline, icerr);
when ".merr " => -- .merr
read_ea(iline, imerr);
when ".anena" => -- .anena (ignore it)
readempty(iline);
when ".rlmon" => -- .rlmon (ignore it)
readempty(iline);
when ".rbmon" => -- .rbmon (ignore it)
readempty(iline);
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
testempty_ea(iline);
next file_loop;
else
ireq := true;
ifunc := c_cpfunc_noop;
irnum := "000";
ichk := false;
idin := (others=>'0');
imsk := (others=>'1');
imemi := false;
idoibr := false;
case dname is
when "brm " => -- brm
read_ea(iline, nblk);
xmicmd := "rmi";
next file_loop;
when "bwm " => -- bwm
read_ea(iline, nblk);
xmicmd := "wmi";
next file_loop;
when "rr| " => -- rr[0-7]
ifunc := c_cpfunc_rreg;
irnum := slv(to_unsigned(rind, 3));
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wr| " => -- wr[0-7]
ifunc := c_cpfunc_wreg;
irnum := slv(to_unsigned(rind, 3));
readoct_ea(iline, idin);
-- Note: there are no field definitions for wal, wah, wibrb because
-- there is no corresponding cp command. Therefore the
-- rbus field definitions are used here
when "wal " => -- wal
readoct_ea(iline, idin);
r_addr := (others=>'0'); -- write to al clears ah !!
r_ena_22bit := '0';
r_ena_ubmap := '0';
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
testempty_ea(iline);
next file_loop;
when "wah " => -- wah
readoct_ea(iline, idin);
r_addr(21 downto 16) := idin(c_ah_rbf_addr);
r_ena_22bit := idin(c_ah_rbf_ena_22bit);
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
testempty_ea(iline);
next file_loop;
when "wibrb " => -- wibrb
readoct_ea(iline, idin);
r_ibrbase := idin(c_ibrb_ibf_base);
if idin(c_ibrb_ibf_be) /= "00" then
r_ibrbe := idin(c_ibrb_ibf_be);
else
r_ibrbe := "11";
end if;
testempty_ea(iline);
next file_loop;
when "rm " => -- rm
ifunc := c_cpfunc_rmem;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "rmi " => -- rmi
ifunc := c_cpfunc_rmem;
imemi := true;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wm " => -- wm
ifunc := c_cpfunc_wmem;
readoct_ea(iline, idin);
when "wmi " => -- wmi
ifunc := c_cpfunc_wmem;
imemi := true;
readoct_ea(iline, idin);
when "ribr " => -- ribr
ifunc := c_cpfunc_rmem;
idoibr := true;
readoct_ea(iline, ioff);
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wibr " => -- wibr
ifunc := c_cpfunc_wmem;
idoibr := true;
readoct_ea(iline, ioff);
readoct_ea(iline, idin);
when "rps " => -- rps
ifunc := c_cpfunc_rpsw;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wps " => -- wps
ifunc := c_cpfunc_wpsw;
readoct_ea(iline, idin);
-- Note: in old version 'sta addr' was an atomic operation, loading
-- the pc and starting the cpu. Now this is action is two step
-- first a wpc followed by a 'sta'.
when "stapc " => -- stapc
ifunc := c_cpfunc_wreg;
irnum := c_gpr_pc;
readoct_ea(iline, idin);
idosta := '1'; -- request 'sta' to be done next
when "sta " => -- sta
ifunc := c_cpfunc_sta;
when "sto " => -- sto
ifunc := c_cpfunc_sto;
when "cont " => -- cont
ifunc := c_cpfunc_cont;
when "step " => -- step
ifunc := c_cpfunc_step;
iwtstp := true;
when "rst " => -- rst
ifunc := c_cpfunc_rst;
when "wtgo " => -- wtgo
iwtgo := true;
ireq := false; -- no cp request !
when "wtlam " => -- wtlam (ignore it)
readempty(iline);
next file_loop;
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
end if;
testempty_ea(iline);
end if;
if idoibr then
CP_ADDR_addr(15 downto 13) <= "111";
CP_ADDR_addr(c_ibrb_ibf_base) <= r_ibrbase;
CP_ADDR_addr(5 downto 1) <= ioff(5 downto 1);
CP_ADDR_racc <= '1';
CP_ADDR_be <= r_ibrbe;
CP_ADDR_ena_22bit <= '0';
CP_ADDR_ena_ubmap <= '0';
else
CP_ADDR_addr <= r_addr;
CP_ADDR_racc <= '0';
CP_ADDR_be <= "11";
CP_ADDR_ena_22bit <= r_ena_22bit;
CP_ADDR_ena_ubmap <= r_ena_ubmap;
end if;
if ireq then
CP_CNTL_req <= '1';
CP_CNTL_func <= ifunc;
CP_CNTL_rnum <= irnum;
end if;
if ichk then
CP_DIN <= (others=>'0');
R_CHKDAT <= idin;
R_CHKMSK <= imsk;
R_CHKREQ <= '1';
else
CP_DIN <= idin;
R_CHKREQ <= '0';
end if;
R_WAITCMD <= '0';
R_WAITSTEP <= '0';
R_WAITGO <= '0';
if iwtgo then
idelta := to_go;
R_WAITGO <= '1';
elsif iwtstp then
idelta := to_stp;
R_WAITSTEP <= '1';
else
idelta := to_cmd;
R_WAITCMD <= '1';
end if;
wait for clock_period;
CP_CNTL_req <= '0';
dcycle := 1;
while idelta>0 and R_WAITOK='0' loop
wait for clock_period;
dcycle := dcycle + 1;
idelta := idelta - 1;
end loop;
if imemi then -- rmi or wmi seen ? then inc ar
r_addr := slv(unsigned(r_addr) + 1);
end if;
write(oline, dcycle, right, 4);
write(oline, string'(" "));
if ireq then
case ifunc is
when c_cpfunc_rreg => write(oline, string'("rreg"));
when c_cpfunc_wreg => write(oline, string'("wreg"));
when c_cpfunc_rpsw => write(oline, string'("rpsw"));
when c_cpfunc_wpsw => write(oline, string'("wpsw"));
when c_cpfunc_rmem =>
if idoibr then
write(oline, string'("ribr"));
else
write(oline, string'("rmem"));
end if;
when c_cpfunc_wmem =>
if idoibr then
write(oline, string'("wibr"));
else
write(oline, string'("wmem"));
end if;
when c_cpfunc_sta => write(oline, string'("sta "));
when c_cpfunc_sto => write(oline, string'("sto "));
when c_cpfunc_cont => write(oline, string'("cont"));
when c_cpfunc_step => write(oline, string'("step"));
when c_cpfunc_rst => write(oline, string'("rst "));
when others =>
write(oline, string'("?"));
writeoct(oline, ifunc, right, 2);
write(oline, string'("?"));
end case;
writeoct(oline, irnum, right, 2);
writeoct(oline, idin, right, 8);
else
write(oline, string'("---- - ------"));
end if;
write(oline, R_CP_STAT.cmdbusy, right, 3);
write(oline, R_CP_STAT.cmdack, right, 2);
write(oline, R_CP_STAT.cmderr, right, 2);
write(oline, R_CP_STAT.cmdmerr, right, 2);
writeoct(oline, R_CP_DOUT, right, 8);
write(oline, R_CP_STAT.cpugo, right, 3);
write(oline, R_CP_STAT.cpustep, right, 2);
write(oline, R_CP_STAT.cpuhalt, right, 2);
writeoct(oline, R_CP_STAT.cpurust, right, 3);
if R_WAITOK = '1' then
if R_CP_STAT.cmderr='1' or icerr=1 then
if R_CP_STAT.cmderr='1' and icerr=0 then
write(oline, string'(" FAIL CMDERR"));
elsif R_CP_STAT.cmderr='1' and icerr=1 then
write(oline, string'(" CHECK CMDERR SEEN"));
elsif R_CP_STAT.cmderr='0' and icerr=1 then
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
end if;
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
if R_CP_STAT.cmdmerr='1' and imerr=0 then
write(oline, string'(" FAIL CMDMERR"));
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
write(oline, string'(" CHECK CMDMERR SEEN"));
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
end if;
elsif R_CHKREQ='1' then
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
write(oline, string'(" CHECK OK"));
else
write(oline, string'(" CHECK FAILED, d="));
writeoct(oline, R_CHKDAT, right, 7);
if unsigned(R_CHKMSK)/=0 then
write(oline, string'(","));
writeoct(oline, R_CHKMSK, right, 7);
end if;
end if;
end if;
if iwtgo then
write(oline, string'(" WAIT GO OK "));
elsif iwtstp then
write(oline, string'(" WAIT STEP OK"));
end if;
else
write(oline, string'(" WAIT FAILED (will reset)"));
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
end if;
writeline(output, oline);
end loop;
wait for 4*clock_period;
CLK_STOP <= '1';
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
R_WAITOK <= '0';
if R_WAITCMD = '1' then
if CP_STAT_cmdack = '1' then
R_WAITOK <= '1';
end if;
elsif R_WAITGO = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
R_WAITOK <= '1';
end if;
elsif R_WAITSTEP = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
R_WAITOK <= '1';
end if;
end if;
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
R_CP_STAT.cmdack <= CP_STAT_cmdack;
R_CP_STAT.cmderr <= CP_STAT_cmderr;
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
R_CP_STAT.cpugo <= CP_STAT_cpugo;
R_CP_STAT.cpustep <= CP_STAT_cpustep;
R_CP_STAT.cpuhalt <= CP_STAT_cpuhalt;
R_CP_STAT.cpurust <= CP_STAT_cpurust;
R_CP_DOUT <= CP_DOUT;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
457ffea74fce52b7b1db91b6dbd4938c
| 0.484777 | 3.614744 | false | false | false | false |
qynvi/rtl-fsm
|
fsm.vhd
| 1 | 1,816 |
-- William Fan
-- 01/24/2011
-- Finite State Machine RTL
library ieee;
use ieee.std_logic_1164.all;
entity FSMtimedmachine is
generic (fclk: integer := 25;
sclk: integer := 8);
port (clk,stop,rst: in std_logic;
ssd: out bit_vector(6 downto 0));
end FSMtimedmachine;
architecture tm of FSMtimedmachine is
type state is (a,ab,b,bc,c,cd,d,de,e,ef,f,fa);
signal pr_state,nx_state: state;
shared variable cv: natural range 0 to 30 := 0;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
begin
process (clk,rst,stop)
variable ncounter: natural range 0 to fclk := 0;
begin
if (rst='1') then
pr_state <= a;
ncounter := 0;
elsif (clk'event and clk='1') then
if (stop='0') then
ncounter := ncounter+1;
if (ncounter>=cv) then
pr_state <= nx_state;
end if;
end if;
end if;
end process;
process (pr_state)
begin
case pr_state is
when a =>
ssd <= "0111111";
nx_state <= ab;
cv := sclk;
when ab =>
ssd <= "0011111";
nx_state <= b;
cv := fclk;
when b =>
ssd <= "1011111";
nx_state <= bc;
cv := sclk;
when bc =>
ssd <= "1001111";
nx_state <= c;
cv := fclk;
when c =>
ssd <= "1101111";
nx_state <= cd;
cv := sclk;
when cd =>
ssd <= "1100111";
nx_state <= d;
cv := fclk;
when d =>
ssd <= "1110111";
nx_state <= de;
cv := sclk;
when de =>
ssd <= "1110011";
nx_state <= e;
cv := fclk;
when e =>
ssd <= "1111011";
nx_state <= ef;
cv := sclk;
when ef =>
ssd <= "1111001";
nx_state <= f;
cv := fclk;
when f =>
ssd <= "1111101";
nx_state <= fa;
cv := sclk;
when fa =>
ssd <= "0111101";
nx_state <= a;
cv := fclk;
end case;
end process;
end architecture;
|
mit
|
f0ee02bda3daf64983367f610cbf5116
| 0.553414 | 2.819876 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/AddBB.vhd
| 1 | 3,406 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity AddBB is
port (
CLK : in std_logic;
RST : in std_logic;
VALID_IN : in std_logic;
READY_IN : in std_logic;
LEFT : in std_logic_vector(31 downto 0);
RIGHT : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic;
READY_OUT : out std_logic;
ADD_OUT : out std_logic_vector(31 downto 0)
);
end AddBB;
architecture arch of AddBB is
signal RESULT :std_logic_vector(31 downto 0);
-- END DSP48E1_inst_1
constant DELAY_ADD_SUB : positive := 2;
--
TYPE iBus_ADD_SUB is array(DELAY_ADD_SUB-1 downto 0) of std_logic;
--
signal ValidsRegBus_ADD_SUB : iBus_ADD_SUB := (others => '0');
--
COMPONENT logic_dff_block
Port (
D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
END COMPONENT;
begin
ADDSUB_MACRO_inst : ADDSUB_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => 2, -- Desired clock cycle latency, 0-2
WIDTH => 32) -- Input / Output bus width, 1-48
port map (
CARRYOUT => open, -- 1-bit carry-out output signal
RESULT => RESULT, -- Add/sub result output, width defined by WIDTH generic
A => LEFT, -- Input A bus, width defined by WIDTH generic
ADD_SUB => '1', -- 1-bit add/sub input, high selects add, low selects subtract
B => RIGHT, -- Input B bus, width defined by WIDTH generic
CARRYIN => '0', -- 1-bit carry-in input
CE => '1', -- 1-bit clock enable input
CLK =>CLK, -- 1-bit clock input
RST => RST -- 1-bit active high synchronous reset
);
validReg_ADD_int: for i in 0 to DELAY_ADD_SUB generate
begin
validdffLeft_ADD: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate validdffLeft_ADD;
--
dffOthers_ADD: if (i > 0 AND i < DELAY_ADD_SUB) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate dffOthers_ADD;
--
dffRight_ADD: if i = DELAY_ADD_SUB generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_ADD;
end generate validReg_ADD_int;
calc_result : process(clk)
begin
if rising_edge(clk) then
ADD_OUT <= RESULT;
end if;
end process;
READY_OUT <= READY_IN;
end architecture ; -- arch
|
gpl-3.0
|
d366d82e587f8d734650f5de65545fdc
| 0.504991 | 4.069295 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/sn_humanio_demu.vhd
| 2 | 5,859 |
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_demu - syn
-- Description: All BTN, SWI, LED handling for atlys
--
-- Dependencies: bpgen/bp_swibtnled
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
-- 2011-10-10 413 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end sn_humanio_demu;
architecture syn of sn_humanio_demu is
constant c_mode_led : slv2 := "00";
constant c_mode_dp : slv2 := "01";
constant c_mode_datl : slv2 := "10";
constant c_mode_dath : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
cnt : slv9; -- msec counter
up_1 : slbit; -- btn up last cycle
dn_1 : slbit; -- btn dn last cycle
led : slv8; -- led state
end record regs_type;
constant regs_init : regs_type := (
c_mode_led, -- mode
(others=>'0'), -- cnt
'0','0', -- up_1, dn_1
(others=>'0') -- led
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN_HW : slv6 := (others=>'0');
signal LED_HW : slv8 := (others=>'0');
begin
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
BWIDTH => 6,
LWIDTH => 8,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN_HW,
LED => LED_HW,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibtn : slv4 := (others=>'0');
variable iup : slbit := '0';
variable idn : slbit := '0';
variable ipuls : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
ibtn(1) := BTN_HW(1);
ibtn(2) := BTN_HW(4);
ibtn(3) := BTN_HW(3);
iup := BTN_HW(0);
idn := BTN_HW(2);
ipuls := '0';
n.up_1 := iup;
n.dn_1 := idn;
if iup='0' and idn='0' then
n.cnt := (others=>'0');
else
if CE_MSEC = '1' then
n.cnt := slv(unsigned(r.cnt) + 1);
if r.cnt = "111111111" then
ipuls := '1';
end if;
end if;
end if;
if iup='1' or idn='1' then
n.led := (others=>'0');
case r.mode is
when c_mode_led => n.led(0) := '1';
when c_mode_dp => n.led(1) := '1';
when c_mode_datl => n.led(2) := '1';
when c_mode_dath => n.led(3) := '1';
when others => null;
end case;
if iup='1' and (r.up_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) + 1);
elsif idn='1' and (r.dn_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) - 1);
end if;
else
case r.mode is
when c_mode_led => n.led := LED;
when c_mode_dp => n.led := "0000" & DSP_DP;
when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
when c_mode_dath => n.led := DSP_DAT(15 downto 8);
when others => null;
end case;
end if;
N_REGS <= n;
BTN <= ibtn;
LED_HW <= r.led;
end process proc_next;
end syn;
|
gpl-2.0
|
65f202a7a533ddaec7ff424d9a4856ca
| 0.479433 | 3.493739 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd
| 1 | 7,687 |
-- $Id: tb_serport_uart_rxtx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rxtx - sim
-- Description: Test bench for serport_uart_rxtx
--
-- Dependencies: simlib/simclk
-- tbd_serport_uart_rxtx [UUT]
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rxtx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-21 91 - 0.26 - - c:ok
-- 2007-10-14 89 - 0.26 - - c:ok
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-12 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 use new simclk/simclkcnt
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_serport_uart_rxtx is
end tb_serport_uart_rxtx;
architecture sim of tb_serport_uart_rxtx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(15, 13));
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXSD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_serport_uart_rxtx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rxtx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
read_ea(iline, irate);
CLKDIV <= slv(to_unsigned(irate-1, 13));
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
while TXBUSY='1' loop
wait for clock_period;
end loop;
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
TXDATA <= itxdata;
TXENA <= '1';
N_MON_VAL <= '1';
N_MON_DAT <= itxdata;
wait for clock_period;
TXENA <= '0';
N_MON_VAL <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
idelta := 0;
while TXBUSY='1' or RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
2eec2a0615fbb7aea6f291d2ce8b8ec6
| 0.524652 | 3.670965 | false | false | false | false |
unhold/hdl
|
vhdl/vether/vether.vhd
| 1 | 7,378 |
library ieee;
use ieee.numeric_bit.all;
--! Ethernet 10BASE-T,
--! IEEE802.3-2008 clauses 3, 7.
package vether is
subtype octet_t is unsigned(7 downto 0);
type data_t is array(natural range <>) of octet_t;
subtype mac_addr_t is unsigned(47 downto 0);
function repeat(data : data_t; count : positive) return data_t;
--- Word/data conversion, high byte first:
function to_data(word : unsigned) return data_t;
function to_word(data : data_t) return unsigned;
--- Frame types of the sublayers:
subtype mac_t is data_t; --! Media Access Control frame
--! TODO: change to record?
subtype pls_t is bit_vector; --! Physical Layer Symbol frame
subtype pma_t is bit_vector; --! Physical Media Attachment frame
--! Encapsulate data into MAC frame, calculate FCS.
function to_mac(dst, src : mac_addr_t; data : data_t) return mac_t;
--! TODO: add padding?
--! TODO: add ethertype I/II options
--! Covert to PLS frame: serialize, add preamble, SFD and ETD.
function to_pls(mac : mac_t) return pls_t;
--! Convert to PMA frame: Manchester-encode.
--! May also be done with clock-XOR.
function to_pma(pls : pls_t) return pma_t;
constant crc32_polynomial : unsigned(31 downto 0) := (
26 => '1', 23 => '1', 22 => '1', 16 => '1', 12 => '1',
11 => '1', 10 => '1', 8 => '1', 7 => '1', 5 => '1',
4 => '1', 2 => '1', 1 => '1', 0 => '1', others => '0');
constant addr : mac_addr_t := x"123456789ABC";
constant data : data_t;
constant mac : mac_t;
constant pls : pls_t;
constant pma : pma_t;
end;
package body vether is
function to_manchester(pls_bit : bit) return pma_t is
begin
case pls_bit is
when '0' => return "10";
when '1' => return "01";
end case;
end function;
function reverse(data : bit_vector) return bit_vector is
constant data_reverse : bit_vector(data'reverse_range) := data;
variable result : bit_vector(data'range);
begin
for i in result'range loop
result(i) := data_reverse(i);
end loop;
return result;
end;
function repeat(data : bit_vector; count : positive)
return bit_vector is
begin
if count = 1 then
return data;
else
return data & repeat(data, count-1);
end if;
end;
function repeat(data : data_t; count : positive) return data_t is
begin
if count = 1 then
return data;
else
return data & repeat(data, count-1);
end if;
end;
function to_pma_data(pls : pls_t) return pma_t is
begin
if pls'length = 0 then
return "";
-- Could do without the elsif, directly in the else,
-- but this avoids warnings about the empty range.
elsif pls'length = 1 then
return to_manchester(pls(pls'left));
else
return to_manchester(pls(pls'left))
& to_pma_data(pls(pls'left+1 to pls'right));
end if;
end;
function to_pma(pls : pls_t) return pma_t is
constant cd0 : pls_t := to_manchester('0');
constant cd1 : pls_t := to_manchester('1');
constant preamble : pls_t := repeat(cd1 & cd0, 28);
constant sfd : pls_t := repeat(cd1 & cd0, 3) & cd1 & cd1;
constant data : pls_t := to_pma_data(pls);
constant idl : pls_t := "1111";
begin
assert preamble'length = 7 * 8 * 2;
assert sfd'length = 1 * 8 * 2;
assert data'length = pls'length * 2;
assert idl'length = 4;
return preamble & sfd & data & idl;
end;
function to_pls(mac : mac_t) return pls_t is
begin
assert mac'length <= 1500;
if mac'length = 0 then
return "";
-- Could do without the elsif, directly in the else,
-- but it avoids warnings about the empty range.
elsif mac'length = 1 then
return reverse(bit_vector(mac(mac'left)));
else
-- LSB first
return reverse(bit_vector(mac(mac'left)))
& to_pls(mac(mac'left+1 to mac'right));
end if;
end;
function to_data(word : unsigned) return data_t is
constant desc : unsigned(word'high downto word'low) := word;
begin
assert desc'length mod 8 = 0
report "to_data: Word length must be multiple of 8.";
if desc'length = 8 then
return data_t'(0 => octet_t(desc));
else
return to_data(desc(desc'high downto desc'high-7)) &
to_data(desc(desc'high-8 downto desc'low));
end if;
end;
function to_word(data : data_t) return unsigned is
begin
if data'length = 0 then
return "";
else
return unsigned(data(data'left))
& to_word(data(data'left+1 to data'right));
end if;
end;
function fcs(pls : pls_t) return pls_t is
variable crc : pls_t(31 downto 0) := (others => '1');
variable msb : bit;
begin
for i in pls'range loop
msb := crc(31);
crc := crc(30 downto 0) & '0';
if (pls(i) xor msb) = '1' then
crc := crc xor pls_t(crc32_polynomial);
end if;
end loop;
return not crc;
end;
function fcs(mac_without_fcs : mac_t) return mac_t is
constant crc : pls_t(31 downto 0) :=
fcs(to_pls(mac_without_fcs));
begin
-- FCS is sent out MSB first, as opposed to all other data,
-- so bit-reverse it on byte level.
return data_t'(
0 => octet_t(reverse(crc(31 downto 24))),
1 => octet_t(reverse(crc(23 downto 16))),
2 => octet_t(reverse(crc(15 downto 8))),
3 => octet_t(reverse(crc( 7 downto 0))));
end;
function to_mac(dst, src : mac_addr_t; data : data_t) return mac_t is
constant mac_without_fcs : mac_t :=
to_data(dst) &
to_data(src) &
--to_data(to_unsigned(data'length, 16)) &
-- -- Ethernet Type I
to_data(x"0800") & -- Ethernet Type II
data;
begin
return mac_without_fcs & fcs(mac_without_fcs);
end;
constant data : data_t := to_data(addr);
constant mac : mac_t := to_mac(addr, addr, data);
constant pls : pls_t := to_pls(mac);
constant pma : pma_t := to_pma(pls);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rtl_pack.all;
use work.vether.all;
entity vether_tx is
generic (
clk_freq_g : natural);
port (
rst_i : in std_ulogic := '0';
clk_i,
stb_i : in std_ulogic;
tx_po,
tx_no,
run_o : out std_ulogic);
end;
architecture rtl of vether_tx is
constant addr : mac_addr_t := x"123456789ABC";
constant data : data_t := repeat(to_data(addr), 8);
constant mac : mac_t := to_mac(addr, addr, data);
constant pls : pls_t := to_pls(mac);
constant pma : pma_t := to_pma(pls);
signal run : std_ulogic := '1';
signal idx : integer range pma'range := pma'left;
signal lp_stb, lp : std_ulogic;
begin
assert mac'length = 18 + data'length
report "mac: Length error.";
assert pls'length = mac'length * 8
report "pls: Length error.";
assert pma'length = 128 + pls'length * 2 + 4
report "pma: Length error.";
process(rst_i, clk_i)
begin
if rst_i = '1' then
run <= '1';
idx <= pma'left;
tx_po <= '0';
tx_no <= '0';
elsif rising_edge(clk_i) then
if run = '1' or stb_i = '1' then
if idx = pma'right then
run <= '0';
idx <= pma'left;
tx_po <= '0';
tx_no <= '0';
else
run <= '1';
idx <= idx + 1;
end if;
tx_po <= to_stdulogic(pma(idx));
tx_no <= to_stdulogic(not pma(idx));
elsif lp = '1' then
tx_po <= '1';
tx_no <= '0';
else
tx_po <= '0';
tx_no <= '0';
end if;
end if;
end process;
lp_stb_gen : entity work.stb_gen
generic map (
period_g => clk_freq_g * 16 / 1000)
port map (
rst_i => rst_i,
clk_i => clk_i,
sync_rst_i => run,
stb_o => lp_stb);
lp_gen : entity work.pulse_gen
generic map (
duration_g => 2)
port map (
rst_i => rst_i,
clk_i => clk_i,
stb_i => lp_stb,
pulse_o => lp);
run_o <= run;
end;
|
gpl-3.0
|
730ade36d17398c9de559a21a831db20
| 0.623882 | 2.748882 | false | false | false | false |
dumpram/zedboard-ofdm
|
vhdl/cyclic_prefix_fsm.vhd
| 1 | 3,919 |
-- Dodati signal fifo_empty i provjeru stanja FIFO buffera
-- Izlaz prema vanjskom reset kontroleru
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity cyclic_prefix_fsm is
port (
reset : in std_logic;
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
rd_en : out std_logic;
fifo_rd_count : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(31 downto 0);
fd_out : out std_logic;
rffd : in std_logic;
dft_data_valid : in std_logic
);
end cyclic_prefix_fsm;
architecture rtl of cyclic_prefix_fsm is
constant prefix_size : integer := 240;
constant data_size : integer := 960;
constant data_threshold : integer := 1024;
type fsm is (rst, cyclic_prefix_wait, fifo_dft_wait, dft_sample, dft_out_wait);
signal state : fsm := rst;
signal data_cnt : std_logic_vector(16 downto 0);
signal prefix_cnt : std_logic_vector(16 downto 0);
begin
dout <= din;
process(clk, reset)
begin
if (clk'event and clk = '1') then
case state is
when rst =>
rd_en <= '1';
fd_out <= '0';
prefix_cnt <= std_logic_vector(to_unsigned(prefix_size - 1, prefix_cnt'length));
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
state <= cyclic_prefix_wait;
-- Cekamo minimalno prefix_size uzoraka i koliko god je jos potrebno do pojave peaka na izlazu FIFO-a
when cyclic_prefix_wait =>
rd_en <= '1';
fd_out <= '0';
prefix_cnt <= prefix_cnt;
if (prefix_cnt /= (prefix_cnt'range => '0')) then
prefix_cnt <= prefix_cnt - '1';
state <= cyclic_prefix_wait;
elsif (to_integer(unsigned(din)) < data_threshold) then
state <= cyclic_prefix_wait;
else
state <= fifo_dft_wait;
end if;
-- Cekamo popunjavanje FIFO buffera i spremnost DFT-a za prihvat uzoraka
when fifo_dft_wait =>
rd_en <= '0';
fd_out <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
if (to_integer(unsigned(fifo_rd_count)) < data_size) then
state <= fifo_dft_wait;
-- FIFO ima dovoljno uzoraka; Provjeravamo spremnost DFT-a
elsif (rffd = '0') then
state <= fifo_dft_wait;
else
fd_out <= '1';
rd_en <= '1';
state <= dft_sample;
end if;
-- Prosljedjujemo uzorke DFT-u
when dft_sample =>
fd_out <= '0';
rd_en <= '1';
prefix_cnt <= std_logic_vector(to_unsigned(prefix_size - 1, prefix_cnt'length));
data_cnt <= data_cnt;
if (data_cnt /= (data_cnt'range => '0')) then
data_cnt <= data_cnt - '1';
state <= dft_sample;
else
rd_en <= '0';
state <= dft_out_wait;
end if;
-- Cekamo dok DFT ne izbaci sve uzorke spektra
when dft_out_wait =>
fd_out <= '0';
rd_en <= '0';
prefix_cnt <= std_logic_vector(to_unsigned(prefix_size - 1, prefix_cnt'length));
if (dft_data_valid = '1') then
state <= dft_out_wait;
else
rd_en <= '0';
state <= cyclic_prefix_wait;
end if;
when others =>
null;
end case;
if ( reset = '1') then
state <= rst;
end if;
end if;
end process;
end rtl;
|
mit
|
e41686cd5ff7d2b136964943d6ca8ba5
| 0.492983 | 3.666043 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_uart_rxtx.vhd
| 1 | 2,841 |
-- $Id: serport_uart_rxtx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx - syn
-- Description: serial port UART - transmitter + receiver
--
-- Dependencies: serport_uart_rx
-- serport_uart_tx
-- Test bench: tb/tb_serport_uart_rxtx
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_uart_rxtx is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end serport_uart_rxtx;
architecture syn of serport_uart_rxtx is
begin
RX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
TX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
|
gpl-2.0
|
4b01a41104b7bfe0fa30bec4b6e8f091
| 0.550862 | 4.190265 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd
| 1 | 6,278 |
-- $Id: bp_rs232_2l4l_iob.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description: iob's for internal(2line) + external(4line) rs232, with select
--
-- Dependencies: bp_rs232_2line_iob
-- bp_rs232_4line_iob
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.2.2 fix mistake in tx and rts relay
-- 2011-08-07 404 1.2.1 add RELAY generic and a relay stage towards IOB's
-- 2011-08-06 403 1.2 add pipeline flops; add RESET signal
-- 2011-07-09 391 1.1 moved and renamed to bpgen
-- 2011-07-02 387 1.0.1 use bp_rs232_[24]line_iob now
-- 2010-04-17 278 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end bp_rs232_2l4l_iob;
architecture syn of bp_rs232_2l4l_iob is
signal RXD0 : slbit := '0';
signal RXD1 : slbit := '0';
signal CTS1_N : slbit := '0';
signal R_RXD : slbit := '1';
signal R_CTS_N : slbit := '0';
signal R_TXD0 : slbit := '1';
signal R_TXD1 : slbit := '1';
signal R_RTS1_N : slbit := '0';
signal RR_RXD0 : slbit := '1';
signal RR_TXD0 : slbit := '1';
signal RR_RXD1 : slbit := '1';
signal RR_TXD1 : slbit := '1';
signal RR_CTS1_N : slbit := '0';
signal RR_RTS1_N : slbit := '0';
begin
-- On Digilent Atlys bords the IOBs for P0 and P1 are on diagonally opposide
-- corners of the die, which causes very long (7-8ns) routing delays to a LUT
-- in the middle. The RELAY generic allows to add 'relay flops' between IOB
-- flops and the mux implented in proc_regs_mux.
--
-- The data flow is
-- iob-flop relay-flop if-flop port
-- RXD0 -> RR_RXD0 -> R_RXD -> RXD
-- TXD0 <- RR_TXD0 <- R_TXD0 <- TXD
-- RXD1 -> RR_RXD1 -> R_RXD -> RXD
-- TXD1 <- RR_TXD1 <- R_TXD1 <- TXD
-- CTS1_N -> RR_CTS1_N -> R_CTS_N -> CTS
-- RTS1_N <- RR_RTS1_N <- R_RTS1_N <- RTS
P0 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD0,
TXD => RR_TXD0,
I_RXD => I_RXD0,
O_TXD => O_TXD0
);
P1 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD1,
TXD => RR_TXD1,
CTS_N => CTS1_N,
RTS_N => RR_RTS1_N,
I_RXD => I_RXD1,
O_TXD => O_TXD1,
I_CTS_N => I_CTS1_N,
O_RTS_N => O_RTS1_N
);
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
RR_RXD1 <= '1';
RR_TXD1 <= '1';
RR_CTS1_N <= '0';
RR_RTS1_N <= '0';
else
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end if;
end if;
end process proc_regs_pipe;
end generate DORELAY;
NORELAY : if not RELAY generate
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end generate NORELAY;
proc_regs_mux: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';
R_TXD0 <= '1';
R_TXD1 <= '1';
R_RTS1_N <= '0';
else
if SEL = '0' then -- use 2-line rs232, no flow cntl
R_RXD <= RR_RXD0; -- get port 0 inputs
R_CTS_N <= '0';
R_TXD0 <= TXD; -- set port 0 output
R_TXD1 <= '1'; -- port 1 outputs to idle state
R_RTS1_N <= '0';
else -- otherwise use 4-line rs232
R_RXD <= RR_RXD1; -- get port 1 inputs
R_CTS_N <= RR_CTS1_N;
R_TXD0 <= '1'; -- port 0 output to idle state
R_TXD1 <= TXD; -- set port 1 outputs
R_RTS1_N <= RTS_N;
end if;
end if;
end if;
end process proc_regs_mux;
RXD <= R_RXD;
CTS_N <= R_CTS_N;
end syn;
|
gpl-2.0
|
a85eb46fc83f3bde79db099344be04c0
| 0.490443 | 3.16272 | false | false | false | false |
freecores/w11
|
rtl/bplib/nexys3/tb/tb_nexys3_core.vhd
| 1 | 3,204 |
-- $Id: tb_nexys3_core.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
gpl-2.0
|
facf5f868469c1d97e10747d74a277ef
| 0.561174 | 3.216867 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd
| 1 | 4,782 |
-- $Id: tst_fx2looplib.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: tst_fx2looplib
-- Description: Definitions for tst_fx2loop records and helpers
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.fx2lib.all;
package tst_fx2looplib is
constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as
constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic
constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
tx2blast : slbit; -- enable tx2 blast
throttle : slbit; -- enable 1 msec tx throttling
end record hio_cntl_type;
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0' -- tx2blast,throttle
);
type hio_stat_type is record -- humanio status
rxhold : slbit; -- rx hold
txbusy : slbit; -- tx busy
tx2busy : slbit; -- tx2 busy
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx word counter
txcnt : slv32; -- tx word counter
tx2cnt : slv32; -- tx2 word counter
end record hio_stat_type;
constant hio_stat_init : hio_stat_type := (
'0','0','0', -- rxhold,txbusy,tx2busy
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0') -- tx2cnt
);
-- -------------------------------------
component tst_fx2loop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit; -- transmit busy
TX2DATA : out slv8; -- transmit 2 data in
TX2ENA : out slbit; -- transmit 2 data enable
TX2BUSY : in slbit -- transmit 2 busy
);
end component;
component tst_fx2loop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
end package tst_fx2looplib;
|
gpl-2.0
|
f3e86a1e87f874928905034fce59bf17
| 0.520494 | 4.069787 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd
| 1 | 11,808 |
-- $Id: sys_tst_fx2loop_n2.vhd 461 2012-04-09 21:17:54Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n2 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100
-- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_fx2loop_n2 is -- top level
-- implements nexys2_aif + fx2 pins
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n2;
architecture syn of sys_tst_fx2loop_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN,
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;
|
gpl-2.0
|
75337f345a82d928a8659accc302eda4
| 0.501694 | 3.113924 | false | false | false | false |
freecores/w11
|
rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd
| 1 | 7,935 |
-- $Id: fx2_2fifo_core.vhd 469 2013-01-05 12:29:44Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifo_core - sim
-- Description: Cypress EZ-USB FX2 (2 fifo core model)
--
-- Dependencies: memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
use work.fx2lib.all;
use work.memlib.all;
entity fx2_2fifo_core is -- EZ-USB FX2 (2 fifo core model)
port (
CLK : in slbit; -- uplink clock
RESET : in slbit; -- reset
RXDATA : in slv8; -- rx data (ext->fx2)
RXENA : in slbit; -- rx enable
RXBUSY : out slbit; -- rx busy
TXDATA : out slv8; -- tx data (fx2->ext)
TXVAL : out slbit; -- tx valid
IFCLK : out slbit; -- fx2 interface clock
FIFO : in slv2; -- fx2 fifo address
FLAG : out slv4; -- fx2 fifo flags
SLRD_N : in slbit; -- fx2 read enable (act.low)
SLWR_N : in slbit; -- fx2 write enable (act.low)
SLOE_N : in slbit; -- fx2 output enable (act.low)
PKTEND_N : in slbit; -- fx2 packet end (act.low)
DATA : inout slv8 -- fx2 data lines
);
end fx2_2fifo_core;
architecture sim of fx2_2fifo_core is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
constant bufsize : positive := 1024;
constant datzero : slv(DATA'range) := (others=>'0');
type buf_type is array (0 to bufsize-1) of slv(DATA'range);
signal CLK30 : slbit := '0';
signal RXFIFO_DO : slv8 := (others=>'0');
signal RXFIFO_VAL : slbit := '0';
signal RXFIFO_HOLD : slbit := '0';
signal TXFIFO_DI : slv8 := (others=>'0');
signal TXFIFO_ENA : slbit := '0';
signal TXFIFO_BUSY : slbit := '0';
signal R_FLAG : slv4 := (others=>'0');
signal R_DATA : slv8 := (others=>'0');
-- added for debug purposes
signal R_rxbuf_rind : natural := 0;
signal R_rxbuf_wind : natural := 0;
signal R_rxbuf_nbyt : natural := 0;
signal R_txbuf_rind : natural := 0;
signal R_txbuf_wind : natural := 0;
signal R_txbuf_nbyt : natural := 0;
begin
RXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => CLK30,
RESETW => '0',
RESETR => '0',
DI => RXDATA,
ENA => RXENA,
BUSY => RXBUSY,
DO => RXFIFO_DO,
VAL => RXFIFO_VAL,
HOLD => RXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
TXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK30,
CLKR => CLK,
RESETW => '0',
RESETR => '0',
DI => TXFIFO_DI,
ENA => TXFIFO_ENA,
BUSY => TXFIFO_BUSY,
DO => TXDATA,
VAL => TXVAL,
HOLD => '0',
SIZEW => open,
SIZER => open
);
proc_ifclk: process
constant offset : time := 200 ns;
constant halfperiod_7 : time := 16700 ps;
constant halfperiod_6 : time := 16600 ps;
begin
CLK30 <= '0';
wait for offset;
clk_loop: loop
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_6;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_6;
exit clk_loop when to_x01(SB_CLKSTOP) = '1';
end loop;
wait; -- endless wait, simulator will stop
end process proc_ifclk;
proc_state: process (CLK30)
variable rxbuf : buf_type := (others=>datzero);
variable rxbuf_rind : natural := 0;
variable rxbuf_wind : natural := 0;
variable rxbuf_nbyt : natural := 0;
variable txbuf : buf_type := (others=>datzero);
variable txbuf_rind : natural := 0;
variable txbuf_wind : natural := 0;
variable txbuf_nbyt : natural := 0;
variable oline : line;
begin
if rising_edge(CLK30) then
RXFIFO_HOLD <= '0';
TXFIFO_ENA <= '0';
-- rxfifo -> rxbuf
if RXFIFO_VAL = '1' then
if rxbuf_nbyt < bufsize then
rxbuf(rxbuf_wind) := RXFIFO_DO;
rxbuf_wind := (rxbuf_wind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt + 1;
else
RXFIFO_HOLD <= '1';
end if;
end if;
-- txbuf -> txfifo
if txbuf_nbyt>0 and TXFIFO_BUSY='0' then
TXFIFO_DI <= txbuf(txbuf_rind);
TXFIFO_ENA <= '1';
txbuf_rind := (txbuf_rind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt - 1;
end if;
-- slrd cycle: rxbuf -> data
if SLRD_N = '0' then
if rxbuf_nbyt > 0 then
rxbuf_rind := (rxbuf_rind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt - 1;
else
write(oline, string'("fx2_2fifo_core: SLRD_N=0 when rxbuf empty"));
writeline(output, oline);
end if;
end if;
R_DATA <= rxbuf(rxbuf_rind);
-- slwr cycle: data -> txbuf
if SLWR_N = '0' then
if txbuf_nbyt < bufsize then
txbuf(txbuf_wind) := DATA;
txbuf_wind := (txbuf_wind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt + 1;
else
write(oline, string'("fx2_2fifo_core: SLWR_N=0 when txbuf full"));
writeline(output, oline);
end if;
end if;
-- prepare flags (note that FLAGs are act.low!)
R_FLAG <= (others=>'1');
-- FLAGA = indexed, PF
-- rx endpoint -> PF 'almost empty' at 3 bytes to go
if FIFO = c_rxfifo then
if rxbuf_nbyt < 4 then
R_FLAG(0) <= '0';
end if;
-- tx endpoint -> PF 'almost full' at 3 bytes to go
elsif FIFO = c_txfifo then
if txbuf_nbyt > bufsize-4 then
R_FLAG(0) <= '0';
end if;
end if;
-- FLAGB = EP6 FF
if txbuf_nbyt = bufsize then
R_FLAG(1) <= '0';
end if;
-- FLAGC = EP4 EF
if rxbuf_nbyt = 0 then
R_FLAG(2) <= '0';
end if;
-- FLAGD = EP8 FF
R_FLAG(3) <= '1';
-- added for debug purposes
R_rxbuf_rind <= rxbuf_rind;
R_rxbuf_wind <= rxbuf_wind;
R_rxbuf_nbyt <= rxbuf_nbyt;
R_txbuf_rind <= txbuf_rind;
R_txbuf_wind <= txbuf_wind;
R_txbuf_nbyt <= txbuf_nbyt;
end if;
end process proc_state;
IFCLK <= CLK30;
FLAG <= R_FLAG;
proc_data: process (SLOE_N, R_DATA)
begin
if SLOE_N = '1' then
DATA <= (others=>'Z');
else
DATA <= R_DATA;
end if;
end process proc_data;
end sim;
|
gpl-2.0
|
d4e6e2fdfd5910c90aa8a87248736aa4
| 0.525394 | 3.59375 | false | false | false | false |
freecores/w11
|
rtl/vlib/memlib/ram_1swar_gen.vhd
| 2 | 3,124 |
-- $Id: ram_1swar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_gen - syn
-- Description: Single-Port RAM with with one synchronous write and one
-- asynchronius read port (as distributed RAM).
-- The code is inspired by Xilinx example rams_04.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm Comments
-- 4 16 - 16 16*RAM16X1S
-- 5 16 - 32 16*RAM32X1S
-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swar_gen;
architecture syn of ram_1swar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDR))) <= DI;
end if;
end if;
end process proc_clk;
DO <= RAM(to_integer(unsigned(ADDR)));
end syn;
|
gpl-2.0
|
996ff5a0618f417fb4a11998dd9ce11e
| 0.573303 | 3.514061 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/d51d3e8f8c8f0315/vio_0_sim_netlist.vhdl
| 1 | 538,816 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:06:15 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.vhdl
-- Design : vio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k160tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
port (
s_drdy_i : out STD_LOGIC;
\wr_en_reg[4]_0\ : out STD_LOGIC;
\wr_en_reg[4]_1\ : out STD_LOGIC;
\wr_en_reg[4]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_do_i : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_rst_o : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
\Bus_Data_out_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
signal Hold_probe_in : STD_LOGIC;
signal clear_int : STD_LOGIC;
signal committ_int : STD_LOGIC;
signal \data_info_probe_in__67\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_cnt_rst : STD_LOGIC;
signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rd_en_p1 : STD_LOGIC;
signal rd_en_p2 : STD_LOGIC;
signal wr_control_reg : STD_LOGIC;
signal \wr_en[2]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[2]_i_2_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_6_n_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_1\ : STD_LOGIC;
signal \^wr_en_reg[4]_2\ : STD_LOGIC;
signal wr_probe_out_modified : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_8_p1 : STD_LOGIC;
signal xsdb_addr_8_p2 : STD_LOGIC;
signal xsdb_drdy_i_1_n_0 : STD_LOGIC;
signal xsdb_rd : STD_LOGIC;
signal xsdb_wr : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Bus_data_out[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Bus_data_out[13]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[15]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wr_en[2]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \wr_en[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wr_en[4]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair14";
begin
\wr_en_reg[4]_0\ <= \^wr_en_reg[4]_0\;
\wr_en_reg[4]_1\ <= \^wr_en_reg[4]_1\;
\wr_en_reg[4]_2\ <= \^wr_en_reg[4]_2\;
\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF00AF000FC000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(0),
I1 => probe_out_modified(0),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => committ_int,
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(0)
);
\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(10),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(10),
O => \data_info_probe_in__67\(10)
);
\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(11),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(11),
O => \data_info_probe_in__67\(11)
);
\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(12),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(12)
);
\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(13),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(13)
);
\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(14),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(14)
);
\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(15),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(15)
);
\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0000FC0A00000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(1),
I1 => probe_out_modified(1),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => xsdb_addr_2_0_p2(0),
I5 => clear_int,
O => \data_info_probe_in__67\(1)
);
\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A000000F00CFCF"
)
port map (
I0 => \Bus_Data_out_reg[11]\(2),
I1 => probe_out_modified(2),
I2 => xsdb_addr_2_0_p2(2),
I3 => int_cnt_rst,
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(2)
);
\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(3),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(3),
O => \data_info_probe_in__67\(3)
);
\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(4),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(4),
O => \data_info_probe_in__67\(4)
);
\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(5),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(5),
O => \data_info_probe_in__67\(5)
);
\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(6),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(6),
O => \data_info_probe_in__67\(6)
);
\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(7),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(7),
O => \data_info_probe_in__67\(7)
);
\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(8),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(8),
O => \data_info_probe_in__67\(8)
);
\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(9),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(9),
O => \data_info_probe_in__67\(9)
);
\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(0),
Q => s_do_i(0),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(10),
Q => s_do_i(10),
R => xsdb_addr_8_p2
);
\bus_data_out_reg[11]_RnM\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(11),
Q => s_do_i(11),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(12),
Q => s_do_i(12),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(13),
Q => s_do_i(13),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(14),
Q => s_do_i(14),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(15),
Q => s_do_i(15),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(1),
Q => s_do_i(1),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(2),
Q => s_do_i(2),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(3),
Q => s_do_i(3),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(4),
Q => s_do_i(4),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(5),
Q => s_do_i(5),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(6),
Q => s_do_i(6),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(7),
Q => s_do_i(7),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(8),
Q => s_do_i(8),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(9),
Q => s_do_i(9),
R => xsdb_addr_8_p2
);
Hold_probe_in_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(3),
Q => Hold_probe_in,
R => s_rst_o
);
clear_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(1),
Q => clear_int,
R => s_rst_o
);
committ_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(0),
Q => committ_int,
R => s_rst_o
);
int_cnt_rst_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(2),
Q => int_cnt_rst,
R => s_rst_o
);
\probe_in_reg[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Hold_probe_in,
O => E(0)
);
\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(0),
Q => probe_out_modified(0),
R => clear_int
);
\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(10),
Q => probe_out_modified(10),
R => clear_int
);
\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(11),
Q => probe_out_modified(11),
R => clear_int
);
\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(12),
Q => probe_out_modified(12),
R => clear_int
);
\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(13),
Q => probe_out_modified(13),
R => clear_int
);
\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(14),
Q => probe_out_modified(14),
R => clear_int
);
\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(15),
Q => probe_out_modified(15),
R => clear_int
);
\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(1),
Q => probe_out_modified(1),
R => clear_int
);
\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(2),
Q => probe_out_modified(2),
R => clear_int
);
\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(3),
Q => probe_out_modified(3),
R => clear_int
);
\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(4),
Q => probe_out_modified(4),
R => clear_int
);
\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(5),
Q => probe_out_modified(5),
R => clear_int
);
\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(6),
Q => probe_out_modified(6),
R => clear_int
);
\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(7),
Q => probe_out_modified(7),
R => clear_int
);
\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(8),
Q => probe_out_modified(8),
R => clear_int
);
\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(9),
Q => probe_out_modified(9),
R => clear_int
);
rd_en_p1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_rd
);
rd_en_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_rd,
Q => rd_en_p1,
R => s_rst_o
);
rd_en_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => rd_en_p1,
Q => rd_en_p2,
R => s_rst_o
);
\wr_en[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => xsdb_wr,
I1 => s_daddr_o(2),
I2 => \^wr_en_reg[4]_0\,
I3 => \^wr_en_reg[4]_2\,
I4 => \^wr_en_reg[4]_1\,
I5 => \wr_en[2]_i_2_n_0\,
O => \wr_en[2]_i_1_n_0\
);
\wr_en[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[2]_i_2_n_0\
);
\wr_en[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => xsdb_wr,
I1 => \^wr_en_reg[4]_0\,
I2 => \^wr_en_reg[4]_2\,
I3 => \^wr_en_reg[4]_1\,
I4 => s_daddr_o(2),
I5 => \wr_en[4]_i_6_n_0\,
O => \wr_en[4]_i_1_n_0\
);
\wr_en[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_wr
);
\wr_en[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_daddr_o(15),
I1 => s_daddr_o(16),
I2 => s_daddr_o(13),
I3 => s_daddr_o(14),
I4 => s_daddr_o(4),
I5 => s_daddr_o(3),
O => \^wr_en_reg[4]_0\
);
\wr_en[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(6),
I1 => s_daddr_o(5),
I2 => s_daddr_o(8),
I3 => s_daddr_o(7),
O => \^wr_en_reg[4]_2\
);
\wr_en[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(10),
I1 => s_daddr_o(9),
I2 => s_daddr_o(12),
I3 => s_daddr_o(11),
O => \^wr_en_reg[4]_1\
);
\wr_en[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[4]_i_6_n_0\
);
\wr_en_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[2]_i_1_n_0\,
Q => wr_control_reg,
R => '0'
);
\wr_en_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[4]_i_1_n_0\,
Q => wr_probe_out_modified,
R => '0'
);
\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(0),
Q => xsdb_addr_2_0_p1(0),
R => '0'
);
\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(1),
Q => xsdb_addr_2_0_p1(1),
R => '0'
);
\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(2),
Q => xsdb_addr_2_0_p1(2),
R => '0'
);
\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(0),
Q => xsdb_addr_2_0_p2(0),
R => '0'
);
\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(1),
Q => xsdb_addr_2_0_p2(1),
R => '0'
);
\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(2),
Q => xsdb_addr_2_0_p2(2),
R => '0'
);
xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(8),
Q => xsdb_addr_8_p1,
R => '0'
);
xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_8_p1,
Q => xsdb_addr_8_p2,
R => '0'
);
xsdb_drdy_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => rd_en_p2,
O => xsdb_drdy_i_1_n_0
);
xsdb_drdy_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_drdy_i_1_n_0,
Q => s_drdy_i,
R => s_rst_o
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC;
\wr_en[4]_i_3\ : in STD_LOGIC;
\wr_en[4]_i_4\ : in STD_LOGIC;
\wr_en[4]_i_5\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
s_rst_o : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC;
signal Read_int : STD_LOGIC;
signal Read_int_i_2_n_0 : STD_LOGIC;
signal data_int_sync1 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of data_int_sync1 : signal is "true";
signal data_int_sync2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg of data_int_sync2 : signal is "true";
signal \dn_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[3]\ : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal probe_in_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true;
signal read_done : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of read_done : signal is "200";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of read_done : signal is "found";
signal read_done_i_1_n_0 : STD_LOGIC;
signal \up_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \up_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[1]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[2]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[3]\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes";
attribute RTL_MAX_FANOUT of read_done_reg : label is "found";
begin
\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(0),
Q => Q(0),
R => '0'
);
\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_in,
Q => Q(10),
R => '0'
);
\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[3]\,
Q => Q(11),
R => '0'
);
\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(1),
Q => Q(1),
R => '0'
);
\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(2),
Q => Q(2),
R => '0'
);
\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(3),
Q => Q(3),
R => '0'
);
\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[0]\,
Q => Q(4),
R => '0'
);
\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[1]\,
Q => Q(5),
R => '0'
);
\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[2]\,
Q => Q(6),
R => '0'
);
\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[3]\,
Q => Q(7),
R => '0'
);
\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[0]\,
Q => Q(8),
R => '0'
);
\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_6_in,
Q => Q(9),
R => '0'
);
Read_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => Read_int_i_2_n_0,
I1 => \wr_en[4]_i_3\,
I2 => \wr_en[4]_i_4\,
I3 => \wr_en[4]_i_5\,
O => \DECODER_INST/rd_en_int_7\
);
Read_int_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
I2 => s_daddr_o(2),
I3 => s_dwe_o,
I4 => s_den_o,
O => Read_int_i_2_n_0
);
Read_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \DECODER_INST/rd_en_int_7\,
Q => Read_int,
R => '0'
);
\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(0),
Q => data_int_sync1(0),
R => '0'
);
\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(1),
Q => data_int_sync1(1),
R => '0'
);
\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(2),
Q => data_int_sync1(2),
R => '0'
);
\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(3),
Q => data_int_sync1(3),
R => '0'
);
\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(0),
Q => data_int_sync2(0),
R => '0'
);
\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(1),
Q => data_int_sync2(1),
R => '0'
);
\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(2),
Q => data_int_sync2(2),
R => '0'
);
\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(3),
Q => data_int_sync2(3),
R => '0'
);
\dn_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[0]\,
I1 => data_int_sync1(0),
I2 => data_int_sync2(0),
O => \dn_activity[0]_i_1_n_0\
);
\dn_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_6_in,
I1 => data_int_sync1(1),
I2 => data_int_sync2(1),
O => \dn_activity[1]_i_1_n_0\
);
\dn_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_9_in,
I1 => data_int_sync1(2),
I2 => data_int_sync2(2),
O => \dn_activity[2]_i_1_n_0\
);
\dn_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[3]\,
I1 => data_int_sync1(3),
I2 => data_int_sync2(3),
O => \dn_activity[3]_i_1_n_0\
);
\dn_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[0]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[0]\,
R => read_done
);
\dn_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[1]_i_1_n_0\,
Q => p_6_in,
R => read_done
);
\dn_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[2]_i_1_n_0\,
Q => p_9_in,
R => read_done
);
\dn_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[3]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[3]\,
R => read_done
);
\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(0),
Q => probe_in_reg(0),
R => '0'
);
\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(1),
Q => probe_in_reg(1),
R => '0'
);
\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(2),
Q => probe_in_reg(2),
R => '0'
);
\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(3),
Q => probe_in_reg(3),
R => '0'
);
read_done_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Read_int,
I1 => read_done,
I2 => s_rst_o,
O => read_done_i_1_n_0
);
read_done_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => read_done_i_1_n_0,
Q => read_done,
R => '0'
);
\up_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[0]\,
I1 => data_int_sync2(0),
I2 => data_int_sync1(0),
O => \up_activity[0]_i_1_n_0\
);
\up_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[1]\,
I1 => data_int_sync2(1),
I2 => data_int_sync1(1),
O => \up_activity[1]_i_1_n_0\
);
\up_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[2]\,
I1 => data_int_sync2(2),
I2 => data_int_sync1(2),
O => \up_activity[2]_i_1_n_0\
);
\up_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[3]\,
I1 => data_int_sync2(3),
I2 => data_int_sync1(3),
O => \up_activity[3]_i_1_n_0\
);
\up_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[0]_i_1_n_0\,
Q => \up_activity_reg_n_0_[0]\,
R => read_done
);
\up_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[1]_i_1_n_0\,
Q => \up_activity_reg_n_0_[1]\,
R => read_done
);
\up_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[2]_i_1_n_0\,
Q => \up_activity_reg_n_0_[2]\,
R => read_done
);
\up_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[3]_i_1_n_0\,
Q => \up_activity_reg_n_0_[3]\,
R => read_done
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
port (
s_rst_o : out STD_LOGIC;
s_dclk_o : out STD_LOGIC;
s_den_o : out STD_LOGIC;
s_dwe_o : out STD_LOGIC;
s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
s_drdy_i : in STD_LOGIC
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2013;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "kintex7";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
signal reg_do : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \reg_do[10]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[15]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[2]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[3]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[6]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[7]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[9]_i_1_n_0\ : STD_LOGIC;
signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
signal reg_drdy : STD_LOGIC;
signal reg_drdy_i_1_n_0 : STD_LOGIC;
signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
signal reg_test0 : STD_LOGIC;
signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \reg_do[10]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \reg_do[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair8";
begin
\^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4);
s_dclk_o <= \^sl_iport_i\(1);
s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21);
s_dwe_o <= \^sl_iport_i\(3);
s_rst_o <= \^sl_iport_i\(0);
\reg_do[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAFFFFAAAAAAAA"
)
port map (
I0 => \reg_do[5]_i_2_n_0\,
I1 => \^sl_iport_i\(4),
I2 => reg_test(0),
I3 => \^sl_iport_i\(6),
I4 => \^sl_iport_i\(5),
I5 => \^sl_iport_i\(8),
O => reg_do(0)
);
\reg_do[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \reg_do[8]_i_2_n_0\,
I2 => \^sl_iport_i\(4),
O => \reg_do[10]_i_1_n_0\
);
\reg_do[10]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(10),
O => \reg_do[10]_i_2_n_0\
);
\reg_do[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
O => \reg_do[15]_i_1_n_0\
);
\reg_do[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20220000"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \^sl_iport_i\(4),
I2 => reg_test(1),
I3 => \^sl_iport_i\(6),
I4 => \reg_do[1]_i_2_n_0\,
O => reg_do(1)
);
\reg_do[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \^sl_iport_i\(8),
I1 => \^sl_iport_i\(10),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(7),
I4 => \^sl_iport_i\(9),
O => \reg_do[1]_i_2_n_0\
);
\reg_do[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(2),
O => \reg_do[2]_i_1_n_0\
);
\reg_do[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(3),
O => \reg_do[3]_i_1_n_0\
);
\reg_do[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(4),
O => \reg_do[4]_i_1_n_0\
);
\reg_do[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800044"
)
port map (
I0 => \^sl_iport_i\(6),
I1 => \^sl_iport_i\(8),
I2 => reg_test(5),
I3 => \^sl_iport_i\(4),
I4 => \^sl_iport_i\(5),
I5 => \reg_do[5]_i_2_n_0\,
O => reg_do(5)
);
\reg_do[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFFFFC"
)
port map (
I0 => \^sl_iport_i\(7),
I1 => \^sl_iport_i\(8),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(9),
O => \reg_do[5]_i_2_n_0\
);
\reg_do[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(6),
O => \reg_do[6]_i_1_n_0\
);
\reg_do[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(7),
O => \reg_do[7]_i_1_n_0\
);
\reg_do[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F00"
)
port map (
I0 => reg_test(8),
I1 => \^sl_iport_i\(4),
I2 => \^sl_iport_i\(5),
I3 => \reg_do[8]_i_2_n_0\,
O => reg_do(8)
);
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \^sl_iport_i\(9),
I1 => \^sl_iport_i\(7),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(8),
I5 => \^sl_iport_i\(6),
O => \reg_do[8]_i_2_n_0\
);
\reg_do[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C008000"
)
port map (
I0 => reg_test(9),
I1 => \reg_do[1]_i_2_n_0\,
I2 => \^sl_iport_i\(6),
I3 => \^sl_iport_i\(5),
I4 => \^sl_iport_i\(4),
O => \reg_do[9]_i_1_n_0\
);
\reg_do_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(0),
Q => \reg_do_reg_n_0_[0]\,
R => '0'
);
\reg_do_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[10]_i_2_n_0\,
Q => \reg_do_reg_n_0_[10]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(11),
Q => \reg_do_reg_n_0_[11]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(12),
Q => \reg_do_reg_n_0_[12]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(13),
Q => \reg_do_reg_n_0_[13]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(14),
Q => \reg_do_reg_n_0_[14]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(15),
Q => \reg_do_reg_n_0_[15]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(1),
Q => \reg_do_reg_n_0_[1]\,
R => '0'
);
\reg_do_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[2]_i_1_n_0\,
Q => \reg_do_reg_n_0_[2]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[3]_i_1_n_0\,
Q => \reg_do_reg_n_0_[3]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[4]_i_1_n_0\,
Q => \reg_do_reg_n_0_[4]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(5),
Q => \reg_do_reg_n_0_[5]\,
R => '0'
);
\reg_do_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[6]_i_1_n_0\,
Q => \reg_do_reg_n_0_[6]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[7]_i_1_n_0\,
Q => \reg_do_reg_n_0_[7]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(8),
Q => \reg_do_reg_n_0_[8]\,
R => '0'
);
\reg_do_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[9]_i_1_n_0\,
Q => \reg_do_reg_n_0_[9]\,
S => \reg_do[10]_i_1_n_0\
);
reg_drdy_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => s_den_o_INST_0_i_1_n_0,
I2 => \^sl_iport_i\(12),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(14),
I5 => \^sl_iport_i\(0),
O => reg_drdy_i_1_n_0
);
reg_drdy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_drdy_i_1_n_0,
Q => reg_drdy,
R => '0'
);
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(3),
I1 => \^sl_iport_i\(2),
I2 => \^sl_iport_i\(14),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(12),
I5 => s_den_o_INST_0_i_1_n_0,
O => reg_test0
);
\reg_test_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(21),
Q => reg_test(0),
R => '0'
);
\reg_test_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(31),
Q => reg_test(10),
R => '0'
);
\reg_test_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(32),
Q => reg_test(11),
R => '0'
);
\reg_test_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(33),
Q => reg_test(12),
R => '0'
);
\reg_test_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(34),
Q => reg_test(13),
R => '0'
);
\reg_test_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(35),
Q => reg_test(14),
R => '0'
);
\reg_test_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(36),
Q => reg_test(15),
R => '0'
);
\reg_test_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(22),
Q => reg_test(1),
R => '0'
);
\reg_test_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(23),
Q => reg_test(2),
R => '0'
);
\reg_test_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(24),
Q => reg_test(3),
R => '0'
);
\reg_test_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(25),
Q => reg_test(4),
R => '0'
);
\reg_test_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(26),
Q => reg_test(5),
R => '0'
);
\reg_test_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(27),
Q => reg_test(6),
R => '0'
);
\reg_test_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(28),
Q => reg_test(7),
R => '0'
);
\reg_test_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(29),
Q => reg_test(8),
R => '0'
);
\reg_test_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(30),
Q => reg_test(9),
R => '0'
);
s_den_o_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAAAAAA"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => \^sl_iport_i\(14),
I2 => \^sl_iport_i\(13),
I3 => \^sl_iport_i\(12),
I4 => s_den_o_INST_0_i_1_n_0,
O => s_den_o
);
s_den_o_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(15),
I1 => \^sl_iport_i\(16),
I2 => \^sl_iport_i\(17),
I3 => \^sl_iport_i\(18),
I4 => \^sl_iport_i\(20),
I5 => \^sl_iport_i\(19),
O => s_den_o_INST_0_i_1_n_0
);
\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_drdy_i,
I1 => reg_drdy,
O => sl_oport_o(0)
);
\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[9]\,
I1 => s_do_i(9),
I2 => reg_drdy,
O => sl_oport_o(10)
);
\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[10]\,
I1 => s_do_i(10),
I2 => reg_drdy,
O => sl_oport_o(11)
);
\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[11]\,
I1 => s_do_i(11),
I2 => reg_drdy,
O => sl_oport_o(12)
);
\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[12]\,
I1 => s_do_i(12),
I2 => reg_drdy,
O => sl_oport_o(13)
);
\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[13]\,
I1 => s_do_i(13),
I2 => reg_drdy,
O => sl_oport_o(14)
);
\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[14]\,
I1 => s_do_i(14),
I2 => reg_drdy,
O => sl_oport_o(15)
);
\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[15]\,
I1 => s_do_i(15),
I2 => reg_drdy,
O => sl_oport_o(16)
);
\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[0]\,
I1 => s_do_i(0),
I2 => reg_drdy,
O => sl_oport_o(1)
);
\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[1]\,
I1 => s_do_i(1),
I2 => reg_drdy,
O => sl_oport_o(2)
);
\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[2]\,
I1 => s_do_i(2),
I2 => reg_drdy,
O => sl_oport_o(3)
);
\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[3]\,
I1 => s_do_i(3),
I2 => reg_drdy,
O => sl_oport_o(4)
);
\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[4]\,
I1 => s_do_i(4),
I2 => reg_drdy,
O => sl_oport_o(5)
);
\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[5]\,
I1 => s_do_i(5),
I2 => reg_drdy,
O => sl_oport_o(6)
);
\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[6]\,
I1 => s_do_i(6),
I2 => reg_drdy,
O => sl_oport_o(7)
);
\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[7]\,
I1 => s_do_i(7),
I2 => reg_drdy,
O => sl_oport_o(8)
);
\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[8]\,
I1 => s_do_i(8),
I2 => reg_drdy,
O => sl_oport_o(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 );
sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 33;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
signal \<const0>\ : STD_LOGIC;
signal Bus_Data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal DECODER_INST_n_1 : STD_LOGIC;
signal DECODER_INST_n_2 : STD_LOGIC;
signal DECODER_INST_n_3 : STD_LOGIC;
signal DECODER_INST_n_4 : STD_LOGIC;
signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
signal bus_clk : STD_LOGIC;
attribute DONT_TOUCH_boolean : boolean;
attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true;
signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC;
signal bus_den : STD_LOGIC;
signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_drdy : STD_LOGIC;
signal bus_dwe : STD_LOGIC;
signal bus_rst : STD_LOGIC;
signal p_0_in : STD_LOGIC;
attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2;
attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0;
attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2;
attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1;
attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013;
attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1;
attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0;
attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7";
attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33;
attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true;
begin
probe_out0(0) <= \<const0>\;
probe_out1(0) <= \<const0>\;
probe_out10(0) <= \<const0>\;
probe_out100(0) <= \<const0>\;
probe_out101(0) <= \<const0>\;
probe_out102(0) <= \<const0>\;
probe_out103(0) <= \<const0>\;
probe_out104(0) <= \<const0>\;
probe_out105(0) <= \<const0>\;
probe_out106(0) <= \<const0>\;
probe_out107(0) <= \<const0>\;
probe_out108(0) <= \<const0>\;
probe_out109(0) <= \<const0>\;
probe_out11(0) <= \<const0>\;
probe_out110(0) <= \<const0>\;
probe_out111(0) <= \<const0>\;
probe_out112(0) <= \<const0>\;
probe_out113(0) <= \<const0>\;
probe_out114(0) <= \<const0>\;
probe_out115(0) <= \<const0>\;
probe_out116(0) <= \<const0>\;
probe_out117(0) <= \<const0>\;
probe_out118(0) <= \<const0>\;
probe_out119(0) <= \<const0>\;
probe_out12(0) <= \<const0>\;
probe_out120(0) <= \<const0>\;
probe_out121(0) <= \<const0>\;
probe_out122(0) <= \<const0>\;
probe_out123(0) <= \<const0>\;
probe_out124(0) <= \<const0>\;
probe_out125(0) <= \<const0>\;
probe_out126(0) <= \<const0>\;
probe_out127(0) <= \<const0>\;
probe_out128(0) <= \<const0>\;
probe_out129(0) <= \<const0>\;
probe_out13(0) <= \<const0>\;
probe_out130(0) <= \<const0>\;
probe_out131(0) <= \<const0>\;
probe_out132(0) <= \<const0>\;
probe_out133(0) <= \<const0>\;
probe_out134(0) <= \<const0>\;
probe_out135(0) <= \<const0>\;
probe_out136(0) <= \<const0>\;
probe_out137(0) <= \<const0>\;
probe_out138(0) <= \<const0>\;
probe_out139(0) <= \<const0>\;
probe_out14(0) <= \<const0>\;
probe_out140(0) <= \<const0>\;
probe_out141(0) <= \<const0>\;
probe_out142(0) <= \<const0>\;
probe_out143(0) <= \<const0>\;
probe_out144(0) <= \<const0>\;
probe_out145(0) <= \<const0>\;
probe_out146(0) <= \<const0>\;
probe_out147(0) <= \<const0>\;
probe_out148(0) <= \<const0>\;
probe_out149(0) <= \<const0>\;
probe_out15(0) <= \<const0>\;
probe_out150(0) <= \<const0>\;
probe_out151(0) <= \<const0>\;
probe_out152(0) <= \<const0>\;
probe_out153(0) <= \<const0>\;
probe_out154(0) <= \<const0>\;
probe_out155(0) <= \<const0>\;
probe_out156(0) <= \<const0>\;
probe_out157(0) <= \<const0>\;
probe_out158(0) <= \<const0>\;
probe_out159(0) <= \<const0>\;
probe_out16(0) <= \<const0>\;
probe_out160(0) <= \<const0>\;
probe_out161(0) <= \<const0>\;
probe_out162(0) <= \<const0>\;
probe_out163(0) <= \<const0>\;
probe_out164(0) <= \<const0>\;
probe_out165(0) <= \<const0>\;
probe_out166(0) <= \<const0>\;
probe_out167(0) <= \<const0>\;
probe_out168(0) <= \<const0>\;
probe_out169(0) <= \<const0>\;
probe_out17(0) <= \<const0>\;
probe_out170(0) <= \<const0>\;
probe_out171(0) <= \<const0>\;
probe_out172(0) <= \<const0>\;
probe_out173(0) <= \<const0>\;
probe_out174(0) <= \<const0>\;
probe_out175(0) <= \<const0>\;
probe_out176(0) <= \<const0>\;
probe_out177(0) <= \<const0>\;
probe_out178(0) <= \<const0>\;
probe_out179(0) <= \<const0>\;
probe_out18(0) <= \<const0>\;
probe_out180(0) <= \<const0>\;
probe_out181(0) <= \<const0>\;
probe_out182(0) <= \<const0>\;
probe_out183(0) <= \<const0>\;
probe_out184(0) <= \<const0>\;
probe_out185(0) <= \<const0>\;
probe_out186(0) <= \<const0>\;
probe_out187(0) <= \<const0>\;
probe_out188(0) <= \<const0>\;
probe_out189(0) <= \<const0>\;
probe_out19(0) <= \<const0>\;
probe_out190(0) <= \<const0>\;
probe_out191(0) <= \<const0>\;
probe_out192(0) <= \<const0>\;
probe_out193(0) <= \<const0>\;
probe_out194(0) <= \<const0>\;
probe_out195(0) <= \<const0>\;
probe_out196(0) <= \<const0>\;
probe_out197(0) <= \<const0>\;
probe_out198(0) <= \<const0>\;
probe_out199(0) <= \<const0>\;
probe_out2(0) <= \<const0>\;
probe_out20(0) <= \<const0>\;
probe_out200(0) <= \<const0>\;
probe_out201(0) <= \<const0>\;
probe_out202(0) <= \<const0>\;
probe_out203(0) <= \<const0>\;
probe_out204(0) <= \<const0>\;
probe_out205(0) <= \<const0>\;
probe_out206(0) <= \<const0>\;
probe_out207(0) <= \<const0>\;
probe_out208(0) <= \<const0>\;
probe_out209(0) <= \<const0>\;
probe_out21(0) <= \<const0>\;
probe_out210(0) <= \<const0>\;
probe_out211(0) <= \<const0>\;
probe_out212(0) <= \<const0>\;
probe_out213(0) <= \<const0>\;
probe_out214(0) <= \<const0>\;
probe_out215(0) <= \<const0>\;
probe_out216(0) <= \<const0>\;
probe_out217(0) <= \<const0>\;
probe_out218(0) <= \<const0>\;
probe_out219(0) <= \<const0>\;
probe_out22(0) <= \<const0>\;
probe_out220(0) <= \<const0>\;
probe_out221(0) <= \<const0>\;
probe_out222(0) <= \<const0>\;
probe_out223(0) <= \<const0>\;
probe_out224(0) <= \<const0>\;
probe_out225(0) <= \<const0>\;
probe_out226(0) <= \<const0>\;
probe_out227(0) <= \<const0>\;
probe_out228(0) <= \<const0>\;
probe_out229(0) <= \<const0>\;
probe_out23(0) <= \<const0>\;
probe_out230(0) <= \<const0>\;
probe_out231(0) <= \<const0>\;
probe_out232(0) <= \<const0>\;
probe_out233(0) <= \<const0>\;
probe_out234(0) <= \<const0>\;
probe_out235(0) <= \<const0>\;
probe_out236(0) <= \<const0>\;
probe_out237(0) <= \<const0>\;
probe_out238(0) <= \<const0>\;
probe_out239(0) <= \<const0>\;
probe_out24(0) <= \<const0>\;
probe_out240(0) <= \<const0>\;
probe_out241(0) <= \<const0>\;
probe_out242(0) <= \<const0>\;
probe_out243(0) <= \<const0>\;
probe_out244(0) <= \<const0>\;
probe_out245(0) <= \<const0>\;
probe_out246(0) <= \<const0>\;
probe_out247(0) <= \<const0>\;
probe_out248(0) <= \<const0>\;
probe_out249(0) <= \<const0>\;
probe_out25(0) <= \<const0>\;
probe_out250(0) <= \<const0>\;
probe_out251(0) <= \<const0>\;
probe_out252(0) <= \<const0>\;
probe_out253(0) <= \<const0>\;
probe_out254(0) <= \<const0>\;
probe_out255(0) <= \<const0>\;
probe_out26(0) <= \<const0>\;
probe_out27(0) <= \<const0>\;
probe_out28(0) <= \<const0>\;
probe_out29(0) <= \<const0>\;
probe_out3(0) <= \<const0>\;
probe_out30(0) <= \<const0>\;
probe_out31(0) <= \<const0>\;
probe_out32(0) <= \<const0>\;
probe_out33(0) <= \<const0>\;
probe_out34(0) <= \<const0>\;
probe_out35(0) <= \<const0>\;
probe_out36(0) <= \<const0>\;
probe_out37(0) <= \<const0>\;
probe_out38(0) <= \<const0>\;
probe_out39(0) <= \<const0>\;
probe_out4(0) <= \<const0>\;
probe_out40(0) <= \<const0>\;
probe_out41(0) <= \<const0>\;
probe_out42(0) <= \<const0>\;
probe_out43(0) <= \<const0>\;
probe_out44(0) <= \<const0>\;
probe_out45(0) <= \<const0>\;
probe_out46(0) <= \<const0>\;
probe_out47(0) <= \<const0>\;
probe_out48(0) <= \<const0>\;
probe_out49(0) <= \<const0>\;
probe_out5(0) <= \<const0>\;
probe_out50(0) <= \<const0>\;
probe_out51(0) <= \<const0>\;
probe_out52(0) <= \<const0>\;
probe_out53(0) <= \<const0>\;
probe_out54(0) <= \<const0>\;
probe_out55(0) <= \<const0>\;
probe_out56(0) <= \<const0>\;
probe_out57(0) <= \<const0>\;
probe_out58(0) <= \<const0>\;
probe_out59(0) <= \<const0>\;
probe_out6(0) <= \<const0>\;
probe_out60(0) <= \<const0>\;
probe_out61(0) <= \<const0>\;
probe_out62(0) <= \<const0>\;
probe_out63(0) <= \<const0>\;
probe_out64(0) <= \<const0>\;
probe_out65(0) <= \<const0>\;
probe_out66(0) <= \<const0>\;
probe_out67(0) <= \<const0>\;
probe_out68(0) <= \<const0>\;
probe_out69(0) <= \<const0>\;
probe_out7(0) <= \<const0>\;
probe_out70(0) <= \<const0>\;
probe_out71(0) <= \<const0>\;
probe_out72(0) <= \<const0>\;
probe_out73(0) <= \<const0>\;
probe_out74(0) <= \<const0>\;
probe_out75(0) <= \<const0>\;
probe_out76(0) <= \<const0>\;
probe_out77(0) <= \<const0>\;
probe_out78(0) <= \<const0>\;
probe_out79(0) <= \<const0>\;
probe_out8(0) <= \<const0>\;
probe_out80(0) <= \<const0>\;
probe_out81(0) <= \<const0>\;
probe_out82(0) <= \<const0>\;
probe_out83(0) <= \<const0>\;
probe_out84(0) <= \<const0>\;
probe_out85(0) <= \<const0>\;
probe_out86(0) <= \<const0>\;
probe_out87(0) <= \<const0>\;
probe_out88(0) <= \<const0>\;
probe_out89(0) <= \<const0>\;
probe_out9(0) <= \<const0>\;
probe_out90(0) <= \<const0>\;
probe_out91(0) <= \<const0>\;
probe_out92(0) <= \<const0>\;
probe_out93(0) <= \<const0>\;
probe_out94(0) <= \<const0>\;
probe_out95(0) <= \<const0>\;
probe_out96(0) <= \<const0>\;
probe_out97(0) <= \<const0>\;
probe_out98(0) <= \<const0>\;
probe_out99(0) <= \<const0>\;
DECODER_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
port map (
\Bus_Data_out_reg[11]\(11 downto 0) => Bus_Data_out(11 downto 0),
E(0) => DECODER_INST_n_4,
Q(15) => \bus_data_int_reg_n_0_[15]\,
Q(14) => \bus_data_int_reg_n_0_[14]\,
Q(13) => \bus_data_int_reg_n_0_[13]\,
Q(12) => \bus_data_int_reg_n_0_[12]\,
Q(11) => \bus_data_int_reg_n_0_[11]\,
Q(10) => \bus_data_int_reg_n_0_[10]\,
Q(9) => \bus_data_int_reg_n_0_[9]\,
Q(8) => \bus_data_int_reg_n_0_[8]\,
Q(7) => \bus_data_int_reg_n_0_[7]\,
Q(6) => \bus_data_int_reg_n_0_[6]\,
Q(5) => \bus_data_int_reg_n_0_[5]\,
Q(4) => \bus_data_int_reg_n_0_[4]\,
Q(3) => \bus_data_int_reg_n_0_[3]\,
Q(2) => \bus_data_int_reg_n_0_[2]\,
Q(1) => p_0_in,
Q(0) => \bus_data_int_reg_n_0_[0]\,
\out\ => bus_clk,
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_den_o => bus_den,
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en_reg[4]_0\ => DECODER_INST_n_1,
\wr_en_reg[4]_1\ => DECODER_INST_n_2,
\wr_en_reg[4]_2\ => DECODER_INST_n_3
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
PROBE_IN_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
port map (
D(3) => probe_in3(0),
D(2) => probe_in2(0),
D(1) => probe_in1(0),
D(0) => probe_in0(0),
E(0) => DECODER_INST_n_4,
Q(11 downto 0) => Bus_Data_out(11 downto 0),
clk => clk,
\out\ => bus_clk,
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en[4]_i_3\ => DECODER_INST_n_1,
\wr_en[4]_i_4\ => DECODER_INST_n_3,
\wr_en[4]_i_5\ => DECODER_INST_n_2
);
U_XSDB_SLAVE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
port map (
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_dclk_o => bus_clk,
s_den_o => bus_den,
s_di_o(15 downto 0) => bus_di(15 downto 0),
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
sl_iport_i(36 downto 0) => sl_iport0(36 downto 0),
sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
);
\bus_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(0),
Q => \bus_data_int_reg_n_0_[0]\,
R => '0'
);
\bus_data_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(10),
Q => \bus_data_int_reg_n_0_[10]\,
R => '0'
);
\bus_data_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(11),
Q => \bus_data_int_reg_n_0_[11]\,
R => '0'
);
\bus_data_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(12),
Q => \bus_data_int_reg_n_0_[12]\,
R => '0'
);
\bus_data_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(13),
Q => \bus_data_int_reg_n_0_[13]\,
R => '0'
);
\bus_data_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(14),
Q => \bus_data_int_reg_n_0_[14]\,
R => '0'
);
\bus_data_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(15),
Q => \bus_data_int_reg_n_0_[15]\,
R => '0'
);
\bus_data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(1),
Q => p_0_in,
R => '0'
);
\bus_data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(2),
Q => \bus_data_int_reg_n_0_[2]\,
R => '0'
);
\bus_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(3),
Q => \bus_data_int_reg_n_0_[3]\,
R => '0'
);
\bus_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(4),
Q => \bus_data_int_reg_n_0_[4]\,
R => '0'
);
\bus_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(5),
Q => \bus_data_int_reg_n_0_[5]\,
R => '0'
);
\bus_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(6),
Q => \bus_data_int_reg_n_0_[6]\,
R => '0'
);
\bus_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(7),
Q => \bus_data_int_reg_n_0_[7]\,
R => '0'
);
\bus_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(8),
Q => \bus_data_int_reg_n_0_[8]\,
R => '0'
);
\bus_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(9),
Q => \bus_data_int_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio_0,vio,{}";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_probe_out0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of inst : label is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of inst : label is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of inst : label is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of inst : label is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of inst : label is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of inst : label is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of inst : label is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of inst : label is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of inst : label is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of inst : label is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of inst : label is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of inst : label is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of inst : label is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of inst : label is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of inst : label is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of inst : label is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of inst : label is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of inst : label is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of inst : label is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of inst : label is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of inst : label is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of inst : label is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of inst : label is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of inst : label is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of inst : label is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of inst : label is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of inst : label is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of inst : label is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of inst : label is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of inst : label is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of inst : label is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of inst : label is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of inst : label is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of inst : label is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of inst : label is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of inst : label is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of inst : label is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of inst : label is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of inst : label is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of inst : label is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of inst : label is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of inst : label is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of inst : label is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of inst : label is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of inst : label is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of inst : label is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of inst : label is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of inst : label is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of inst : label is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of inst : label is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of inst : label is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of inst : label is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of inst : label is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of inst : label is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of inst : label is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of inst : label is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of inst : label is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of inst : label is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of inst : label is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of inst : label is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of inst : label is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of inst : label is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of inst : label is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of inst : label is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of inst : label is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of inst : label is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of inst : label is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of inst : label is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of inst : label is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of inst : label is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of inst : label is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of inst : label is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of inst : label is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of inst : label is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of inst : label is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of inst : label is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of inst : label is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of inst : label is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of inst : label is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of inst : label is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of inst : label is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of inst : label is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of inst : label is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of inst : label is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of inst : label is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of inst : label is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of inst : label is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of inst : label is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of inst : label is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of inst : label is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of inst : label is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of inst : label is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of inst : label is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of inst : label is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of inst : label is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of inst : label is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of inst : label is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of inst : label is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of inst : label is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of inst : label is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of inst : label is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of inst : label is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of inst : label is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of inst : label is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of inst : label is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of inst : label is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of inst : label is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of inst : label is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of inst : label is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of inst : label is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of inst : label is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of inst : label is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of inst : label is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of inst : label is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of inst : label is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of inst : label is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of inst : label is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of inst : label is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of inst : label is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of inst : label is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of inst : label is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of inst : label is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of inst : label is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of inst : label is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of inst : label is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of inst : label is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of inst : label is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of inst : label is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of inst : label is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of inst : label is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of inst : label is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of inst : label is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of inst : label is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of inst : label is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of inst : label is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of inst : label is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of inst : label is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of inst : label is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of inst : label is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of inst : label is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of inst : label is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of inst : label is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of inst : label is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of inst : label is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of inst : label is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of inst : label is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of inst : label is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of inst : label is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of inst : label is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of inst : label is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of inst : label is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of inst : label is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of inst : label is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of inst : label is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of inst : label is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of inst : label is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of inst : label is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of inst : label is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of inst : label is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of inst : label is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of inst : label is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of inst : label is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of inst : label is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of inst : label is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of inst : label is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of inst : label is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of inst : label is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of inst : label is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of inst : label is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of inst : label is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of inst : label is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of inst : label is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of inst : label is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of inst : label is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of inst : label is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of inst : label is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of inst : label is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of inst : label is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of inst : label is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of inst : label is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of inst : label is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of inst : label is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of inst : label is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of inst : label is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of inst : label is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of inst : label is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of inst : label is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of inst : label is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of inst : label is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of inst : label is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of inst : label is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of inst : label is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of inst : label is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of inst : label is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of inst : label is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of inst : label is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of inst : label is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of inst : label is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of inst : label is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of inst : label is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of inst : label is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of inst : label is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of inst : label is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of inst : label is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of inst : label is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of inst : label is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of inst : label is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of inst : label is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of inst : label is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of inst : label is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of inst : label is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of inst : label is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of inst : label is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of inst : label is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of inst : label is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of inst : label is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of inst : label is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of inst : label is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of inst : label is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of inst : label is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of inst : label is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of inst : label is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of inst : label is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of inst : label is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of inst : label is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of inst : label is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of inst : label is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of inst : label is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of inst : label is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of inst : label is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of inst : label is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of inst : label is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of inst : label is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of inst : label is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of inst : label is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of inst : label is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of inst : label is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of inst : label is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of inst : label is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of inst : label is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of inst : label is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of inst : label is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of inst : label is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of inst : label is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of inst : label is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of inst : label is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of inst : label is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of inst : label is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of inst : label is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of inst : label is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of inst : label is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of inst : label is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of inst : label is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of inst : label is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of inst : label is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of inst : label is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of inst : label is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of inst : label is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of inst : label is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of inst : label is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of inst : label is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of inst : label is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of inst : label is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of inst : label is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of inst : label is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of inst : label is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of inst : label is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of inst : label is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of inst : label is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of inst : label is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of inst : label is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of inst : label is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of inst : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of inst : label is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of inst : label is std.standard.true;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 0;
attribute syn_noprune : string;
attribute syn_noprune of inst : label is "1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
port map (
clk => clk,
probe_in0(0) => probe_in0(0),
probe_in1(0) => probe_in1(0),
probe_in10(0) => '0',
probe_in100(0) => '0',
probe_in101(0) => '0',
probe_in102(0) => '0',
probe_in103(0) => '0',
probe_in104(0) => '0',
probe_in105(0) => '0',
probe_in106(0) => '0',
probe_in107(0) => '0',
probe_in108(0) => '0',
probe_in109(0) => '0',
probe_in11(0) => '0',
probe_in110(0) => '0',
probe_in111(0) => '0',
probe_in112(0) => '0',
probe_in113(0) => '0',
probe_in114(0) => '0',
probe_in115(0) => '0',
probe_in116(0) => '0',
probe_in117(0) => '0',
probe_in118(0) => '0',
probe_in119(0) => '0',
probe_in12(0) => '0',
probe_in120(0) => '0',
probe_in121(0) => '0',
probe_in122(0) => '0',
probe_in123(0) => '0',
probe_in124(0) => '0',
probe_in125(0) => '0',
probe_in126(0) => '0',
probe_in127(0) => '0',
probe_in128(0) => '0',
probe_in129(0) => '0',
probe_in13(0) => '0',
probe_in130(0) => '0',
probe_in131(0) => '0',
probe_in132(0) => '0',
probe_in133(0) => '0',
probe_in134(0) => '0',
probe_in135(0) => '0',
probe_in136(0) => '0',
probe_in137(0) => '0',
probe_in138(0) => '0',
probe_in139(0) => '0',
probe_in14(0) => '0',
probe_in140(0) => '0',
probe_in141(0) => '0',
probe_in142(0) => '0',
probe_in143(0) => '0',
probe_in144(0) => '0',
probe_in145(0) => '0',
probe_in146(0) => '0',
probe_in147(0) => '0',
probe_in148(0) => '0',
probe_in149(0) => '0',
probe_in15(0) => '0',
probe_in150(0) => '0',
probe_in151(0) => '0',
probe_in152(0) => '0',
probe_in153(0) => '0',
probe_in154(0) => '0',
probe_in155(0) => '0',
probe_in156(0) => '0',
probe_in157(0) => '0',
probe_in158(0) => '0',
probe_in159(0) => '0',
probe_in16(0) => '0',
probe_in160(0) => '0',
probe_in161(0) => '0',
probe_in162(0) => '0',
probe_in163(0) => '0',
probe_in164(0) => '0',
probe_in165(0) => '0',
probe_in166(0) => '0',
probe_in167(0) => '0',
probe_in168(0) => '0',
probe_in169(0) => '0',
probe_in17(0) => '0',
probe_in170(0) => '0',
probe_in171(0) => '0',
probe_in172(0) => '0',
probe_in173(0) => '0',
probe_in174(0) => '0',
probe_in175(0) => '0',
probe_in176(0) => '0',
probe_in177(0) => '0',
probe_in178(0) => '0',
probe_in179(0) => '0',
probe_in18(0) => '0',
probe_in180(0) => '0',
probe_in181(0) => '0',
probe_in182(0) => '0',
probe_in183(0) => '0',
probe_in184(0) => '0',
probe_in185(0) => '0',
probe_in186(0) => '0',
probe_in187(0) => '0',
probe_in188(0) => '0',
probe_in189(0) => '0',
probe_in19(0) => '0',
probe_in190(0) => '0',
probe_in191(0) => '0',
probe_in192(0) => '0',
probe_in193(0) => '0',
probe_in194(0) => '0',
probe_in195(0) => '0',
probe_in196(0) => '0',
probe_in197(0) => '0',
probe_in198(0) => '0',
probe_in199(0) => '0',
probe_in2(0) => probe_in2(0),
probe_in20(0) => '0',
probe_in200(0) => '0',
probe_in201(0) => '0',
probe_in202(0) => '0',
probe_in203(0) => '0',
probe_in204(0) => '0',
probe_in205(0) => '0',
probe_in206(0) => '0',
probe_in207(0) => '0',
probe_in208(0) => '0',
probe_in209(0) => '0',
probe_in21(0) => '0',
probe_in210(0) => '0',
probe_in211(0) => '0',
probe_in212(0) => '0',
probe_in213(0) => '0',
probe_in214(0) => '0',
probe_in215(0) => '0',
probe_in216(0) => '0',
probe_in217(0) => '0',
probe_in218(0) => '0',
probe_in219(0) => '0',
probe_in22(0) => '0',
probe_in220(0) => '0',
probe_in221(0) => '0',
probe_in222(0) => '0',
probe_in223(0) => '0',
probe_in224(0) => '0',
probe_in225(0) => '0',
probe_in226(0) => '0',
probe_in227(0) => '0',
probe_in228(0) => '0',
probe_in229(0) => '0',
probe_in23(0) => '0',
probe_in230(0) => '0',
probe_in231(0) => '0',
probe_in232(0) => '0',
probe_in233(0) => '0',
probe_in234(0) => '0',
probe_in235(0) => '0',
probe_in236(0) => '0',
probe_in237(0) => '0',
probe_in238(0) => '0',
probe_in239(0) => '0',
probe_in24(0) => '0',
probe_in240(0) => '0',
probe_in241(0) => '0',
probe_in242(0) => '0',
probe_in243(0) => '0',
probe_in244(0) => '0',
probe_in245(0) => '0',
probe_in246(0) => '0',
probe_in247(0) => '0',
probe_in248(0) => '0',
probe_in249(0) => '0',
probe_in25(0) => '0',
probe_in250(0) => '0',
probe_in251(0) => '0',
probe_in252(0) => '0',
probe_in253(0) => '0',
probe_in254(0) => '0',
probe_in255(0) => '0',
probe_in26(0) => '0',
probe_in27(0) => '0',
probe_in28(0) => '0',
probe_in29(0) => '0',
probe_in3(0) => probe_in3(0),
probe_in30(0) => '0',
probe_in31(0) => '0',
probe_in32(0) => '0',
probe_in33(0) => '0',
probe_in34(0) => '0',
probe_in35(0) => '0',
probe_in36(0) => '0',
probe_in37(0) => '0',
probe_in38(0) => '0',
probe_in39(0) => '0',
probe_in4(0) => '0',
probe_in40(0) => '0',
probe_in41(0) => '0',
probe_in42(0) => '0',
probe_in43(0) => '0',
probe_in44(0) => '0',
probe_in45(0) => '0',
probe_in46(0) => '0',
probe_in47(0) => '0',
probe_in48(0) => '0',
probe_in49(0) => '0',
probe_in5(0) => '0',
probe_in50(0) => '0',
probe_in51(0) => '0',
probe_in52(0) => '0',
probe_in53(0) => '0',
probe_in54(0) => '0',
probe_in55(0) => '0',
probe_in56(0) => '0',
probe_in57(0) => '0',
probe_in58(0) => '0',
probe_in59(0) => '0',
probe_in6(0) => '0',
probe_in60(0) => '0',
probe_in61(0) => '0',
probe_in62(0) => '0',
probe_in63(0) => '0',
probe_in64(0) => '0',
probe_in65(0) => '0',
probe_in66(0) => '0',
probe_in67(0) => '0',
probe_in68(0) => '0',
probe_in69(0) => '0',
probe_in7(0) => '0',
probe_in70(0) => '0',
probe_in71(0) => '0',
probe_in72(0) => '0',
probe_in73(0) => '0',
probe_in74(0) => '0',
probe_in75(0) => '0',
probe_in76(0) => '0',
probe_in77(0) => '0',
probe_in78(0) => '0',
probe_in79(0) => '0',
probe_in8(0) => '0',
probe_in80(0) => '0',
probe_in81(0) => '0',
probe_in82(0) => '0',
probe_in83(0) => '0',
probe_in84(0) => '0',
probe_in85(0) => '0',
probe_in86(0) => '0',
probe_in87(0) => '0',
probe_in88(0) => '0',
probe_in89(0) => '0',
probe_in9(0) => '0',
probe_in90(0) => '0',
probe_in91(0) => '0',
probe_in92(0) => '0',
probe_in93(0) => '0',
probe_in94(0) => '0',
probe_in95(0) => '0',
probe_in96(0) => '0',
probe_in97(0) => '0',
probe_in98(0) => '0',
probe_in99(0) => '0',
probe_out0(0) => NLW_inst_probe_out0_UNCONNECTED(0),
probe_out1(0) => NLW_inst_probe_out1_UNCONNECTED(0),
probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0),
probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
);
end STRUCTURE;
|
mit
|
10a3be6b79c5b446b06b4e737ebec10b
| 0.709641 | 2.992574 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd
| 1 | 2,471 |
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-27 512 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
gpl-2.0
|
7d3d4bb26c3eb7bc45d9634b479587a6
| 0.651558 | 3.738275 | false | false | false | false |
freecores/w11
|
rtl/bplib/micron/mt45w8mw16b.vhd
| 2 | 9,403 |
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: mt45w8mw16b - sim
-- Description: Micron MT45W8MW16B CellularRAM model
-- Currently a much simplified model
-- - only async accesses
-- - ignores CLK and CRE
-- - simple model for response of DATA lines, but no
-- check for timing violations of control lines
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.3.2 now numeric_std clean
-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
-- 2010-06-03 298 1.3 add timing model again
-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
-- 2010-05-21 293 1.1 add BCR (only read of default so far)
-- 2010-05-16 291 1.0 Initial version (inspired by is61lv25616al)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Asynchronous Mode (BCR(15)=1)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Read L L L L H L L act data-out
-- Write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- CRE write L L L H L H X act 'z'
-- CRE read L L L L H H L act conf-out
--
-- Burst Mode (BCR(15)=0)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Async read L L L L H L L act data-out
-- Async write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- Initial burst read 0-1 L L X H L L act X
-- Initial burst write 0-1 L L H L L X act X
-- Burst continue 0-1 H L X X X X act data-in/out
-- CRE write 0-1 L L H L H X act 'z'
-- CRE read 0-1 L L L H H L act conf-out
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity mt45w8mw16b is -- Micron MT45W8MW16B CellularRAM model
port (
CLK : in slbit; -- clock for synchonous operation
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
UB_N : in slbit; -- upper byte enable (act.low)
LB_N : in slbit; -- lower byte enable (act.low)
ADV_N : in slbit; -- address valid (act.low)
CRE : in slbit; -- control register enable
MWAIT : out slbit; -- wait (for burst read/write)
ADDR : in slv23; -- address lines
DATA : inout slv16 -- data lines
);
end mt45w8mw16b;
architecture sim of mt45w8mw16b is
-- timing constants for -701 speed grade (70 ns; 104 MHz)
constant T_aa : time := 70 ns; -- address access time (max)
constant T_apa : time := 20 ns; -- page acess time (max)
constant T_oh : time := 5 ns; -- output hold from addr change (max)
constant T_oe : time := 20 ns; -- output enable to valid output (max)
constant T_ohz : time := 8 ns; -- output disable to high-z output (max)
constant T_olz : time := 3 ns; -- output enable to low-z output (min)
constant T_lz : time := 10 ns; -- chip enable to low-z output (min)
constant T_hz : time := 8 ns; -- chip disable to high-z output (max)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
constant bcr_f_mode : integer := 15; -- operating mode
constant bcr_f_ilat : integer := 14; -- initial latency
subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
constant bcr_f_wp : integer := 10; -- wait polarity
constant bcr_f_wc : integer := 8; -- wait configuration
subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
constant bcr_f_bw : integer := 3; -- burst wrap
subtype bcr_f_bl is integer range 2 downto 0; -- burst length
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal BE_L : slbit := '0';
signal BE_U : slbit := '0';
signal ADV : slbit := '0';
signal WE_L_EFF : slbit := '0';
signal WE_U_EFF : slbit := '0';
signal R_BCR_MODE : slbit := '1'; -- mode: def: async
signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3
signal R_BCR_WP : slbit := '1'; -- wp: def: active high
signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
signal L_ADDR : slv23 := (others=>'0');
signal DOUT_VAL_EN : slbit := '0';
signal DOUT_VAL_AA : slbit := '0';
signal DOUT_VAL_PA : slbit := '0';
signal DOUT_VAL_OE : slbit := '0';
signal DOUT_LZ_CE : slbit := '0';
signal DOUT_LZ_OE : slbit := '0';
signal OEWE : slbit := '0';
signal DOUT : slv16 := (others=>'0');
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
BE_L <= not LB_N;
BE_U <= not UB_N;
ADV <= not ADV_N;
WE_L_EFF <= CE and WE and BE_L;
WE_U_EFF <= CE and WE and BE_U;
-- address valid logic, latch ADDR when ADV true
proc_adv: process (ADV, ADDR)
begin
if ADV = '1' then
L_ADDR <= ADDR;
end if;
end process proc_adv;
proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR)
variable addr_last : slv23 := (others=>'1');
begin
if (CE'event and CE='1') or
(BE_L'event and BE_L='1') or
(BE_U'event and BE_U='1') or
(WE'event and WE='0') or
(ADV'event and ADV='1') then
DOUT_VAL_EN <= '0', '1' after T_aa;
end if;
if L_ADDR'event then
DOUT_VAL_PA <= '0', '1' after T_apa;
if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
DOUT_VAL_AA <= '0', '1' after T_aa;
end if;
addr_last := L_ADDR;
end if;
if rising_edge(OE) then
DOUT_VAL_OE <= '0', '1' after T_oe;
end if;
end process proc_dout_val;
-- to simplify things assume that OE and (not WE) have same effect on output
-- drivers. The timing rules are very similar indeed...
OEWE <= OE and (not WE);
proc_dout_lz: process (CE, OEWE)
begin
if (CE'event) then
if CE = '1' then
DOUT_LZ_CE <= '1' after T_lz;
else
DOUT_LZ_CE <= '0' after T_hz;
end if;
end if;
if (OEwe'event) then
if OEWE = '1' then
DOUT_LZ_OE <= '1' after T_olz;
else
DOUT_LZ_OE <= '0' after T_ohz;
end if;
end if;
end process proc_dout_lz;
proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
-- end of write cycle
-- note: to_x01 used below to prevent that 'z' a written into mem.
if falling_edge(WE_L_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
end if;
if falling_edge(WE_U_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
end if;
DOUT <= ram(to_integer(unsigned(L_ADDR)));
end process proc_cram;
proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
DOUT_LZ_CE, DOUT_LZ_OE)
variable idout : slv16 := (others=>'0');
begin
idout := DOUT;
if DOUT_VAL_EN='0' or DOUT_VAL_AA='0' or
DOUT_VAL_PA='0' or DOUT_VAL_OE='0' then
idout := (others=>'X');
end if;
if DOUT_LZ_CE='0' or DOUT_LZ_OE='0' then
idout := (others=>'Z');
end if;
DATA <= idout;
end process proc_data;
proc_mwait: process (CE)
begin
-- WT driver (just a dummy)
if CE = '1' then
MWAIT <= '1';
else
MWAIT <= 'Z';
end if;
end process proc_mwait;
end sim;
|
gpl-2.0
|
17fe23404a0ab5c8182fd711266eb459
| 0.53015 | 3.219103 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_uart_rx.vhd
| 2 | 11,298 |
-- $Id: serport_uart_rx.vhd 421 2011-11-07 21:23:50Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
-- The uart expects CLKDIV+1 wide input bit symbols.
-- This implementation counts the number of 1's in the first CLKDIV clock
-- cycles, and checks in the last cycle of the symbol time whether the
-- number of 1's was > CLKDIV/2. This supresses short glitches nicely,
-- especially for larger clock dividers.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rx - syn
-- Description: serial port UART - receiver
--
-- Dependencies: -
-- Test bench: tb/tb_serport_uart_rxtx
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 2.0.3 now numeric_std clean
-- 2009-07-12 233 2.0.2 remove snoopers
-- 2008-03-02 121 2.0.1 comment out snoopers
-- 2007-10-21 91 2.0 re-designed and -implemented with state machine.
-- allow CLKDIV=0 with 1 stop bit; allow max. CLKDIV
-- (all 1's); aborts bad start bit after 1/2 cell;
-- accepts stop bit after 1/2 cell, permits tx clock
-- be ~3 percent faster than rx clock.
-- for 3s1000ft256: 50 -> 58 slices for CDWIDTH=13
-- 2007-10-14 89 1.1 almost full rewrite, handles now CLKDIV=0 properly
-- for 3s1000ft256: 43 -> 50 slices for CDWIDTH=13
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_rx is -- serial port uart: receive part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end serport_uart_rx;
architecture syn of serport_uart_rx is
type state_type is (
s_idle, -- s_idle: idle
s_colb0, -- s_colb0: collect b0 (start bit)
s_endb0, -- s_endb0: finish b0 (start bit)
s_colbx, -- s_colbx: collect bx
s_endbx, -- s_endbx: finish bx
s_colb9, -- s_colb9: collect bx (stop bit)
s_endb9 -- s_endb9: finish bx (stop bit)
);
type regs_type is record
state : state_type; -- state
ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv(CDWIDTH downto 0); -- data '1' counter
bcnt : slv4; -- bit counter
sreg : slv8; -- input shift register
end record regs_type;
constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
ccntzero, -- ccnt
dcntzero, -- dcnt
(others=>'0'), -- bcnt
(others=>'0') -- sreg
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CLKDIV, RXSD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable dbit : slbit := '0';
variable ld_ccnt : slbit := '0';
variable tc_ccnt : slbit := '0';
variable tc_bcnt : slbit := '0';
variable ld_dcnt : slbit := '0';
variable ld_bcnt : slbit := '0';
variable ce_bcnt : slbit := '0';
variable iact : slbit := '0';
variable ival : slbit := '0';
variable ierr : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
dbit := '0';
ld_ccnt := '0';
tc_ccnt := '0';
tc_bcnt := '0';
ld_dcnt := '0';
ld_bcnt := '0';
ce_bcnt := '0';
iact := '1';
ival := '0';
ierr := '0';
if unsigned(r.ccnt) = 0 then
tc_ccnt := '1';
end if;
if unsigned(r.bcnt) = 9 then
tc_bcnt := '1';
end if;
if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then
dbit := '1';
end if;
case r.state is
when s_idle => -- s_idle: idle ----------------------
iact := '0';
ld_dcnt := '1'; -- always keep dcnt in reset
if RXSD = '0' then -- if start bit seen
if tc_ccnt = '1' then
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- start next bit
ce_bcnt := '1';
else
n.state := s_colb0; -- collect b0
end if;
else -- otherwise
ld_ccnt := '1'; -- keep all counters in reset
ld_bcnt := '1';
end if;
when s_colb0 => -- s_colb0: collect b0 (start bit) ---
if tc_ccnt = '1' then -- last cycle of b0 ?
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- "
ce_bcnt := '1';
else -- continue in b0 ?
if dbit='1' and RXSD='1' then -- too many 1's ?
n.state := s_idle; -- abort to idle
ld_dcnt := '1'; -- put counters in reset
ld_ccnt := '1';
ld_bcnt := '1';
end if;
end if;
when s_endb0 => -- s_endb0: finish b0 (start bit) ---
ld_dcnt := '1'; -- start next bit
if dbit = '1' then -- was it a 1 ?
n.state := s_idle; -- abort to idle
ld_ccnt := '1'; -- put counters in reset
ld_bcnt := '1';
else
if tc_ccnt = '1' then -- last cycle of bx ?
n.state := s_endbx; -- finish bx
ld_ccnt := '1';
ce_bcnt := '1';
else -- continue in b0 ?
n.state := s_colbx; -- collect bx
end if;
end if;
when s_colbx => -- s_colbx: collect bx ---------------
if tc_ccnt = '1' then -- last cycle of bx ?
n.state := s_endbx; -- finish bx
ld_ccnt := '1';
ce_bcnt := '1';
end if;
when s_endbx => -- s_endbx: finish bx ---------------
ld_dcnt := '1'; -- start next bit
n.sreg := dbit & r.sreg(7 downto 1);
if tc_ccnt = '1' then -- last cycle of bx ?
if tc_bcnt = '1' then
n.state := s_endb9; -- finish b9
ld_bcnt := '1'; -- and wrap bcnt
else
n.state := s_endbx; -- finish bx
ce_bcnt := '1';
end if;
ld_ccnt := '1';
else -- continue in bx ?
if tc_bcnt = '1' then
n.state := s_colb9; -- collect b9
else
n.state := s_colbx; -- collect bx
end if;
end if;
when s_colb9 => -- s_colb9: collect bx (stop bit) ----
if tc_ccnt = '1' then -- last cycle of b9 ?
n.state := s_endb9; -- finish b9
ld_ccnt := '1'; -- "
ld_bcnt := '1'; -- and wrap bcnt
else -- continue in b9 ?
if dbit='1' and RXSD='1' then -- already enough 1's ?
n.state := s_idle; -- finish to idle
ld_dcnt := '1'; -- put counters in reset
ld_ccnt := '1';
ld_bcnt := '1';
ival := '1';
end if;
end if;
when s_endb9 => -- s_endb9: finish bx (stop bit) ----
ld_dcnt := '1'; -- start next bit
if dbit = '1' then -- was it a valid stop bit ?
ival := '1';
else
ierr := '1';
end if;
if RXSD = '1' then -- line in idle state ?
n.state := s_idle; -- finish to idle state
ld_ccnt := '1'; -- and put counters in reset
ld_bcnt := '1'; -- "
else
if tc_ccnt = '1' then -- last cycle of b9 ?
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- "
ce_bcnt := '1';
else -- continue in b0 ?
n.state := s_colb0; -- collect bx
end if;
end if;
when others => null; -- -----------------------------------
end case;
if RESET = '1' then -- RESET seen
ld_ccnt := '1'; -- keep all counters in reset
ld_dcnt := '1';
ld_bcnt := '1';
n.state := s_idle;
end if;
if ld_ccnt = '1' then -- implement ccnt
n.ccnt := CLKDIV;
else
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
if ld_dcnt = '1' then -- implement dcnt
n.dcnt(CDWIDTH downto 1) := (others=>'0');
n.dcnt(0) := RXSD;
else
if RXSD = '1' then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
end if;
if ld_bcnt = '1' then -- implement bcnt
n.bcnt := (others=>'0');
else
if ce_bcnt = '1' then
n.bcnt := slv(unsigned(r.bcnt) + 1);
end if;
end if;
N_REGS <= n;
RXDATA <= r.sreg;
RXACT <= iact;
RXVAL <= ival;
RXERR <= ierr;
end process proc_next;
end syn;
|
gpl-2.0
|
31bae6dcb3d3faac0288b699d7467625
| 0.440874 | 3.961431 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
libraries/standard_textio_additions_c.vhdl
| 2 | 15,973 |
------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007-03-13 14:25:58-04 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007-03-13 14:25:58-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
procedure FLUSH (file F : TEXT);
function MINIMUM (L, R : SIDE) return SIDE;
function MAXIMUM (L, R : SIDE) return SIDE;
function TO_STRING (VALUE : SIDE) return STRING;
function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
procedure TEE (file F : TEXT; L : inout LINE);
procedure WRITE (L : inout LINE; VALUE : in REAL;
FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body standard_textio_additions is
-- pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
swrite ( L => L,
VALUE => to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
|
gpl-3.0
|
56482c13ebd7c8dff5aa095c57d5ccbe
| 0.522256 | 3.830456 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd
| 1 | 2,816 |
-- $Id: tbd_serport_uart_rx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rx - syn
-- Description: Wrapper for serport_uart_rx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rx
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 26 67 0 - t 8.17
-- 2007-10-27 92 9.1 J30 xc3s1000-4 26 67 0 - t 8.25
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 29 90 0 47 s 8.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 31 92 0 - s 8.25
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity tbd_serport_uart_rx is -- serial port uart rx [tb design]
-- generic: CDWIDTH=5
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv5; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end tbd_serport_uart_rx;
architecture syn of tbd_serport_uart_rx is
begin
UART : serport_uart_rx
generic map (
CDWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
end syn;
|
gpl-2.0
|
9c120ec46f001b7fb0a0ea3615a41e68
| 0.546875 | 3.724868 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
| 1 | 22,545 |
-- $Id: sys_w11a_n2.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n2 - syn
-- Description: w11a test design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2rlink/rlink_sp1c_fx2
-- bplib/fx2rlink/ioleds_sp1c_fx2
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_bram
-- vlib/nxcramlib/nx_cram_dummy
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- bplib/nxcramlib/nx_cram_memctl_as
-- ibus/ib_sres_or_2
-- ibus/ibdr_minisys
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_sys_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 1541 4598 334 2889 ok: now + FX2 !
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II
-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II
-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II
-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II
-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II
-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II
-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II
-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II
-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II
-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II
-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II
-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.4 added fx2 (cuff) support; ATOWIDTH=7
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-12-18 440 1.2.7 use rlink_sp1c
-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
-- 2011-11-19 427 1.2.4 now numeric_std clean
-- 2011-11-17 426 1.2.3 use dcm_sfs now
-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.2.1 use now sn_humanio
-- 2010-12-30 351 1.2 ported to rbv3
-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
-- BUGFIX: resolve rbus address clash hio<->ibr
-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;
-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust)
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport
-- use s3_humanio_rri
-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
------------------------------------------------------------------------------
--
-- w11a test design for nexys2
-- w11a + rlink + serport + cuff
--
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:3): no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1): 1 enable XON
-- (0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3:0) shows IO activity
-- if SWI(2)=0 (serport)
-- (3): not SER_MONI.txok (shows tx back preasure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back preasure)
-- (0): SER_MONI.rxact (shows rx activity)
-- if SWI(2)=1 (fx2-usb)
-- (3): RB_SRES.busy (shows rbus back preasure)
-- (2): RLB_TXBUSY (shows tx back preasure)
-- (1): RLB_TXENA (shows tx activity)
-- (0): RLB_RXVAL (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.fx2lib.all;
use work.fx2rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n2 is -- top level
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_w11a_n2;
architecture syn of sys_w11a_n2 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal RLB_MONI : rlb_moni_type := rlb_moni_init;
signal SER_MONI : serport_moni_type := serport_moni_init;
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CPU_RESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal CACHE_CHIT : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
signal DISPREG : slv16 := (others=>'0');
constant rbaddr_core0 : slv8 := "00000000";
constant rbaddr_ibus : slv8 := "10000000";
constant rbaddr_hio : slv8 := "11000000";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c_fx2
generic map (
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
ENAFX2 => SWI(2),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
FX2_MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RB_SRES_OR : rb_sres_or_3
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_3 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
CORE : pdp11_core
port map (
CLK => CLK,
RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM_BRAM: if sys_conf_bram > 0 generate
signal HM_VAL_BRAM : slbit := '0';
begin
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => EM_MREQ.req,
HM_VAL => HM_VAL_BRAM,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end generate MEM_BRAM;
MEM_SRAM: if sys_conf_bram = 0 generate
CACHE: pdp11_cache
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
CHIT => CACHE_CHIT,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => HM_ENA,
HM_VAL => CACHE_CHIT,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
SRAM_CTL: nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => CPU_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end generate MEM_SRAM;
IB_SRES_OR : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES_IBDR,
IB_SRES_OR => IB_SRES
);
IBD_MINI : if false generate
begin
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MINI;
IBD_MAXI : if true generate
begin
IBDR_SYS : ibdr_maxisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MAXI;
IOLEDS : ioleds_sp1c_fx2
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => CPU_RESET,
ENAFX2 => SWI(2),
RB_SRES => RB_SRES,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
DSP_DAT(15 downto 0) <= DISPREG;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= CACHE_CHIT;
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
cd9ca5b7092d709dbe5cbe4082f354ee
| 0.502772 | 3.010415 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/0b898fe3767163cf/fifo_generator_rx_inst_sim_netlist.vhdl
| 1 | 318,718 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 17:53:12 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => Q(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 2) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(1 downto 0) => B"00",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => din(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 4),
DOBDO(3 downto 0) => dout(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 6) => B"00000000000000000000000000",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg_0(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gcc0.gc0.count_d1_reg[10]\,
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
D(11 downto 0) <= \^d\(11 downto 0);
\gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(3),
O => \gc0.count[0]_i_2_n_0\
);
\gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(2),
O => \gc0.count[0]_i_3_n_0\
);
\gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(1),
O => \gc0.count[0]_i_4_n_0\
);
\gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^d\(0),
O => \gc0.count[0]_i_5_n_0\
);
\gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(7),
O => \gc0.count[4]_i_2_n_0\
);
\gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(6),
O => \gc0.count[4]_i_3_n_0\
);
\gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(5),
O => \gc0.count[4]_i_4_n_0\
);
\gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(4),
O => \gc0.count[4]_i_5_n_0\
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(11),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(10),
O => \gc0.count[8]_i_3_n_0\
);
\gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(9),
O => \gc0.count[8]_i_4_n_0\
);
\gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(8),
O => \gc0.count[8]_i_5_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(0),
Q => Q(0),
R => srst
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(10),
Q => Q(10),
R => srst
);
\gc0.count_d1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(11),
Q => Q(11),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(1),
Q => Q(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(2),
Q => Q(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(3),
Q => Q(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(4),
Q => Q(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(5),
Q => Q(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(6),
Q => Q(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(7),
Q => Q(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(8),
Q => Q(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^d\(9),
Q => Q(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_7\,
Q => \^d\(0),
S => srst
);
\gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gc0.count_reg[0]_i_1_n_4\,
O(2) => \gc0.count_reg[0]_i_1_n_5\,
O(1) => \gc0.count_reg[0]_i_1_n_6\,
O(0) => \gc0.count_reg[0]_i_1_n_7\,
S(3) => \gc0.count[0]_i_2_n_0\,
S(2) => \gc0.count[0]_i_3_n_0\,
S(1) => \gc0.count[0]_i_4_n_0\,
S(0) => \gc0.count[0]_i_5_n_0\
);
\gc0.count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_5\,
Q => \^d\(10),
R => srst
);
\gc0.count_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_4\,
Q => \^d\(11),
R => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_6\,
Q => \^d\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_5\,
Q => \^d\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[0]_i_1_n_4\,
Q => \^d\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_7\,
Q => \^d\(4),
R => srst
);
\gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[4]_i_1_n_4\,
O(2) => \gc0.count_reg[4]_i_1_n_5\,
O(1) => \gc0.count_reg[4]_i_1_n_6\,
O(0) => \gc0.count_reg[4]_i_1_n_7\,
S(3) => \gc0.count[4]_i_2_n_0\,
S(2) => \gc0.count[4]_i_3_n_0\,
S(1) => \gc0.count[4]_i_4_n_0\,
S(0) => \gc0.count[4]_i_5_n_0\
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_6\,
Q => \^d\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_5\,
Q => \^d\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[4]_i_1_n_4\,
Q => \^d\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_7\,
Q => \^d\(8),
R => srst
);
\gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[8]_i_1_n_4\,
O(2) => \gc0.count_reg[8]_i_1_n_5\,
O(1) => \gc0.count_reg[8]_i_1_n_6\,
O(0) => \gc0.count_reg[8]_i_1_n_7\,
S(3) => \gc0.count[8]_i_2_n_0\,
S(2) => \gc0.count[8]_i_3_n_0\,
S(1) => \gc0.count[8]_i_4_n_0\,
S(0) => \gc0.count[8]_i_5_n_0\
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \gc0.count_reg[8]_i_1_n_6\,
Q => \^d\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
srst : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gcc0.gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\gcc0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(3),
O => \gcc0.gc0.count[0]_i_2_n_0\
);
\gcc0.gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(2),
O => \gcc0.gc0.count[0]_i_3_n_0\
);
\gcc0.gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(1),
O => \gcc0.gc0.count[0]_i_4_n_0\
);
\gcc0.gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(7),
O => \gcc0.gc0.count[4]_i_2_n_0\
);
\gcc0.gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(6),
O => \gcc0.gc0.count[4]_i_3_n_0\
);
\gcc0.gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(5),
O => \gcc0.gc0.count[4]_i_4_n_0\
);
\gcc0.gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(4),
O => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(11),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(10),
O => \gcc0.gc0.count[8]_i_3_n_0\
);
\gcc0.gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(9),
O => \gcc0.gc0.count[8]_i_4_n_0\
);
\gcc0.gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(8),
O => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(10),
Q => \^q\(10),
R => srst
);
\gcc0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(11),
Q => \^q\(11),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_7\,
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gcc0.gc0.count_reg[0]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[0]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[0]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[0]_i_1_n_7\,
S(3) => \gcc0.gc0.count[0]_i_2_n_0\,
S(2) => \gcc0.gc0.count[0]_i_3_n_0\,
S(1) => \gcc0.gc0.count[0]_i_4_n_0\,
S(0) => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_5\,
Q => p_12_out(10),
R => srst
);
\gcc0.gc0.count_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_4\,
Q => p_12_out(11),
R => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_6\,
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_5\,
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_4\,
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_7\,
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[4]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[4]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[4]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[4]_i_1_n_7\,
S(3) => \gcc0.gc0.count[4]_i_2_n_0\,
S(2) => \gcc0.gc0.count[4]_i_3_n_0\,
S(1) => \gcc0.gc0.count[4]_i_4_n_0\,
S(0) => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_6\,
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_5\,
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[4]_i_1_n_4\,
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_7\,
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gcc0.gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[8]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[8]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[8]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[8]_i_1_n_7\,
S(3) => \gcc0.gc0.count[8]_i_2_n_0\,
S(2) => \gcc0.gc0.count[8]_i_3_n_0\,
S(1) => \gcc0.gc0.count[8]_i_4_n_0\,
S(0) => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[8]_i_1_n_6\,
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => D(0),
I2 => \^q\(1),
I3 => D(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => D(2),
I2 => \^q\(3),
I3 => D(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => D(4),
I2 => \^q\(5),
I3 => D(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => D(6),
I2 => \^q\(7),
I3 => D(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => D(8),
I2 => \^q\(9),
I3 => D(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => ram_empty_i_reg_3
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_0(5)
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => D(10),
I2 => \^q\(11),
I3 => D(11),
O => v1_reg(5)
);
\gmux.gm[5].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => p_12_out(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_1(5)
);
\gmux.gm[5].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => ram_empty_i_reg_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => srst,
I1 => ram_empty_fb_i,
I2 => rd_en,
O => tmp_ram_rd_en
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2
port map (
comp1 => comp1,
v1_reg(5 downto 0) => v1_reg(5 downto 0)
);
\gc0.count_d1[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => \gcc0.gc0.count_d1_reg[11]\
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0
port map (
comp1 => comp1,
v1_reg_0(5 downto 0) => v1_reg_0(5 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(12 downto 4),
dout(8 downto 0) => dout(12 downto 4),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(21 downto 13),
dout(8 downto 0) => dout(21 downto 13),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(30 downto 22),
dout(8 downto 0) => dout(30 downto 22),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[4].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(39 downto 31),
dout(8 downto 0) => dout(39 downto 31),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[5].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(48 downto 40),
dout(8 downto 0) => dout(48 downto 40),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[6].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(57 downto 49),
dout(8 downto 0) => dout(57 downto 49),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[7].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(63 downto 58),
dout(5 downto 0) => dout(63 downto 58),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \grss.rsts_n_2\ : STD_LOGIC;
begin
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
E(0) => \grss.rsts_n_2\,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
E(0) => \grss.rsts_n_2\,
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gcc0.gc0.count_d1_reg[11]\ : STD_LOGIC;
begin
\gcc0.gc0.count_d1_reg[11]\ <= \^gcc0.gc0.count_d1_reg[11]\;
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
clk => clk,
full => full,
\gcc0.gc0.count_d1_reg[11]\ => \^gcc0.gc0.count_d1_reg[11]\,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_0(5 downto 0) => \c1/v1_reg\(5 downto 0),
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
ram_empty_i_reg_4 => ram_empty_i_reg_4,
ram_full_fb_i_reg => \^gcc0.gc0.count_d1_reg[11]\,
srst => srst,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
v1_reg_0(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_1(5 downto 0) => \c1/v1_reg\(5 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_25\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_26\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
Q(11 downto 0) => p_0_out(11 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.wr_n_26\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_23\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_24\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_25\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\gcc0.gc0.count_d1_reg[11]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_22\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_23\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_24\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_25\,
ram_empty_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_26\,
rd_en => rd_en,
srst => srst,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(11) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(11 downto 0) => NLW_U0_data_count_UNCONNECTED(11 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(11 downto 0) => B"000000000000",
prog_empty_thresh_assert(11 downto 0) => B"000000000000",
prog_empty_thresh_negate(11 downto 0) => B"000000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(11 downto 0) => B"000000000000",
prog_full_thresh_assert(11 downto 0) => B"000000000000",
prog_full_thresh_negate(11 downto 0) => B"000000000000",
rd_clk => '0',
rd_data_count(11 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(11 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(11 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(11 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
532915b9ffdd59d3444c4a833700d094
| 0.688838 | 3.518286 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/core/generic_neuron.vhd
| 1 | 3,742 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : generic_neuron.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : GENERIC_NEURON
-- ARCHITECTURE : behaviour
--=============================================================================
-- AUTORS(s) : Agostini, N
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : NOV 28, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.NN_TYPES_pkg.all;
--=============================================================================
-- Entity declaration for GENERIC_NEURON
--=============================================================================
entity GENERIC_NEURON is
generic (
NUMBER_OF_INPUTS : natural;
NEURON_WEIGHTS : ARRAY_OF_SFIXED
);
port (
IN_VALUES :in ARRAY_OF_SFIXED;
CONTROL :in std_logic;
CLK :in std_logic;
OUTPUT :out CONSTRAINED_SFIXED
);
end GENERIC_NEURON;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture BEHAVIOUR of GENERIC_NEURON is
signal BIAS : CONSTRAINED_SFIXED;
signal TO_SIGMOID : CONSTRAINED_SFIXED;
component SIGMOID_SELECT
port (
CLK : in std_logic;
X_VALUE : in CONSTRAINED_SFIXED;
Y_VALUE : out CONSTRAINED_SFIXED
);
end component;
--=============================================================================
-- architecture begin
--=============================================================================
begin
--initialization
BIAS <= NEURON_WEIGHTS(NUMBER_OF_INPUTS);
FORWARDPROPAGATION: process (
IN_VALUES,
CONTROL,
CLK
)
variable NEWVALUE: CONSTRAINED_SFIXED;
begin
if CLK'event and CLK ='1'then
NEWVALUE := to_sfixed(0 ,U_SIZE,L_SIZE);
for I in 0 to (NUMBER_OF_INPUTS-1) loop
NEWVALUE := resize(
(NEWVALUE + resize(
(IN_VALUES(I) * NEURON_WEIGHTS(I)),
NEWVALUE'high,NEWVALUE'low))
,NEWVALUE'high,NEWVALUE'low);
end loop;
NEWVALUE := resize(
(NEWVALUE + BIAS),
NEWVALUE'high,NEWVALUE'low);
end if;
TO_SIGMOID <= NEWVALUE;
end process;
SIGMOID: SIGMOID_SELECT
port map (
CLK => CLK,
X_VALUE => TO_SIGMOID,
Y_VALUE => OUTPUT
);
end;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
7076fbc989f21540c566bac36de70b06
| 0.460449 | 4.513872 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/w11a/nexys3/sys_conf.vhd
| 1 | 4,274 |
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2013-10-05 537 1.1.1 use 72 MHz, no closure w/ ISE 14.x for 80 anymore
-- 2013-04-21 509 1.1 add fx2 settings
-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432)
-- 2011-11-20 430 1.0 Initial version (derived from _n2 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd):
-- div mul clksys read0 read1 write
-- 2 1 50.0 2 2 3
-- 4 3 75.0 4 4 5 (also 70 MHz)
-- 5 4 80.0 5 5 5
-- 20 17 85.0 5 5 6
-- 10 9 90.0 6 6 6 (also 95 MHz)
-- 1 1 100.0 6 6 7
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 25;
constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_memctl_read0delay : positive := 4;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 5;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
95aebabd28f8ea4170593786e47b8ad1
| 0.60014 | 3.486134 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/tst_serloop.vhd
| 1 | 7,740 |
-- $Id: tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop - syn
-- Description: simple stand-alone tester for serport components
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-06 420 1.0 Initial version
-- 2011-10-14 416 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end tst_serloop;
architecture syn of tst_serloop is
type regs_type is record
rxdata : slv8; -- next rx char
txdata : slv8; -- next tx char
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
rxok_1 : slbit; -- rxok last cycle
txok_1 : slbit; -- txok last cycle
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0'), -- txokcnt
'0','0', -- rxok_1,txok_1
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI,
RXDATA, RXVAL, TXBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxhold : slbit := '1';
variable itxena : slbit := '0';
variable itxdata : slv8 := (others=>'0');
variable skipxon : slbit := '0';
function nextchar(skipxon: in slbit; data: in slv8) return slv8 is
variable inc : slv8 := (others=>'0');
begin
inc := "00000001";
if skipxon='1' and (data=c_serport_xon or data=c_serport_xoff) then
inc := "00000010";
end if;
return slv(unsigned(data)+unsigned(inc));
end function nextchar;
begin
r := R_REGS;
n := R_REGS;
irxhold := '1';
itxena := '0';
itxdata := RXDATA;
if HIO_CNTL.mode = c_mode_txblast then
itxdata := r.txdata;
end if;
skipxon := '0';
if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then
skipxon := '1';
end if;
if HIO_CNTL.enathrottle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXVAL='1' and r.rxthrottle='0' then
irxhold := '0';
if RXDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := nextchar(skipxon, RXDATA);
end if;
when c_mode_txblast =>
if TXBUSY = '0' then
itxena := '1';
n.txdata := nextchar(skipxon, r.txdata);
end if;
irxhold := '0';
if RXVAL = '1' then
n.rxuicnt := slv(unsigned(r.rxuicnt) + 1);
n.rxuidat := RXDATA;
end if;
when c_mode_loop =>
if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then
irxhold := '0';
itxena := '1';
end if;
when others => null;
end case;
if SER_MONI.abact = '1' then -- if auto bauder active
n.rxfecnt := (others=>'0'); -- reset frame error counter
else -- otherwise
if SER_MONI.rxerr = '1' then -- count rx frame errors
n.rxfecnt := slv(unsigned(r.rxfecnt) + 1);
end if;
end if;
if SER_MONI.rxovr = '1' then
n.rxoecnt := slv(unsigned(r.rxoecnt) + 1);
end if;
if RXVAL='1' and irxhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
n.rxok_1 := SER_MONI.rxok;
n.txok_1 := SER_MONI.txok;
if SER_MONI.rxok='0' and r.rxok_1='1' then
n.rxokcnt := slv(unsigned(r.rxokcnt) + 1);
end if;
if SER_MONI.txok='0' and r.txok_1='1' then
n.txokcnt := slv(unsigned(r.txokcnt) + 1);
end if;
N_REGS <= n;
RXHOLD <= irxhold;
TXENA <= itxena;
TXDATA <= itxdata;
HIO_STAT.rxfecnt <= r.rxfecnt;
HIO_STAT.rxoecnt <= r.rxoecnt;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.rxuicnt <= r.rxuicnt;
HIO_STAT.rxuidat <= r.rxuidat;
HIO_STAT.rxokcnt <= r.rxokcnt;
HIO_STAT.txokcnt <= r.txokcnt;
end process proc_next;
end syn;
|
gpl-2.0
|
1a3553655e1796145a5497121cddfdd7
| 0.503618 | 3.965164 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd
| 1 | 2,468 |
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk
-- 2012-04-09 461 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 2;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
gpl-2.0
|
fde300140671e746a90c580bbaf38a98
| 0.649514 | 3.728097 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/bpgenrbuslib.vhd
| 1 | 4,546 |
-- $Id: bpgenrbuslib.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: bpgenrbuslib
-- Description: Generic Board/Part components using rbus
--
-- Dependencies: -
-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package bpgenrbuslib is
component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
end package bpgenrbuslib;
|
gpl-2.0
|
4dae86cc79761469d653ae5b60380da9
| 0.536956 | 3.902146 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd
| 1 | 12,625 |
-- $Id: sys_tst_fx2loop_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n3 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100
--
-- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100
--
-- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100
-- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk
-- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_fx2loop_n3 is -- top level
-- implements nexys3_aif + fx2 pins
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n3;
architecture syn of sys_tst_fx2loop_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 8, -- good for up to 255 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;
|
gpl-2.0
|
9b5753d5831947a46e267009fce3e695
| 0.505743 | 3.066553 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11.vhd
| 2 | 54,460 |
-- $Id: pdp11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: pdp11
-- Description: Definitions for pdp11 components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.8 now numeric_std clean
-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
-- reassign cp command codes and rename: c_cp_func_...
-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
-- reassign rbus adresses and rename: c_rb_addr_...
-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
-- -> c_stat_rbf_...
-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2010-03-21 270 1.2.6 add pdp11_du_drv
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
-- move (and rename) intbus defs to iblib package;
-- move intbus devices to ibdlib package;
-- rename ubf_ --> ibf_;
-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
-- _vmbox,_mmu interface changed
-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
-- mod pdp11_intmap;
-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- add ibdr_kw11l.
-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.rblib.all;
package pdp11 is
type psw_type is record -- processor status
cmode : slv2; -- current mode
pmode : slv2; -- previous mode
rset : slbit; -- register set
pri : slv3; -- processor priority
tflag : slbit; -- trace flag
cc : slv4; -- condition codes (NZVC).
end record psw_type;
constant psw_init : psw_type := (
"00","00", -- cmode, pmode (=kernel)
'0',"111",'0', -- rset, pri (=7), tflag
"0000" -- cc NZVC=0
);
constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
constant c_psw_umode : slv2 := "11"; -- processor mode: user
subtype psw_ibf_cmode is integer range 15 downto 14;
subtype psw_ibf_pmode is integer range 13 downto 12;
constant psw_ibf_rset: integer := 11;
subtype psw_ibf_pri is integer range 7 downto 5;
constant psw_ibf_tflag: integer := 4;
subtype psw_ibf_cc is integer range 3 downto 0;
type sarsdr_type is record -- combined SAR/SDR MMU status
saf : slv16; -- segment address field
slf : slv7; -- segment length field
ed : slbit; -- expansion direction
acf : slv3; -- access control field
end record sarsdr_type;
constant sarsdr_init : sarsdr_type := (
(others=>'0'), -- saf
"0000000",'0',"000" -- slf, ed, acf
);
type dpath_cntl_type is record -- data path control
gpr_asrc : slv3; -- src register address
gpr_adst : slv3; -- dst register address
gpr_mode : slv2; -- psw mode for gpr access
gpr_rset : slbit; -- register set
gpr_we : slbit; -- gpr write enable
gpr_bytop : slbit; -- gpr high byte enable
gpr_pcinc : slbit; -- pc increment enable
psr_ccwe : slbit; -- enable update cc
psr_we: slbit; -- write enable psw (from DIN)
psr_func : slv3; -- write function psw (from DIN)
dsrc_sel : slbit; -- src data register source select
dsrc_we : slbit; -- src data register write enable
ddst_sel : slbit; -- dst data register source select
ddst_we : slbit; -- dst data register write enable
dtmp_sel : slv2; -- tmp data register source select
dtmp_we : slbit; -- tmp data register write enable
ounit_asel : slv2; -- ounit a port selector
ounit_azero : slbit; -- ounit a port force zero
ounit_const : slv9; -- ounit b port const
ounit_bsel : slv2; -- ounit b port selector
ounit_opsub : slbit; -- ounit operation
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
aunit_bytop : slbit; -- aunit byte operation
lunit_func : slv4; -- lunit function
lunit_bytop : slbit; -- lunit byte operation
munit_func : slv2; -- munit function
munit_s_div : slbit; -- munit s_opg_div state
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
munit_s_ash : slbit; -- munit s_opg_ash state
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
munit_s_ashc : slbit; -- munit s_opg_ashc state
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
ireg_we : slbit; -- ireg register write enable
cres_sel : slv3; -- result bus (cres) select
dres_sel : slv3; -- result bus (dres) select
vmaddr_sel : slv2; -- virtual address select
cpdout_we : slbit; -- capture dres for cpdout
end record dpath_cntl_type;
constant dpath_cntl_init : dpath_cntl_type := (
"000","000","00",'0','0','0','0', -- gpr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- ounit
"00","00","00",'0',"000",'0', -- aunit
"0000",'0', -- lunit
"00",'0','0','0','0','0','0','0', -- munit
'0',"000","000","00",'0' -- rest
);
constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
type dpath_stat_type is record -- data path status
ccout_z : slbit; -- current effective Z cc flag
shc_tc : slbit; -- last shc cycle (shc==0)
div_cr : slbit; -- division: reminder correction needed
div_cq : slbit; -- division: quotient correction needed
div_zero : slbit; -- division: divident or divisor zero
div_ovfl : slbit; -- division: overflow
end record dpath_stat_type;
constant dpath_stat_init : dpath_stat_type := (others=>'0');
type decode_stat_type is record -- decode status
is_dstmode0 : slbit; -- dest. is register mode
is_srcpc : slbit; -- source is pc
is_srcpcmode1 : slbit; -- source is pc and mode=1
is_dstpc : slbit; -- dest. is pc
is_dstw_reg : slbit; -- dest. register to be written
is_dstw_pc : slbit; -- pc register to be written
is_rmwop : slbit; -- read-modify-write operation
is_bytop : slbit; -- byte operation
is_res : slbit; -- reserved operation code
op_rtt : slbit; -- RTT instruction
op_mov : slbit; -- MOV instruction
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
updt_dstadsrc : slbit; -- update dsrc in dsta flow
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
lunit_func : slv4; -- lunit function
munit_func : slv2; -- munit function
res_sel : slv3; -- result bus (cres/dres) select
fork_op : slv4; -- op fork after idecode state
fork_srcr : slv2; -- src-read fork after idecode state
fork_dstr : slv2; -- dst-read fork after src read state
fork_dsta : slv2; -- dst-addr fork after idecode state
fork_opg : slv4; -- opg fork
fork_opa : slv3; -- opa fork
do_fork_op : slbit; -- execute fork_op
do_fork_srcr : slbit; -- execute fork_srcr
do_fork_dstr : slbit; -- execute fork_dstr
do_fork_dsta : slbit; -- execute fork_dsta
do_fork_opg : slbit; -- execute fork_opg
do_pref_dec : slbit; -- can do prefetch at decode phase
end record decode_stat_type;
constant decode_stat_init : decode_stat_type := (
'0','0','0','0','0','0','0','0','0', -- is_
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
"00","00","00",'0',"000", -- aunit_
"0000","00","000", -- lunit_, munit_, res_
"0000","00","00","00","0000","000", -- fork_
'0','0','0','0','0', -- do_fork_
'0' -- do_pref_
);
constant c_fork_op_halt : slv4 := "0000";
constant c_fork_op_wait : slv4 := "0001";
constant c_fork_op_rtti : slv4 := "0010";
constant c_fork_op_trap : slv4 := "0011";
constant c_fork_op_reset: slv4 := "0100";
constant c_fork_op_rts : slv4 := "0101";
constant c_fork_op_spl : slv4 := "0110";
constant c_fork_op_mcc : slv4 := "0111";
constant c_fork_op_br : slv4 := "1000";
constant c_fork_op_mark : slv4 := "1001";
constant c_fork_op_sob : slv4 := "1010";
constant c_fork_op_mtp : slv4 := "1011";
constant c_fork_srcr_def : slv2:= "00";
constant c_fork_srcr_inc : slv2:= "01";
constant c_fork_srcr_dec : slv2:= "10";
constant c_fork_srcr_ind : slv2:= "11";
constant c_fork_dstr_def : slv2:= "00";
constant c_fork_dstr_inc : slv2:= "01";
constant c_fork_dstr_dec : slv2:= "10";
constant c_fork_dstr_ind : slv2:= "11";
constant c_fork_dsta_def : slv2:= "00";
constant c_fork_dsta_inc : slv2:= "01";
constant c_fork_dsta_dec : slv2:= "10";
constant c_fork_dsta_ind : slv2:= "11";
constant c_fork_opg_gen : slv4 := "0000";
constant c_fork_opg_wdef : slv4 := "0001";
constant c_fork_opg_winc : slv4 := "0010";
constant c_fork_opg_wdec : slv4 := "0011";
constant c_fork_opg_wind : slv4 := "0100";
constant c_fork_opg_mul : slv4 := "0101";
constant c_fork_opg_div : slv4 := "0110";
constant c_fork_opg_ash : slv4 := "0111";
constant c_fork_opg_ashc : slv4 := "1000";
constant c_fork_opa_jsr : slv3 := "000";
constant c_fork_opa_jmp : slv3 := "001";
constant c_fork_opa_mtp : slv3 := "010";
constant c_fork_opa_mfp_reg : slv3 := "011";
constant c_fork_opa_mfp_mem : slv3 := "100";
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
constant c_cpurust_recrsv : slv4 := "1001"; -- recursive red-stack halt
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
type cpustat_type is record -- CPU status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
cpfunc : slv5; -- current control port function
cprnum : slv3; -- current control port register number
waitsusp : slbit; -- WAIT instruction suspended
intvect : slv9_2; -- current interrupt vector
trap_mmu : slbit; -- mmu trace trap pending
trap_ysv : slbit; -- ysv trap pending
prefdone : slbit; -- prefetch done
do_gprwe : slbit; -- pending gpr_we
do_intrsv : slbit; -- active rsv interrupt sequence
end record cpustat_type;
constant cpustat_init : cpustat_type := (
'0','0','0','0', -- cmd..
'0','0','0','0', -- cpu..
c_cpurust_init, -- cpurust
"00000","000", -- cpfunc, cprnum
'0', -- waitsusp
(others=>'0'), -- intvect
'0','0','0', -- trap_(mmu|ysv), prefdone
'0','0' -- do_gprwe, do_intrsv
);
type cpuerr_type is record -- CPU error register
illhlt : slbit; -- illegal halt (in non-kernel mode)
adderr : slbit; -- address error (odd, jmp/jsr reg)
nxm : slbit; -- non-existent memory
iobto : slbit; -- I/O bus timeout (non-exist UB)
ysv : slbit; -- yellow stack violation
rsv : slbit; -- red stack violation
end record cpuerr_type;
constant cpuerr_init : cpuerr_type := (others=>'0');
type vm_cntl_type is record -- virt memory control port
req : slbit; -- request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
dspace : slbit; -- dspace operation
kstack : slbit; -- access through kernel stack
intrsv : slbit; -- active rsv interrupt sequence
mode : slv2; -- mode
trap_done : slbit; -- mmu trap taken (to set ssr0 bit)
end record vm_cntl_type;
constant vm_cntl_init : vm_cntl_type := (
'0','0','0','0', -- req, wacc, macc,cacc
'0','0','0', -- bytop, dspace, kstack
'0',"00",'0' -- intrsv, mode, trap_done
);
type vm_stat_type is record -- virt memory status port
ack : slbit; -- acknowledge
err : slbit; -- error (see err_xxx for reason)
fail : slbit; -- failure (machine check)
err_odd : slbit; -- abort: odd address error
err_mmu : slbit; -- abort: mmu reject
err_nxm : slbit; -- abort: non-existing memory
err_iobto : slbit; -- abort: non-existing I/O resource
err_rsv : slbit; -- abort: red stack violation
trap_ysv : slbit; -- trap: yellow stack violation
trap_mmu : slbit; -- trap: mmu trace trap
end record vm_stat_type;
constant vm_stat_init : vm_stat_type := (others=>'0');
type em_mreq_type is record -- external memory - master request
req : slbit; -- request
we : slbit; -- write enable
be : slv2; -- byte enables
cancel : slbit; -- cancel request
addr : slv22_1; -- address
din : slv16; -- data in (input to memory)
end record em_mreq_type;
constant em_mreq_init : em_mreq_type := (
'0','0',"00",'0', -- req, we, be, cancel
(others=>'0'),(others=>'0') -- addr, din
);
type em_sres_type is record -- external memory - slave response
ack_r : slbit; -- acknowledge read
ack_w : slbit; -- acknowledge write
dout : slv16; -- data out (output from memory)
end record em_sres_type;
constant em_sres_init : em_sres_type := (
'0','0', -- ack_r, ack_w
(others=>'0') -- dout
);
type mmu_cntl_type is record -- mmu control port
req : slbit; -- translate request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access (bypass mmu)
dspace : slbit; -- dspace access
mode : slv2; -- processor mode
trap_done : slbit; -- mmu trap taken (set ssr0 bit)
end record mmu_cntl_type;
constant mmu_cntl_init : mmu_cntl_type := (
'0','0','0','0', -- req, wacc, macc, cacc
'0',"00",'0' -- dspace, mode, trap_done
);
type mmu_stat_type is record -- mmu status port
vaok : slbit; -- virtual address valid
trap : slbit; -- mmu trap request
ena_mmu : slbit; -- mmu enable (ssr0 bit 0)
ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4)
ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5)
end record mmu_stat_type;
constant mmu_stat_init : mmu_stat_type := (others=>'0');
type mmu_moni_type is record -- mmu monitor port
istart : slbit; -- instruction start
idone : slbit; -- instruction done
pc : slv16; -- PC of new instruction
regmod : slbit; -- register modified
regnum : slv3; -- register number
delta : slv4; -- register offset
isdec : slbit; -- offset to be subtracted
trace_prev : slbit; -- use ssr12 trace state of prev. state
end record mmu_moni_type;
constant mmu_moni_init : mmu_moni_type := (
'0','0',(others=>'0'), -- istart, idone, pc
'0',"000","0000", -- regmod, regnum, delta
'0','0' -- isdec, trace_prev
);
type mmu_ssr0_type is record -- MMU ssr0
abo_nonres : slbit; -- abort non resident
abo_length : slbit; -- abort segment length
abo_rdonly : slbit; -- abort read-only
trap_mmu : slbit; -- trap management
ena_trap : slbit; -- enable traps
inst_compl : slbit; -- instruction complete
seg_mode : slv2; -- segement mode
dspace : slbit; -- address space (D=1, I=0)
seg_num : slv3; -- segment number
ena_mmu : slbit; -- enable memory management
trace_prev : slbit; -- ssr12 trace status in prev. state
end record mmu_ssr0_type;
constant mmu_ssr0_init : mmu_ssr0_type := (
inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
others=>'0'
);
type mmu_ssr1_type is record -- MMU ssr1
rb_delta : slv5; -- RB: amount change
rb_num : slv3; -- RB: register number
ra_delta : slv5; -- RA: amount change
ra_num : slv3; -- RA: register number
end record mmu_ssr1_type;
constant mmu_ssr1_init : mmu_ssr1_type := (
"00000","000", -- rb_...
"00000","000" -- ra_...
);
type mmu_ssr3_type is record -- MMU ssr3
ena_ubmap : slbit; -- enable unibus mapping
ena_22bit : slbit; -- enable 22 bit mapping
dspace_km : slbit; -- enable dspace kernel
dspace_sm : slbit; -- enable dspace supervisor
dspace_um : slbit; -- enable dspace user
end record mmu_ssr3_type;
constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
-- control port definitions --------------------------------------------------
type cp_cntl_type is record -- control port control
req : slbit; -- request
func : slv5; -- function
rnum : slv3; -- register number
end record cp_cntl_type;
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start
constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop
constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue
constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step
constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft)
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
type cp_stat_type is record -- control port status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
end record cp_stat_type;
constant cp_stat_init : cp_stat_type := (
'0','0','0','0', -- cmd...
'0','0','0','0', -- cpu...
(others=>'0') -- cpurust
);
type cp_addr_type is record -- control port address
addr : slv22_1; -- address
racc : slbit; -- ibr access
be : slv2; -- byte enables
ena_22bit : slbit; -- enable 22 bit mode
ena_ubmap : slbit; -- enable unibus mapper
end record cp_addr_type;
constant cp_addr_init : cp_addr_type := (
(others=>'0'), -- addr
'0',"00", -- racc, be
'0','0' -- ena_...
);
-- debug and monitoring port definitions -------------------------------------
type dm_cntl_type is record -- debug and monitor control
dum1 : slbit; -- dummy 1
dum2 : slbit; -- dummy 2
end record dm_cntl_type;
constant dm_cntl_init : dm_cntl_type := (others=>'0');
type dm_stat_dp_type is record -- debug and monitor status - dpath
pc : slv16; -- pc
psw : psw_type; -- psw
ireg : slv16; -- ireg
ireg_we : slbit; -- ireg we
dsrc : slv16; -- dsrc register
ddst : slv16; -- ddst register
dtmp : slv16; -- dtmp register
dres : slv16; -- dres bus
gpr_adst : slv3; -- gpr dst regsiter
gpr_mode : slv2; -- gpr mode
gpr_bytop : slbit; -- gpr bytop
gpr_we : slbit; -- gpr we
end record dm_stat_dp_type;
constant dm_stat_dp_init : dm_stat_dp_type := (
(others=>'0'), -- pc
psw_init, -- psw
(others=>'0'),'0', -- ireg, ireg_we
(others=>'0'),(others=>'0'), -- dsrc, ddst
(others=>'0'),(others=>'0'), -- dtmp, dres
(others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
'0','0' -- gpr_bytop, gpr_we
);
type dm_stat_vm_type is record -- debug and monitor status - vmbox
ibmreq : ib_mreq_type; -- ibus master request
ibsres : ib_sres_type; -- ibus slave response
end record dm_stat_vm_type;
constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);
type dm_stat_co_type is record -- debug and monitor status - core
cpugo : slbit; -- cpugo state flag
cpuhalt : slbit; -- cpuhalt state flag
end record dm_stat_co_type;
constant dm_stat_co_init : dm_stat_co_type := ('0','0');
type dm_stat_sy_type is record -- debug and monitor status - system
emmreq : em_mreq_type; -- external memory: request
emsres : em_sres_type; -- external memory: response
chit : slbit; -- cache hit
end record dm_stat_sy_type;
constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0');
-- rbus interface definitions ------------------------------------------------
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
constant c_rbaddr_ibrb : slv5 := "10000"; -- R/W ibr base address
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
subtype c_ibrb_ibf_base is integer range 12 downto 6; -- ibrb: base addr
subtype c_ibrb_ibf_be is integer range 1 downto 0; -- ibrb: be's
-- -------------------------------------
component pdp11_gpr is -- general purpose registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end component;
constant c_gpr_r5 : slv3 := "101"; -- register number of r5
constant c_gpr_sp : slv3 := "110"; -- register number of SP
constant c_gpr_pc : slv3 := "111"; -- register number of PC
component pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
constant c_psr_func_wall : slv3 := "100"; -- write all fields
component pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end component;
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
component pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
component pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
component pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state
S_DIV_CN : in slbit; -- s_opg_div_cn state
S_DIV_CR : in slbit; -- s_opg_div_cr state
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: reminder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_ZERO : out slbit; -- division: divident or divisor zero
DIV_OVFL : out slbit; -- division: overflow
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_munit_func_mul : slv2 := "00"; -- MUL
constant c_munit_func_div : slv2 := "01"; -- DIV
constant c_munit_func_ash : slv2 := "10"; -- ASH
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
component pdp11_mmu_sadr is -- mmu SAR/SDR register set
port (
CLK : in slbit; -- clock
MODE : in slv2; -- mode
ASN : in slv4; -- augmented segment number (1+3 bit)
AIB_WE : in slbit; -- update AIB
AIB_SETA : in slbit; -- set access AIB
AIB_SETW : in slbit; -- set write AIB
SARSDR : out sarsdr_type; -- combined SAR/SDR
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end component;
component pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
);
end component;
component pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end component;
component pdp11_sequencer is -- cpu sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
CRESET : out slbit; -- console reset
BRESET : out slbit; -- ibus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
INT_ACK : out slbit; -- interrupt acknowledge
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_sys70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_cache is -- cache
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
CHIT : out slbit; -- cache hit flag
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32 -- memory: data out (memory view)
);
end component;
component pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
BRESET : out slbit; -- ibus reset
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_du_drv is -- display unit low level driver
generic (
CDWIDTH : positive := 3); -- clock divider width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
ROW0 : in slv22; -- led row 0 (22 leds, top)
ROW1 : in slv16; -- led row 1 (16 leds)
ROW2 : in slv16; -- led row 2 (16 leds)
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
SWOPT : out slv8; -- option pattern from du
SWOPT_RDY : out slbit; -- marks update of swopt
DU_SCLK : out slbit; -- DU: sclk
DU_SS_N : out slbit; -- DU: ss_n
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
DU_MISO : in slbit -- DU: miso (master in, slave out)
);
end component;
component pdp11_bram is -- BRAM based ext. memory dummy
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end component;
component pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end component;
-- ----- move later to pdp11_conf --------------------------------------------
constant conf_vect_pirq : integer := 8#240#;
constant conf_pri_pirq_1 : integer := 1;
constant conf_pri_pirq_2 : integer := 2;
constant conf_pri_pirq_3 : integer := 3;
constant conf_pri_pirq_4 : integer := 4;
constant conf_pri_pirq_5 : integer := 5;
constant conf_pri_pirq_6 : integer := 6;
constant conf_pri_pirq_7 : integer := 7;
end package pdp11;
|
gpl-2.0
|
471a16cce813465e5d0d77e99ba6aad0
| 0.504866 | 3.825513 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/pezhman_mem/simulation/pezhman_mem_synth.vhd
| 1 | 7,101 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pezhman_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY pezhman_mem_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE pezhman_mem_synth_ARCH OF pezhman_mem_synth IS
COMPONENT pezhman_mem_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: pezhman_mem_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
67f39b9439446638a36a51ece2bdae57
| 0.560203 | 3.77512 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd
| 1 | 7,486 |
-- $Id: sys_tst_serloop1_n2.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n2 - syn
-- Description: Tester serial link for nexys2
--
-- Dependencies: genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-16 439 13.1 O40d xc3s1200e-4 433 634 64 490 t 13.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop1_n2;
architecture syn of sys_tst_serloop1_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
gpl-2.0
|
900576d704a0b7e6e888fa4749709f35
| 0.492252 | 3.338983 | false | false | false | false |
freecores/w11
|
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd
| 1 | 12,001 |
-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nx_cram_memctl - sim
-- Description: Test bench for nx_cram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/micron/mt45w8mw16b
-- tbd_nx_cram_memctl [UUT, abstact]
--
-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as)
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl
-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl
-- 2010-05-23 293 1.0 Initial version (derived from tb_s3_sram_memctl)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_nx_cram_memctl is
end tb_nx_cram_memctl;
architecture sim of tb_nx_cram_memctl is
component tbd_nx_cram_memctl is -- CRAM driver (abstract) [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv22 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slbit := '0';
signal O_MEM_BE_N : slv2 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADV_N : slbit := '0';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'0');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv22 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv22 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv22 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 7.5 ns; -- compatible ucf for
constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UUT : tbd_nx_cram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_nx_cram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv22 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 7, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 7, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 6, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 4, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
|
gpl-2.0
|
a12c5f5ddc2e24df8966595e9387219e
| 0.497709 | 3.535946 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/pezhman_mem/simulation/pezhman_mem_tb.vhd
| 1 | 4,508 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: pezhman_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY pezhman_mem_tb IS
END ENTITY;
ARCHITECTURE pezhman_mem_tb_ARCH OF pezhman_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
pezhman_mem_synth_inst:ENTITY work.pezhman_mem_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
3fdea6d2b625ca1a6ba3e82a4879855d
| 0.602041 | 4.432645 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_xontx.vhd
| 1 | 4,808 |
-- $Id: serport_xontx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx - syn
-- Description: serial port: xon/xoff logic tx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-10-22 417 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx;
architecture syn of serport_xontx is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end syn;
|
gpl-2.0
|
ca92db81ae54d81f9a5dd3771c1c3144
| 0.488769 | 3.944217 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_uart_rxtx_ab.vhd
| 1 | 3,868 |
-- $Id: serport_uart_rxtx_ab.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx_ab - syn
-- Description: serial port UART - transmitter-receiver + autobauder
--
-- Dependencies: serport_uart_autobaud
-- serport_uart_rxtx
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.1.1 now numeric_std clean
-- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
);
end serport_uart_rxtx_ab;
architecture syn of serport_uart_rxtx_ab is
signal CLKDIV : slv(CDWIDTH-1 downto 0) := slv(to_unsigned(0, CDWIDTH));
signal ABACT_L : slbit := '0'; -- local readable copy of ABACT
signal UART_RESET : slbit := '0';
begin
AB : serport_uart_autobaud
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
CLKDIV => CLKDIV,
ACT => ABACT_L,
DONE => ABDONE
);
UART_RESET <= ABACT_L or RESET;
ABACT <= ABACT_L;
ABCLKDIV <= CLKDIV;
RXTX : serport_uart_rxtx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
|
gpl-2.0
|
6e17b63acb567b52c86952ab62ea2e3b
| 0.552223 | 4.016615 | false | false | false | false |
superboy0712/MIPS
|
uart/uartTop.vhd
| 3 | 2,417 |
-----------------------------------------------------------------------------------------
-- uart top level module
--
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart2BusTop_pkg.all;
entity uartTop is
port ( -- global signals
clr : in std_logic; -- global reset input
clk : in std_logic; -- global clock input
-- uart serial signals
serIn : in std_logic; -- serial data input
serOut : out std_logic; -- serial data output
-- transmit and receive internal interface signals
txData : in std_logic_vector(7 downto 0); -- data byte to transmit
newTxData : in std_logic; -- asserted to indicate that there is a new data byte for transmission
txBusy : out std_logic; -- signs that transmitter is busy
rxData : out std_logic_vector(7 downto 0); -- data byte received
newRxData : out std_logic; -- signs that a new byte was received
-- baud rate configuration register - see baudGen.vhd for details
baudFreq : in std_logic_vector(11 downto 0); -- baud rate setting registers - see header description
baudLimit : in std_logic_vector(15 downto 0); -- baud rate setting registers - see header description
baudClk : out std_logic); --
end uartTop;
architecture Behavioral of uartTop is
signal ce16 : std_logic; -- clock enable at bit rate
begin
-- baud rate generator module
bg : baudGen
port map (
clr => clr,
clk => clk,
baudFreq => baudFreq,
baudLimit => baudLimit,
ce16 => ce16);
-- uart receiver
ut : uartTx
port map (
clr => clr,
clk => clk,
ce16 => ce16,
txData => txData,
newTxData => newTxData,
serOut => serOut,
txBusy => txBusy);
-- uart transmitter
ur : uartRx
port map (
clr => clr,
clk => clk,
ce16 => ce16,
serIn => serIn,
rxData => rxData,
newRxData => newRxData);
baudClk <= ce16;
end Behavioral;
|
mit
|
e9a36fca037e62ed71b3f4ac9a9bccb3
| 0.487381 | 4.983505 | false | false | false | false |
freecores/w11
|
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
| 1 | 9,933 |
-- $Id: tb_nexys2_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp_cuff - sim
-- Description: Test bench for nexys2 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink_dcm
-- tb_nexys2_core
-- serport/serport_uart_rxtx
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys2_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-03 469 1.1 add fx2 model and data path
-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2_fusp_cuff is
end tb_nexys2_fusp_cuff;
architecture sim of tb_nexys2_fusp_cuff is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
SB_CLKSTOP <= CLK_STOP;
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_cuff_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXACT => UART_RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_FX2 <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
49e045260138fecd3d8b12853a5d8d54
| 0.527333 | 3.057248 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/dcm_sfs_gsim.vhd
| 2 | 3,665 |
-- $Id: dcm_sfs_gsim.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - sim
-- Description: DCM for simple frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.1 rename dcm_sp_sfs -> dcm_sfs
-- 2010-11-12 338 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture sim of dcm_sfs is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * CLKFX_DIVIDE) / CLKFX_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "dcm_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := CLKFX_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to CLKFX_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= CLKFX_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;
|
gpl-2.0
|
7884554264afabec2b95d8622e9ccc2f
| 0.552251 | 3.957883 | false | false | false | false |
freecores/w11
|
rtl/ibus/ib_sres_or_4.vhd
| 2 | 2,808 |
-- $Id: ib_sres_or_4.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_4 - syn
-- Description: ibus: result or, 4 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_4 is -- ibus result or, 4 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_4;
architecture syn of ib_sres_or_4 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack or
IB_SRES_3.ack or
IB_SRES_4.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy or
IB_SRES_3.busy or
IB_SRES_4.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout or
IB_SRES_3.dout or
IB_SRES_4.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => IB_SRES_4
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
c265920398696323bae5fe59bd8eeb02
| 0.537393 | 3.30742 | false | false | false | false |
freecores/w11
|
rtl/vlib/genlib/gray_cnt_n.vhd
| 2 | 3,154 |
-- $Id: gray_cnt_n.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_n - syn
-- Description: Genric width Gray code counter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- DWIDTH LUT Flop clock(xst est.)
-- 4 6 5 305MHz/ 3.28ns
-- 5 8 6 286MHz/ 2.85ns
-- 8 13 9 234MHz/ 4.26ns
-- 16 56 17 149MHz/ 6.67ns
-- 32 95 33 161MHz/ 6.19ns
-- 64 188 68 126MHz/ 7.90ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
entity gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_n;
architecture syn of gray_cnt_n is
signal R_AUX : slbit := '1';
signal R_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
signal N_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
begin
assert DWIDTH>=3
report "assert(DWIDTH>=3): only 3 bit or larger supported"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_AUX <= '1';
R_DATA <= (others=>'0');
elsif CE = '1' then
R_AUX <= not R_AUX;
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_AUX, R_DATA)
variable r : slv(DWIDTH-1 downto 0) := (others=>'0');
variable n : slv(DWIDTH-1 downto 0) := (others=>'0');
variable s : slbit := '0';
begin
r := R_DATA;
n := R_DATA;
s := '1';
if R_AUX = '1' then
n(0) := not r(0);
else
for i in 1 to DWIDTH-2 loop
if s='1' and r(i-1)='1' then
n(i) := not r(i);
end if;
s := s and not r(i-1);
end loop;
if s = '1' then
n(DWIDTH-1) := r(DWIDTH-2);
end if;
end if;
N_DATA <= n;
end process proc_next;
DATA <= R_DATA;
end syn;
|
gpl-2.0
|
5e3b4761fd7c0fdbeed8dd1c8b9c72ee
| 0.533291 | 3.337566 | false | false | false | false |
dumpram/zedboard-ofdm
|
vhdl/xillydemo.vhd
| 1 | 27,692 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
-- For Vivado, delete the port declarations for PS_CLK, PS_PORB and
-- PS_SRSTB, and uncomment their declarations as signals further below.
--PS_CLK : IN std_logic;
--PS_PORB : IN std_logic;
--PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : IN std_logic;
user_r_audio_open : OUT std_logic;
user_w_audio_wren : OUT std_logic;
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : IN std_logic;
user_r_smb_open : OUT std_logic;
user_w_smb_wren : OUT std_logic;
user_w_smb_full : IN std_logic;
user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component cyclic_prefix_fsm
port (
reset : in std_logic;
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
rd_en : out std_logic;
fifo_rd_count : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(31 downto 0);
fd_out : out std_logic;
rffd : in std_logic;
dft_data_valid : in std_logic
);
end component;
component dft_in_fsm
port (
reset : in std_logic;
clk : in std_logic;
fifo_data : in std_logic_vector(31 downto 0);
fifo_rd_en : out std_logic;
fifo_rd_count : in std_logic_vector(9 downto 0);
dft_data : out std_logic_vector(31 downto 0);
dft_fd_in : out std_logic;
dft_rffd : in std_logic;
dft_data_valid : in std_logic;
fifo_watchdog_reset : out std_logic
);
end component;
component dft_out_fsm
port (
reset : in std_logic;
clk : in std_logic;
dft_ce : out std_logic;
dft_dout : in std_logic_vector(31 downto 0);
dft_fd_out : in std_logic;
fifo_data : out std_logic_vector(31 downto 0);
fifo_wr_en : out std_logic;
fifo_wr_count : in std_logic_vector(9 downto 0);
fifo_watchdog_reset : out std_logic
);
end component;
COMPONENT dft_16
PORT (
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
XN_RE : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
XN_IM : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
FD_IN : IN STD_LOGIC;
FWD_INV : IN STD_LOGIC;
SIZE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RFFD : OUT STD_LOGIC;
XK_RE : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
XK_IM : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
BLK_EXP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FD_OUT : OUT STD_LOGIC;
DATA_VALID : OUT STD_LOGIC
);
END COMPONENT;
component reset_controller
port (
clk : in std_logic;
input_fsm_wd_reset : in std_logic;
output_fsm_wd_reset : in std_logic;
reset : out std_logic
);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
COMPONENT fifo_32x1024
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
component i2s_audio
port (
bus_clk : IN std_logic;
clk_100 : IN std_logic;
quiesce : IN std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
user_r_audio_rden : IN std_logic;
user_r_audio_empty : OUT std_logic;
user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : OUT std_logic;
user_r_audio_open : IN std_logic;
user_w_audio_wren : IN std_logic;
user_w_audio_full : OUT std_logic;
user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_w_audio_open : IN std_logic);
end component;
component smbus
port (
bus_clk : IN std_logic;
quiesce : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
user_r_smb_rden : IN std_logic;
user_r_smb_empty : OUT std_logic;
user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : OUT std_logic;
user_r_smb_open : IN std_logic;
user_w_smb_wren : IN std_logic;
user_w_smb_full : OUT std_logic;
user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_r_audio_eof : std_logic;
signal user_r_audio_open : std_logic;
signal user_w_audio_wren : std_logic;
signal user_w_audio_full : std_logic;
signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_w_audio_open : std_logic;
signal user_r_smb_rden : std_logic;
signal user_r_smb_empty : std_logic;
signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_r_smb_eof : std_logic;
signal user_r_smb_open : std_logic;
signal user_w_smb_wren : std_logic;
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
-- Note that none of the ARM processor's direct connections to pads is
-- defined as I/O on this module. Normally, they should be connected
-- as toplevel ports here, but that confuses Vivado 2013.4 to think that
-- some of these ports are real I/Os, causing an implementation failure.
-- This detachment results in a lot of warnings during synthesis and
-- implementation, but has no practical significance, as these pads are
-- completely unrelated to the FPGA bitstream.
signal PS_CLK : std_logic;
signal PS_PORB : std_logic;
signal PS_SRSTB : std_logic;
signal DDR_Addr : std_logic_vector(14 DOWNTO 0);
signal DDR_BankAddr : std_logic_vector(2 DOWNTO 0);
signal DDR_CAS_n : std_logic;
signal DDR_CKE : std_logic;
signal DDR_CS_n : std_logic;
signal DDR_Clk : std_logic;
signal DDR_Clk_n : std_logic;
signal DDR_DM : std_logic_vector(3 DOWNTO 0);
signal DDR_DQ : std_logic_vector(31 DOWNTO 0);
signal DDR_DQS : std_logic_vector(3 DOWNTO 0);
signal DDR_DQS_n : std_logic_vector(3 DOWNTO 0);
signal DDR_DRSTB : std_logic;
signal DDR_ODT : std_logic;
signal DDR_RAS_n : std_logic;
signal DDR_VRN : std_logic;
signal DDR_VRP : std_logic;
signal MIO : std_logic_vector(53 DOWNTO 0);
signal DDR_WEB : std_logic;
-- Signali za input FSM
signal input_fsm_reset : std_logic;
-- Signali za output FSM
signal output_fsm_reset : std_logic;
signal output_fsm_dft_ce : std_logic;
-- Signali za ulazni FIFO
signal fifo_read_data : std_logic_vector(31 downto 0);
signal fifo_read_rd_en : std_logic;
signal fifo_in_reset : std_logic;
signal fifo_in_empty : std_logic;
signal fifo_read_count : std_logic_vector(9 downto 0);
-- Signali za izlazni FIFO
signal fifo_write_data : std_logic_vector(31 downto 0);
signal fifo_write_wr_en : std_logic;
signal fifo_out_reset : std_logic;
signal fifo_out_full : std_logic;
signal fifo_write_count : std_logic_vector(9 downto 0);
-- Signali za DFT IP core
-- DFT-960 => size_const = 29 = 0x1d = 0b011101
constant dft_size_const : std_logic_vector(5 downto 0) := "011101";
signal dft_data_in : std_logic_vector(31 downto 0);
signal dft_out_I : std_logic_vector(15 downto 0);
signal dft_out_Q : std_logic_vector(15 downto 0);
signal dft_out_blk_exp : std_logic_vector(3 downto 0);
signal dft_fd_in : std_logic;
signal dft_fd_out : std_logic;
signal dft_data_valid : std_logic;
signal dft_rffd : std_logic;
signal dft_sclr : std_logic;
signal dft_out : std_logic_vector(31 downto 0);
-- Reset controller signals
signal controller_reset : std_logic;
signal input_fsm_wd_reset : std_logic;
signal output_fsm_wd_reset : std_logic;
-- DEBUG
signal led_sig : std_logic;
signal led_cnt : std_logic_vector(7 downto 0);
signal dft_fd_out_prev : std_logic := dft_fd_out;
signal PS_GPIO_xillybus : std_logic_vector(55 downto 0);
signal heartbeat_led_cnt : std_logic_vector(23 downto 0);
signal led_heartbeat : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
-- CPU to FPGA signals:
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open,
-- Ports related to /dev/xillybus_smb
-- FPGA to CPU signals:
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
-- CPU to FPGA signals:
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open,
-- General signals
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
clk_100 => clk_100,
otg_oc => otg_oc,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
PS_GPIO => PS_GPIO_xillybus,
DDR_WEB => DDR_WEB,
GPIO_LED => GPIO_LED,
bus_clk => bus_clk,
quiesce => quiesce,
vga4_blue => vga4_blue,
vga4_green => vga4_green,
vga4_red => vga4_red,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
---- 32-bit loopback
-- fifo_32 : fifo_32x512
-- port map(
-- clk => bus_clk,
-- srst => reset_32,
-- din => user_w_write_32_data,
-- wr_en => user_w_write_32_wren,
-- rd_en => user_r_read_32_rden,
-- dout => user_r_read_32_data,
-- full => user_w_write_32_full,
-- empty => user_r_read_32_empty
-- );
-- reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
-- user_r_read_32_eof <= '0';
-- INPUT FIFO
fifo_in : fifo_32x1024
port map(
clk => bus_clk,
srst => fifo_in_reset,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => fifo_read_rd_en,
dout => fifo_read_data,
full => user_w_write_32_full,
empty => fifo_in_empty,
data_count => fifo_read_count
);
fifo_in_reset <= controller_reset;
-- OUTPUT FIFO
fifo_out : fifo_32x1024
port map(
clk => bus_clk,
srst => fifo_out_reset,
din => fifo_write_data,
wr_en => fifo_write_wr_en,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => fifo_out_full,
empty => user_r_read_32_empty,
data_count => fifo_write_count
);
fifo_out_reset <= controller_reset;
input_fsm : dft_in_fsm
port map (
reset => input_fsm_reset,
clk => bus_clk,
fifo_data => fifo_read_data,
fifo_rd_en => fifo_read_rd_en,
fifo_rd_count => fifo_read_count,
dft_data => dft_data_in,
dft_fd_in => dft_fd_in,
dft_rffd => dft_rffd,
dft_data_valid => dft_data_valid,
fifo_watchdog_reset => input_fsm_wd_reset
);
input_fsm_reset <= controller_reset;
output_fsm : dft_out_fsm
port map (
reset => output_fsm_reset,
clk => bus_clk,
dft_ce => output_fsm_dft_ce,
dft_dout => dft_out,
dft_fd_out => dft_fd_out,
fifo_data => fifo_write_data,
fifo_wr_en => fifo_write_wr_en,
fifo_wr_count => fifo_write_count,
fifo_watchdog_reset => output_fsm_wd_reset
);
output_fsm_reset <= controller_reset;
dft_out_I <= dft_out(31 downto 16);
dft_out_Q <= dft_out(15 downto 0);
dft_16_I : dft_16
PORT MAP (
CLK => bus_clk,
SCLR => dft_sclr,
CE => output_fsm_dft_ce,
SIZE => dft_size_const,
FWD_INV => '1',
-- Vremenska domena
XN_RE => dft_data_in(31 downto 16),
XN_IM => dft_data_in(15 downto 0),
FD_IN => dft_fd_in,
RFFD => dft_rffd,
-- Frekvencijska domena
XK_RE => dft_out_I,
XK_IM => dft_out_Q,
BLK_EXP => dft_out_blk_exp,
FD_OUT => dft_fd_out,
DATA_VALID => dft_data_valid
);
dft_sclr <= controller_reset;
-- Reset controller
reset_controller_I : reset_controller
port map (
clk => bus_clk,
input_fsm_wd_reset => input_fsm_wd_reset,
output_fsm_wd_reset => output_fsm_wd_reset,
reset => controller_reset
);
PS_GPIO <= PS_GPIO_xillybus(55 downto 11) & led_sig & led_heartbeat & PS_GPIO_xillybus(8 downto 0);
process(bus_clk)
begin
if rising_edge(bus_clk) then
if (dft_fd_out /= dft_fd_out_prev) then
dft_fd_out_prev <= dft_fd_out;
if led_cnt /= (led_cnt'range => '0') then
led_cnt <= x"ff";
led_sig <= not led_sig;
else
led_cnt <= led_cnt - '1';
led_sig <= led_sig;
end if;
end if;
end if;
end process;
process(bus_clk)
begin
if rising_edge(bus_clk) then
if heartbeat_led_cnt /= (heartbeat_led_cnt'range => '0') then
heartbeat_led_cnt <= x"ffffff";
led_heartbeat <= not led_heartbeat;
else
heartbeat_led_cnt <= heartbeat_led_cnt - '1';
led_heartbeat <= led_heartbeat;
end if;
end if;
end process;
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
audio_ins : i2s_audio
port map(
bus_clk => bus_clk,
clk_100 => clk_100,
quiesce => quiesce,
audio_mclk => audio_mclk,
audio_dac => audio_dac,
audio_adc => audio_adc,
audio_bclk => audio_bclk,
audio_lrclk => audio_lrclk,
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open
);
smbus_ins : smbus
port map(
bus_clk => bus_clk,
quiesce => quiesce,
smb_sclk => smb_sclk,
smb_sdata => smb_sdata,
smbus_addr => smbus_addr,
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open
);
end sample_arch;
|
mit
|
5ce00e037608e8031d6b3457d8d3389f
| 0.572945 | 3.098926 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/MulBB.vhd
| 1 | 43,492 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/29/2015 11:08:18 AM
-- Design Name:
-- Module Name: dsp_32x32Mul_block - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity MulBB is
port (
CLK : in std_logic;
RST : in std_logic;
VALID_IN : in std_logic;
READY_IN : in std_logic;
LEFT : in std_logic_vector(31 downto 0);
RIGHT : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic;
READY_OUT : out std_logic;
MUL_OUT : out std_logic_vector(31 downto 0)
);
end MulBB;
architecture Behavioral of MulBB is
signal A_INPUT : std_logic_vector(41 downto 0) := (others => '0');
signal B_INPUT : std_logic_vector(34 downto 0) := (others => '0');
signal P_OUTPUT : std_logic_vector(75 downto 0) := (others => '0');
--
constant DELAY_MUL : positive := 7;
TYPE iBus_MUL is array(DELAY_MUL-1 downto 0) of std_logic;
signal ValidsRegBus_MUL : iBus_MUL := (others => '0');
--
COMPONENT logic_dff_block
Port (
D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
END COMPONENT;
--
-- BEGIN DSP48E1_inst_4
signal MULTISIGNOUT_DSP4 : std_logic := '0';
signal CARRYCASCOUT_DSP4 : std_logic := '0';
signal OVERFLOW_DSP4 : std_logic := '0';
signal PATTERNBDETECT_DSP4 : std_logic := '0';
signal PATTERNDETECT_DSP4 : std_logic := '0';
signal UNDERFLOW_DSP4 : std_logic := '0';
--
signal P_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP4 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP4 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP4 : std_logic := '0';
signal MULTISIGNIN_DSP4 : std_logic := '0';
signal PCIN_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP4 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP4 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP4 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP4 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP4 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP4 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP4 : std_logic := '0';
signal D_DSP4 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_4
-- BEGIN DSP48E1_inst_3
signal MULTISIGNOUT_DSP3 : std_logic := '0';
signal CARRYCASCOUT_DSP3 : std_logic := '0';
signal OVERFLOW_DSP3 : std_logic := '0';
signal PATTERNBDETECT_DSP3 : std_logic := '0';
signal PATTERNDETECT_DSP3 : std_logic := '0';
signal UNDERFLOW_DSP3 : std_logic := '0';
--
signal P_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP3 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP3 : std_logic_vector(17 downto 0) := (others => '0');
signal ACOUT_DSP3 : std_logic_vector(29 downto 0) := (others => '0');
signal BCOUT_DSP3 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP3 : std_logic := '0';
signal MULTISIGNIN_DSP3 : std_logic := '0';
signal PCIN_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP3 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP3 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP3 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP3 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP3 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP3 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP3 : std_logic := '0';
signal D_DSP3 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_3
-- BEGIN DSP48E1_inst_2
signal MULTISIGNOUT_DSP2 : std_logic := '0';
signal CARRYCASCOUT_DSP2 : std_logic := '0';
signal OVERFLOW_DSP2 : std_logic := '0';
signal PATTERNBDETECT_DSP2 : std_logic := '0';
signal PATTERNDETECT_DSP2 : std_logic := '0';
signal UNDERFLOW_DSP2 : std_logic := '0';
--
signal P_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP2 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP2 : std_logic_vector(17 downto 0) := (others => '0');
signal ACOUT_DSP2 : std_logic_vector(29 downto 0) := (others => '0');
signal BCOUT_DSP2 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP2 : std_logic := '0';
signal MULTISIGNIN_DSP2 : std_logic := '0';
signal PCIN_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP2 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP2 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP2 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP2 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP2 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP2 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP2 : std_logic := '0';
signal D_DSP2 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_2
-- BEGIN DSP48E1_inst_1
signal MULTISIGNOUT_DSP1 : std_logic := '0';
signal CARRYCASCOUT_DSP1 : std_logic := '0';
signal OVERFLOW_DSP1 : std_logic := '0';
signal PATTERNBDETECT_DSP1 : std_logic := '0';
signal PATTERNDETECT_DSP1 : std_logic := '0';
signal UNDERFLOW_DSP1 : std_logic := '0';
--
signal P_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
signal ACOUT_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal BCOUT_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP1 : std_logic := '0';
signal MULTISIGNIN_DSP1 : std_logic := '0';
signal PCIN_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP1 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP1 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP1 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP1 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP1 : std_logic := '0';
signal D_DSP1 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_1
COMPONENT dsp_sreg_block
Generic (
WIDTH : natural;
LENGTH : natural
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT dsp_dff_block
Generic (
Width : natural
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
END COMPONENT;
begin
-- DSP_4 OPMODE: 1010101 (shift PCIN | M | M)
-- ^
-- |
-- DSP_3 OPMODE: 0010101 (PCIN | M | M)
-- ^
-- |
-- DSP_2 OPMODE: 1010101 (shift PCIN | M | M)
-- ^
-- |
-- DSP_1 OPMODE: 0000101 (0 | M | M)
-- ############################################################################
DSP48E1_inst_4 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP4, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP4, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP4, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP4, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP4, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP4, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP4, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP4, -- 30-bit input: A cascade data input
BCIN => BCOUT_DSP3, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP4, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP4, -- 1-bit input: Multiplier sign input
PCIN => PCOUT_DSP3, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP4, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP4, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP4, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP4, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP4, -- 30-bit input: A data input
B => B_DSP4, -- 18-bit input: B data input
C => C_DSP4, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP4, -- 1-bit input: Carry input signal
D => D_DSP4, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
DSP48E1_inst_3 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT_DSP3, -- 30-bit output: A port cascade output
BCOUT => BCOUT_DSP3, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP3, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP3, -- 1-bit output: Multiplier sign cascade output
PCOUT => PCOUT_DSP3, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP3, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP3, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP3, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP3, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP3, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP3, -- 30-bit input: A cascade data input
BCIN => BCIN_DSP3, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP3, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP3, -- 1-bit input: Multiplier sign input
PCIN => PCOUT_DSP2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP3, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP3, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP3, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP3, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP3, -- 30-bit input: A data input
B => B_DSP3, -- 18-bit input: B data input
C => C_DSP3, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP3, -- 1-bit input: Carry input signal
D => D_DSP3, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
DSP48E1_inst_2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT_DSP2, -- 30-bit output: A port cascade output
BCOUT => BCOUT_DSP2, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP2, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP2, -- 1-bit output: Multiplier sign cascade output
PCOUT => PCOUT_DSP2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP2, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP2, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP2, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP2, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP2, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP2, -- 30-bit input: A cascade data input
BCIN => BCOUT_DSP1, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP2, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP2, -- 1-bit input: Multiplier sign input
PCIN => PCOUT_DSP1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP2, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP2, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP2, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP2, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP2, -- 30-bit input: A data input
B => B_DSP2, -- 18-bit input: B data input
C => C_DSP2, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP2, -- 1-bit input: Carry input signal
D => D_DSP2, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
DSP48E1_inst_1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT_DSP1, -- 30-bit output: A port cascade output
BCOUT => BCOUT_DSP1, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP1, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP1, -- 1-bit output: Multiplier sign cascade output
PCOUT => PCOUT_DSP1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP1, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP1, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP1, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP1, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP1, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP1, -- 30-bit input: A cascade data input
BCIN => BCIN_DSP1, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP1, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP1, -- 1-bit input: Multiplier sign input
PCIN => PCIN_DSP1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP1, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP1, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP1, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP1, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP1, -- 30-bit input: A data input
B => B_DSP1, -- 18-bit input: B data input
C => C_DSP1, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP1, -- 1-bit input: Carry input signal
D => D_DSP1, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
-- ############################################################################
ALUMODE_DSP4 <= "0000";
ALUMODE_DSP3 <= "0000";
ALUMODE_DSP2 <= "0000";
ALUMODE_DSP1 <= "0000";
OPMODE_DSP4 <= "1010101"; -- (shift PCIN | M | M)
OPMODE_DSP3 <= "0010101"; -- (PCIN | M | M)
OPMODE_DSP2 <= "1010101"; -- (shift PCIN | M | M)
OPMODE_DSP1 <= "0000101"; -- (0 | M | M)
-- ############################################################################
-- DSP INPUT REGISTERS
-------------------------------------------------------------------------------
IRegA_Dsp4: component dsp_sreg_block
generic map (
WIDTH => 25,
LENGTH => 3
)
port map (
D => A_INPUT(41 downto 17),
CLK => CLK,
RST => RST,
Q => A_DSP4(24 downto 0)
);
IRegA_Dsp3: component dsp_sreg_block
generic map (
WIDTH => 18,
LENGTH => 2
)
port map (
D => A_DSP1(17 downto 0),
CLK => CLK,
RST => RST,
Q => A_DSP3(17 downto 0)
);
IRegB_Dsp3: component dsp_sreg_block
generic map (
WIDTH => 18,
LENGTH => 2
)
port map (
D => B_INPUT(34 downto 17),
CLK => CLK,
RST => RST,
Q => B_DSP3(17 downto 0)
);
IRegA_Dsp2: component dsp_dff_block
generic map (
WIDTH => 25
)
port map (
D => A_INPUT(41 downto 17),
CLK => CLK,
RST => RST,
Q => A_DSP2(24 downto 0)
);
A_DSP1(17 downto 0) <= '0' & A_INPUT(16 downto 0);
B_DSP1(17 downto 0) <= '0' & B_INPUT(16 downto 0);
-------------------------------------------------------------------------------
-- DSP OUTPUT REGISTERS
-------------------------------------------------------------------------------
P_OUTPUT(75 downto 34) <= P_DSP4(41 downto 0);
ORegP_Dsp3: component dsp_dff_block
generic map (
WIDTH => 17
)
port map (
D => P_DSP3(16 downto 0),
CLK => CLK,
RST => RST,
Q => P_OUTPUT(33 downto 17)
);
ORegP_Dsp1: component dsp_sreg_block
generic map (
WIDTH => 17,
LENGTH => 3
)
port map (
D => P_DSP1(16 downto 0),
CLK => CLK,
RST => RST,
Q => P_OUTPUT(16 downto 0)
);
validReg_MUL_int: for i in 0 to DELAY_MUL generate
begin
validdffLeft_MUL: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_MUL(i)
);
end generate validdffLeft_MUL;
--
dffOthers_MUL: if (i > 0 AND i < DELAY_MUL) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_MUL(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_MUL(i)
);
end generate dffOthers_MUL;
--
dffRight_MUL: if i = DELAY_MUL generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_MUL(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_MUL;
end generate validReg_MUL_int;
-- ############################################################################
calc_result : process(clk)
begin
if rising_edge(clk) then
A_INPUT <= (41 downto 32 => '0') & LEFT;
B_INPUT <= (34 downto 32 => '0') & RIGHT;
MUL_OUT <= P_OUTPUT(31 downto 0);
end if;
end process;
READY_OUT <= READY_IN;
end Behavioral;
|
gpl-3.0
|
22b1efd1536bbbf3ce605592028e1079
| 0.488504 | 4.226217 | false | false | false | false |
freecores/w11
|
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
| 1 | 6,943 |
-- $Id: tb_s3board_fusp.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_fusp - sim
-- Description: Test bench for s3board (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- tb_s3board_core
-- s3board_fusp_aif [UUT]
-- serport/serport_uart_rxtx
--
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8
-- 2010-05-01 286 1.0 Initial version (derived from tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board_fusp is
end tb_s3board_fusp;
architecture sim of tb_s3board_fusp is
signal CLK : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLK,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : s3board_fusp_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
24684962c304f3cc6f2fb152f3ff606a
| 0.535647 | 3.138788 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/ben_mem/simulation/ben_mem_tb.vhd
| 1 | 4,484 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ben_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ben_mem_tb IS
END ENTITY;
ARCHITECTURE ben_mem_tb_ARCH OF ben_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ben_mem_synth_inst:ENTITY work.ben_mem_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
9814680b045f2fb0f87b6cbe6f034971
| 0.599911 | 4.413386 | false | false | false | false |
freecores/w11
|
rtl/vlib/simlib/simbus.vhd
| 1 | 1,960 |
-- $Id: simbus.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: simbus
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 remove global clock cycle signal
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package simbus is
signal SB_CLKSTOP : slbit := '0'; -- global clock stop
signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := '0'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
-- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
-- strong ('0','1') drivers. Therefore always remove strenght before
-- using, e.g. with to_x01()
end package simbus;
|
gpl-2.0
|
7ac6f41738bb6d88dfc20bfcf7bdfbce
| 0.593878 | 3.698113 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/tb/tb_serport_uart_rx.vhd
| 1 | 9,998 |
-- $Id: tb_serport_uart_rx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rx - sim
-- Description: Test bench for serport_uart_rx
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_serport_uart_rx [UUT]
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (63488 cl 15.21s)
-- 2007-10-21 91 - 0.26 - - c:ok (63488 cl 7.12s)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-10-22 417 1.0.3 now numeric_std clean
-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_serport_uart_rx is
end tb_serport_uart_rx;
architecture sim of tb_serport_uart_rx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv5 := slv(to_unsigned(15, 5));
signal RXSD : slbit := '1';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_ERR : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_ERR_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_ERR_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_serport_uart_rx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable irxerr : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
type bit_10_array_type is array (0 to 9) of slbit;
type int_10_array_type is array (0 to 9) of integer;
variable valpuls : bit_10_array_type := (others=>'0');
variable delpuls : int_10_array_type := (others=>0);
variable npuls : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
idelta := 0;
while RXACT='1' loop -- ensure that uart isn't active
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
read_ea(iline, irate);
wait for 2*clock_period;
CLKDIV <= slv(to_unsigned(irate-1, CLKDIV'length));
wait for 2*clock_period;
when ".xrate" => -- .xrate
read_ea(iline, irate);
when "puls " => -- puls
writetimestamp(oline, CLK_CYCLE, ": puls ");
read_ea(iline, irxval);
read_ea(iline, irxerr);
read_ea(iline, irxdata);
npuls := 0;
for i in valpuls'range loop
testempty(iline, ok);
if ok then
exit;
end if;
read_ea(iline, valpuls(i));
read_ea(iline, delpuls(i));
assert delpuls(i)>0
report "assert puls length > 0" severity failure;
npuls := npuls + 1;
write(oline, valpuls(i), right, 3);
write(oline, delpuls(i), right, 3);
end loop; -- i
writeline(output, oline);
if npuls > 0 then
N_MON_VAL <= irxval;
N_MON_ERR <= irxerr;
N_MON_DAT <= irxdata;
for i in 0 to npuls-1 loop
RXSD <= valpuls(i);
wait for clock_period;
N_MON_VAL <= '0';
wait for (delpuls(i)-1)*clock_period;
end loop; -- i
end if;
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
RXSD <= '1';
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
N_MON_VAL <= '1';
N_MON_ERR <= '0';
N_MON_DAT <= itxdata;
RXSD <= '0'; -- start bit
wait for clock_period;
N_MON_VAL <= '0';
wait for (irate-1)*clock_period;
RXSD <= '1';
for i in itxdata'reverse_range loop -- transmit lsb first
RXSD <= itxdata(i); -- data bit
wait for irate*clock_period;
end loop;
RXSD <= '1'; -- stop bit
wait for irate*clock_period;
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
idelta := 0;
while RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING ERR="));
write(oline, R_MON_ERR_2);
write(oline, string'(" DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_ERR_2 <= R_MON_ERR_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_ERR_1 <= N_MON_ERR;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_ERR_2 = '0' then
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
else
if RXERR = '1' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, RXERR=1 expected"));
end if;
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
9f734831fc2c91d98e971c2bb7fc4127
| 0.5009 | 3.830651 | false | false | false | false |
freecores/w11
|
rtl/ibus/ibdr_rk11.vhd
| 2 | 18,400 |
-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rk11 - syn
-- Description: ibus dev(rem): RK11-A/B
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
-- BUGFIX: sector counter now counts 000,...,013.
-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
-- BUGFIX: re-work the seek complete handling
-- 2008-08-22 161 1.0.6 use iblib
-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE
-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0
-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code
-- fix bug in control reset logic (we's missing)
-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done
-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET
-- 2008-01-06 111 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_rk11;
architecture syn of ibdr_rk11 is
constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
constant ibaddr_rker : slv3 := "001"; -- rker address offset
constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
subtype rkds_ibf_id is integer range 15 downto 13;
constant rkds_ibf_adry : integer := 6;
constant rkds_ibf_scsa : integer := 4;
subtype rkds_ibf_sc is integer range 3 downto 0;
subtype rker_ibf_he is integer range 15 downto 5;
constant rker_ibf_cse : integer := 1;
constant rker_ibf_wce : integer := 0;
constant rkcs_ibf_err : integer := 15;
constant rkcs_ibf_he : integer := 14;
constant rkcs_ibf_scp : integer := 13;
constant rkcs_ibf_maint : integer := 12;
constant rkcs_ibf_rdy : integer := 7;
constant rkcs_ibf_ide : integer := 6;
subtype rkcs_ibf_mex is integer range 5 downto 4;
subtype rkcs_ibf_func is integer range 3 downto 1;
constant rkcs_ibf_go : integer := 0;
subtype rkda_ibf_drsel is integer range 15 downto 13;
subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id
constant rkmr_ibf_crdone: integer := 11; -- contr. reset done
constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's
constant rkmr_ibf_creset: integer := 9; -- control reset
constant rkmr_ibf_fdone : integer := 8; -- func done
subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done
type state_type is (
s_idle,
s_init
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
id : slv3; -- rkds: drive id of search done
sc : slv4; -- rkds: sector counter
cse : slbit; -- rker: check sum error
wce : slbit; -- rker: write check error
he : slbit; -- rkcs: hard error
scp : slbit; -- rkcs: seek complete
maint : slbit; -- rkcs: maintenance mode
rdy : slbit; -- rkcs: control ready
ide : slbit; -- rkcs: interrupt on done enable
drsel : slv3; -- rkda: currently selected drive
fireq : slbit; -- func done interrupt request flag
sireq : slv8; -- seek done interrupt request flags
sbusy : slv8; -- seek busy flags
rid : slv3; -- drive id for rem ds reads
icnt : slv3; -- init state counter
creset : slbit; -- control reset flag
crdone : slbit; -- control reset done since last fdone
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_init, -- state
(others=>'0'), -- id
(others=>'0'), -- sc
'0','0', -- cse, wce
'0','0','0', -- he, scp, maint
'1', -- rdy (SET TO 1)
'0', -- ide
(others=>'0'), -- drsel
'0', -- fireq
(others=>'0'), -- sireq
(others=>'0'), -- sbusy
(others=>'0'), -- rid
(others=>'0'), -- icnt
'0','1' -- creset, crdone
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv4 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' or R_REGS.creset='1' then
R_REGS <= regs_init;
if R_REGS.creset = '1' then
R_REGS.sbusy <= N_REGS.sbusy;
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable icrip : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iscval : slbit := '0';
variable iscid : slv3 := (others=>'0');
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv4 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
icrip := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc or r.maint;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iscval := '0';
iscid := (others=>'0');
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := '0' & IB_MREQ.addr(3 downto 1);
imem_din := IB_MREQ.din;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
n.ibsel := '1';
end if;
-- internal state machine (for control reset)
case r.state is
when s_idle =>
null;
when s_init =>
ibhold := r.ibsel; -- hold ibus when controller busy
icrip := '1';
n.icnt := slv(unsigned(r.icnt) + 1);
if unsigned(r.icnt) = 7 then
n.state := s_idle;
end if;
when others => null;
end case;
-- ibus transactions
if r.ibsel='1' and ibhold='0' then -- selected and not holding
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
case IB_MREQ.addr(3 downto 1) is
when ibaddr_rkds => -- RKDS -- drive status register ----
if ibrem = '0' then
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr.
else
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr.
end if;
idout(rkds_ibf_id) := r.id;
if ibrem = '0' then -- loc ? simulate drive sector monitor
if r.sc = MEM_DOUT(rkds_ibf_sc) then
idout(rkds_ibf_scsa) := '1';
else
idout(rkds_ibf_scsa) := '0';
end if;
idout(rkds_ibf_sc) := r.sc;
end if;
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
end if;
if ibwrem = '1' then -- rem write ? than update ds data
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rker => -- RKER -- error register ------------
idout(4 downto 2) := (others=>'0'); -- unassigned bits
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !)
idout(rker_ibf_wce) := r.wce;
if ibwrem = '1' then -- rem write ?
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ?
n.he := '1';
else
n.he := '0';
end if;
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rkcs => -- RKCS -- control status register ---
idout(rkcs_ibf_err) := r.he or r.cse or r.wce;
idout(rkcs_ibf_he) := r.he;
idout(rkcs_ibf_scp) := r.scp;
idout(rkcs_ibf_rdy) := r.rdy;
idout(rkcs_ibf_go) := not r.rdy;
if ibw1 = '1' then
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit
end if;
if ibw0 = '1' then
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit
if n.ide = '0' then -- if IE 0 or set to 0
n.fireq := '0'; -- cancel all pending
n.sireq := (others=>'0'); -- interrupt requests
end if;
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ?
if r.rdy = '1' then -- ready and GO ?
n.scp := '0'; -- go clears scp !
n.rdy := '0'; -- mark busy
n.cse := '0'; -- clear soft errors
n.wce := '0';
n.fireq := '0'; -- cancel pend. int
if unsigned(IB_MREQ.din(rkcs_ibf_func))=0 then -- control reset?
n.creset := '1'; -- handle locally
else
ilam := '1'; -- issue lam
end if;
if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek
unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy
end if;
end if;
else -- GO=0
if r.ide = '0' and -- if ide now 0
IB_MREQ.din(rkcs_ibf_ide)='1' and -- and is set to 1
r.rdy='1' then -- and controller ready
n.fireq := '1'; -- issue interrupt
end if;
end if;
end if;
when ibaddr_rkda => -- RKDA -- disk address register -----
if ibrem = '0' then -- loc access ?
if r.rdy = '0' then -- controller busy ?
imem_we0 := '0'; -- suppress write
imem_we1 := '0';
end if;
end if;
if imem_we1 = '1' then
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits
end if;
when ibaddr_rkmr => -- RKMR -- maintenance register ------
idout := (others=>'0');
idout(rkmr_ibf_rid) := r.rid;
idout(rkmr_ibf_crdone) := r.crdone;
idout(rkmr_ibf_sdone) := r.sbusy;
if ibwrem = '1' then -- rem write ?
n.rid := IB_MREQ.din(rkmr_ibf_rid);
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy);
end if;
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone);
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed
n.rdy := '1';
n.crdone := '0';
if r.ide = '1' then
n.fireq := '1';
end if;
end if;
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset
n.creset := '1';
end if;
end if;
when others => -- all other regs
null;
end case;
end if;
iscval := '1';
if r.sireq(7) = '1' then iscid := "111";
elsif r.sireq(6) = '1' then iscid := "110";
elsif r.sireq(5) = '1' then iscid := "101";
elsif r.sireq(4) = '1' then iscid := "100";
elsif r.sireq(3) = '1' then iscid := "011";
elsif r.sireq(2) = '1' then iscid := "010";
elsif r.sireq(1) = '1' then iscid := "001";
elsif r.sireq(0) = '1' then iscid := "000";
else
iscval := '0';
end if;
if r.ide = '1' then
if r.fireq='1' or iscval='1' then
iei_req := '1';
end if;
end if;
if EI_ACK = '1' then -- interrupt executed
if r.fireq = '1' then
n.scp := '0'; -- clear scp flag, is command end
n.fireq := '0';
elsif iscval = '1' then -- was a seek done
n.scp := '1'; -- signal seek complete interrupt
n.id := iscid; -- load id
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
end if;
end if;
if icrip = '1' then -- control reset in progress ?
imem_addr := '0' & r.icnt; -- use icnt as addr
imem_din := (others=>'0'); -- force data to zero
imem_we0 := '1'; -- enable writes
imem_we1 := '1';
end if;
if CE_MSEC = '1' then -- advance sector counter every msec
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
n.sc := (others=>'0');
else
n.sc := slv(unsigned(r.sc) + 1);
end if;
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
|
gpl-2.0
|
40f33e9f0875a2be6c23d284bc781a42
| 0.469891 | 3.687375 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rb_mon.vhd
| 1 | 4,933 |
-- $Id: rb_mon.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon - sim
-- Description: rbus monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rblib.all;
entity rb_mon is -- rbus monitor (for tb's)
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon;
architecture sim of rb_mon is
begin
proc_moni: process
variable oline : line;
variable nhold : integer := 0;
variable data : slv16 := (others=>'0');
variable tag : string(1 to 8) := (others=>' ');
variable err : slbit := '0';
procedure write_data(L: inout line;
tag: in string;
data: in slv16;
nhold: in integer := 0;
cond: in boolean := false;
ctxt: in string := " ") is
begin
writetimestamp(L, CLK_CYCLE, tag);
write(L, RB_MREQ.addr, right, 10);
write(L, string'(" "));
writegen(L, data, right, 0, DBASE);
write(L, RB_STAT, right, 4);
if nhold > 0 then
write(L, string'(" nhold="));
write(L, nhold);
end if;
if cond then
write(L, ctxt);
end if;
writeline(output, L);
end procedure write_data;
begin
loop
if ENA = '0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
if RB_SRES.err = '1' then
err := '1';
end if;
if RB_SRES.busy = '1' then
nhold := nhold + 1;
else
data := (others=>'0');
tag := ": ???? ";
if RB_MREQ.re = '1' then
data := RB_SRES.dout;
tag := ": rbre ";
end if;
if RB_MREQ.we = '1' then
data := RB_MREQ.din;
tag := ": rbwe ";
end if;
write_data(oline, tag, data, nhold, err='1', " ERR='1'");
nhold := 0;
end if;
else
if nhold > 0 then
write_data(oline, tag, data, nhold, true, " TIMEOUT");
end if;
nhold := 0;
err := '0';
end if;
if RB_MREQ.init = '1' then -- init
if RB_MREQ.we = '1' then
write_data(oline, ": rbini ", RB_MREQ.din); -- external
else
write_data(oline, ": rbint ", RB_MREQ.din); -- internal
end if;
end if;
if unsigned(RB_LAM) /= 0 then
write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active");
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
cf695b660cf2a8aa9f22bfa0dc1f6009
| 0.511251 | 3.554035 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/sn_humanio.vhd
| 1 | 4,227 |
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio - syn
-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3
--
-- Dependencies: xlib/iob_reg_o_gen
-- bpgen/bp_swibtnled
-- bpgen/sn_4x7segctl
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
-- 2011-07-02 387 1.1.2 use bp_swibtnled
-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
-- 2010-04-10 275 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio;
architecture syn of sn_humanio is
signal N_ANO_N : slv4 := (others=>'0');
signal N_SEG_N : slv8 := (others=>'0');
begin
IOB_ANO_N : iob_reg_o_gen
generic map (DWIDTH => 4)
port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
IOB_SEG_N : iob_reg_o_gen
generic map (DWIDTH => 8)
port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
BWIDTH => BWIDTH,
LWIDTH => 8,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
DRV : sn_4x7segctl
generic map (
CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
port map (
CLK => CLK,
DIN => DSP_DAT,
DP => DSP_DP,
ANO_N => N_ANO_N,
SEG_N => N_SEG_N
);
end syn;
|
gpl-2.0
|
d601a87cdb41901b9db26569a624ebf2
| 0.507452 | 3.461916 | false | false | false | false |
superboy0712/MIPS
|
MIPS_ALU_ctrl.vhd
| 1 | 1,963 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:12:28 10/16/2014
-- Design Name:
-- Module Name: MIPS_ALU_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MIPS_ALU_ctrl is
Port ( funct_code : in STD_LOGIC_VECTOR (5 downto 0);
ALU_op : in STD_LOGIC_VECTOR (1 downto 0);
ALU_ctrl : out STD_LOGIC_VECTOR (3 downto 0));
end MIPS_ALU_ctrl;
architecture Behavioral of MIPS_ALU_ctrl is
begin
process(funct_code, ALU_op)
variable alu_ctrl_tmp : std_logic_vector (3 downto 0);
begin
--
alu_ctrl_tmp := (others => 'X');
--
if ALU_op = "00" then -- LW/SW
alu_ctrl_tmp := "0010";
elsif ALU_op(0) = '1' then -- BEQ
alu_ctrl_tmp := "0110";
elsif ALU_op(1) = '1' then -- R type
if funct_code( 3 downto 0 ) = "0000" then -- add
alu_ctrl_tmp := "0010";
elsif funct_code( 3 downto 0 ) = "0010" then-- sub
alu_ctrl_tmp := "0110";
elsif funct_code( 3 downto 0 ) = "0100" then-- and
alu_ctrl_tmp := "0000";
elsif funct_code( 3 downto 0 ) = "0101" then-- or
alu_ctrl_tmp := "0001";
elsif funct_code( 3 downto 0 ) = "1010" then-- slt
alu_ctrl_tmp := "0111";
--
end if;
else alu_ctrl_tmp := (others => 'X');
end if;
ALU_ctrl <= alu_ctrl_tmp;
end process;
end Behavioral;
|
mit
|
3c6a51c50bd55db3f31b6c7be55a2718
| 0.556801 | 3.25539 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_psr.vhd
| 2 | 5,986 |
-- $Id: pdp11_psr.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_psr - syn
-- Description: pdp11: processor status word register
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_psr;
architecture syn of pdp11_psr is
constant ibaddr_psr : slv16 := slv(to_unsigned(8#177776#,16));
signal IBSEL_PSR : slbit := '0';
signal R_PSW : psw_type := psw_init; -- ps register
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_psr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PSR
);
proc_ibres: process (IBSEL_PSR, IB_MREQ, R_PSW)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_PSR = '1' then
idout(psw_ibf_cmode) := R_PSW.cmode;
idout(psw_ibf_pmode) := R_PSW.pmode;
idout(psw_ibf_rset) := R_PSW.rset;
idout(psw_ibf_pri) := R_PSW.pri;
idout(psw_ibf_tflag) := R_PSW.tflag;
idout(psw_ibf_cc) := R_PSW.cc;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PSR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_psw : process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_PSW <= psw_init;
else
if CCWE = '1' then
R_PSW.cc <= CCIN;
end if;
if WE = '1' then
case FUNC is
when c_psr_func_wspl => -- wspl
R_PSW.pri <= DIN(2 downto 0);
when c_psr_func_wcc => -- wcc
if DIN(4) = '1' then -- set cc opcodes
R_PSW.cc <= R_PSW.cc or DIN(3 downto 0);
else -- clear cc opcodes
R_PSW.cc <= R_PSW.cc and not DIN(3 downto 0);
end if;
when c_psr_func_wint => -- wint (interupt handling)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.cmode; -- save current mode
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wrti => -- wrti (rti/rtt in non-kernel mode)
R_PSW.cmode <= R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.pmode or DIN(psw_ibf_pmode) or
R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.rset <= R_PSW.rset or DIN(psw_ibf_rset);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wall => -- wall (rti/rtt kernel mode)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= DIN(psw_ibf_pmode);
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when others => null;
end case;
end if;
end if;
if IBSEL_PSR='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_PSW.cmode <= IB_MREQ.din(psw_ibf_cmode);
R_PSW.pmode <= IB_MREQ.din(psw_ibf_pmode);
R_PSW.rset <= IB_MREQ.din(psw_ibf_rset);
end if;
if IB_MREQ.be0 = '1' then
R_PSW.pri <= IB_MREQ.din(psw_ibf_pri);
R_PSW.cc <= IB_MREQ.din(psw_ibf_cc);
end if;
end if;
end if;
end process proc_psw;
PSW <= R_PSW;
end syn;
|
gpl-2.0
|
8238aa1203d8ac59b141ef67693045a9
| 0.503842 | 3.395349 | false | false | false | false |
palbicoc/AUX_Bus
|
AUX_bus.srcs/sources_1/new/auxbus.vhd
| 1 | 220,378 |
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: xpack.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description: AUXBUS Slave Implementation
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 1.0 - 03/2016 - Albicocco P. - First Version
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package xpack is
-----------------------------------------------------------------
---- TYPES ----
-----------------------------------------------------------------
type test_data_pattern is array (0 to 3) of std_logic_vector(11 downto 0);
-------- CLK PERIOD -------
constant clock_period : integer := 5;
-----------------------------------------------------------------
---- RECORDS ----
-----------------------------------------------------------------
--------------------
-- ro_reg
--------------------
type ro_reg_type is
record
-------- TRIGGER -------
-- A FIFO Trigger Number (Test Mode)
atest_Ntrig : std_logic_vector (11 downto 0);
-- B FIFO Trigger Number (Test Mode)
btest_Ntrig : std_logic_vector (11 downto 0);
-- Voted Trigger Number Valid
Ntrig_voter_v : std_logic;
-- Voted Trigger Number
Ntrig_voter : std_logic_vector (11 downto 0);
-- Local Trigger Number
Ntrig_local : std_logic_vector (11 downto 0);
-- FPGA A Trigger Number
Ntrig_devA : std_logic_vector (11 downto 0);
-- FPGA B Trigger Number
Ntrig_devB : std_logic_vector (11 downto 0);
-------- XFIFO -------
-- A FIFO Full
AFIFO_isfull : std_logic;
-- A FIFO Almost Full
AFIFO_isafull : std_logic;
-- A FIFO Prog Full
AFIFO_ispfull : std_logic;
-- A FIFO Empty
AFIFO_isempty : std_logic;
-- B FIFO Full
BFIFO_isfull : std_logic;
-- B FIFO Almost Full
BFIFO_isafull : std_logic;
-- B FIFO Prog Full
BFIFO_ispfull : std_logic;
-- B FIFO Empty
BFIFO_isempty : std_logic;
-------- AXI FIFO Regs and Signals -------
-- A read data (Reg?)
A_read_data : std_logic_vector (21 DOWNTO 0);
-- A FIFO empty (not valid) (Sig)
A_empty : std_logic;
-- A Almost Full (Sig)
A_afull : std_logic;
-- B read data (Reg?)
B_read_data : std_logic_vector (21 DOWNTO 0);
-- B FIFO empty (not valid) (Sig)
B_empty : std_logic;
-- B Almost Full (Sig)
B_afull : std_logic;
end record;
--------------------
-- rw_reg
--------------------
type rw_reg_type is
record
-------- RESET -------
-- Reset Aux Bus
reset : std_logic;
-- Reset FIFOs
fiforeset : std_logic;
-- Trigger Counters Reset (A+B+Local)
triggerreset : std_logic;
-------- TEST -------
-- Enable Test Mode: 0 Disable, 1 Enable.
test_mode : std_logic;
-- Trigger Mode : 1: Voted Trigger Mode : '0' : Localtrigger (Count trigger only in Local FPGA)
trig_mode : std_logic;
-- Test Trigger Number -- Unused
test_Ntrig : std_logic_vector (11 DOWNTO 0);
-- A Busy flag in test mode
A_is_busy : std_logic;
-- B Busy flag in test mode
B_is_busy : std_logic;
-------- AXI FIFO Regs and Signals -------
-- Enable Read from A FIFO (Reg)
A_FIFO_read_en : std_logic;
-- A Read Enable (Sig)
A_read_en : std_logic;
-- Enable Write to A FIFO (Sig)
A_FIFO_write_en : std_logic;
-- A write data (Reg?)
A_write_data : std_logic_vector (31 DOWNTO 0);
-- A Write Enable (Sig)
A_write_en : std_logic;
-- Enable Read from B FIFO (Reg)
B_FIFO_read_en : std_logic;
-- B read enable (Sig)
B_read_en : std_logic;
-- Enable Write to B FIFO (Sig)
B_FIFO_write_en : std_logic;
-- B write data (Reg?)
B_write_data : std_logic_vector (31 DOWNTO 0);
-- B Write Enable (Sig)
B_write_en : std_logic;
-------- TEST PATTERN --------
-- Enable A Fixed Pattern
A_pattern_isfixed: std_logic;
-- Number of events for A (0 to 4)
A_Nevent : std_logic_vector (2 DOWNTO 0);
-- 4 pattern registers for A
A_event_data : test_data_pattern;
-- Enable B Fixed Pattern
B_pattern_isfixed: std_logic;
-- Number of events for B (0 to 4)
B_Nevent : std_logic_vector (2 DOWNTO 0);
-- 4 pattern registers for B
B_event_data : test_data_pattern;
-------- AUX TIMING --------
-- Delay to be added to the required 35 ns setup time.
thold35 : std_logic_vector (7 DOWNTO 0);
-- Delay to be added to the required 15 ns setup time.
thold15 : std_logic_vector (7 DOWNTO 0);
end record;
------------------------------------------------------------------
---- CONSTANTS ----
------------------------------------------------------------------
constant rw_defaults : rw_reg_type := (
-------- RESET -------
'0', -- Reset Aux Bus
'0', -- Reset FIFOs
'0', -- Trigger Counters Reset (A+B+Local)
-------- TEST -------
'0', -- test_mode - Enable Test Mode: 0 Disable, 1 Enable.
'1', -- Trigger Test Mode : '0' : count real trigger, '1' : Count trigger only in Local FPGA.
x"555", -- Test Trigger Number
'0', -- A Busy flag in test mode
'0', -- B Busy flag in test mode
-------- AXI FIFO -------
'0', -- Enable Read from A FIFO
'0', -- A Read Enable
'0', -- Enable Write to A FIFO
(others => '0'), -- A write data
'0', -- A Write Enable
'0', -- Enable Read from B FIFO
'0', -- B read enable
'0', -- Enable Write to B FIFO
(others => '0'), -- B write data
'0', -- B Write Enable
--------- TEST PATTERN --------
'0', -- Enable A Fixed Pattern
"001", -- Number of events for A (0 to 4)
(x"AAA", x"555", x"0F0", x"F0F"), -- A pattern
'0', -- Enable B Fixed Pattern
"001", -- Number of events for B (0 to 4)
(x"AAA", x"555", x"0F0", x"F0F"), -- B pattern
-------- AUX TIMING --------
x"24",--(others => '0'), -- thold 35
x"24"--(others => '0') -- thold 15
);
------------------------------------------------------------------
---- FUNCTIONS ----
------------------------------------------------------------------
--------------------
-- or_reduce
--------------------
function or_reduce(x: std_logic_vector) return std_logic;
--------------------
-- and_reduce
--------------------
function and_reduce(x : std_logic_vector) return std_logic;
--------------------
-- log2
--------------------
function log2( i : integer) return integer;
end xpack;
package body xpack is
------------------------------------------------------------------
---- FUNCTIONS ----
------------------------------------------------------------------
--------------------
-- or_reduce
--------------------
function or_reduce(x : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end or_reduce;
--------------------
-- and_reduce
--------------------
function and_reduce(x : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in x'range loop
r := r and x(i);
end loop;
return r;
end and_reduce;
--------------------
-- log2
--------------------
function log2( i : integer) return integer is
variable t : integer := i;
variable r : integer := 0;
begin
while t > 1 loop
r := r + 1;
t := t / 2;
end loop;
return r;
end function;
end xpack;
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: auxbus.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description: AUXBUS Slave Implementation
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 1.0 - 02/2016 - Albicocco P. - First Version
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.xpack.all;
entity auxbus is
Generic (
-------- CLK PERIOD -------
-- clock_period : integer := 10; moved in xpack
-------- AXI-4 LITE -------
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 9
);
Port (
-------- SYSTEM PORTS -------
-- System clock
clk : in STD_LOGIC;
clk2x : in STD_LOGIC;
-- System reset
rst : in STD_LOGIC;
-------- Trigger PORTS -------
-- Local Input Trigger
trig_in : in STD_LOGIC;
-- A Input Trigger
atrig_det : in STD_LOGIC;
-- B Input Trigger
btrig_det : in STD_LOGIC;
-------- A FIFO Interface -------
A_Wr_clk : in STD_LOGIC;
A_Din : in STD_LOGIC_VECTOR(22-1 DOWNTO 0);
A_Wr_en : in STD_LOGIC;
A_Full : out STD_LOGIC;
A_Almost_full : out STD_LOGIC;
A_Prog_full : out STD_LOGIC;
A_Empty : out STD_LOGIC;
-------- B FIFO Interface -------
B_Wr_clk : in STD_LOGIC;
B_Din : in STD_LOGIC_VECTOR(22-1 DOWNTO 0);
B_Wr_en : in STD_LOGIC;
B_Full : out STD_LOGIC;
B_Almost_full : out STD_LOGIC;
B_Prog_full : out STD_LOGIC;
B_Empty : out STD_LOGIC;
-------- AXI-4 LITE -------
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-------- ROCK OUTPUT -------
-- Trigger Bus, first valid trigger is 001
xt : in STD_LOGIC_VECTOR (11 downto 0);
-- Trigger Bus Data is valide, Active LOW
xtrgv_n : in STD_LOGIC;
-- Address Bus
xa : in STD_LOGIC_VECTOR (3 downto 0);
-- Address Bus is Valid
xas_n : in STD_LOGIC;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
xds : in STD_LOGIC;
-- Master is initiating a synch check, Active LOW
xsyncrd_n : in STD_LOGIC;
-- ROCK send a system HALT due to Error,
xsyshalt : in STD_LOGIC;
-- ROCK produces a create level AUX reset
xsysreset : in STD_LOGIC;
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave xsds bit is valid, Active HIGH
xbk : out STD_LOGIC;
-- Slave has an error, Active LOW
xberr_n : out STD_LOGIC;
-- Slave is full, Active LOW
xbusy_n : out STD_LOGIC;
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
xsel_n : out STD_LOGIC;
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk : out STD_LOGIC;
-- Actual Slave Data Word is the last, Active LOW
xeob_n : out STD_LOGIC;
-- Slave Data
xd : out STD_LOGIC_VECTOR (19 downto 0);
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds : out STD_LOGIC;
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
sa : in STD_LOGIC_VECTOR (3 downto 0);
-------- EXTERNAL DEVICE SELECTION -------
-- Use external Device Selection, Active HIGH
ext_s_en : in STD_LOGIC;
-- External Device selection , Active HIGH
x_ssel : in STD_LOGIC;
-------- AUX BUS ENABLE -------
-- Enable AUXBUS
AUX_Enable : in STD_LOGIC
);
end auxbus;
architecture rtl of auxbus is
------------------------------------------------------------------
---- COMPONENTS DECLARATION----
------------------------------------------------------------------
--------------------
-- xTRIG
--------------------
-- Trigger Counters and Voter.
--------------------
component xtrig is
Port (
-------- System Signals -------
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-------- Status Registers -------
ro_reg : out ro_reg_type;
-------- Ctrl Registers -------
rw_reg : in rw_reg_type;
-------- Trigger Signals -------
-- Local Input Trigger
trig_in : in STD_LOGIC;
-- A Input Trigger
atrig_det : in STD_LOGIC;
-- B Input Trigger
btrig_det : in STD_LOGIC;
-- Output Trigger
trigger : out STD_LOGIC_VECTOR(11 DOWNTO 0);
-- Output Trigger Valid
trigger_v : out STD_LOGIC
);
end component xtrig;
--------------------
-- xTEST
--------------------
-- Protocol Test Environment.
--------------------
component xtest is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-------- Status Registers -------
ro_reg : out ro_reg_type;
-------- Ctrl Registers -------
rw_reg : in rw_reg_type;
-------- Test Control Bit -------
test_mode : out STD_LOGIC;
-------- Input Trigger -------
trigger : in STD_LOGIC_VECTOR(11 DOWNTO 0);
-------- A FIFO Interface -------
A_Wr_clk : in STD_LOGIC;
A_Din : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
A_Wr_en : out STD_LOGIC;
A_Full : in STD_LOGIC;
A_Almost_full : in STD_LOGIC;
A_Prog_full : in STD_LOGIC;
A_busy : out STD_LOGIC;
-------- B FIFO Interface -------
B_Wr_clk : in STD_LOGIC;
B_Din : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
B_Wr_en : out STD_LOGIC;
B_Full : in STD_LOGIC;
B_Almost_full : in STD_LOGIC;
B_Prog_full : in STD_LOGIC;
B_busy : out STD_LOGIC
);
end component xtest;
--------------------
-- xFIFO
--------------------
-- 2 FIFO receiving data from AFE.
--------------------
component xfifo is
Port (
Rst : in STD_LOGIC;
Rd_clk : in STD_LOGIC;
-------- A FIFO Interface -------
A_Wr_clk : in STD_LOGIC;
A_Din : in STD_LOGIC_VECTOR(22-1 DOWNTO 0);
A_Wr_en : in STD_LOGIC;
A_Full : out STD_LOGIC;
A_Almost_full : out STD_LOGIC;
A_Prog_full : out STD_LOGIC;
A_Rd_en : in STD_LOGIC;
A_Dout : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
A_Empty : out STD_LOGIC;
A_Valid : out STD_LOGIC;
-------- B FIFO Interface -------
B_Wr_clk : in STD_LOGIC;
B_Din : in STD_LOGIC_VECTOR(22-1 DOWNTO 0);
B_Wr_en : in STD_LOGIC;
B_Full : out STD_LOGIC;
B_Almost_full : out STD_LOGIC;
B_Prog_full : out STD_LOGIC;
B_Rd_en : in STD_LOGIC;
B_Dout : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
B_Empty : out STD_LOGIC;
B_Valid : out STD_LOGIC
);
end component;
--------------------
-- xCTRL
--------------------
-- xCTRL provide data saved in FIFO to the auxbus when requested.
--------------------
component xctrl is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- A FIFO Side
a_d : in STD_LOGIC_VECTOR(21 downto 0);
a_dv : in STD_LOGIC;
a_rd_en : out STD_LOGIC;
-- B FIFO Side
b_d : in STD_LOGIC_VECTOR(21 downto 0);
b_dv : in STD_LOGIC;
b_rd_en : out STD_LOGIC;
-- AUXBUS Side
-- Data, Data Valid, Last Event Data and New Event or Data Request
x_d : buffer STD_LOGIC_VECTOR(19 downto 0);
x_dv : out STD_LOGIC;
x_last : out STD_LOGIC;
x_rd_en : in STD_LOGIC;
-- Header Number and Header Number Valid (Valid is asserted when related data is ready)
x_hdr_d : buffer STD_LOGIC_VECTOR(19 downto 0);
x_hdr_dv : out STD_LOGIC;
-- Actual Header has no data
x_nodata : out STD_LOGIC;
--Error: Header Number Mismatch between A and B FIFO
x_mmatch : out STD_LOGIC
);
end component;
--------------------
-- xFRONT
--------------------
-- xFRONT manage the auxbus signals.
--------------------
component xfront is
Generic (
clock_period : integer := 10
);
Port (
-------- SYSTEM SIGNALS -------
-- System clock
clk : in STD_LOGIC;
clk2x : in STD_LOGIC;
-- System reset
rst : in STD_LOGIC;
-------- Ctrl Registers -------
rw_reg : in rw_reg_type;
-------- Control Interface -------
-- Trigger Number
i_t : in STD_LOGIC_VECTOR(11 downto 0);
-- Trigger Number Data Valid
i_tv : in STD_LOGIC;
-- Trigger Number Request
i_t_req : out STD_LOGIC;
-- Data, Data Valid, Last Event Data and New Event or Data Request
i_d : in STD_LOGIC_VECTOR(19 downto 0);
i_dv : in STD_LOGIC;
i_last : in STD_LOGIC;
i_rd_en : out STD_LOGIC;
-- Header Number and Header Number Valid (Valid is asserted when related data is ready)
i_hdr_d : in STD_LOGIC_VECTOR(11 downto 0);
i_hdr_dv : in STD_LOGIC;
-- Actual Header has no data
i_nodata : in STD_LOGIC;
--Error: Header Number Mismatch between A and B FIFO
i_mmatch : in STD_LOGIC;
-- FIFO Full Flag, propagated and kept to xbusy
i_full : in STD_LOGIC;
-------- ROCK OUTPUT -------
-- Trigger Bus, first valid trigger is 001
xt : in STD_LOGIC_VECTOR (11 downto 0);
-- Trigger Bus Data is valide, Active LOW
xtrgv_n : in STD_LOGIC;
-- Address Bus
xa : in STD_LOGIC_VECTOR (3 downto 0);
-- Address Bus is Valid
xas_n : in STD_LOGIC;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
xds : in STD_LOGIC;
-- Master is initiating a synch check, Active LOW
xsyncrd_n : in STD_LOGIC;
-- ROCK send a system HALT due to Error,
xsyshalt : in STD_LOGIC;
-- ROCK produces a create level AUX reset
xsysreset : in STD_LOGIC;
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave xsds bit is valid, Active HIGH
xbk : out STD_LOGIC;
-- Slave has an error, Active LOW
xberr_n : out STD_LOGIC;
-- Slave is full, Active LOW
xbusy_n : out STD_LOGIC;
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
xsel_n : out STD_LOGIC;
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk : out STD_LOGIC;
-- Actual Slave Data Word is the last, Active LOW
xeob_n : out STD_LOGIC;
-- Slave Data
xd : out STD_LOGIC_VECTOR (19 downto 0);
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds : out STD_LOGIC;
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
sa : in STD_LOGIC_VECTOR (3 downto 0);
-------- EXTERNAL DEVICE SELECTION -------
-- Use external Device Selection, Active HIGH
ext_s_en : in STD_LOGIC;
-- External Device selection , Active HIGH
x_ssel : in STD_LOGIC
);
end component;
--------------------
-- xAXI
--------------------
-- AXI-4 LITE Control and Status Registers.
--------------------
component xaxi is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 9
);
port (
-------- Status Registers -------
ro_reg : in ro_reg_type;
-------- Ctrl Registers -------
rw_reg : out rw_reg_type;
-------- AXI-4 PORTS -------
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (i ssued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end component xaxi;
------------------------------------------------------------------
---- SIGNALS DECLARATION ----
------------------------------------------------------------------
-------- Status Registers -------
signal ro_reg : ro_reg_type;
signal ro_reg_xtest: ro_reg_type;
signal ro_reg_xtrig: ro_reg_type;
-------- Ctrl Registers -------
signal rw_reg : rw_reg_type;
--------------------
-- xTRIG
--------------------
-- Trigger Counters and Voter.
--------------------
signal xtrig_reset : STD_LOGIC;
signal trigger : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal trigger_v : STD_LOGIC;
--------------------
-- xTEST
--------------------
-- xtest Reset
signal xtest_reset : STD_LOGIC;
-- Test Control Bit
signal test_mode : STD_LOGIC;
-- A FIFO Side
signal A_Din_t : STD_LOGIC_VECTOR(21 downto 0);
signal A_Wr_en_t : STD_LOGIC;
signal A_busy_t : STD_LOGIC;
-- B FIFO Side
signal B_Din_t : STD_LOGIC_VECTOR(21 downto 0);
signal B_Wr_en_t : STD_LOGIC;
signal B_busy_t : STD_LOGIC;
-- FIFOs Common
signal busy_t : STD_LOGIC;
--------------------
-- xFIFO
--------------------
-- FIFOs' reset
signal xfifo_reset : std_logic;
-- A FIFO Side
signal A_Din_i : STD_LOGIC_VECTOR(21 downto 0);
signal A_Wr_en_i : STD_LOGIC;
signal a_d : STD_LOGIC_VECTOR(21 downto 0);
signal a_dv : STD_LOGIC;
signal a_rd_en : STD_LOGIC;
signal afull : STD_LOGIC;
signal aafull : STD_LOGIC;
signal apfull : STD_LOGIC;
signal aempty : STD_LOGIC;
-- B FIFO Side
signal B_Din_i : STD_LOGIC_VECTOR(21 downto 0);
signal B_Wr_en_i : STD_LOGIC;
signal b_d : STD_LOGIC_VECTOR(21 downto 0);
signal b_dv : STD_LOGIC;
signal b_rd_en : STD_LOGIC;
signal bfull : STD_LOGIC;
signal bafull : STD_LOGIC;
signal bpfull : STD_LOGIC;
signal bempty : STD_LOGIC;
-- FIFOs Common
signal full_i : STD_LOGIC;
--------------------
-- xCTRL
--------------------
-- xCTRL reset
signal xctrl_reset : std_logic;
-------- FIFO Interface -------
signal a_dv_xctrl : std_logic;
signal b_dv_xctrl : std_logic;
signal a_rd_en_xctrl : std_logic;
signal b_rd_en_xctrl : std_logic;
-------- Control Interface -------
-- Data, Data Valid, Last Event Data and New Event or Data Request
signal d : STD_LOGIC_VECTOR(19 downto 0);
signal dv : STD_LOGIC;
signal last : STD_LOGIC;
signal rd_en : STD_LOGIC;
-- Header Number and Header Number Valid (Valid is asserted when related data is ready)
signal hdr_d : STD_LOGIC_VECTOR(19 downto 0);
signal hdr_dv : STD_LOGIC;
-- Actual Header has no data
signal nodata : STD_LOGIC;
--Error: Header Number Mismatch between A and B FIFO
signal mmatch : STD_LOGIC;
-- FIFO Full Flag, propagated and kept to xbusy
signal full : STD_LOGIC;
--------------------
-- xFRONT
--------------------
-- xFRONT reset
signal xfront_reset: STD_LOGIC;
begin
--------------------
-- xTRIG
--------------------
-- Trigger Counters and Voter.
--------------------
xtrig_reset <= rst or rw_reg.reset or rw_reg.triggerreset;
xtrig_inst: xtrig
Port Map(
-------- System Signals -------
clk => clk,
rst => xtrig_reset,
-------- Status Registers -------
ro_reg => ro_reg_xtrig,
-------- Ctrl Registers -------
rw_reg => rw_reg,
-------- Trigger Signals -------
-- Local Input Trigger
trig_in => trig_in,
-- A Input Trigger
atrig_det => atrig_det,
-- B Input Trigger
btrig_det => btrig_det,
-- Output Trigger
trigger => trigger,
-- Output Trigger Valid
trigger_v => trigger_v
);
-- Voted Trigger Number Valid
ro_reg.Ntrig_voter_v <= ro_reg_xtrig.Ntrig_voter_v;
-- Voted Trigger Number
ro_reg.Ntrig_voter <= ro_reg_xtrig.Ntrig_voter;
-- Local Trigger Number
ro_reg.Ntrig_local <= ro_reg_xtrig.Ntrig_local;
-- FPGA A Trigger Number
ro_reg.Ntrig_devA <= ro_reg_xtrig.Ntrig_devA;
-- FPGA B Trigger Number
ro_reg.Ntrig_devB <= ro_reg_xtrig.Ntrig_devB;
--------------------
-- xTEST
--------------------
-- Protocol Test Environment.
--------------------
xtest_reset <= rst or rw_reg.reset;
xtest_int: xtest
Port Map (
clk => clk,
rst => xtest_reset,
-------- Status Registers -------
ro_reg => ro_reg_xtest,
-------- Ctrl Registers -------
rw_reg => rw_reg,
-------- Test Control Bit -------
test_mode => test_mode,
-------- Input Trigger -------
trigger => trigger,
-------- A FIFO Interface -------
A_Wr_clk => A_Wr_clk,
A_Din => A_Din_t,
A_Wr_en => A_Wr_en_t,
A_Full => afull,
A_Almost_full => aafull,
A_Prog_full => apfull,
A_busy => A_busy_t,
-------- B FIFO Interface -------
B_Wr_clk => B_Wr_clk,
B_Din => B_Din_t,
B_Wr_en => B_Wr_en_t,
B_Almost_full => bafull,
B_Full => bfull,
B_Prog_full => bpfull,
B_busy => B_busy_t
);
-------- XTEST Status Register -------
ro_reg.atest_Ntrig <= ro_reg_xtest.atest_Ntrig;
ro_reg.btest_Ntrig <= ro_reg_xtest.btest_Ntrig;
--------------------
-- xFIFO
--------------------
xfifo_reset <= rst or rw_reg.fiforeset or rw_reg.reset;
A_Full <= afull;
B_Full <= bfull;
A_Prog_full <= apfull;
B_Prog_full <= bpfull;
A_Empty <= aempty;
B_Empty <= bempty;
xfifo_inst: xfifo
Port Map(
Rst => xfifo_reset,
Rd_clk => clk,
-------- A FIFO Interface -------
A_Wr_clk => A_Wr_clk,
A_Din => A_Din_i,
A_Wr_en => A_Wr_en_i,
A_Full => afull,
A_Almost_full => aafull,
A_Prog_full => apfull,
A_Rd_en => a_rd_en,
A_Dout => a_d,
A_Empty => aempty,
A_Valid => a_dv,
-------- B FIFO Interface -------
B_Wr_clk => B_Wr_clk,
B_Din => B_Din_i,
B_Wr_en => B_Wr_en_i,
B_Full => bfull,
B_Almost_full => bafull,
B_Prog_full => bpfull,
B_Rd_en => b_rd_en,
B_Dout => b_d,
B_Empty => bempty,
B_Valid => b_dv
);
-------- XFIFO Status Register -------
-- A FIFO Full
ro_reg.AFIFO_isfull <= afull;
-- A FIFO Almost Full
ro_reg.AFIFO_isafull <= aafull;
-- A FIFO Prog Full
ro_reg.AFIFO_ispfull <= apfull;
-- A FIFO Empty
ro_reg.AFIFO_isempty <= aempty; --not a_dv;
-- B FIFO Full
ro_reg.BFIFO_isfull <= bfull;
-- B FIFO Almost Full
ro_reg.BFIFO_isafull <= bafull;
-- B FIFO Prog Full
ro_reg.BFIFO_ispfull <= bpfull;
-- B FIFO Empty
ro_reg.BFIFO_isempty <= bempty; --not b_dv;
-------- FIFO AXI/Test/Normal Mode -------
-- Data Read to XAXI
ro_reg.A_read_data <= a_d when rw_reg.A_FIFO_read_en = '1' else
(others => '0');
ro_reg.B_read_data <= b_d when rw_reg.B_FIFO_read_en = '1' else
(others => '0');
-- Empty to XAXI
ro_reg.A_empty<= not a_dv when rw_reg.A_FIFO_read_en = '1' else
'0';
ro_reg.B_empty<= not b_dv when rw_reg.B_FIFO_read_en = '1' else
'0';
-- Full to XAXI
ro_reg.A_afull<= aafull when rw_reg.A_FIFO_write_en = '1' else
'0';
ro_reg.B_afull<= bafull when rw_reg.B_FIFO_write_en = '1' else
'0';
-- Data Read to XCTRL
-- Directly connected
-- Data Valid to XCTRL
a_dv_xctrl <= '0' when rw_reg.A_FIFO_read_en = '1' or rw_reg.B_FIFO_read_en = '1' else
a_dv;
b_dv_xctrl <= '0' when rw_reg.A_FIFO_read_en = '1' or rw_reg.B_FIFO_read_en = '1' else
b_dv;
-- Full to XFRONT
full_i <= --'0' when rw_reg.A_FIFO_write_en = '1' or rw_reg.B_FIFO_write_en = '1' else
--busy_t when test_mode = '1' else
'0' when aempty='1' and bempty='1' else
full;
busy_t <= A_busy_t or B_busy_t;
-- Data Read Enable to XFIFO
a_rd_en <= rw_reg.A_read_en when rw_reg.A_FIFO_read_en = '1' else
'0' when rw_reg.B_FIFO_read_en = '1' else
a_rd_en_xctrl;
b_rd_en <= rw_reg.B_read_en when rw_reg.B_FIFO_read_en = '1' else
'0' when rw_reg.A_FIFO_read_en = '1' else
b_rd_en_xctrl;
-- Data Write to XFIFO
A_Din_i <= rw_reg.A_write_data (21 DOWNTO 0)
when rw_reg.A_FIFO_write_en = '1' else
(others => '0') when rw_reg.B_FIFO_write_en = '1' else
A_Din_t when test_mode = '1' else
A_Din;
B_Din_i <= rw_reg.B_write_data (21 DOWNTO 0)
when rw_reg.B_FIFO_write_en = '1' else
(others => '0') when rw_reg.A_FIFO_write_en = '1' else
B_Din_t when test_mode = '1' else
B_Din;
-- Write Enable to XFIFO
A_Wr_en_i <= rw_reg.A_write_en when rw_reg.A_FIFO_write_en = '1' else
'0' when rw_reg.B_FIFO_write_en = '1' else
A_Wr_en_t when test_mode = '1' else
A_Wr_en;
B_Wr_en_i <= rw_reg.B_write_en when rw_reg.B_FIFO_write_en = '1' else
'0' when rw_reg.A_FIFO_write_en = '1' else
B_Wr_en_t when test_mode = '1' else
B_Wr_en;
--------------------
-- xCTRL
--------------------
xctrl_reset <= rst or rw_reg.reset or AUX_Enable;
xctrl_inst: xctrl
Port Map(
clk => clk,
rst => xctrl_reset,
-- A FIFO Side
a_d => a_d,
a_dv => a_dv_xctrl,
a_rd_en => a_rd_en_xctrl,
-- B FIFO Side
b_d => b_d,
b_dv => b_dv_xctrl,
b_rd_en => b_rd_en_xctrl,
-- AUXBUS Side
-- Data, Data Valid, Last Event Data and New Event or Data Request
x_d => d,
x_dv => dv,
x_last => last,
x_rd_en => rd_en,
-- Header Number and Header Number Valid (Valid is asserted when related data is ready)
x_hdr_d => hdr_d,
x_hdr_dv => hdr_dv,
-- Actual Header has no data
x_nodata => nodata,
--Error: Header Number Mismatch between A and B FIFO
x_mmatch => mmatch
);
--------------------
-- xFRONT
--------------------
xfront_reset <= rst or rw_reg.reset or AUX_Enable;
full <= apfull or bpfull;
xfront_inst: xfront
Generic Map(
clock_period => clock_period
)
Port Map(
-------- SYSTEM SIGNALS -------
-- System clock
clk => clk,
clk2x => clk2x,
-- System reset
rst => xfront_reset,
-------- Ctrl Registers -------
rw_reg => rw_reg,
-------- Control Interface -------
-- Trigger Number
i_t => trigger,
-- Trigger Number Data Valid
i_tv => trigger_v,
-- Trigger Number Request
i_t_req => open,
-- Data, Data Valid, Last Event Data and New Event or Data Request
i_d => d,
i_dv => dv,
i_last => last,
i_rd_en => rd_en,
-- Header Number and Header Number Valid (Valid is asserted when related data is ready)
i_hdr_d => hdr_d(11 downto 0),
i_hdr_dv => hdr_dv,
-- Actual Header has no data
i_nodata => nodata,
--Error: Header Number Mismatch between A and B FIFO; propagated to xberr
i_mmatch => mmatch,
-- FIFO Full Flag, propagated and kept to xbusy
i_full => full_i,
-------- ROCK OUTPUT -------
-- Trigger Bus, first valid trigger is 001
xt => xt,
-- Trigger Bus Data is valide, Active LOW
xtrgv_n => xtrgv_n,
-- Address Bus
xa => xa,
-- Address Bus is Valid
xas_n => xas_n,
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
xds => xds,
-- Master is initiating a synch check, Active LOW
xsyncrd_n => xsyncrd_n,
-- ROCK send a system HALT due to Error,
xsyshalt => xsyshalt,
-- ROCK produces a create level AUX reset
xsysreset => xsysreset,
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave xsds bit is valid, Active HIGH
xbk => xbk,
-- Slave has an error, Active LOW
xberr_n => xberr_n,
-- Slave is full, Active LOW
xbusy_n => xbusy_n,
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
xsel_n => xsel_n,
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk => xdk,
-- Actual Slave Data Word is the last, Active LOW
xeob_n => xeob_n,
-- Slave Data
xd => xd,
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds => xsds,
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
sa => sa,
-------- EXTERNAL DEVICE SELECTION -------
-- Use external Device Selection, Active HIGH
ext_s_en => ext_s_en,
-- External Device selection , Active HIGH
x_ssel => x_ssel
);
--------------------
-- xAXI
--------------------
xaxi_inst: xaxi
Generic Map(
-------- AXI-4 LITE -------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
Port Map(
-------- Status Registers -------
ro_reg => ro_reg,
-------- Ctrl Registers -------
rw_reg => rw_reg,
-------- AXI-4 PORTS -------
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
S_AXI_ARADDR => S_AXI_ARADDR ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY
);
end rtl;
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: xtrig.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description: Trigger Front End, Counters and Voter.
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
library work;
use work.xpack.all;
entity xtrig is
Port (
-------- System Signals -------
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-------- Status Registers -------
ro_reg : out ro_reg_type;
-------- Ctrl Registers -------
rw_reg : in rw_reg_type;
-------- Trigger Signals -------
-- Local Input Trigger
trig_in : in STD_LOGIC;
-- A Input Trigger
atrig_det : in STD_LOGIC;
-- B Input Trigger
btrig_det : in STD_LOGIC;
-- Output Trigger
trigger : out STD_LOGIC_VECTOR(11 DOWNTO 0);
-- Output Trigger Valid
trigger_v : out STD_LOGIC
);
end xtrig;
architecture rtl of xtrig is
------------------------------------------------------------------
---- SIGNALS DECLARATION ----
------------------------------------------------------------------
--------------------
-- Trigger Detector
--------------------
-- Trigger detection Register
signal trig_det_reg : std_logic_vector (6 downto 0);
-- Async Reg
attribute ASYNC_REG : STRING;
--attribute ASYNC_REG of trig_det_reg(1 downto 0) : signal is "TRUE"; -- Modify to set as async
--------------------
-- Trigger Synchronization
--------------------
signal trig_sync_reg : std_logic_vector (1 downto 0);
-- Async Reg
attribute ASYNC_REG of trig_sync_reg : signal is "TRUE";
--------------------
-- Trigger Counter
--------------------
signal trig_counter : std_logic_vector (11 downto 0);
--------------------
-- A Trigger Synchronization
--------------------
signal atrig_sync_reg : std_logic_vector (1 downto 0);
-- Async Reg
attribute ASYNC_REG of atrig_sync_reg : signal is "TRUE";
--------------------
-- A Trigger Counter
--------------------
signal atrig_counter : std_logic_vector (11 downto 0);
--------------------
-- B Trigger Synchronization
--------------------
signal btrig_sync_reg : std_logic_vector (1 downto 0);
-- Async Reg
attribute ASYNC_REG of btrig_sync_reg : signal is "TRUE";
--------------------
-- B Trigger Counter
--------------------
signal btrig_counter : std_logic_vector (11 downto 0);
--------------------
-- Trigger Timeout
--------------------
signal timeout_done : std_logic;
signal start_timeout_counter : std_logic;
signal timeout_counter : std_logic_vector (1 downto 0);
constant timeout : std_logic_vector (1 downto 0) := "10";
--------------------
-- RX Trigger
--------------------
signal trig_rec : std_logic_vector (2 downto 0);
--------------------
-- Trigger Voter
--------------------
signal trigger_i : std_logic_vector (11 downto 0);
signal trigger_v_i : std_logic;
begin
--------------------
-- Trigger Detector
--------------------
trig_det_pr: process(rst, trig_det_reg(trig_det_reg'high), trig_in)
begin
if rst = '1' or trig_det_reg(trig_det_reg'high) = '1' then
trig_det_reg(0) <= '0';
elsif trig_in'event and trig_in='1' then
trig_det_reg(0) <= '1';
end if;
end process;
trig_shift_pr: process(rst, trig_det_reg(trig_det_reg'high), clk)
begin
if rst = '1' or (trig_det_reg(trig_det_reg'high)='1') then
trig_det_reg(trig_det_reg'high-1 DOWNTO 1) <= (others => '0');
elsif clk'event and clk='1' then
trig_det_reg(trig_det_reg'high-1 DOWNTO 1) <= trig_det_reg(trig_det_reg'high-2 DOWNTO 0);
end if;
end process;
trig_reset_pr: process(rst, clk)
begin
if rst = '1' then
trig_det_reg(trig_det_reg'high) <= '0';
elsif clk'event and clk='1' then
trig_det_reg(trig_det_reg'high) <= trig_det_reg(trig_det_reg'high-1);
end if;
end process;
--------------------
-- Trigger Synchronization
--------------------
trig_sync_pr: process(rst, clk)
begin
if rst = '1' then
trig_sync_reg <= "00";
elsif clk'event and clk='1' then
trig_sync_reg(0) <= trig_det_reg(0);
trig_sync_reg(1) <= trig_sync_reg(0);
end if;
end process;
--------------------
-- Trigger Counter
--------------------
trig_counter_pr: process(rst, clk)
begin
if rst = '1' then
trig_counter <= (others => '0');
elsif clk'event and clk='1' then
if trig_sync_reg = "10" then
trig_counter <= trig_counter + 1;
else
trig_counter <= trig_counter;
end if;
end if;
end process;
--------------------
-- A Trigger Synchronization
--------------------
atrig_sync_pr: process(rst, clk)
begin
if rst = '1' then
atrig_sync_reg <= "00";
elsif clk'event and clk='1' then
atrig_sync_reg(0) <= atrig_det;
atrig_sync_reg(1) <= atrig_sync_reg(0);
end if;
end process;
--------------------
-- A Trigger Counter
--------------------
atrig_counter_pr: process(rst, clk)
begin
if rst = '1' then
atrig_counter <= (others => '0');
elsif clk'event and clk='1' then
if atrig_sync_reg = "10" then
atrig_counter <= atrig_counter + 1;
else
atrig_counter <= atrig_counter;
end if;
end if;
end process;
--------------------
-- B Trigger Synchronization
--------------------
btrig_sync_pr: process(rst, clk)
begin
if rst = '1' then
btrig_sync_reg <= "00";
elsif clk'event and clk='1' then
btrig_sync_reg(0) <= btrig_det;
btrig_sync_reg(1) <= btrig_sync_reg(0);
end if;
end process;
--------------------
-- B Trigger Counter
--------------------
btrig_counter_pr: process(rst, clk)
begin
if rst = '1' then
btrig_counter <= (others => '0');
elsif clk'event and clk='1' then
if btrig_sync_reg = "10" then
btrig_counter <= btrig_counter + 1;
else
btrig_counter <= btrig_counter;
end if;
end if;
end process;
--------------------
-- Trigger Timeout
--------------------
trig_timeout_pr: process(rst, clk)
begin
if rst = '1' then
timeout_counter <= (others => '0');
timeout_done <= '1';
elsif clk'event and clk='1' then
if timeout_counter = timeout then
timeout_done <= '1';
elsif start_timeout_counter='1' then
timeout_done <= '0';
else
timeout_done <= timeout_done;
end if;
if timeout_done = '0' then
timeout_counter <= timeout_counter + 1;
else
timeout_counter <= (others => '0');
end if;
end if;
end process;
--------------------
-- RX Trigger
--------------------
trig_rx_pr: process(rst, clk)
begin
if rst = '1' then
start_timeout_counter <= '0';
trig_rec <= "000";
elsif clk'event and clk='1' then
if (timeout_done = '1') and ((trig_sync_reg = "10") or (atrig_sync_reg = "10") or (btrig_sync_reg = "10")) then
-- Start Timout Counter and Set RX Triggers
start_timeout_counter <= '1';
if trig_sync_reg = "10" then
trig_rec(0) <= '1';
else
trig_rec(0) <= '0';
end if;
if atrig_sync_reg = "10" then
trig_rec(1) <= '1';
else
trig_rec(1) <= '0';
end if;
if btrig_sync_reg = "10" then
trig_rec(2) <= '1';
else
trig_rec(2) <= '0';
end if;
else
start_timeout_counter <= '0';
if timeout_done = '0' then
-- Wait for triggers
if trig_sync_reg = "10" then
trig_rec(0) <= '1';
else
trig_rec(0) <= trig_rec(0);
end if;
if atrig_sync_reg = "10" then
trig_rec(1) <= '1';
else
trig_rec(1) <= trig_rec(1);
end if;
if btrig_sync_reg = "10" then
trig_rec(2) <= '1';
else
trig_rec(2) <= trig_rec(2);
end if;
else
-- Timeout Reached
trig_rec <= trig_rec;
end if;
end if;
end if;
end process;
--------------------
-- Trigger Voter
--------------------
trig_voter_pr: process(rst, clk)
begin
if rst = '1' then
trigger_i <= (others => '0');
trigger_v_i <= '0';
elsif clk'event and clk='1' then
if (trig_rec = "111") or (timeout_done='1') then
-- all triggers received or timeout
if atrig_counter = btrig_counter then
-- Send A and B Trigger Number, local trigger number is not checked
trigger_i <= atrig_counter;
trigger_v_i <= '1';
elsif atrig_counter = trig_counter then
-- Send the Least Likely Trigger Number, but is not validated
trigger_i <= btrig_counter;
trigger_v_i <= '0';
else
-- Send the Least Likely Trigger Number, but is not validated
trigger_i <= atrig_counter;
trigger_v_i <= '0';
end if;
else
-- waiting for trigger or timeout
trigger_i <= trigger_i;
trigger_v_i <= trigger_v_i;
end if;
end if;
end process;
--trigger <= trigger_i when rw_reg.test_mode='1' and rw_reg.trig_mode='0' else trig_counter; --else rw_reg.test_Ntrig;
--trigger_v <= trigger_v_i when rw_reg.test_mode='1' and rw_reg.trig_mode='0' else '1';
trigger <= trigger_i when rw_reg.trig_mode='0' else trig_counter; --else rw_reg.test_Ntrig;
trigger_v <= trigger_v_i when rw_reg.trig_mode='0' else '1';
--------------------
-- Status Register
--------------------
-- Voted Trigger Number Valid
ro_reg.Ntrig_voter_v <= trigger_v_i;
-- Voted Trigger Number
ro_reg.Ntrig_voter <= trigger_i;
-- Local Trigger Number
ro_reg.Ntrig_local <= trig_counter;
-- FPGA A Trigger Number
ro_reg.Ntrig_devA <= atrig_counter;
-- FPGA B Trigger Number
ro_reg.Ntrig_devB <= btrig_counter;
end rtl;
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: xtest.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description: Protocol Test Environment.
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
library work;
use work.xpack.all;
entity xtest is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-------- Status Registers -------
ro_reg : out ro_reg_type;
-------- Ctrl Registers -------
rw_reg : in rw_reg_type;
-------- Test Control Bit -------
test_mode : out STD_LOGIC;
-------- Input Trigger -------
trigger : in STD_LOGIC_VECTOR(11 DOWNTO 0);
-------- A FIFO Interface -------
A_Wr_clk : in STD_LOGIC;
A_Din : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
A_Wr_en : out STD_LOGIC;
A_Full : in STD_LOGIC;
A_Almost_full : in STD_LOGIC;
A_Prog_full : in STD_LOGIC;
A_busy : out STD_LOGIC;
-------- B FIFO Interface -------
B_Wr_clk : in STD_LOGIC;
B_Din : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
B_Wr_en : out STD_LOGIC;
B_Full : in STD_LOGIC;
B_Almost_full : in STD_LOGIC;
B_Prog_full : in STD_LOGIC;
B_busy : out STD_LOGIC
);
end xtest;
architecture rtl of xtest is
------------------------------------------------------------------
---- COMPONENTS DECLARATION ----
------------------------------------------------------------------
--------------------
-- PRBS_ANY
--------------------
component PRBS_ANY
generic (
-- out alp:
--CHK_MODE: boolean := false;
INV_PATTERN : boolean := false;
POLY_LENGHT : natural range 0 to 63 := 31;
POLY_TAP : natural range 0 to 63 := 3;
NBITS : natural range 0 to 512 := 22
);
port (
-- in alp:
CHK_MODE : in std_logic;
RST : in std_logic; -- sync reset active high
CLK : in std_logic; -- system clock
DATA_IN : in std_logic_vector(NBITS - 1 downto 0); -- inject error/data to be checked
EN : in std_logic; -- enable/pause pattern generation
DATA_OUT : out std_logic_vector(NBITS - 1 downto 0) -- generated prbs pattern/errors found
);
end component;
------------------------------------------------------------------
---- CONSTANTS DECLARATION ----
------------------------------------------------------------------
--------------------
-- PRBS_ANY
--------------------
-- PRBS-15 Settings
constant A_INV_PATTERN : boolean := true;
constant B_INV_PATTERN : boolean := true;
constant POLY_LENGHT : natural range 0 to 63 := 15;
constant POLY_TAP : natural range 0 to 63 := 14;
constant B_INV_PATTERN_Nev : boolean := false;
constant B_POLY_LENGHT_Nev : natural range 0 to 63 := 20;
constant B_POLY_TAP_Nev : natural range 0 to 63 := 3;
------------------------------------------------------------------
---- SIGNALS DECLARATION ----
------------------------------------------------------------------
-- test mode: 0 Disable, 1 Enable.
SIGNAL test : STD_LOGIC;
--------------------
-- PRBS_ANY: A DATA GENERATION
--------------------
SIGNAL a_inj : STD_LOGIC_VECTOR(11 downto 0);
SIGNAL a_req : STD_LOGIC;
SIGNAL areq : STD_LOGIC;
SIGNAL a_data : STD_LOGIC_VECTOR(11 downto 0);
SIGNAL a_data_prbs : STD_LOGIC_VECTOR(11 downto 0);
--------------------
-- PRBS_ANY: A EVENT GENERATION
--------------------
SIGNAL an : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL A_Nevent : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL an_10bit : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL aev_req : STD_LOGIC;
--------------------
-- A FIFO WRITE
--------------------
SIGNAL adone : STD_LOGIC;
SIGNAL acnt : STD_LOGIC_VECTOR(6 downto 0);
SIGNAL acnt_r : STD_LOGIC_VECTOR(6 downto 0);
SIGNAL achannel : STD_LOGIC_VECTOR(6 downto 0);
--------------------
-- A FIFO STIMULI
--------------------
SIGNAL aw : STD_LOGIC;
SIGNAL ad : STD_LOGIC_VECTOR(21 downto 0);
SIGNAL A_Din_i : STD_LOGIC_VECTOR(21 downto 0);
SIGNAL ainc : STD_LOGIC_VECTOR(11 downto 0) := (others => '0');
SIGNAL adone_reg : STD_LOGIC;
--------------------
-- PRBS_ANY: B DATA GENERATION
--------------------
SIGNAL b_inj : STD_LOGIC_VECTOR(11 downto 0);
SIGNAL b_req : STD_LOGIC;
SIGNAL breq : STD_LOGIC;
SIGNAL b_data_prbs : STD_LOGIC_VECTOR(11 downto 0);
SIGNAL b_data : STD_LOGIC_VECTOR(11 downto 0);
--------------------
-- PRBS_ANY: B EVENT GENERATION
--------------------
SIGNAL bn : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL B_Nevent : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bn_10bit : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL bev_req : STD_LOGIC;
--------------------
-- B FIFO WRITE
--------------------
SIGNAL bdone : STD_LOGIC;
SIGNAL bcnt : STD_LOGIC_VECTOR(6 downto 0);
SIGNAL bcnt_r : STD_LOGIC_VECTOR(6 downto 0);
SIGNAL bchannel : STD_LOGIC_VECTOR(6 downto 0);
--------------------
-- B FIFO STIMULI
--------------------
SIGNAL bw : STD_LOGIC;
SIGNAL bd : STD_LOGIC_VECTOR(21 downto 0);
SIGNAL B_Din_i : STD_LOGIC_VECTOR(21 downto 0);
SIGNAL binc : STD_LOGIC_VECTOR(11 downto 0) := (others => '0');
SIGNAL bdone_reg : STD_LOGIC;
SIGNAL b_req_init : STD_LOGIC;
begin
--------------------
-- rw_reg assignments
--------------------
test <= rw_reg.test_mode;
test_mode <= rw_reg.test_mode;
A_busy <= rw_reg.A_is_busy;
B_busy <= rw_reg.B_is_busy;
--------------------
-- ro_reg assignments
--------------------
ro_reg.atest_Ntrig <= ainc;
ro_reg.btest_Ntrig <= binc;
--------------------
-- PRBS_ANY: A DATA GENERATION
--------------------
areq <= a_req and not A_Almost_full;
a_inj <= (others => '0');
a_data_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => A_INV_PATTERN,
POLY_LENGHT => POLY_LENGHT,
POLY_TAP => POLY_TAP,
NBITS => a_data'high+1
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => A_Wr_clk,
DATA_IN => a_inj,
EN => areq,
DATA_OUT => a_data_prbs
);
a_data <= rw_reg.A_event_data(to_integer(unsigned(acnt_r(1 downto 0)))) when rw_reg.A_pattern_isfixed = '1' else
a_data_prbs;
--------------------
-- PRBS_ANY: B DATA GENERATION
--------------------
breq <= b_req and not B_Almost_full;
b_inj <= (others => '0');
b_data_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => B_INV_PATTERN,
POLY_LENGHT => POLY_LENGHT,
POLY_TAP => POLY_TAP,
NBITS => b_data'high+1
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => B_Wr_clk,
DATA_IN => b_inj,
EN => breq,
DATA_OUT => b_data_prbs
);
b_data <= rw_reg.B_event_data(to_integer(unsigned(bcnt_r(1 downto 0)))) when rw_reg.B_pattern_isfixed='1' else
b_data_prbs;
--------------------
-- PRBS_ANY: A EVENT GENERATION
--------------------
aevent_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => A_INV_PATTERN,
POLY_LENGHT => POLY_LENGHT,
POLY_TAP => POLY_TAP,
NBITS => 10
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => A_Wr_clk,
DATA_IN => (others=>'0'),
EN => aev_req,
DATA_OUT => an_10bit
);
A_Nevent <= "000" when rw_reg.A_Nevent(2 downto 0) = "000" else
"001" when rw_reg.A_Nevent(2 downto 0) = "001" else
"010" when rw_reg.A_Nevent(2 downto 0) = "010" else
"011" when rw_reg.A_Nevent(2 downto 0) = "011" else
"100";
an <= "000" & A_Nevent when rw_reg.A_pattern_isfixed='1' else
std_logic_vector( unsigned('0' & an_10bit(9 downto 5)) + unsigned(an_10bit(4 downto 1)) + unsigned(an_10bit(0 downto 0)) );
--an <= "000" & std_logic_vector(1 + unsigned('0' & rw_reg.A_Nevent(1 downto 0))) when rw_reg.A_pattern_isfixed='1' else
-- std_logic_vector( unsigned('0' & an_10bit(9 downto 5)) + unsigned(an_10bit(4 downto 1)) + unsigned(an_10bit(0 downto 0)) );
--------------------
-- PRBS_ANY: B EVENT GENERATION
--------------------
bevent_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => B_INV_PATTERN_Nev,
POLY_LENGHT => B_POLY_LENGHT_Nev,
POLY_TAP => B_POLY_TAP_Nev,
NBITS => 10
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => B_Wr_clk,
DATA_IN => (others=>'0'),
EN => bev_req,
DATA_OUT => bn_10bit
);
B_Nevent <= "000" when rw_reg.B_Nevent(2 downto 0) = "000" else
"001" when rw_reg.B_Nevent(2 downto 0) = "001" else
"010" when rw_reg.B_Nevent(2 downto 0) = "010" else
"011" when rw_reg.B_Nevent(2 downto 0) = "011" else
"100";
bn <= "000" & B_Nevent when rw_reg.B_pattern_isfixed = '1' else
std_logic_vector( unsigned('0' & bn_10bit(9 downto 5)) + unsigned(bn_10bit(4 downto 1)) + unsigned(bn_10bit(0 downto 0)) );
--bn <= "000" & std_logic_vector(1 + unsigned('0' & rw_reg.B_Nevent(1 downto 0))) when rw_reg.B_pattern_isfixed = '1' else
-- std_logic_vector( unsigned('0' & bn_10bit(9 downto 5)) + unsigned(bn_10bit(4 downto 1)) + unsigned(bn_10bit(0 downto 0)) );
--------------------
-- A FIFO STIMULI
--------------------
-- Data from FIFO:
-- a_d/b_d: 22 bit data
-- 00&DATA| is data , not last , DATA
-- 01&DATA| is data , is last , DATA
-- 10&EV_N| is header, data exist, EVENT NUMBER
-- 11&EV_N| is header, no data , EVENT NUMBER
-- a_dv/b_dv: data valid
astim_pr: process(rst, A_Wr_clk)
variable a_dataexist : std_logic := '0';
variable a_dataislast : std_logic := '0';
begin
if rst = '1' then
ainc <= (others => '0');
acnt_r <= (others => '0');
aw <= '0';
a_dataexist := '0';
a_dataislast := '0';
adone_reg <= '0';
ad <= (others => '0');
elsif A_Wr_clk'event and A_Wr_clk='1' then
adone_reg <= adone;
acnt_r <= acnt;
ainc <= ainc;
aw <= '0';
if adone = '1' then
-- Start a new write process
if adone_reg = '1' and std_logic_vector(unsigned(trigger) + 1) /= ainc then
aw <= '1';
end if;
if adone_reg = '0' then
-- Increment trigger number
ainc <= std_logic_vector( unsigned(ainc) + 1);
end if;
else
-- Provide words to be written (Header or Data)
if acnt = std_logic_vector(to_unsigned(0, acnt'high)) then
-- Heaader
if an/=std_logic_vector(to_unsigned(0, acnt'high)) then
a_dataexist := '0';
else
a_dataexist := '1';
end if;
ad <= '1' & a_dataexist & X"00" & ainc;
else
-- Data
if acnt=an then
a_dataislast := '1';
else
a_dataislast := '0';
end if;
ad <= '0' & a_dataislast & achannel & '0' & a_data;
end if;
end if;
if A_Almost_full='1' then
-- Wait until A_Almost_full='0'
ad <= ad;
end if;
if test = '0' then
-- Test mode is disabled
ainc <= (others => '1');
aw <= '0';
a_dataexist := '0';
a_dataislast := '0';
adone_reg <= '0';
end if;
end if;
end process;
--------------------
-- B FIFO STIMULI
--------------------
-- Data from FIFO:
-- a_d/b_d: 22 bit data
-- 00&DATA| is data , not last , DATA
-- 01&DATA| is data , is last , DATA
-- 10&EV_N| is header, data exist, EVENT NUMBER
-- 11&EV_N| is header, no data , EVENT NUMBER
-- a_dv/b_dv: data valid
bstim_pr: process(rst, B_Wr_clk)
variable b_dataexist : std_logic := '0';
variable b_dataislast : std_logic := '0';
begin
if rst = '1' then
binc <= (others => '0');
bcnt_r <= (others => '0');
bw <= '0';
b_dataexist := '0';
b_dataislast := '0';
bdone_reg <= '0';
bd <= (others => '0');
elsif B_Wr_clk'event and B_Wr_clk='1' then
bdone_reg <= bdone;
bcnt_r <= bcnt;
binc <= binc;
bw <= '0';
if bdone = '1' then
-- Start a new write process
if bdone_reg = '1' and std_logic_vector(unsigned(trigger) + 1) /= binc then
bw <= '1';
end if;
if bdone_reg = '0' then
-- Increment trigger number
binc <= std_logic_vector( unsigned(binc) + 1 );
end if;
else
-- Provide words to be written (Header or Data)
if bcnt = std_logic_vector(to_unsigned(0, bcnt'high)) then
-- Heaader
if bn/=std_logic_vector(to_unsigned(0, bcnt'high)) then
b_dataexist := '0';
else
b_dataexist := '1';
end if;
bd <= '1' & b_dataexist & X"00" & binc;
else
-- Data
if bcnt=bn then
b_dataislast := '1';
else
b_dataislast := '0';
end if;
bd <= '0' & b_dataislast & bchannel & '0' & b_data;
end if;
end if;
if B_Almost_full='1' then
-- Wait until B_Almost_full='0'
bd <= bd;
end if;
if test = '0' then
-- Test mode is disabled
binc <= (others => '1');
bw <= '0';
b_dataexist := '0';
b_dataislast := '0';
bdone_reg <= '0';
end if;
end if;
end process;
--------------------
-- A FIFO WRITE
--------------------
A_Din <= A_Din_i;
aw_pr: process(rst, A_Wr_clk)
begin
if rst = '1' then
acnt <= (others => '0');
achannel<= (others => '0');
adone <= '1';
A_Din_i <= (others => '0');
A_Wr_en <= '0';
a_req <= '1';
aev_req <= '0';
elsif A_Wr_clk'event and A_Wr_clk='1' then
acnt <= (others => '0');
achannel<= (others => '0');
adone <= '1';
A_Din_i <= (others => '0');
A_Wr_en <= '0';
a_req <= '0' or (b_req_init and B_Almost_full);
aev_req <= '0';
if aw = '1' or adone = '0' then
-- Start FIFO Write
adone <= '0';
if acnt <= std_logic_vector( unsigned(an)+1) then
-- Write all requested data (1 header + an data)
A_Din_i <= ad;
A_Wr_en <= not aw;
if adone='0' then
acnt <= std_logic_vector(unsigned(acnt) + 1);
else
acnt <= acnt;
end if;
achannel<= acnt;
if (acnt = an) or (acnt = std_logic_vector( unsigned(an)+1)) then
-- Do not request new data
a_req <= '0';
elsif acnt = std_logic_vector(to_unsigned(0,acnt'high)) then
-- Request new data
a_req <= not adone;
else
-- Request next data
a_req <= '1';
end if;
if A_Almost_full='1' then
-- Wait until A_Almost_full='0'
A_Wr_en <= '0';
A_Din_i <= A_Din_i;
acnt <= acnt;
achannel<= achannel;
a_req <= a_req;
end if;
else
-- Done
adone <= '1';
-- Request new event
aev_req <= '1';
end if;
end if;
if test = '0' then
-- Test mode is disabled
acnt <= (others => '0');
achannel<= (others => '0');
adone <= '1';
A_Din_i <= (others => '0');
A_Wr_en <= '0';
a_req <= '0';
aev_req <= '0';
end if;
end if;
end process;
--------------------
-- B FIFO WRITE
--------------------
B_Din <= B_Din_i;
bw_pr: process(rst, B_Wr_clk)
begin
if rst = '1' then
bcnt <= (others => '0');
bchannel<= (others => '0');
bdone <= '1';
B_Din_i <= (others => '0');
B_Wr_en <= '0';
b_req <= '0';
b_req_init <= '1';
bev_req <= '0';
elsif B_Wr_clk'event and B_Wr_clk='1' then
b_req_init <= B_Almost_full and b_req_init;
bcnt <= (others => '0');
bchannel<= (others => '0');
bdone <= '1';
B_Din_i <= (others => '0');
B_Wr_en <= '0';
b_req <= '0' or (b_req_init and B_Almost_full);
bev_req <= '0';
if bw = '1' or bdone = '0' then
-- Start FIFO Write
bdone <= '0';
if bcnt <= std_logic_vector( unsigned(bn)+1) then
-- Write all requested data (1 header + an data)
B_Din_i <= bd;
B_Wr_en <= not bw;
if bdone='0' then
-- Write Header
bcnt <= std_logic_vector(unsigned(bcnt) + 1);
else
-- Write Data
bcnt <= bcnt;
end if;
bchannel<= bcnt;
if (bcnt = bn) or (bcnt = std_logic_vector( unsigned(bn)+1)) then
-- Do not request new data
b_req <= '0';
elsif bcnt = std_logic_vector( to_unsigned(0,bcnt'high) ) then
-- Request new data
b_req <= not bdone;
else
-- Request next data
b_req <= '1';
end if;
if B_Almost_full='1' then
-- Wait until B_Almost_full='0'
B_Wr_en <= '0';
B_Din_i <= B_Din_i;
bcnt <= bcnt;
bchannel<= bchannel;
b_req <= b_req;
end if;
else
-- Done
bdone <= '1';
-- Request new event
bev_req <= '1';
end if;
end if;
if test = '0' then
-- Test mode is disabled
bcnt <= (others => '0');
bchannel<= (others => '0');
bdone <= '1';
B_Din_i <= (others => '0');
B_Wr_en <= '0';
b_req <= '0';
bev_req <= '0';
end if;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: xfifo.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description: 2 FIFO receiving data from AFE.
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 1.0 - 02/2016 - Albicocco P. - First Version
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity xfifo is
Port (
Rst : in STD_LOGIC;
Rd_clk : in STD_LOGIC;
-------- A FIFO Interface -------
A_Wr_clk : in STD_LOGIC;
A_Din : in STD_LOGIC_VECTOR(22-1 DOWNTO 0);
A_Wr_en : in STD_LOGIC;
A_Full : out STD_LOGIC;
A_Prog_full : out STD_LOGIC;
A_Almost_full : out STD_LOGIC;
A_Rd_en : in STD_LOGIC;
A_Dout : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
A_Empty : out STD_LOGIC;
A_Valid : out STD_LOGIC;
-------- B FIFO Interface -------
B_Wr_clk : in STD_LOGIC;
B_Din : in STD_LOGIC_VECTOR(22-1 DOWNTO 0);
B_Wr_en : in STD_LOGIC;
B_Full : out STD_LOGIC;
B_Prog_full : out STD_LOGIC;
B_Almost_full : out STD_LOGIC;
B_Rd_en : in STD_LOGIC;
B_Dout : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
B_Empty : out STD_LOGIC;
B_Valid : out STD_LOGIC
);
end xfifo;
architecture rtl of xfifo is
------------------------------------------------------------------
---- COMPONENTS DECLARATION ----
------------------------------------------------------------------
component xINFIFO
port (
Rst : in STD_LOGIC;
Wr_clk : in STD_LOGIC;
Rd_clk : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR(22-1 DOWNTO 0);
Wr_en : in STD_LOGIC;
Rd_en : in STD_LOGIC;
Dout : out STD_LOGIC_VECTOR(22-1 DOWNTO 0);
Full : out STD_LOGIC;
Almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
Empty : out STD_LOGIC;
Valid : out STD_LOGIC
);
end component;
begin
--------------------
-- AFIFO
--------------------
AFIFO: xINFIFO
port map(
Rst => Rst,
Wr_clk => A_Wr_clk,
Rd_clk => Rd_clk,
Din => A_Din,
Wr_en => A_Wr_en,
Rd_en => A_Rd_en,
Dout => A_Dout,
Full => A_Full,
Almost_full => A_Almost_full,
prog_full => A_Prog_full,
Empty => A_Empty,
Valid => A_Valid
);
--------------------
-- BFIFO
--------------------
BFIFO: xINFIFO
port map(
Rst => Rst,
Wr_clk => B_Wr_clk,
Rd_clk => Rd_clk,
Din => B_Din,
Wr_en => B_Wr_en,
Rd_en => B_Rd_en,
Dout => B_Dout,
Full => B_Full,
Almost_full => B_Almost_full,
prog_full => B_Prog_full,
Empty => B_Empty,
Valid => B_Valid
);
end rtl;
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: xctrl.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description:
-- xCTRL provide data saved in FIFO to the auxbus when requested.
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 1.0 - 02/2016 - Albicocco P. - First Version
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
-- Data from FIFO:
-- a_d/b_d: 22 bit data
-- 00&DATA| is data , not last , DATA
-- 01&DATA| is data , is last , DATA
-- 10&EV_N| is header, data exist, EVENT NUMBER
-- 11&EV_N| is header, no data , EVENT NUMBER
-- a_dv/b_dv: data valid
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity xctrl is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- A FIFO Side
a_d : in STD_LOGIC_VECTOR(21 downto 0);
a_dv : in STD_LOGIC;
a_rd_en : out STD_LOGIC;
-- B FIFO Side
b_d : in STD_LOGIC_VECTOR(21 downto 0);
b_dv : in STD_LOGIC;
b_rd_en : out STD_LOGIC;
-- AUXBUS Side
-- Data, Data Valid, Last Event Data and New Event or Data Request
x_d : buffer STD_LOGIC_VECTOR(19 downto 0);
x_dv : out STD_LOGIC;
x_last : out STD_LOGIC;
x_rd_en : in STD_LOGIC;
-- Header Number and Header Number Valid (Valid is asserted when related data is ready)
x_hdr_d : buffer STD_LOGIC_VECTOR(19 downto 0);
x_hdr_dv : out STD_LOGIC;
-- Actual Header has no data
x_nodata : out STD_LOGIC;
--Error: Header Number Mismatch between A and B FIFO
x_mmatch : out STD_LOGIC
);
end xctrl;
architecture rtl of xctrl is
------------------------------------------------------------------
---- CONSTANTS ----
------------------------------------------------------------------
constant RESET_STATE : std_logic_vector (2 downto 0) := "000";
constant WAITAHEADER : std_logic_vector (2 downto 0) := "001";
constant WAITBHEADER : std_logic_vector (2 downto 0) := "010";
constant SEND_A_DATA : std_logic_vector (2 downto 0) := "011";
constant SEND_B_DATA : std_logic_vector (2 downto 0) := "100";
constant SEND_ABDATA : std_logic_vector (2 downto 0) := "101";
constant NOFOUNDDATA : std_logic_vector (2 downto 0) := "110";
constant HEADER_MISM : std_logic_vector (2 downto 0) := "111";
------------------------------------------------------------------
---- FUNCTIONS ----
------------------------------------------------------------------
--------------------
-- is_header
--------------------
function is_header(data: std_logic_vector; data_valid: std_logic) return boolean is
variable r : boolean := FALSE;
begin
if data_valid='1' and data(data'high)='1' then
r := TRUE;
end if;
return r;
end is_header;
--------------------
-- dataexist
--------------------
function dataexist(data: std_logic_vector; data_valid: std_logic) return boolean is
variable r : boolean := FALSE;
begin
if data_valid='1' and data(data'high downto data'high-1)="10" then
r := TRUE;
end if;
return r;
end dataexist;
--------------------
-- get_header
--------------------
function get_header(data: std_logic_vector; data_valid: std_logic) return std_logic_vector is
variable r : std_logic_vector(data'high-2 downto data'low-0) := (others => 'X');
begin
if data_valid='1' and data(data'high)='1' then
r := data(data'high-2 downto data'low-0);
end if;
return r;
end get_header;
--------------------
-- is_last
--------------------
function is_last(data: std_logic_vector; data_valid: std_logic) return boolean is
variable r : boolean := FALSE;
begin
if data_valid='1' and data(data'high downto data'high-1)="01" then
r := TRUE;
end if;
return r;
end is_last;
------------------------------------------------------------------
---- SIGNALS ----
------------------------------------------------------------------
-- State machine signals
signal pstate : std_logic_vector (2 downto 0) := RESET_STATE;
signal nstate : std_logic_vector (2 downto 0);
signal x_d_r : std_logic_vector(19 downto 0);
signal x_hdr_d_r : std_logic_vector(19 downto 0);
signal b_header : std_logic_vector(19 downto 0);
signal a_header : std_logic_vector(19 downto 0);
signal b_header_r : std_logic_vector(19 downto 0);
signal a_header_r : std_logic_vector(19 downto 0);
begin
seq_fsm: process(clk, rst) is
begin
if rst = '1' then
a_header_r <= (others => '0');
b_header_r <= (others => '0');
x_hdr_d_r <= (others => '0');
x_d_r <= (others => '0');
pstate <= RESET_STATE;
elsif clk='1' and clk'event then
a_header_r <= a_header;
b_header_r <= b_header;
x_hdr_d_r <= x_hdr_d;
x_d_r <= x_d;
pstate <= nstate;
end if;
end process;
cmb_fsm: process (pstate, a_d, a_dv, b_d, b_dv, a_header_r, x_rd_en, x_hdr_d_r, b_header_r, x_d_r) is
begin
-- Default Values
a_header <= a_header_r;
a_rd_en <= a_dv;
b_header <= b_header_r;
b_rd_en <= b_dv;
x_d <= x_d_r;
x_dv <= '0';
x_last <= '0';
x_nodata <= '0';
x_hdr_d <= x_hdr_d_r;
x_hdr_dv <= '0';
x_mmatch <= '0';
case pstate is
when RESET_STATE =>
-- Reset
nstate <= WAITAHEADER;
a_rd_en <= '0';
b_rd_en <= '0';
when WAITAHEADER =>
-- Wait for the First Header and look forward for second header
nstate <= WAITAHEADER;
-- Check A Header
if is_header(a_d, a_dv) then
a_header <= get_header(a_d, a_dv);
x_hdr_d <= get_header(a_d, a_dv);
if is_header(b_d, b_dv) then
-- Both Headers found: request the new data to be sent
b_header <= get_header(b_d, b_dv);
x_hdr_dv <= '1';
if dataexist(a_d, a_dv) and dataexist(b_d, b_dv) then
-- Disable B, Request A
nstate <= SEND_ABDATA;
b_rd_en <= '0';
elsif dataexist(a_d, a_dv) then
-- Disable B, Request A
nstate <= SEND_A_DATA;
b_rd_en <= '0';
elsif dataexist(b_d, b_dv) then
-- Disable A, Request B
nstate <= SEND_B_DATA;
a_rd_en <= '0';
else
-- Request new A and B Header
nstate <= NOFOUNDDATA;
x_nodata <= '1';
end if;
else
-- B header not found. Disable A, req new B data and go in WAITBHEADER
a_rd_en <= '0';
nstate <= WAITBHEADER;
end if;
-- Check B Header
elsif is_header(b_d, b_dv) then
-- B found: disable B, request new A data and wait for A header
b_header <= get_header(b_d, b_dv);
b_rd_en <= '0';
end if;
when WAITBHEADER =>
if is_header(b_d, b_dv) then
-- Both Headers found: go in send state and request new data to be sent
b_header <= get_header(b_d, b_dv);
x_hdr_dv <= '1';
if dataexist(a_d, a_dv) and dataexist(b_d, b_dv) then
-- Disable B, Request A
nstate <= SEND_ABDATA;
b_rd_en <= '0';
elsif dataexist(a_d, a_dv) then
-- Disable B, Request A
nstate <= SEND_A_DATA;
b_rd_en <= '0';
elsif dataexist(b_d, b_dv) then
-- Disable A, Request B
nstate <= SEND_B_DATA;
a_rd_en <= '0';
else
-- Request new A and B Header
nstate <= NOFOUNDDATA;
x_nodata <= '1';
end if;
else
-- B header not found. disable A, request new B data and wait for B header
a_rd_en <= '0';
nstate <= WAITBHEADER;
end if;
when SEND_A_DATA =>
x_hdr_dv <= '1';
a_rd_en <= x_rd_en and a_dv;
b_rd_en <= '0';
x_dv <= a_dv;
x_d <= a_d(19 downto 0);
nstate <= SEND_A_DATA;
-- Check for last data
if is_last(a_d, a_dv) then
-- Last data sent.
-- x_rd_en requests a new header: req. new data for both A and B and wait for headers.
b_rd_en <= x_rd_en and a_dv;
if x_rd_en = '1' then
nstate <= WAITAHEADER;
end if;
x_last <= '1';
end if;
when SEND_ABDATA =>
x_hdr_dv <= '1';
a_rd_en <= x_rd_en;
b_rd_en <= '0';
x_dv <= a_dv;
x_d <= a_d(19 downto 0);
nstate <= SEND_ABDATA;
-- Check for last data
if is_last(a_d, a_dv) then
-- Last A data sent.
-- x_rd_en requests a new B data: disable A and req. new B data.
b_rd_en <= x_rd_en;
a_rd_en <= '0'; -- New header for A is requested in state SEND_B_DATA.
if x_rd_en = '1' then
nstate <= SEND_B_DATA;
end if;
end if;
when SEND_B_DATA =>
x_hdr_dv <= '1';
b_rd_en <= x_rd_en;
a_rd_en <= '0';
x_dv <= b_dv;
x_d <= std_logic_vector(unsigned(b_d(19 downto 0))+unsigned((std_logic_vector(to_unsigned(48,7)) & '0' & x"000")));
nstate <= SEND_B_DATA;
-- Check for last data
if is_last(b_d, b_dv) then
-- Last data sent.
-- x_rd_en requests a new header: req. new data for both A and B and wait for headers.
a_rd_en <= x_rd_en;
if x_rd_en = '1' then
nstate <= WAITAHEADER;
end if;
x_last <= '1';
end if;
when NOFOUNDDATA =>
x_hdr_dv <= '1';
x_nodata <= '1';
nstate <= NOFOUNDDATA;
if x_rd_en = '1' then
-- End of Cycle
nstate <= WAITAHEADER;
end if;
-- New data already requested. Check for headers.
-- Check A Header
if is_header(a_d, a_dv) then
a_header <= get_header(a_d, a_dv);
a_rd_en <= '0';
end if;
-- Check B Header
if is_header(b_d, b_dv) then
b_header <= get_header(b_d, b_dv);
b_rd_en <= '0';
end if;
when HEADER_MISM =>
-- Header Mismatch
-- Should never go in this state.
-- Can be solved by using TrigNum from ROCK if A abd B are synchronous.
x_mmatch <= '1';
nstate <= HEADER_MISM;
a_rd_en <= '0';
b_rd_en <= '0';
when others =>
nstate <= RESET_STATE;
a_rd_en <= '0';
b_rd_en <= '0';
end case;
end process;
end rtl;
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: xfront.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description: xFRONT manage the auxbus signals.
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 1.0 - 02/2016 - Albicocco P. - First Version
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.xpack.all;
entity xfront is
Generic (
clock_period : integer := 10
);
Port (
-------- SYSTEM SIGNALS -------
-- System clock
clk : in STD_LOGIC;
clk2x : in STD_LOGIC;
-- System reset
rst : in STD_LOGIC;
-------- Ctrl Registers -------
rw_reg : in rw_reg_type;
-------- Control Interface -------
-- Trigger Number
i_t : in STD_LOGIC_VECTOR(11 downto 0);
-- Trigger Number Data Valid
i_tv : in STD_LOGIC;
-- Trigger Number Request
i_t_req : out STD_LOGIC;
-- Data, Data Valid, Last Event Data and New Event or Data Request
i_d : in STD_LOGIC_VECTOR(19 downto 0);
i_dv : in STD_LOGIC;
i_last : in STD_LOGIC;
i_rd_en : out STD_LOGIC;
-- Header Number and Header Number Valid (Valid is asserted when related data is ready)
i_hdr_d : in STD_LOGIC_VECTOR(11 downto 0);
i_hdr_dv : in STD_LOGIC;
-- Actual Header has no data
i_nodata : in STD_LOGIC;
--Error: Header Number Mismatch between A and B FIFO
i_mmatch : in STD_LOGIC;
-- FIFO Full Flag, propagated and kept to xbusy
i_full : in STD_LOGIC;
-------- ROCK OUTPUT -------
-- Trigger Bus, first valid trigger is 000
xt : in STD_LOGIC_VECTOR (11 downto 0);
-- Trigger Bus Data is valide, Active LOW
xtrgv_n : in STD_LOGIC;
-- Address Bus
xa : in STD_LOGIC_VECTOR (3 downto 0);
-- Address Bus is Valid
xas_n : in STD_LOGIC;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
xds : in STD_LOGIC;
-- Master is initiating a synch check, Active LOW
xsyncrd_n : in STD_LOGIC;
-- ROCK send a system HALT due to Error,
xsyshalt : in STD_LOGIC;
-- ROCK produces a create level AUX reset
xsysreset : in STD_LOGIC;
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave xsds bit is valid, Active HIGH
xbk : out STD_LOGIC;
-- Slave has an error, Active LOW
xberr_n : out STD_LOGIC;
-- Slave is full, Active LOW
xbusy_n : out STD_LOGIC;
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
xsel_n : out STD_LOGIC;
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk : out STD_LOGIC;
-- Actual Slave Data Word is the last, Active LOW
xeob_n : out STD_LOGIC;
-- Slave Data
xd : out STD_LOGIC_VECTOR (19 downto 0);
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds : out STD_LOGIC;
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
sa : in STD_LOGIC_VECTOR (3 downto 0);
-------- EXTERNAL DEVICE SELECTION -------
-- Use external Device Selection, Active HIGH
ext_s_en : in STD_LOGIC;
-- External Device selection , Active HIGH
x_ssel : in STD_LOGIC
);
end xfront;
architecture rtl of xfront is
------------------------------------------------------------------
---- CONSTANTS ----
------------------------------------------------------------------
--constant thold35 : integer := (1000*(35+clock_period)-1)/1000/clock_period-1;
--constant thold15 : integer := (1000*(15+clock_period)-1)/1000/clock_period+1;
constant thold35_min : integer := (1000*(35+clock_period)-1)/1000/clock_period-1;
constant thold15_min : integer := (1000*(15+clock_period)-1)/1000/clock_period+1;
--------------------
-- Counter
--------------------
--constant Ncnt : integer := 1+log2(thold15);
constant Ncnt : integer := 12;
------------------------------------------------------------------
---- SIGNALS ----
------------------------------------------------------------------
-- Slave Address Selection
signal ssel : std_logic;
-- State machine signals
signal done : std_logic;
type xstate is (idle, sync, trig, readout);
signal pstate : xstate := idle;
signal nstate : xstate;
-- Registerd Signals
signal full_r : std_logic;
signal full : std_logic;
signal read_data : std_logic;
signal read_data_r : std_logic;
signal first_word_flag : std_logic;
signal first_word_flag_r : std_logic;
signal read_on_last : std_logic;
signal read_on_last_r : std_logic;
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
signal xdk_r : std_logic;
signal odk : std_logic;
-- Actual Slave Data Word is the last, Active LOW
signal xeob_n_r : std_logic;
signal oeob_n : std_logic;
-- Slave Data (19 downto 0)
signal xd_r : std_logic_vector(19 downto 0);
signal od : std_logic_vector(19 downto 0);
-- Counter signals
signal cvalue : std_logic_vector(Ncnt-1 downto 0);
signal ccnt : std_logic_vector(Ncnt-1 downto 0);
signal cvalid : std_logic;
signal thold35 : integer; --std_logic_vector(7 downto 0);
signal thold15 : integer; --std_logic_vector(7 downto 0);
-- Counter State Machine
type cstate is (idle, reset, start, run, freerun);
-- PS
signal cps : cstate := reset;
signal ccntr : std_logic_vector(Ncnt-1 downto 0) := (others => '0');
-- NS
signal cns : cstate;
-- AUXBUS INPUT SYNCRONIZATION
attribute async_reg : STRING;
-- Trigger Bus, first valid trigger is 001
signal it : STD_LOGIC_VECTOR (11 downto 0);
signal mt : STD_LOGIC_VECTOR (11 downto 0);
attribute async_reg of it : signal is "TRUE";
attribute async_reg of mt : signal is "TRUE";
-- Trigger Bus Data is valide, Active LOW
signal itrgv_n : STD_LOGIC;
signal mtrgv_n : STD_LOGIC;
attribute async_reg of itrgv_n : signal is "TRUE";
attribute async_reg of mtrgv_n : signal is "TRUE";
-- Address Bus
signal ia : STD_LOGIC_VECTOR (3 downto 0);
signal ma : STD_LOGIC_VECTOR (3 downto 0);
attribute async_reg of ia : signal is "TRUE";
attribute async_reg of ma : signal is "TRUE";
-- Address Bus is Valid
signal ias_n : STD_LOGIC;
signal mas_n : STD_LOGIC;
attribute async_reg of ias_n : signal is "TRUE";
attribute async_reg of mas_n : signal is "TRUE";
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
signal ids : STD_LOGIC;
signal mds : STD_LOGIC;
attribute async_reg of ids : signal is "TRUE";
attribute async_reg of mds : signal is "TRUE";
-- Master is initiating a synch check, Active LOW
signal isyncrd_n : STD_LOGIC;
signal msyncrd_n : STD_LOGIC;
attribute async_reg of isyncrd_n : signal is "TRUE";
attribute async_reg of msyncrd_n : signal is "TRUE";
-- ROCK send a system HALT due to Error,
signal isyshalt : STD_LOGIC;
signal msyshalt : STD_LOGIC;
attribute async_reg of isyshalt : signal is "TRUE";
attribute async_reg of msyshalt : signal is "TRUE";
-- ROCK produces a create level AUX reset
signal isysreset : STD_LOGIC;
signal msysreset : STD_LOGIC;
attribute async_reg of isysreset : signal is "TRUE";
attribute async_reg of msysreset : signal is "TRUE";
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
signal isa : STD_LOGIC_VECTOR (3 downto 0);
signal msa : STD_LOGIC_VECTOR (3 downto 0);
attribute async_reg of isa : signal is "TRUE";
attribute async_reg of msa : signal is "TRUE";
-------- EXTERNAL DEVICE SELECTION -------
signal i_ssel : STD_LOGIC;
signal m_ssel : STD_LOGIC;
attribute async_reg of i_ssel : signal is "TRUE";
attribute async_reg of m_ssel : signal is "TRUE";
-- Tristate Output Enable (Active High)
signal tris_en : std_logic;
begin
-- Timing
thold35 <= thold35_min+to_integer(unsigned(rw_reg.thold35));
thold15 <= thold35_min+to_integer(unsigned(rw_reg.thold15));
-- Input Synchronisation
insync_pr: process (rst, clk, clk2x) is
begin
if rst='1' then
mt <= (others => '0');
it <= (others => '0');
-- Trigger Bus Data is valide, Active LOW
mtrgv_n <= '1';
itrgv_n <= '1';
-- Address Bus
ma <= (others => '0');
ia <= (others => '0');
-- Address Bus is Valid
mas_n <= '1';
ias_n <= '1';
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
mds <= '1';
ids <= '1';
-- Master is initiating a synch check, Active LOW
msyncrd_n <= '1';
isyncrd_n <= '1';
-- ROCK send a system HALT due to Error,
msyshalt <= '0';
isyshalt <= '0';
-- ROCK produces a create level AUX reset
msysreset <= '0';
isysreset <= '0';
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
msa <= (others => '0');
isa <= (others => '0');
-------- EXTERNAL DEVICE SELECTION -------
-- External Device selection , Active HIGH
m_ssel <= '0';
i_ssel <= '0';
else
if clk2x'event and clk2x='1' then
-- Trigger Bus, first valid trigger is 001
mt <= xt;
-- Trigger Bus Data is valide, Active LOW
mtrgv_n <= xtrgv_n;
-- Address Bus
ma <= xa;
-- Address Bus is Valid
mas_n <= xas_n;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
mds <= xds;
-- Master is initiating a synch check, Active LOW
msyncrd_n <= xsyncrd_n;
-- ROCK send a system HALT due to Error,
msyshalt <= xsyshalt;
-- ROCK produces a create level AUX reset
msysreset <= xsysreset;
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
msa <= sa;
-------- EXTERNAL DEVICE SELECTION -------
-- External Device selection , Active HIGH
m_ssel <= x_ssel;
------------------------
-- Trigger Bus, first valid trigger is 001
it <= mt;
-- Trigger Bus Data is valide, Active LOW
itrgv_n <= mtrgv_n;
-- Address Bus
ia <= ma;
-- Address Bus is Valid
ias_n <= mas_n;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
ids <= mds;
-- Master is initiating a synch check, Active LOW
isyncrd_n <= msyncrd_n;
-- ROCK send a system HALT due to Error,
isyshalt <= msyshalt;
-- ROCK produces a create level AUX reset
isysreset <= msysreset;
-------- BACKPLANE HARDWIRED INPUT -------
-- Slave Geographical Address
isa <= msa;
-------- EXTERNAL DEVICE SELECTION -------
-- External Device selection , Active HIGH
i_ssel <= m_ssel;
end if;
end if;
end process;
-- Slave Address Selection
ssel <= '0' when rst='1' else
i_ssel when ext_s_en = '1' else
and_reduce (ia xnor isa);
--Signal registering
sig_reg_p: process(clk, rst) is
begin
if rst='1' then
full_r <= '0';
elsif clk'event and clk='1' then
full_r <= full;
end if;
end process;
-- Slave is busy
full <= i_full;-- or full_r;
-- Slave has an error, Active LOW
--xberr_n <= not i_mmatch;
-------- COUNTER -------
-- Counter Seq. Network
cseq_pr: process(clk, rst) is
begin
if rst = '1' then
cps <= reset;
ccntr <= (others => '0');
elsif clk='1' and clk'event then
cps <= cns;
if cps = start then
ccntr <= (0 => '1', others => '0');
else
ccntr <= ccnt;
end if;
end if;
end process;
-- Counter Output Network
ccomb_pr: process(cps, ccnt, ccntr, cvalue) is
begin
case cps is
when reset =>
-- Reset
ccnt <= (others => '0');
cvalid <= '0';
when idle =>
-- Idle
ccnt <= ccntr;
if ccntr=cvalue then
cvalid <= '1';
else
cvalid <= '0';
end if;
when start =>
-- Start
ccnt <= (ccnt'low => '1', others => '0');
cvalid <= '0';
when run =>
-- Run
if ccntr=cvalue then
ccnt <= ccntr;
cvalid <= '1';
else
ccnt <= ccntr + 1;
cvalid <= '0';
end if;
when freerun =>
-- Free Run
ccnt <= ccntr + 1;
--if and_reduce(ccnt) = '1' then
if ccnt=cvalue then
cvalid <= '1';
else
cvalid <= '0';
end if;
when others =>
-- Idle
ccnt <= ccntr;
if ccnt=cvalue then
cvalid <= '1';
else
cvalid <= '0';
end if;
end case;
end process;
-------- PROTOCOL -------
-- Sequential network
xseq_pr: process(clk, rst) is
begin
if rst = '1' then
read_data_r <= '0';
first_word_flag_r <= '0';
pstate <= idle;
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk_r <= '1';
-- Actual Slave Data Word is the last, Active LOW
xeob_n_r <= '1';
-- Slave Data (19 downto 0)
xd_r <= (others => '0');
elsif clk='1' and clk'event then
read_data_r <= read_data;
first_word_flag_r <= first_word_flag;
pstate <= nstate;
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk_r <= odk;
-- Actual Slave Data Word is the last, Active LOW
xeob_n_r <= oeob_n;
-- Slave Data (19 downto 0)
xd_r <= od;
end if;
end process;
-- State Transition Process
-- missing error and reset
xcomb_pr: process(pstate, itrgv_n, isyncrd_n, done, i_nodata) is
begin
-- Trigger Value Request
i_t_req <= '0';
case pstate is
when idle =>
-- Wait for a Trigger Cycle or a Sync Cycle
if (itrgv_n = '0') and (isyncrd_n = '0') then
nstate <= trig;--sync; -- Sync Cycle
elsif (itrgv_n = '0') then
nstate <= trig; -- Trigger Cycle
-- if (i_hdr_d/=xt_s) then
-- nstate <= send_error;
-- end if;
else
nstate <= idle; -- Wait for an event
end if;
when trig =>
-- Trigger Cycle
if (itrgv_n = '1') and (isyncrd_n = '0') and done = '1' then
nstate <= sync;
elsif (itrgv_n = '1') and done = '1' and i_nodata='1' then
nstate <= idle; -- No data
elsif (itrgv_n = '1') and done = '1' then
nstate <= readout; -- Readout Procedure
else
nstate <= trig; -- Wait for an event
end if;
when readout =>
-- Performe the Readout Procedure
if (done = '0') then
nstate <= readout; -- Sending data
else
nstate <= idle; -- End of Frame
end if;
when sync =>
-- Synchronisation Cycle
if ( isyncrd_n = '1') or (done = '1') then
nstate <= idle; -- End of Synchronisation Cycle
i_t_req <= '1';
else
nstate <= sync; -- Performing Synchronisation
end if;
-- when others =>
-- pstate <= idle; -- Wait for an event; or return Error? Halt?
end case;
end process;
ocomb_pr: process(pstate,ids, cvalid, ssel, i_last, ias_n, i_d, isyncrd_n, first_word_flag_r, i_nodata, i_dv, i_t, odk, xdk_r, oeob_n, xeob_n_r, od, xd_r, i_tv, i_hdr_d, i_mmatch, i_hdr_dv, it, full) is
begin
read_data <= '0';
first_word_flag <= '0';
odk <= '1';
oeob_n <= '1';
od <= (others => '0');
read_on_last <= '0';
case pstate is
when idle =>
-- Timing
cvalue <= (others => '0');
done <= '0';
cns <= reset;
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave xsds bit is valid, Active HIGH
xbk <= '0';
-- Slave has an error, Active LOW
xberr_n <= '1';
-- Slave is full, Active LOW
xbusy_n <= not full;
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
tris_en <= '1';
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk <= '1';
-- Actual Slave Data Word is the last, Active LOW
xeob_n <= '1';
-- Slave Data (19 downto 0)
xd <= (others => '0');
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds <= '0';
when trig =>
-- Timing
cvalue <= std_logic_vector(to_unsigned(thold35, Ncnt));
done <= '0';
if (i_hdr_dv='1') and (i_hdr_d=it) and (i_mmatch = '0') then
-- Count 35 ns after data is ready for requested trigger number
cns <= run;
elsif (i_tv='1') and (isyncrd_n = '0') then
cns <= run;
else
-- Waiting data for requested trigger number
cns <= reset;
end if;
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds <= i_nodata and isyncrd_n;
--osds_en <= '0';
-- Slave xsds bit is valid, Active HIGH
xbk <= '0';
if cvalid ='1' then
-- Wait for the end of the trigger cycle (i.e. xtrgv = '1')
xbk <= '1';
done <= '1';
if nstate /= trig then
read_data <= i_nodata and isyncrd_n;
end if;
end if;
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave has an error, Active LOW
xberr_n <= '1';
-- Slave is full, Active LOW
xbusy_n <= not full;
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
tris_en <= '1';
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk <= '1';
-- Actual Slave Data Word is the last, Active LOW
xeob_n <= '1';
-- Slave Data (19 downto 0)
xd <= (others => '0');
-- when readout =>
-- -- Timing
-- cvalue <= (others => '0');
-- done <= '0';
-- cns <= reset;
-- -------- ROCK OPEN COLLECOTR INPUT -------
-- -- Slave xsds bit is valid, Active HIGH
-- xbk <= '0';
-- -- Slave has an error, Active LOW
-- xberr_n <= '1';
-- -- Slave is full, Active LOW
-- xbusy_n <= not full;
-- -------- ROCK TRISTATE INPUT -------
-- -- Slave Enable Tristate (Active Low)
-- tris_en <= '0';
-- -- Slave data is valid, Active LOW
-- -- Slave recognized Master finished cycle, Active HIGH
-- xdk <= '1';
-- -- Actual Slave Data Word is the last, Active LOW
-- xeob_n <= '1';
-- -- Slave Data (19 downto 0)
-- xd <= (others => '0');
-- -- Slave has data for a given Trigger Number
-- -- Can be either tristate or always enabled
-- xsds <= '0';
-- -------- START DATA READOUT -------
-- first_word_flag <= first_word_flag_r;
-- if (ssel = '1') and ias_n = '0' then
-- -- Slave Enable Tristate (Active Low)
-- tris_en <= '1';
-- if (ids = '0') or (i_last = '1') then
-- first_word_flag <= first_word_flag_r or '1';
-- -- Set valid data in xd
-- -- Slave Data (19 downto 0)
-- xd <= i_d;
-- -- Actual Slave Data Word is the last, Active LOW
-- xeob_n <= not i_last;
-- -- Wait for 15ns after data valid
-- cvalue <= std_logic_vector(to_unsigned(thold15, Ncnt));
-- if i_dv = '1' then
-- cns <= run;
-- end if;
-- if cvalid = '1' then
-- -- After 15 ns assert xdk and xeob
-- -- Slave data is valid, Active LOW
-- -- Slave recognized Master finished cycle, Active HIGH
-- xdk <= '0';
-- end if;
-- else
-- -- Request new data
-- read_data <= '1' and first_word_flag_r;
-- end if;
-- elsif first_word_flag_r = '1' then
-- done <= '1';
-- read_data <= '1';
-- end if;
when readout =>
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk <= odk;
odk <= xdk_r;
-- Actual Slave Data Word is the last, Active LOW
xeob_n <= oeob_n;
oeob_n <= xeob_n_r;
-- Slave Data (19 downto 0)
xd <= od;
od <= xd_r;
-- Timing: Wait for 15ns after data valid
cvalue <= std_logic_vector(to_unsigned(thold15, Ncnt));
cns <= reset;
done <= '0';
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave xsds bit is valid, Active HIGH
xbk <= '0';
-- Slave has an error, Active LOW
xberr_n <= '1';
-- Slave is full, Active LOW
xbusy_n <= not full;
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
tris_en <= '0';
-- Latched Output
if (ids = '1') then
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
odk <= '1';
-- Actual Slave Data Word is the last, Active LOW
oeob_n <= not i_last;
-- Slave Data (19 downto 0)
od <= i_d;
end if;
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds <= '0';
-------- START DATA READOUT -------
first_word_flag <= first_word_flag_r;
read_on_last <= read_on_last_r and i_last and read_data and not read_data_r;
if (ssel = '1') and ias_n = '0' then
cns <= run;
if i_dv = '0' then
cns <= reset;
end if;
-- Slave Enable Tristate (Active Low)
tris_en <= '1';
if (ids = '0') then
first_word_flag <= first_word_flag_r or '1';
if cvalid = '1' then
-- After at least 15 ns xdk and xeob are assert
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
odk <= '0'; -- Latched
-- A new data can be requested
read_data <= '1';
end if;
if odk = '0' then
cns <= reset;
end if;
end if;
elsif first_word_flag_r = '1' then
done <= '1';
read_data <= '1';
end if;
-------- END DATA READOUT -------
when sync =>
-- Timing
cvalue <= (others => '0');
done <= '0';
cns <= reset;
-------- ROCK OPEN COLLECOTR INPUT -------
-- Slave xsds bit is valid, Active HIGH
xbk <= '0';
-- Slave has an error, Active LOW
xberr_n <= '1';
-- Slave is full, Active LOW
xbusy_n <= not full;
-------- ROCK TRISTATE INPUT -------
-- Slave Enable Tristate (Active Low)
tris_en <= '0';
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk <= '1';
-- Actual Slave Data Word is the last, Active LOW
xeob_n <= '1';
-- Slave Data (19 downto 0)
xd <= X"00" & i_t;
-- Slave has data for a given Trigger Number
-- Can be either tristate or always enabled
xsds <= '0';
-------- START SYNC READOUT -------
first_word_flag <= first_word_flag_r;
if (ssel = '1') and ias_n = '0' then
cns <= run;
if i_tv = '0' then
cns <= reset;
end if;
-- Slave Enable Tristate (Active Low)
tris_en <= '1';
first_word_flag <= first_word_flag_r or '1';
-- Actual Slave Data Word is the last, Active LOW
xeob_n <= '0';
-- Wait for 15ns after data valid
cvalue <= std_logic_vector(to_unsigned(thold15, Ncnt));
-- if i_tv = '1' then
-- cns <= run;
-- end if;
if cvalid = '1' and ids = '0' then
-- After 15 ns assert xdk and xeob
-- Slave data is valid, Active LOW
-- Slave recognized Master finished cycle, Active HIGH
xdk <= '0';
end if;
elsif first_word_flag_r = '1' then
done <= '1';
end if;
-------- END SYNC READOUT -------
end case;
if nstate /= pstate then
cns <= reset;
end if;
end process;
-- New Data Request
--newdata_req: process(clk, rst) is
--begin
-- if rst = '1' then
-- i_rd_en <= '0';
-- elsif clk'event and clk='1' then
-- if read_data='1' and read_data_r='0' then
-- i_rd_en <= '1';
-- else
-- i_rd_en <= '0';
-- end if;
-- end if;
--end process;
i_rd_en <= '0' when rst = '1' else
'1' when read_data='1' and read_data_r='0' and read_on_last = '0' else
'0';
-- Tristate Output Enable
ts_enable_pr: process(ias_n, tris_en, ssel) is
begin
if (ias_n = '0') and (ssel = '1') then
-- Output depends on the protocol
xsel_n <= not tris_en;
else
-- Output is disabled
xsel_n <= '1';
end if;
end process;
end rtl;
----------------------------------------------------------------------------------
-- Company: LNF - INFN
-- Authors: Albicocco Pietro
-- Contact: [email protected]
----------------------------------------------------------------------------------
-- File Name: xaxi.vhd
-- Target Devices: Xilinx - 7 Series
-- Tool Versions: VIVADO 2015.4
-- Description: Protocol Test Environment.
--
-- Dependencies:
--
----------------------------------------------------------------------------------
-- Revision History:
-- Revision 2.0 - 03/2016 - Albicocco P. - Integrated Test Strategy
----------------------------------------------------------------------------------
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xpack.all;
entity xaxi is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 9
);
port (
-------- Status Registers -------
ro_reg : in ro_reg_type;
-------- Ctrl Registers -------
rw_reg : out rw_reg_type;
-------- AXI-4 PORTS -------
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end xaxi;
architecture arch_imp of xaxi is
-- Read Only Registers
type ro_reg_mat_type is array (69 DOWNTO 0) of std_logic_vector (31 DOWNTO 0);
signal ro_reg_mat : ro_reg_mat_type := (others => (others =>'0'));
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready: std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready: std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- FIFO Signals
signal A_req : std_logic := '0';
signal A_req_r : std_logic := '0';
signal B_req : std_logic := '0';
signal B_req_r : std_logic := '0';
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 6;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 128
-- Reset Register
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := ( rw_defaults.thold35 & -- Delay to be added to the required 35 ns setup time.
rw_defaults.thold15 & -- Delay to be added to the required 15 ns setup time.
x"000" & '0' & -- 31 DOWNTO 3
rw_defaults.triggerreset & -- 2: Trigger Counters Reset (A+B+Local)
rw_defaults.fiforeset & -- 1: Reset FIFOs
rw_defaults.reset ); -- 0: Reset Aux Bus
-- Test Register
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := ( x"0000" & -- 31 DOWNTO 16
rw_defaults.test_Ntrig & -- 15 DOWNTO 4: Unused
rw_defaults.B_is_busy & -- 3: B Busy flag in test mode
rw_defaults.A_is_busy & -- 2: A Busy flag in test mode
rw_defaults.trig_mode & -- 1: Voted Trigger Mode : '0' : Localtrigger (Count trigger only in Local FPGA)
rw_defaults.test_mode ); -- 0: Enable Test Mode: 0 Disable, 1 Enable.
-- FIFO Control Register
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := ( x"0000_00" & b"00" & -- 31 DOWNTO 6
rw_defaults.B_FIFO_write_en & -- 5: Enable Write from B FIFO
rw_defaults.A_FIFO_write_en & -- 4: Enable Write from A FIFO
b"00" & -- 3 DOWNTO 2
rw_defaults.B_FIFO_read_en & -- 1: Enable Read from B FIFO
rw_defaults.A_FIFO_read_en ); -- 0: Enable Read from A FIFO
-- A FIFO Write Data
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);-- := ( rw_defaults.A_write_data ); -- 22 DOWNTO 0
-- B FIFO Write DATA
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);-- := ( rw_defaults.B_write_data ); -- 22 DOWNTO 0
-- TEST FIXED PATTERNS
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := ( "000" &
rw_defaults.A_pattern_isfixed & -- Enable B Fixed Pattern
'0' & rw_defaults.A_Nevent & -- Number of event of B
rw_defaults.A_event_data(0) & -- 1st pattern registers for B
rw_defaults.A_event_data(1) ); -- 2nd pattern registers for B
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := ( x"00" &
rw_defaults.A_event_data(2) & -- 3rd pattern registers for B
rw_defaults.A_event_data(3) ); -- 4th pattern registers for B
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := ( "000" &
rw_defaults.B_pattern_isfixed & -- Enable B Fixed Pattern
'0' & rw_defaults.B_Nevent & -- Number of event of B
rw_defaults.B_event_data(1) & -- 1st pattern registers for B
rw_defaults.B_event_data(0) ); -- 2nd pattern registers for B
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := ( x"00" &
rw_defaults.B_event_data(3) & -- 3rd pattern registers for B
rw_defaults.B_event_data(2) ); -- 4th pattern registers for B
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg32 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg33 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg34 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg35 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg36 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg37 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg38 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg39 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg40 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg41 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg42 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg43 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg44 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg45 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg46 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg47 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg48 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg49 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg50 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg51 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg52 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg53 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg54 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg55 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg56 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg57 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg58 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg59 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg60 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg61 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg62 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg63 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg64 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg65 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg66 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg67 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg68 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg69 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg70 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg71 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg72 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg73 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg74 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg75 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg76 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg77 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg78 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg79 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg80 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg81 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg82 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg83 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg84 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg85 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg86 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg87 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg88 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg89 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg90 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg91 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg92 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg93 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg94 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg95 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg96 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg97 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg98 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg99 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg100 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg101 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg102 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg103 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg104 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg105 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg106 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg107 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg108 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg109 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg110 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg111 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg112 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg113 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg114 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg115 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg116 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg117 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg118 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg119 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg120 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg121 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg122 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg123 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg124 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg125 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg126 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg127 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
--areset <= not S_AXI_ARESETN;
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
if S_AXI_AWADDR = b"0000011" & "00" then
axi_awready <= not ro_reg.A_afull;
elsif S_AXI_AWADDR = b"0000100" & "00" then
axi_awready <= not ro_reg.B_afull;
else
axi_awready <= '1';
end if;
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
if S_AXI_AWADDR = b"0000011" & "00" then
axi_wready <= not ro_reg.A_afull;
elsif S_AXI_AWADDR = b"0000100" & "00" then
axi_wready <= not ro_reg.B_afull;
else
axi_wready <= '1';
end if;
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
rw_reg.A_write_data <= (others => '0');
rw_reg.A_write_en <= '0';
rw_reg.B_write_data <= (others => '0');
rw_reg.B_write_en <= '0';
if S_AXI_ARESETN = '0' then
-- Reset Register
-- Reset Register
slv_reg0 <= ( rw_defaults.thold35 & -- Delay to be added to the required 35 ns setup time.
rw_defaults.thold15 & -- Delay to be added to the required 15 ns setup time.
x"000" & '0' & -- 15 DOWNTO 3
rw_defaults.triggerreset & -- 2
rw_defaults.fiforeset & -- 1
rw_defaults.reset ); -- 0
-- Test Register
slv_reg1 <= ( x"0000" & -- 31 DOWNTO 16
rw_defaults.test_Ntrig & -- 15 DOWNTO 4
rw_defaults.B_is_busy & -- 3
rw_defaults.A_is_busy & -- 2
rw_defaults.trig_mode & -- 1
rw_defaults.test_mode ); -- 0
slv_reg2 <= ( x"0000_00" & b"00" & -- 31 DOWNTO 2
rw_defaults.B_FIFO_write_en & -- 5: Enable Read from B FIFO
rw_defaults.A_FIFO_write_en & -- 4: Enable Read from A FIFO
b"00" & -- 3 DOWNTO 2
rw_defaults.B_FIFO_read_en & -- 1: Enable Read from B FIFO
rw_defaults.A_FIFO_read_en ); -- 0: Enable Read from A FIFO
-- A Write Data (reg 3): rw_reg.A_write_data
slv_reg3 <= (others => '0');
-- B Write Data (reg 4): rw_reg.B_write_data
slv_reg4 <= (others => '0');
-- TEST FIXED PATTERNS
slv_reg5 <= ( "000" &
rw_defaults.A_pattern_isfixed & -- Enable A Fixed Pattern
'0' & rw_defaults.A_Nevent & -- Number of event of A
rw_defaults.A_event_data(1) & -- 1st pattern registers for A
rw_defaults.A_event_data(0) ); -- 2nd pattern registers for A
slv_reg6 <= ( x"00" &
rw_defaults.A_event_data(3) & -- 3rd pattern registers for A
rw_defaults.A_event_data(2) ); -- 4th pattern registers for A
slv_reg7 <= ( "000" &
rw_defaults.B_pattern_isfixed & -- Enable B Fixed Pattern
'0' & rw_defaults.B_Nevent & -- Number of event of B
rw_defaults.B_event_data(1) & -- 1st pattern registers for B
rw_defaults.B_event_data(0) ); -- 2nd pattern registers for B
slv_reg8 <= ( x"00" &
rw_defaults.B_event_data(3) & -- 3rd pattern registers for B
rw_defaults.B_event_data(2) ); -- 4th pattern registers for B
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
slv_reg32 <= (others => '0');
slv_reg33 <= (others => '0');
slv_reg34 <= (others => '0');
slv_reg35 <= (others => '0');
slv_reg36 <= (others => '0');
slv_reg37 <= (others => '0');
slv_reg38 <= (others => '0');
slv_reg39 <= (others => '0');
slv_reg40 <= (others => '0');
slv_reg41 <= (others => '0');
slv_reg42 <= (others => '0');
slv_reg43 <= (others => '0');
slv_reg44 <= (others => '0');
slv_reg45 <= (others => '0');
slv_reg46 <= (others => '0');
slv_reg47 <= (others => '0');
slv_reg48 <= (others => '0');
slv_reg49 <= (others => '0');
slv_reg50 <= (others => '0');
slv_reg51 <= (others => '0');
slv_reg52 <= (others => '0');
slv_reg53 <= (others => '0');
slv_reg54 <= (others => '0');
slv_reg55 <= (others => '0');
slv_reg56 <= (others => '0');
slv_reg57 <= (others => '0');
slv_reg58 <= (others => '0');
slv_reg59 <= (others => '0');
slv_reg60 <= (others => '0');
slv_reg61 <= (others => '0');
slv_reg62 <= (others => '0');
slv_reg63 <= (others => '0');
slv_reg64 <= (others => '0');
slv_reg65 <= (others => '0');
slv_reg66 <= (others => '0');
slv_reg67 <= (others => '0');
slv_reg68 <= (others => '0');
slv_reg69 <= (others => '0');
slv_reg70 <= (others => '0');
slv_reg71 <= (others => '0');
slv_reg72 <= (others => '0');
slv_reg73 <= (others => '0');
slv_reg74 <= (others => '0');
slv_reg75 <= (others => '0');
slv_reg76 <= (others => '0');
slv_reg77 <= (others => '0');
slv_reg78 <= (others => '0');
slv_reg79 <= (others => '0');
slv_reg80 <= (others => '0');
slv_reg81 <= (others => '0');
slv_reg82 <= (others => '0');
slv_reg83 <= (others => '0');
slv_reg84 <= (others => '0');
slv_reg85 <= (others => '0');
slv_reg86 <= (others => '0');
slv_reg87 <= (others => '0');
slv_reg88 <= (others => '0');
slv_reg89 <= (others => '0');
slv_reg90 <= (others => '0');
slv_reg91 <= (others => '0');
slv_reg92 <= (others => '0');
slv_reg93 <= (others => '0');
slv_reg94 <= (others => '0');
slv_reg95 <= (others => '0');
slv_reg96 <= (others => '0');
slv_reg97 <= (others => '0');
slv_reg98 <= (others => '0');
slv_reg99 <= (others => '0');
slv_reg100 <= (others => '0');
slv_reg101 <= (others => '0');
slv_reg102 <= (others => '0');
slv_reg103 <= (others => '0');
slv_reg104 <= (others => '0');
slv_reg105 <= (others => '0');
slv_reg106 <= (others => '0');
slv_reg107 <= (others => '0');
slv_reg108 <= (others => '0');
slv_reg109 <= (others => '0');
slv_reg110 <= (others => '0');
slv_reg111 <= (others => '0');
slv_reg112 <= (others => '0');
slv_reg113 <= (others => '0');
slv_reg114 <= (others => '0');
slv_reg115 <= (others => '0');
slv_reg116 <= (others => '0');
slv_reg117 <= (others => '0');
slv_reg118 <= (others => '0');
slv_reg119 <= (others => '0');
slv_reg120 <= (others => '0');
slv_reg121 <= (others => '0');
slv_reg122 <= (others => '0');
slv_reg123 <= (others => '0');
slv_reg124 <= (others => '0');
slv_reg125 <= (others => '0');
slv_reg126 <= (others => '0');
slv_reg127 <= (others => '0');
else
--------------------- Read Only Registers ---------------------
slv_reg32 <= ro_reg_mat(0);
slv_reg33 <= ro_reg_mat(1);
slv_reg34 <= ro_reg_mat(2);
-- Used for A FIFO DATA Read
slv_reg35 <= ro_reg_mat(3);
-- Used for B FIFO DATA Read
slv_reg36 <= ro_reg_mat(4);
slv_reg37 <= ro_reg_mat(5);
slv_reg38 <= ro_reg_mat(6);
slv_reg39 <= ro_reg_mat(7);
slv_reg40 <= ro_reg_mat(8);
slv_reg41 <= ro_reg_mat(9);
slv_reg42 <= ro_reg_mat(10);
slv_reg43 <= ro_reg_mat(11);
slv_reg44 <= ro_reg_mat(12);
slv_reg45 <= ro_reg_mat(13);
slv_reg46 <= ro_reg_mat(14);
slv_reg47 <= ro_reg_mat(15);
slv_reg48 <= ro_reg_mat(16);
slv_reg49 <= ro_reg_mat(17);
slv_reg50 <= ro_reg_mat(18);
slv_reg51 <= ro_reg_mat(19);
slv_reg52 <= ro_reg_mat(20);
slv_reg53 <= ro_reg_mat(21);
slv_reg54 <= ro_reg_mat(22);
slv_reg55 <= ro_reg_mat(23);
slv_reg56 <= ro_reg_mat(24);
slv_reg57 <= ro_reg_mat(25);
slv_reg58 <= ro_reg_mat(26);
slv_reg59 <= ro_reg_mat(27);
slv_reg60 <= ro_reg_mat(28);
slv_reg61 <= ro_reg_mat(29);
slv_reg62 <= ro_reg_mat(30);
slv_reg63 <= ro_reg_mat(31);
slv_reg64 <= ro_reg_mat(32);
slv_reg65 <= ro_reg_mat(33);
slv_reg66 <= ro_reg_mat(34);
slv_reg67 <= ro_reg_mat(35);
slv_reg68 <= ro_reg_mat(36);
slv_reg69 <= ro_reg_mat(37);
slv_reg70 <= ro_reg_mat(38);
slv_reg71 <= ro_reg_mat(39);
slv_reg72 <= ro_reg_mat(40);
slv_reg73 <= ro_reg_mat(41);
slv_reg74 <= ro_reg_mat(42);
slv_reg75 <= ro_reg_mat(43);
slv_reg76 <= ro_reg_mat(44);
slv_reg77 <= ro_reg_mat(45);
slv_reg78 <= ro_reg_mat(46);
slv_reg79 <= ro_reg_mat(47);
slv_reg80 <= ro_reg_mat(48);
slv_reg81 <= ro_reg_mat(49);
slv_reg82 <= ro_reg_mat(50);
slv_reg83 <= ro_reg_mat(51);
slv_reg84 <= ro_reg_mat(52);
slv_reg85 <= ro_reg_mat(53);
slv_reg86 <= ro_reg_mat(54);
slv_reg87 <= ro_reg_mat(55);
slv_reg88 <= ro_reg_mat(56);
slv_reg89 <= ro_reg_mat(57);
slv_reg90 <= ro_reg_mat(58);
slv_reg91 <= ro_reg_mat(59);
slv_reg92 <= ro_reg_mat(60);
slv_reg93 <= ro_reg_mat(61);
slv_reg94 <= ro_reg_mat(62);
slv_reg95 <= ro_reg_mat(63);
slv_reg96 <= ro_reg_mat(64);
slv_reg97 <= ro_reg_mat(65);
slv_reg98 <= ro_reg_mat(66);
slv_reg99 <= ro_reg_mat(67);
slv_reg100 <= ro_reg_mat(68);
slv_reg101 <= ro_reg_mat(69);
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
rw_reg.A_write_data(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); --S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
rw_reg.A_write_en <= '1';
end if;
end loop;
when b"0000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
rw_reg.B_write_data(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); --S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
rw_reg.B_write_en <= '1';
end if;
end loop;
when b"0000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 24
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 25
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 26
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 27
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 28
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 29
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 30
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 31
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"0100000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 32
-- slv_reg32(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0100001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 33
-- slv_reg33(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0100010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 34
-- slv_reg34(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0100011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 35
-- slv_reg35(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0100100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 36
-- slv_reg36(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0100101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 37
-- slv_reg37(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0100110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 38
-- slv_reg38(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0100111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 39
-- slv_reg39(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 40
-- slv_reg40(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 41
-- slv_reg41(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 42
-- slv_reg42(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 43
-- slv_reg43(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 44
-- slv_reg44(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 45
-- slv_reg45(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 46
-- slv_reg46(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0101111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 47
-- slv_reg47(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 48
-- slv_reg48(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 49
-- slv_reg49(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 50
-- slv_reg50(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 51
-- slv_reg51(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 52
-- slv_reg52(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 53
-- slv_reg53(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 54
-- slv_reg54(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0110111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 55
-- slv_reg55(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 56
-- slv_reg56(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 57
-- slv_reg57(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 58
-- slv_reg58(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 59
-- slv_reg59(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 60
-- slv_reg60(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 61
-- slv_reg61(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 62
-- slv_reg62(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"0111111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 63
-- slv_reg63(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 64
-- slv_reg64(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 65
-- slv_reg65(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 66
-- slv_reg66(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 67
-- slv_reg67(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 68
-- slv_reg68(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 69
-- slv_reg69(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 70
-- slv_reg70(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1000111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 71
-- slv_reg71(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 72
-- slv_reg72(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 73
-- slv_reg73(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 74
-- slv_reg74(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 75
-- slv_reg75(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 76
-- slv_reg76(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 77
-- slv_reg77(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 78
-- slv_reg78(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1001111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 79
-- slv_reg79(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 80
-- slv_reg80(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 81
-- slv_reg81(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 82
-- slv_reg82(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 83
-- slv_reg83(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 84
-- slv_reg84(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 85
-- slv_reg85(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 86
-- slv_reg86(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1010111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 87
-- slv_reg87(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 88
-- slv_reg88(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 89
-- slv_reg89(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 90
-- slv_reg90(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 91
-- slv_reg91(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 92
-- slv_reg92(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 93
-- slv_reg93(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011110" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 94
-- slv_reg94(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1011111" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 95
-- slv_reg95(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1100000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 96
-- slv_reg96(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1100001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 97
-- slv_reg97(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1100010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 98
-- slv_reg98(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1100011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 99
-- slv_reg99(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1100100" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 100
-- slv_reg100(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"1100101" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 101
-- slv_reg101(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"1100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 102
slv_reg102(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 103
slv_reg103(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 104
slv_reg104(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 105
slv_reg105(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 106
slv_reg106(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 107
slv_reg107(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 108
slv_reg108(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 109
slv_reg109(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 110
slv_reg110(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 111
slv_reg111(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 112
slv_reg112(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 113
slv_reg113(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 114
slv_reg114(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 115
slv_reg115(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 116
slv_reg116(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 117
slv_reg117(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 118
slv_reg118(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 119
slv_reg119(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 120
slv_reg120(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 121
slv_reg121(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 122
slv_reg122(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 123
slv_reg123(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 124
slv_reg124(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 125
slv_reg125(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 126
slv_reg126(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 127
slv_reg127(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
--------------------- Read Write Registers -------------------
-- The register are written starting from the right (i.e. LSB)
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
slv_reg102 <= slv_reg102;
slv_reg103 <= slv_reg103;
slv_reg104 <= slv_reg104;
slv_reg105 <= slv_reg105;
slv_reg106 <= slv_reg106;
slv_reg107 <= slv_reg107;
slv_reg108 <= slv_reg108;
slv_reg109 <= slv_reg109;
slv_reg110 <= slv_reg110;
slv_reg111 <= slv_reg111;
slv_reg112 <= slv_reg112;
slv_reg113 <= slv_reg113;
slv_reg114 <= slv_reg114;
slv_reg115 <= slv_reg115;
slv_reg116 <= slv_reg116;
slv_reg117 <= slv_reg117;
slv_reg118 <= slv_reg118;
slv_reg119 <= slv_reg119;
slv_reg120 <= slv_reg120;
slv_reg121 <= slv_reg121;
slv_reg122 <= slv_reg122;
slv_reg123 <= slv_reg123;
slv_reg124 <= slv_reg124;
slv_reg125 <= slv_reg125;
slv_reg126 <= slv_reg126;
slv_reg127 <= slv_reg127;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
A_req <= '0';
B_req <= '0';
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
--out alp: AXI get stuck if fifo is empty => empty moved also in fifo data reg.
-- if S_AXI_ARADDR = b"0100011" & "00" then -- 35
-- axi_arready <= not ro_reg.A_empty;
-- A_req <= not ro_reg.A_empty;
-- elsif S_AXI_ARADDR = b"0100100" & "00" then -- 36
-- axi_arready <= not ro_reg.B_empty;
-- B_req <= not ro_reg.B_empty;
-- else
-- axi_arready <= '1';
-- end if;
axi_arready <= '1';
if S_AXI_ARADDR = b"0100011" & "00" then -- 35
A_req <= not ro_reg.A_empty;
elsif S_AXI_ARADDR = b"0100100" & "00" then -- 36
B_req <= not ro_reg.B_empty;
end if;
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
rw_reg.A_read_en <= '0';
rw_reg.B_read_en <= '0';
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
A_req_r <= '0';
B_req_r <= '0';
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
A_req_r <= A_req;
B_req_r <= B_req;
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
A_req_r <= '0';
B_req_r <= '0';
rw_reg.A_read_en <= A_req_r;
rw_reg.B_read_en <= B_req_r;
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39, slv_reg40, slv_reg41, slv_reg42, slv_reg43, slv_reg44, slv_reg45, slv_reg46, slv_reg47, slv_reg48, slv_reg49, slv_reg50, slv_reg51, slv_reg52, slv_reg53, slv_reg54, slv_reg55, slv_reg56, slv_reg57, slv_reg58, slv_reg59, slv_reg60, slv_reg61, slv_reg62, slv_reg63, slv_reg64, slv_reg65, slv_reg66, slv_reg67, slv_reg68, slv_reg69, slv_reg70, slv_reg71, slv_reg72, slv_reg73, slv_reg74, slv_reg75, slv_reg76, slv_reg77, slv_reg78, slv_reg79, slv_reg80, slv_reg81, slv_reg82, slv_reg83, slv_reg84, slv_reg85, slv_reg86, slv_reg87, slv_reg88, slv_reg89, slv_reg90, slv_reg91, slv_reg92, slv_reg93, slv_reg94, slv_reg95, slv_reg96, slv_reg97, slv_reg98, slv_reg99, slv_reg100, slv_reg101, slv_reg102, slv_reg103, slv_reg104, slv_reg105, slv_reg106, slv_reg107, slv_reg108, slv_reg109, slv_reg110, slv_reg111, slv_reg112, slv_reg113, slv_reg114, slv_reg115, slv_reg116, slv_reg117, slv_reg118, slv_reg119, slv_reg120, slv_reg121, slv_reg122, slv_reg123, slv_reg124, slv_reg125, slv_reg126, slv_reg127, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000000" =>
reg_data_out <= slv_reg0;
when b"0000001" =>
reg_data_out <= slv_reg1;
when b"0000010" =>
reg_data_out <= slv_reg2;
when b"0000011" =>
reg_data_out <= slv_reg3;
when b"0000100" =>
reg_data_out <= slv_reg4;
when b"0000101" =>
reg_data_out <= slv_reg5;
when b"0000110" =>
reg_data_out <= slv_reg6;
when b"0000111" =>
reg_data_out <= slv_reg7;
when b"0001000" =>
reg_data_out <= slv_reg8;
when b"0001001" =>
reg_data_out <= slv_reg9;
when b"0001010" =>
reg_data_out <= slv_reg10;
when b"0001011" =>
reg_data_out <= slv_reg11;
when b"0001100" =>
reg_data_out <= slv_reg12;
when b"0001101" =>
reg_data_out <= slv_reg13;
when b"0001110" =>
reg_data_out <= slv_reg14;
when b"0001111" =>
reg_data_out <= slv_reg15;
when b"0010000" =>
reg_data_out <= slv_reg16;
when b"0010001" =>
reg_data_out <= slv_reg17;
when b"0010010" =>
reg_data_out <= slv_reg18;
when b"0010011" =>
reg_data_out <= slv_reg19;
when b"0010100" =>
reg_data_out <= slv_reg20;
when b"0010101" =>
reg_data_out <= slv_reg21;
when b"0010110" =>
reg_data_out <= slv_reg22;
when b"0010111" =>
reg_data_out <= slv_reg23;
when b"0011000" =>
reg_data_out <= slv_reg24;
when b"0011001" =>
reg_data_out <= slv_reg25;
when b"0011010" =>
reg_data_out <= slv_reg26;
when b"0011011" =>
reg_data_out <= slv_reg27;
when b"0011100" =>
reg_data_out <= slv_reg28;
when b"0011101" =>
reg_data_out <= slv_reg29;
when b"0011110" =>
reg_data_out <= slv_reg30;
when b"0011111" =>
reg_data_out <= slv_reg31;
when b"0100000" =>
reg_data_out <= slv_reg32;
when b"0100001" =>
reg_data_out <= slv_reg33;
when b"0100010" =>
reg_data_out <= slv_reg34;
when b"0100011" =>
reg_data_out <= "000" & ro_reg.A_empty & x"0" & b"00" & ro_reg.A_read_data;
when b"0100100" =>
reg_data_out <= "000" & ro_reg.B_empty & x"0" & b"00" & ro_reg.B_read_data;
when b"0100101" =>
reg_data_out <= slv_reg37;
when b"0100110" =>
reg_data_out <= slv_reg38;
when b"0100111" =>
reg_data_out <= slv_reg39;
when b"0101000" =>
reg_data_out <= slv_reg40;
when b"0101001" =>
reg_data_out <= slv_reg41;
when b"0101010" =>
reg_data_out <= slv_reg42;
when b"0101011" =>
reg_data_out <= slv_reg43;
when b"0101100" =>
reg_data_out <= slv_reg44;
when b"0101101" =>
reg_data_out <= slv_reg45;
when b"0101110" =>
reg_data_out <= slv_reg46;
when b"0101111" =>
reg_data_out <= slv_reg47;
when b"0110000" =>
reg_data_out <= slv_reg48;
when b"0110001" =>
reg_data_out <= slv_reg49;
when b"0110010" =>
reg_data_out <= slv_reg50;
when b"0110011" =>
reg_data_out <= slv_reg51;
when b"0110100" =>
reg_data_out <= slv_reg52;
when b"0110101" =>
reg_data_out <= slv_reg53;
when b"0110110" =>
reg_data_out <= slv_reg54;
when b"0110111" =>
reg_data_out <= slv_reg55;
when b"0111000" =>
reg_data_out <= slv_reg56;
when b"0111001" =>
reg_data_out <= slv_reg57;
when b"0111010" =>
reg_data_out <= slv_reg58;
when b"0111011" =>
reg_data_out <= slv_reg59;
when b"0111100" =>
reg_data_out <= slv_reg60;
when b"0111101" =>
reg_data_out <= slv_reg61;
when b"0111110" =>
reg_data_out <= slv_reg62;
when b"0111111" =>
reg_data_out <= slv_reg63;
when b"1000000" =>
reg_data_out <= slv_reg64;
when b"1000001" =>
reg_data_out <= slv_reg65;
when b"1000010" =>
reg_data_out <= slv_reg66;
when b"1000011" =>
reg_data_out <= slv_reg67;
when b"1000100" =>
reg_data_out <= slv_reg68;
when b"1000101" =>
reg_data_out <= slv_reg69;
when b"1000110" =>
reg_data_out <= slv_reg70;
when b"1000111" =>
reg_data_out <= slv_reg71;
when b"1001000" =>
reg_data_out <= slv_reg72;
when b"1001001" =>
reg_data_out <= slv_reg73;
when b"1001010" =>
reg_data_out <= slv_reg74;
when b"1001011" =>
reg_data_out <= slv_reg75;
when b"1001100" =>
reg_data_out <= slv_reg76;
when b"1001101" =>
reg_data_out <= slv_reg77;
when b"1001110" =>
reg_data_out <= slv_reg78;
when b"1001111" =>
reg_data_out <= slv_reg79;
when b"1010000" =>
reg_data_out <= slv_reg80;
when b"1010001" =>
reg_data_out <= slv_reg81;
when b"1010010" =>
reg_data_out <= slv_reg82;
when b"1010011" =>
reg_data_out <= slv_reg83;
when b"1010100" =>
reg_data_out <= slv_reg84;
when b"1010101" =>
reg_data_out <= slv_reg85;
when b"1010110" =>
reg_data_out <= slv_reg86;
when b"1010111" =>
reg_data_out <= slv_reg87;
when b"1011000" =>
reg_data_out <= slv_reg88;
when b"1011001" =>
reg_data_out <= slv_reg89;
when b"1011010" =>
reg_data_out <= slv_reg90;
when b"1011011" =>
reg_data_out <= slv_reg91;
when b"1011100" =>
reg_data_out <= slv_reg92;
when b"1011101" =>
reg_data_out <= slv_reg93;
when b"1011110" =>
reg_data_out <= slv_reg94;
when b"1011111" =>
reg_data_out <= slv_reg95;
when b"1100000" =>
reg_data_out <= slv_reg96;
when b"1100001" =>
reg_data_out <= slv_reg97;
when b"1100010" =>
reg_data_out <= slv_reg98;
when b"1100011" =>
reg_data_out <= slv_reg99;
when b"1100100" =>
reg_data_out <= slv_reg100;
when b"1100101" =>
reg_data_out <= slv_reg101;
when b"1100110" =>
reg_data_out <= slv_reg102;
when b"1100111" =>
reg_data_out <= slv_reg103;
when b"1101000" =>
reg_data_out <= slv_reg104;
when b"1101001" =>
reg_data_out <= slv_reg105;
when b"1101010" =>
reg_data_out <= slv_reg106;
when b"1101011" =>
reg_data_out <= slv_reg107;
when b"1101100" =>
reg_data_out <= slv_reg108;
when b"1101101" =>
reg_data_out <= slv_reg109;
when b"1101110" =>
reg_data_out <= slv_reg110;
when b"1101111" =>
reg_data_out <= slv_reg111;
when b"1110000" =>
reg_data_out <= slv_reg112;
when b"1110001" =>
reg_data_out <= slv_reg113;
when b"1110010" =>
reg_data_out <= slv_reg114;
when b"1110011" =>
reg_data_out <= slv_reg115;
when b"1110100" =>
reg_data_out <= slv_reg116;
when b"1110101" =>
reg_data_out <= slv_reg117;
when b"1110110" =>
reg_data_out <= slv_reg118;
when b"1110111" =>
reg_data_out <= slv_reg119;
when b"1111000" =>
reg_data_out <= slv_reg120;
when b"1111001" =>
reg_data_out <= slv_reg121;
when b"1111010" =>
reg_data_out <= slv_reg122;
when b"1111011" =>
reg_data_out <= slv_reg123;
when b"1111100" =>
reg_data_out <= slv_reg124;
when b"1111101" =>
reg_data_out <= slv_reg125;
when b"1111110" =>
reg_data_out <= slv_reg126;
when b"1111111" =>
reg_data_out <= slv_reg127;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
--------------------
-- ro_reg: Read Only Register
--------------------
-- AXI Address is shifted by 32 with respect to ro_reg_mat address.
-------- Test Triggers -------
-- A FIFO Trigger Number (Test Mode)
ro_reg_mat(0)(11 DOWNTO 0) <= ro_reg.atest_Ntrig;
-- B FIFO Trigger Number (Test Mode)
ro_reg_mat(0)(27 DOWNTO 16) <= ro_reg.btest_Ntrig;
-------- Trigger Voter -------
-- Voted Trigger Number Valid
ro_reg_mat(1)(12) <= ro_reg.Ntrig_voter_v;
-- Voted Trigger Number
ro_reg_mat(1)(11 DOWNTO 0) <= ro_reg.Ntrig_voter;
-------- Trigger Counters -------
-- Local Trigger Number
ro_reg_mat(1)(27 DOWNTO 16) <= ro_reg.Ntrig_local;
-- FPGA A Trigger Number
ro_reg_mat(2)(11 DOWNTO 0) <= ro_reg.Ntrig_devA;
-- FPGA B Trigger Number
ro_reg_mat(2)(27 DOWNTO 16) <= ro_reg.Ntrig_devB;
-- Reg 35 and 36 used to read data from A and B FIFO respectively.
-------- XFIFO -------
-- A FIFO Full
ro_reg_mat(5)(0) <= ro_reg.AFIFO_isfull;
-- A FIFO Almost Full
ro_reg_mat(5)(1) <= ro_reg.AFIFO_isafull;
-- A FIFO Prog Full
ro_reg_mat(5)(2) <= ro_reg.AFIFO_ispfull;
-- A FIFO Empty
ro_reg_mat(5)(3) <= ro_reg.AFIFO_isempty;
-- B FIFO Full
ro_reg_mat(5)(4) <= ro_reg.BFIFO_isfull;
-- B FIFO Almost Full
ro_reg_mat(5)(5) <= ro_reg.BFIFO_isafull;
-- B FIFO Prog Full
ro_reg_mat(5)(6) <= ro_reg.BFIFO_ispfull;
-- B FIFO Empty
ro_reg_mat(5)(7) <= ro_reg.BFIFO_isempty;
--------------------
-- rw_reg: Read Write Registers
--------------------
-------- RESET -------
-- Reset Aux Bus
rw_reg.reset <= slv_reg0(0);
-- Reset FIFOs
rw_reg.fiforeset <= slv_reg0(1);
-- Trigger Counters Reset (A+B+Local)
rw_reg.triggerreset <= slv_reg0(2);
-------- AUX TIMINGS -------
-- Delay to be added to the required 35 ns setup time.
rw_reg.thold35 <= slv_reg0(31 downto 24);
-- Delay to be added to the required 15 ns setup time.
rw_reg.thold15 <= slv_reg0(23 downto 16);
-------- TEST -------
-- Enable Test Mode: 0 Disable, 1 Enable.
rw_reg.test_mode <= slv_reg1(0);
-- Trigger Mode : 1: Voted Trigger Mode : '0' : Localtrigger (Count trigger only in Local FPGA)
rw_reg.trig_mode <= slv_reg1(1);
-- Test Trigger Number
rw_reg.test_Ntrig <= slv_reg1(15 DOWNTO 4);
-- A Busy flag in test mode
rw_reg.A_is_busy <= slv_reg1(2);
-- B Busy flag in test mode
rw_reg.B_is_busy <= slv_reg1(3);
-------- AXI FIFO -------
rw_reg.A_FIFO_read_en <= slv_reg2(0);
rw_reg.B_FIFO_read_en <= slv_reg2(1);
rw_reg.A_FIFO_write_en <= slv_reg2(4);
rw_reg.B_FIFO_write_en <= slv_reg2(5);
-- Note: slv_reg3 and 4 used to write data in A and B FIFO
-- Enable A Fixed Pattern
rw_reg.A_pattern_isfixed <= slv_reg5(28);
-- Number of event of A
rw_reg.A_Nevent <= slv_reg5(26 downto 24);
-- 4 pattern registers for A
rw_reg.A_event_data <= (slv_reg5(11 downto 0), slv_reg5(23 downto 12), slv_reg6(11 downto 0), slv_reg6(23 downto 12));
-- Enable B Fixed Pattern
rw_reg.B_pattern_isfixed <= slv_reg7(28);
-- Number of event of B
rw_reg.B_Nevent <= slv_reg7(26 downto 24);
-- 4 pattern registers for B
rw_reg.B_event_data <= (slv_reg7(11 downto 0), slv_reg7(23 downto 12), slv_reg8(11 downto 0), slv_reg8(23 downto 12));
end arch_imp;
|
mit
|
8b5d2205ec3a50a9f5604c6740425482
| 0.507033 | 3.51021 | false | false | false | false |
freecores/w11
|
rtl/ibus/ib_sres_or_2.vhd
| 2 | 2,410 |
-- $Id: ib_sres_or_2.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_2 - syn
-- Description: ibus: result or, 2 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_2 is -- ibus result or, 2 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_2;
architecture syn of ib_sres_or_2 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => ib_sres_init,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
c5ca580a57603e916dbf4683ca224a30
| 0.557261 | 3.305898 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd
| 1 | 7,894 |
-- $Id: tst_fx2loop.vhd 510 2013-04-26 16:14:57Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop - syn
-- Description: simple stand-alone tester for fx2lib components
--
-- Dependencies: comlib/byte2word
-- comlib/word2byte
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next
-- 2012-01-15 453 1.0 Initial version
-- 2011-12-26 445 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
-- ----------------------------------------------------------------------------
entity tst_fx2loop is -- tester for fx2lib components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit; -- transmit busy
TX2DATA : out slv8; -- transmit 2 data in
TX2ENA : out slbit; -- transmit 2 data enable
TX2BUSY : in slbit -- transmit 2 busy
);
end tst_fx2loop;
architecture syn of tst_fx2loop is
type regs_type is record
rxdata : slv16; -- next rx word
txdata : slv16; -- next tx word
tx2data : slv16; -- next tx2 word
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx word counter
txcnt : slv32; -- tx word counter
tx2cnt : slv32; -- tx2 word counter
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- tx2data
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- tx2cnt
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RXWDATA : slv16 := (others=>'0');
signal RXWVAL : slbit := '0';
signal RXWHOLD : slbit := '0';
signal RXODD : slbit := '0';
signal TXWDATA : slv16 := (others=>'0');
signal TXWENA : slbit := '0';
signal TXWBUSY : slbit := '0';
signal TXODD : slbit := '0';
signal TX2WDATA : slv16 := (others=>'0');
signal TX2WENA : slbit := '0';
signal TX2WBUSY : slbit := '0';
signal TX2ODD : slbit := '0';
signal RXHOLD_L : slbit := '0'; -- local copy of out port signal
signal TXENA_L : slbit := '0'; -- local copy of out port signal
signal TX2ENA_L : slbit := '0'; -- local copy of out port signal
signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal
begin
CNTL_RESET_L <= '0'; -- so far unused
RXB2W : byte2word
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => RXDATA,
ENA => RXVAL,
BUSY => RXHOLD_L,
DO => RXWDATA,
VAL => RXWVAL,
HOLD => RXWHOLD,
ODD => RXODD
);
TX1W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TXWDATA,
ENA => TXWENA,
BUSY => TXWBUSY,
DO => TXDATA,
VAL => TXENA_L,
HOLD => TXBUSY,
ODD => TXODD
);
TX2W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TX2WDATA,
ENA => TX2WENA,
BUSY => TX2WBUSY,
DO => TX2DATA,
VAL => TX2ENA_L,
HOLD => TX2BUSY,
ODD => TX2ODD
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI,
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY,
RXHOLD_L, TXBUSY, TX2BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxwhold : slbit := '1';
variable itxwena : slbit := '0';
variable itxwdata : slv16 := (others=>'0');
variable itx2wena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irxwhold := '1';
itxwena := '0';
itxwdata := RXWDATA;
itx2wena := '0';
if HIO_CNTL.throttle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXWVAL='1' and r.rxthrottle='0' then
irxwhold := '0';
if RXWDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := slv(unsigned(RXWDATA) + 1);
end if;
when c_mode_txblast =>
itxwdata := r.txdata;
if TXWBUSY = '0' then
itxwena := '1';
n.txdata := slv(unsigned(r.txdata) + 1);
end if;
irxwhold := '0';
when c_mode_loop =>
itxwdata := RXWDATA;
if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then
irxwhold := '0';
itxwena := '1';
end if;
when others => null;
end case;
if HIO_CNTL.tx2blast = '1' then
if TX2WBUSY = '0' then
itx2wena := '1';
n.tx2data := slv(unsigned(r.tx2data) + 1);
end if;
end if;
if RXWVAL='1' and irxwhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxwena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
if itx2wena = '1' then
n.tx2cnt := slv(unsigned(r.tx2cnt) + 1);
end if;
N_REGS <= n;
RXWHOLD <= irxwhold;
TXWENA <= itxwena;
TXWDATA <= itxwdata;
TX2WENA <= itx2wena;
TX2WDATA <= r.tx2data;
HIO_STAT.rxhold <= RXHOLD_L;
HIO_STAT.txbusy <= TXBUSY;
HIO_STAT.tx2busy <= TX2BUSY;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.tx2cnt <= r.tx2cnt;
end process proc_next;
RXHOLD <= RXHOLD_L;
TXENA <= TXENA_L;
TX2ENA <= TX2ENA_L;
end syn;
|
gpl-2.0
|
c4155ad1c9241a2ece6037d1da4d2f2c
| 0.50342 | 3.624426 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd
| 1 | 18,705 |
-- $Id: tb_tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/simlib/simclkcnt
-- vlib/serport/serport_uart_rxtx
-- vlib/serport/serport_xontx
--
-- To test: sys_tst_serloop_xx
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclkcnt
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_tst_serloop is
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
CLK_STOP : out slbit; -- clock stop
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
P0_CTS_N : out slbit; -- port 0 cts_n
P1_RXD : out slbit; -- port 1 receive data (board view)
P1_TXD : in slbit; -- port 1 transmit data (board view)
P1_RTS_N : in slbit; -- port 1 rts_n
P1_CTS_N : out slbit; -- port 1 cts_n
SWI : out slv8; -- hio switches
BTN : out slv4 -- hio buttons
);
end tb_tst_serloop;
architecture sim of tb_tst_serloop is
signal CLK_STOP_L : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal ACTPORT : slbit := '0';
signal BREAK : slbit := '0';
signal CTS_CYCLE : integer := 0;
signal CTS_FRACT : integer := 0;
signal XON_CYCLE : integer := 0;
signal XON_FRACT : integer := 0;
signal S2M_ACTIVE : slbit := '0';
signal S2M_SIZE : integer := 0;
signal S2M_ENAESC : slbit := '0';
signal S2M_ENAXON : slbit := '0';
signal M2S_XONSEEN : slbit := '0';
signal M2S_XOFFSEEN : slbit := '0';
signal R_XONRXOK : slbit := '1';
signal R_XONTXOK : slbit := '1';
begin
CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE);
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLKS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
XONTX : serport_xontx
port map (
CLK => CLKS,
RESET => UART_RESET,
ENAXON => S2M_ENAXON,
ENAESC => S2M_ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => UART_TXENA,
UART_TXBUSY => UART_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => R_XONRXOK,
TXOK => R_XONTXOK
);
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
variable eff_txd : slbit := '0';
begin
if BREAK = '0' then -- if no break active
eff_txd := UART_TXD; -- send uart
else -- otherwise
eff_txd := '0'; -- force '0'
end if;
if ACTPORT = '0' then -- use port 0
P0_RXD <= eff_txd; -- write port 0 inputs
P0_CTS_N <= CTS_N;
UART_RXD <= P0_TXD; -- get port 0 outputs
RTS_N <= P0_RTS_N;
P1_RXD <= '1'; -- port 1 inputs to idle state
P1_CTS_N <= '0';
else -- use port 1
P1_RXD <= eff_txd; -- write port 1 inputs
P1_CTS_N <= CTS_N;
UART_RXD <= P1_TXD; -- get port 1 outputs
RTS_N <= P1_RTS_N;
P0_RXD <= '1'; -- port 0 inputs to idle state
P0_CTS_N <= '0';
end if;
end process proc_port_mux;
proc_cts: process(CLKS)
variable cts_timer : integer := 0;
begin
if rising_edge(CLKS) then
if CTS_CYCLE = 0 then -- if cts throttle off
CTS_N <= '0'; -- cts permanently asserted
else -- otherwise determine throttling
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
cts_timer := cts_timer - 1; -- decrement
else
cts_timer := CTS_CYCLE-1; -- otherwise reload
end if;
if cts_timer < cts_fract then -- if in lower 'fract' counts
CTS_N <= '1'; -- throttle: deassert CTS
else -- otherwise
CTS_N <= '0'; -- let go: assert CTS
end if;
end if;
end if;
end process proc_cts;
proc_xonrxok: process(CLKS)
variable xon_timer : integer := 0;
begin
if rising_edge(CLKS) then
if XON_CYCLE = 0 then -- if xon throttle off
R_XONRXOK <= '1'; -- xonrxok permanently asserted
else -- otherwise determine throttling
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
xon_timer := xon_timer - 1; -- decrement
else
xon_timer := XON_CYCLE-1; -- otherwise reload
end if;
if xon_timer < xon_fract then -- if in lower 'fract' counts
R_XONRXOK <= '0'; -- throttle: deassert xonrxok
else -- otherwise
R_XONRXOK <= '1'; -- let go: assert xonrxok
end if;
end if;
end if;
end process proc_xonrxok;
proc_xontxok: process(CLKS)
begin
if rising_edge(CLKS) then
if M2S_XONSEEN = '1' then
R_XONTXOK <= '1';
elsif M2S_XOFFSEEN = '1' then
R_XONTXOK <= '0';
end if;
end if;
end process proc_xontxok;
proc_stim: process
file fstim : text open read_mode is "tb_tst_serloop_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable iactport : slbit := '0';
variable iswi : slv8 := (others=>'0');
variable btn_num : integer := 0;
variable i_cycle : integer := 0;
variable i_fract : integer := 0;
variable nbyte : integer := 0;
variable enaesc : slbit := '0';
variable enaxon : slbit := '0';
variable bcnt : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
procedure waitclk(ncyc : in integer) is
begin
for i in 1 to ncyc loop
wait until rising_edge(CLKS);
end loop; -- i
end procedure waitclk;
begin
-- initialize some top level out signals
SWI <= (others=>'0');
BTN <= (others=>'0');
wait until rising_edge(CLKS);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wait " => -- wait
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": wait ");
write(oline, idelta, right, 5);
writeline(output, oline);
waitclk(idelta);
when "port " => -- switch rs232 port
read_ea(iline, iactport);
ACTPORT <= iactport;
writetimestamp(oline, CLK_CYCLE, ": port ");
write(oline, iactport, right, 5);
writeline(output, oline);
when "cts " => -- setup cts throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
CTS_CYCLE <= i_cycle;
CTS_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "xon " => -- setup xon throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
XON_CYCLE <= i_cycle;
XON_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "swi " => -- new SWI settings
read_ea(iline, iswi);
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": swi ");
write(oline, iswi, right, 10);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
SWI <= iswi;
wait until rising_edge(CLKS);
waitclk(idelta);
when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
read_ea(iline, btn_num);
read_ea(iline, idelta);
if btn_num>=0 and btn_num<=3 then
writetimestamp(oline, CLK_CYCLE, ": btn ");
write(oline, btn_num, right, 5);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
BTN(btn_num) <= '0';
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKS);
waitclk(idelta);
else
write(oline, string'("!! btn: btn number out of range"));
writeline(output, oline);
end if;
when "expect" => -- expect n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": expect");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
if nbyte > 0 then
S2M_ACTIVE <= '1';
S2M_SIZE <= nbyte;
else
S2M_ACTIVE <= '0';
end if;
S2M_ENAESC <= enaesc;
S2M_ENAXON <= enaxon;
wait until rising_edge(CLKS);
when "send " => -- send n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
bcnt := 0;
itxdata := (others=>'0');
wait until falling_edge(CLKS);
while bcnt < nbyte loop
while TXBUSY='1' or RTS_N='1' loop
wait until falling_edge(CLKS);
end loop;
TXDATA <= itxdata;
itxdata := slv(unsigned(itxdata) + 1);
bcnt := bcnt + 1;
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until falling_edge(CLKS);
end loop;
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
wait until falling_edge(CLKS);
end loop;
wait until rising_edge(CLKS);
when "break " => -- send a break for n cycles
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": break ");
write(oline, idelta, right, 5);
writeline(output, oline);
-- send break for n cycles
BREAK <= '1';
waitclk(idelta);
BREAK <= '0';
-- wait for 3 bit cell width
waitclk(3*to_integer(unsigned(CLKDIV)+1));
-- send 'sync' character
wait until falling_edge(CLKS);
TXDATA <= "10000000";
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until rising_edge(CLKS);
when "clkdiv" => -- set new clock divider
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
write(oline, idelta, right, 5);
writeline(output, oline);
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
UART_RESET <= '1';
wait until rising_edge(CLKS);
UART_RESET <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
CLK_STOP_L <= '1';
wait for 500 ns; -- allows dcm's to stop
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
CLK_STOP <= CLK_STOP_L;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
variable active_1 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable irxeff : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable doesc : slbit := '0';
variable bcnt : integer := 0;
variable xseen : slbit := '0';
begin
loop
wait until falling_edge(CLKS);
M2S_XONSEEN <= '0';
M2S_XOFFSEEN <= '0';
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
irxdata := (others=>'0');
bcnt := 0;
end if;
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
if bcnt = S2M_SIZE then
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
else
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
write(oline, bcnt, right, 5);
write(oline, string'(" expect="));
write(oline, S2M_SIZE, right, 5);
end if;
writeline(output, oline);
end if;
active_1 := S2M_ACTIVE;
if RXVAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": char: ");
write(oline, RXDATA, right, 10);
write(oline, string'(" ("));
writeoct(oline, RXDATA, right, 3);
write(oline, string'(") dt="));
write(oline, dclk, right, 4);
irxeff := RXDATA;
irxval := '1';
if doesc = '1' then
irxeff := not RXDATA;
irxval := '1';
doesc := '0';
write(oline, string'(" eff="));
write(oline, irxeff, right, 10);
write(oline, string'(" ("));
writeoct(oline, irxeff, right, 3);
write(oline, string'(")"));
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
doesc := '1';
irxval := '0';
write(oline, string'(" XESC seen"));
end if;
xseen := '0';
if S2M_ENAXON = '1' then
if RXDATA = c_serport_xon then
write(oline, string'(" XON seen"));
M2S_XONSEEN <= '1';
xseen := '1';
elsif RXDATA = c_serport_xoff then
write(oline, string'(" XOFF seen"));
M2S_XOFFSEEN <= '1';
xseen := '1';
end if;
end if;
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
if irxeff = irxdata then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL: expect="));
write(oline, irxdata, right, 10);
end if;
irxdata := slv(unsigned(irxdata) + 1);
bcnt := bcnt + 1;
end if;
writeline(output, oline);
dclk := 0;
end if;
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
writeline(output, oline);
end if;
dclk := dclk + 1;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
92a5e927d20142a8c9b72de66b4309b2
| 0.487089 | 4.122768 | false | false | false | false |
freecores/w11
|
rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd
| 2 | 5,685 |
-- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_1ar_gen - syn
-- Description: Dual-Port RAM with with one synchronous write and two
-- asynchronius read ports (as distributed RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's
-- 2008-03-08 123 1.0.1 use shorter label names
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_1swar_1ar_gen;
architecture syn of ram_1swar_1ar_gen is
begin
assert AWIDTH>=4 and AWIDTH<=5
report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported"
severity failure;
AW_4: if AWIDTH = 4 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB(i),
SPO => DOA(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_4;
-- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge..
AW_5: if AWIDTH = 5 generate
signal WE0 : slbit := '0';
signal WE1 : slbit := '0';
signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0');
begin
WE0 <= WE and not ADDRA(4);
WE1 <= WE and ADDRA(4);
GL: for i in DWIDTH-1 downto 0 generate
MEM0 : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB0(i),
SPO => DOA0(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE0
);
MEM1 : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB1(i),
SPO => DOA1(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE1
);
DOA <= DOA0 when ADDRA(4)='0' else DOA1;
DOB <= DOB0 when ADDRB(4)='0' else DOB1;
end generate GL;
end generate AW_5;
-- AW_6: if AWIDTH = 6 generate
-- GL: for i in DWIDTH-1 downto 0 generate
-- MEM : RAM64X1D
-- generic map (
-- INIT => X"0000000000000000")
-- port map (
-- DPO => DOB(i),
-- SPO => DOA(i),
-- A0 => ADDRA(0),
-- A1 => ADDRA(1),
-- A2 => ADDRA(2),
-- A3 => ADDRA(3),
-- A4 => ADDRA(4),
-- A5 => ADDRA(5),
-- D => DI(i),
-- DPRA0 => ADDRB(0),
-- DPRA1 => ADDRB(1),
-- DPRA2 => ADDRB(2),
-- DPRA3 => ADDRB(3),
-- DPRA4 => ADDRB(4),
-- DPRA5 => ADDRB(5),
-- WCLK => CLK,
-- WE => WE
-- );
-- end generate GL;
-- end generate AW_6;
end syn;
-- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong.
-- The annotation states that DPO is the port A output and SPO is port B
-- output. The text before is correct, DPO is port B and SPO is port A.
|
gpl-2.0
|
2d5cda18286061d32a65e7db302d3c50
| 0.484609 | 3.466463 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_bram.vhd
| 2 | 4,224 |
-- $Id: pdp11_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_bram - syn
-- Description: pdp11: BRAM based ext. memory dummy
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
-- 2008-02-17 117 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
entity pdp11_bram is -- cache
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end pdp11_bram;
architecture syn of pdp11_bram is
type regs_type is record
req_r : slbit; -- read request
req_w : slbit; -- write request
be : slv2; -- byte enables
addr : slv(AWIDTH-1 downto 1); -- address
end record regs_type;
constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
constant regs_init : regs_type := (
'0','0', -- req_r,w
(others=>'0'), -- be
addrzero -- addr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal MEM_ENB : slbit := '0';
signal MEM_WEA : slv2 := "00";
signal MEM_DOA : slv16 := (others=>'0');
begin
MEM_BYT0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(0),
WEB => R_REGS.be(0),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(7 downto 0),
DIB => MEM_DOA(7 downto 0),
DOA => MEM_DOA(7 downto 0),
DOB => open
);
MEM_BYT1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(1),
WEB => R_REGS.be(1),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(15 downto 8),
DIB => MEM_DOA(15 downto 8),
DOA => MEM_DOA(15 downto 8),
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
N_REGS.be <= EM_MREQ.be;
N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
EM_SRES.ack_r <= R_REGS.req_r;
EM_SRES.ack_w <= R_REGS.req_w;
EM_SRES.dout <= MEM_DOA;
end syn;
|
gpl-2.0
|
9c6d55a629b0f45470d100bf6780750b
| 0.537642 | 3.341772 | false | false | false | false |
dumpram/zedboard-ofdm
|
vhdl/reset_controller.vhd
| 1 | 1,181 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity reset_controller is
port (
clk : in std_logic;
input_fsm_wd_reset : in std_logic;
output_fsm_wd_reset : in std_logic;
reset : out std_logic
);
end reset_controller;
architecture rtl of reset_controller is
-- Watchdog signals
signal watchdog_timer : std_logic_vector(7 downto 0) := x"ff";
-- Internal reset
signal reset_int : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
watchdog_timer <= watchdog_timer;
reset_int <= '0';
-- WATCHDOG
-- Timer reset
-- ... if input fifo is changing
-- ... if output fifo is changing
-- FSMs handle control signals
if ( input_fsm_wd_reset = '1' ) or ( output_fsm_wd_reset = '1' ) then
watchdog_timer <= x"ff";
else
watchdog_timer <= watchdog_timer - '1';
end if;
-- Watchdog reset signal
if watchdog_timer = (watchdog_timer'range => '0') then
reset_int <= '1';
else
reset_int <= '0';
end if;
end if;
end process;
reset <= reset_int;
end rtl;
|
mit
|
02410973c6a20fb91a2c3450d186e126
| 0.594412 | 3.364672 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_2clock.vhd
| 1 | 12,222 |
-- $Id: serport_2clock.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_2clock - syn
-- Description: serial port: serial port module, 2 clock domain
--
-- Dependencies: genlib/cdc_pulse
-- serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-11-07 421 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.genlib.all;
use work.memlib.all;
entity serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end serport_2clock;
architecture syn of serport_2clock is
type synu_type is record
rxact_c : slbit; -- rxact (capt from CLKS->CLKU)
rxact_s : slbit; -- rxact (sync in CLKU)
txact_c : slbit; -- txact (capt from CLKS->CLKU)
txact_s : slbit; -- txact (sync in CLKU)
abact_c : slbit; -- abact (capt from CLKS->CLKU)
abact_s : slbit; -- abact (sync in CLKU)
rxok_c : slbit; -- rxok (capt from CLKS->CLKU)
rxok_s : slbit; -- rxok (sync in CLKU)
txok_c : slbit; -- txok (capt from CLKS->CLKU)
txok_s : slbit; -- txok (sync in CLKU)
abclkdiv_c : slv(CDWIDTH-1 downto 0); -- abclkdiv (capt from CLKS->CLKU)
abclkdiv_s : slv(CDWIDTH-1 downto 0); -- abclkdiv (sync in CLKU)
end record synu_type;
constant synu_init : synu_type := (
'0','0', -- rxact_c,_s
'0','0', -- txact_c,_s
'0','0', -- abact_c,_s
'0','0', -- rxok_c,_s
'0','0', -- txok_c,_s
slv(to_unsigned(0,CDWIDTH)), -- abclkdiv_c
slv(to_unsigned(0,CDWIDTH)) -- abclkdiv_s
);
type syns_type is record
enaxon_c : slbit; -- enaxon (capt from CLKU->CLKS)
enaxon_s : slbit; -- enaxon (sync in CLKS)
enaesc_c : slbit; -- enaesc (capt from CLKU->CLKS)
enaesc_s : slbit; -- enaesc (sync in CLKS)
end record syns_type;
constant syns_init : syns_type := (
'0','0', -- enaxon_c,_s
'0','0' -- enaxon_c,_s
);
signal R_SYNU : synu_type := synu_init; -- sync registers (clku)
signal R_SYNS : syns_type := syns_init; -- sync registers (clks)
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal RESET_CLKS : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
signal RXERR_CLKU : slbit := '0';
signal RXOVR_CLKU : slbit := '0';
signal ABDONE_CLKU : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
CDC_RESET : cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => false)
port map (
CLKM => CLKU,
RESET => '0',
CLKS => CLKS,
PIN => RESET,
BUSY => open,
POUT => RESET_CLKS
);
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLKS,
CE_MSEC => CES_MSEC,
RESET => RESET_CLKS,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
RESET_INT <= RESET_CLKS or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKS,
CLKR => CLKU,
RESETW => ABACT, -- clear fifo on abact
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXFIFO_SIZEW,
SIZER => open
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKU,
CLKR => CLKS,
RESETW => RESET,
RESETR => ABACT, -- clear fifo on abact
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
-- receive back preasure
-- on if fifo more than 3/4 full (less than 1/4 free)
-- off if fifo less than 1/2 full (more than 1/2 free)
proc_rxok: process (CLKS)
constant rxsize_rxok_off : slv2 := "01";
constant rxsize_rxok_on : slv2 := "10";
variable rxsize_msb : slv2 := "00";
begin
if rising_edge(CLKS) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
proc_synu: process (CLKU)
begin
if rising_edge(CLKU) then
R_SYNU.rxact_c <= RXACT;
R_SYNU.rxact_s <= R_SYNU.rxact_c;
R_SYNU.txact_c <= UART_TXBUSY;
R_SYNU.txact_s <= R_SYNU.txact_c;
R_SYNU.abact_c <= ABACT;
R_SYNU.abact_s <= R_SYNU.abact_c;
R_SYNU.rxok_c <= RXOK;
R_SYNU.rxok_s <= R_SYNU.rxok_c;
R_SYNU.txok_c <= TXOK;
R_SYNU.txok_s <= R_SYNU.txok_c;
R_SYNU.abclkdiv_c <= ABCLKDIV;
R_SYNU.abclkdiv_s <= R_SYNU.abclkdiv_c;
end if;
end process proc_synu;
proc_syns: process (CLKS)
begin
if rising_edge(CLKS) then
R_SYNS.enaxon_c <= ENAXON;
R_SYNS.enaxon_s <= R_SYNS.enaxon_c;
R_SYNS.enaesc_c <= ENAESC;
R_SYNS.enaesc_s <= R_SYNS.enaesc_c;
end if;
end process proc_syns;
CDC_RXERR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXERR,
BUSY => open,
POUT => RXERR_CLKU
);
CDC_RXOVR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXOVR,
BUSY => open,
POUT => RXOVR_CLKU
);
CDC_ABDONE : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => ABDONE,
BUSY => open,
POUT => ABDONE_CLKU
);
MONI.rxerr <= RXERR_CLKU;
MONI.rxovr <= RXOVR_CLKU;
MONI.rxact <= R_SYNU.rxact_s;
MONI.txact <= R_SYNU.txact_s;
MONI.abact <= R_SYNU.abact_s;
MONI.abdone <= ABDONE_CLKU;
MONI.rxok <= R_SYNU.rxok_s;
MONI.txok <= R_SYNU.txok_s;
proc_abclkdiv: process (R_SYNU.abclkdiv_s)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s;
end process proc_abclkdiv;
end syn;
|
gpl-2.0
|
4c7f68b642cccfa58650e3f2c0b5f48c
| 0.518655 | 3.615976 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/a20c6ed85b6d6fbe/fifo_generator_rx_inst_sim_netlist.vhdl
| 1 | 266,926 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:37:19 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => Q(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 2) => B"00",
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => Q(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 2) => B"00",
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => Q(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 2) => B"00",
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_79\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => Q(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 13) => B"0000000000000000000",
DIADI(12 downto 8) => din(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => din(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_71\,
DOBDO(12 downto 8) => dout(9 downto 5),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_79\,
DOBDO(4 downto 0) => dout(4 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_comb : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gc0.count_d1_reg[10]\,
S(0) => v1_reg(4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0055000000FFC0C0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => wr_rst_busy,
I4 => \out\,
I5 => ram_empty_fb_i_reg(0),
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gc0.count_d1_reg[10]\,
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gc0.count_d1_reg[10]\,
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_reg[10]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gc0.count_reg[10]\,
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
\gc0.count_d1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \gc0.count[10]_i_2_n_0\ : STD_LOGIC;
signal \^gc0.count_d1_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 10 to 10 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0";
begin
Q(10 downto 0) <= \^q\(10 downto 0);
\gc0.count_d1_reg[9]_0\(9 downto 0) <= \^gc0.count_d1_reg[9]_0\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(0),
O => plusOp(0)
);
\gc0.count[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(8),
I1 => \^gc0.count_d1_reg[9]_0\(6),
I2 => \gc0.count[10]_i_2_n_0\,
I3 => \^gc0.count_d1_reg[9]_0\(7),
I4 => \^gc0.count_d1_reg[9]_0\(9),
I5 => rd_pntr_plus1(10),
O => plusOp(10)
);
\gc0.count[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(5),
I1 => \^gc0.count_d1_reg[9]_0\(3),
I2 => \^gc0.count_d1_reg[9]_0\(1),
I3 => \^gc0.count_d1_reg[9]_0\(0),
I4 => \^gc0.count_d1_reg[9]_0\(2),
I5 => \^gc0.count_d1_reg[9]_0\(4),
O => \gc0.count[10]_i_2_n_0\
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(0),
I1 => \^gc0.count_d1_reg[9]_0\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(0),
I1 => \^gc0.count_d1_reg[9]_0\(1),
I2 => \^gc0.count_d1_reg[9]_0\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(1),
I1 => \^gc0.count_d1_reg[9]_0\(0),
I2 => \^gc0.count_d1_reg[9]_0\(2),
I3 => \^gc0.count_d1_reg[9]_0\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(2),
I1 => \^gc0.count_d1_reg[9]_0\(0),
I2 => \^gc0.count_d1_reg[9]_0\(1),
I3 => \^gc0.count_d1_reg[9]_0\(3),
I4 => \^gc0.count_d1_reg[9]_0\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(3),
I1 => \^gc0.count_d1_reg[9]_0\(1),
I2 => \^gc0.count_d1_reg[9]_0\(0),
I3 => \^gc0.count_d1_reg[9]_0\(2),
I4 => \^gc0.count_d1_reg[9]_0\(4),
I5 => \^gc0.count_d1_reg[9]_0\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[10]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[9]_0\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[10]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[9]_0\(6),
I2 => \^gc0.count_d1_reg[9]_0\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(6),
I1 => \gc0.count[10]_i_2_n_0\,
I2 => \^gc0.count_d1_reg[9]_0\(7),
I3 => \^gc0.count_d1_reg[9]_0\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(7),
I1 => \gc0.count[10]_i_2_n_0\,
I2 => \^gc0.count_d1_reg[9]_0\(6),
I3 => \^gc0.count_d1_reg[9]_0\(8),
I4 => \^gc0.count_d1_reg[9]_0\(9),
O => plusOp(9)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(0),
Q => \^q\(0)
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(10),
Q => \^q\(10)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(1),
Q => \^q\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(2),
Q => \^q\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(3),
Q => \^q\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(4),
Q => \^q\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(5),
Q => \^q\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(6),
Q => \^q\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(7),
Q => \^q\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(8),
Q => \^q\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(9),
Q => \^q\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^gc0.count_d1_reg[9]_0\(0)
);
\gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(10),
Q => rd_pntr_plus1(10)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^gc0.count_d1_reg[9]_0\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^gc0.count_d1_reg[9]_0\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^gc0.count_d1_reg[9]_0\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => \^gc0.count_d1_reg[9]_0\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(5),
Q => \^gc0.count_d1_reg[9]_0\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(6),
Q => \^gc0.count_d1_reg[9]_0\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(7),
Q => \^gc0.count_d1_reg[9]_0\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(8),
Q => \^gc0.count_d1_reg[9]_0\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(9),
Q => \^gc0.count_d1_reg[9]_0\(9)
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => \gcc0.gc0.count_d1_reg[10]\(0),
O => ram_full_i_reg
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(10),
I1 => \gcc0.gc0.count_d1_reg[10]\(0),
O => ram_empty_i_reg
);
\gmux.gm[5].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => \gcc0.gc0.count_reg[10]\(0),
O => ram_full_i_reg_0
);
\gmux.gm[5].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => \gcc0.gc0.count_d1_reg[10]\(0),
O => ram_empty_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gcc0.gc0.count[10]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(10 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(10 downto 0);
Q(0) <= \^q\(0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(8),
I1 => p_12_out(6),
I2 => \gcc0.gc0.count[10]_i_2_n_0\,
I3 => p_12_out(7),
I4 => p_12_out(9),
I5 => \^q\(0),
O => \plusOp__0\(10)
);
\gcc0.gc0.count[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[10]_i_2_n_0\
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[10]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[10]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[10]_i_2_n_0\,
I2 => p_12_out(7),
I3 => p_12_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(7),
I1 => \gcc0.gc0.count[10]_i_2_n_0\,
I2 => p_12_out(6),
I3 => p_12_out(8),
I4 => p_12_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gcc0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(10)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(10),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => p_12_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => p_12_out(8)
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => p_12_out(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => ram_empty_i_reg_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(17 downto 0) => din(17 downto 0),
dout(17 downto 0) => dout(17 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(17 downto 0) => din(17 downto 0),
dout(17 downto 0) => dout(17 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(17 downto 0) => din(17 downto 0),
dout(17 downto 0) => dout(17 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_reg[10]\ : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\gc0.count_d1_reg[10]\ => \gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
\gc0.count_reg[10]\ => \gc0.count_reg[10]\,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
\gc0.count_d1[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[10]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_comb : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\gc0.count_d1_reg[10]\ => \gc0.count_d1_reg[10]\,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0),
ram_full_comb => ram_full_comb,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
\gc0.count_d1_reg[10]\ => \gc0.count_d1_reg[10]_0\,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(17 downto 0) => din(17 downto 0),
dout(17 downto 0) => dout(17 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(17 downto 0) => din(35 downto 18),
dout(17 downto 0) => dout(35 downto 18),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(17 downto 0) => din(53 downto 36),
dout(17 downto 0) => dout(53 downto 36),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(9 downto 0) => din(63 downto 54),
dout(9 downto 0) => dout(63 downto 54),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
\gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
ram_full_i_reg_0 : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal rpntr_n_12 : STD_LOGIC;
signal rpntr_n_14 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[10]\ => rpntr_n_14,
\gc0.count_reg[10]\ => rpntr_n_12,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
\gc0.count_d1_reg[9]_0\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gcc0.gc0.count_d1_reg[10]\(0) => \gcc0.gc0.count_d1_reg[10]\(0),
\gcc0.gc0.count_reg[10]\(0) => \gcc0.gc0.count_reg[10]\(0),
ram_empty_i_reg => rpntr_n_12,
ram_empty_i_reg_0 => rpntr_n_14,
ram_full_i_reg => ram_full_i_reg,
ram_full_i_reg_0 => ram_full_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[10]\ : in STD_LOGIC;
\gc0.count_d1_reg[10]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^gcc0.gc0.count_d1_reg[10]\ : STD_LOGIC;
begin
\gcc0.gc0.count_d1_reg[10]\ <= \^gcc0.gc0.count_d1_reg[10]\;
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^gcc0.gc0.count_d1_reg[10]\,
clk => clk,
full => full,
\gc0.count_d1_reg[10]\ => \gc0.count_d1_reg[10]\,
\gc0.count_d1_reg[10]_0\ => \gc0.count_d1_reg[10]_0\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\,
\out\ => \out\,
ram_empty_fb_i_reg(0) => E(0),
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(10 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(10 downto 0),
E(0) => \^gcc0.gc0.count_d1_reg[10]\,
Q(0) => Q(0),
clk => clk,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(10 downto 0) => Q(10 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => \gcc0.gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_25\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 10 to 10 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(10 downto 0) => p_0_out(10 downto 0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[10]\(0) => p_11_out(10),
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_23\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_24\,
\gcc0.gc0.count_reg[10]\(0) => p_12_out(10),
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_full_i_reg => \gntv_or_sync_fifo.gl0.rd_n_3\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.rd_n_25\,
rd_en => rd_en,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(10 downto 0) => p_11_out(10 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(0) => p_12_out(10),
clk => clk,
full => full,
\gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.rd_n_3\,
\gc0.count_d1_reg[10]_0\ => \gntv_or_sync_fifo.gl0.rd_n_25\,
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gcc0.gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_20\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_22\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_23\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_24\,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(10 downto 0) => p_0_out(10 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gcc0.gc0.count_d1_reg[10]\(10 downto 0) => p_11_out(10 downto 0),
\out\(0) => rd_rst_i(0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 10 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 11;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "2kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2046;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2045;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 11;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2048;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 11;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 11;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2048;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 11;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "2kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 2046;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 2045;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 2048;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 11;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 2048;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 11;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(10 downto 0) => NLW_U0_data_count_UNCONNECTED(10 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(10 downto 0) => B"00000000000",
prog_empty_thresh_assert(10 downto 0) => B"00000000000",
prog_empty_thresh_negate(10 downto 0) => B"00000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(10 downto 0) => B"00000000000",
prog_full_thresh_assert(10 downto 0) => B"00000000000",
prog_full_thresh_negate(10 downto 0) => B"00000000000",
rd_clk => '0',
rd_data_count(10 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(10 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(10 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(10 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
5bf7494d0368e717f60e06691ec60e5e
| 0.668968 | 3.218535 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_xonrx.vhd
| 1 | 4,232 |
-- $Id: serport_xonrx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx - syn
-- Description: serial port: xon/xoff logic rx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx;
architecture syn of serport_xonrx is
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
n.rxovr := '0'; -- ensure single clock pulse
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
else
if r.escseen = '1' then
n.escseen := '0';
end if;
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
end syn;
|
gpl-2.0
|
fa061c984cd59a022a7ed73044d312ad
| 0.509216 | 3.98869 | false | false | false | false |
freecores/w11
|
rtl/vlib/comlib/crc8.vhd
| 2 | 2,809 |
-- $Id: crc8.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: crc8 - syn
-- Description: 8bit CRC generator, use 'A6' polynomial of Koopman and
-- Chakravarty. Has HD=3 for up to 247 bits and optimal HD=2
-- error detection for longer messages:
--
-- x^8 + x^6 + x^3 + x^2 + 1 (0xa6)
--
-- It is irreducible, and can be implemented with <= 37 xor's
-- This polynomial is described in
-- http://dx.doi.org/10.1109%2FDSN.2004.1311885
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 8 25 - 13 (A6 polynom)
-- 2011-09-17 409 13.1 O40d xc3s1200e-4 8 18 - 10 (SAE J1850)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 409 1.1 use now 'A6' polynomial of Koopman et al.
-- 2011-08-14 406 1.0.1 remove superfluous variable r
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.comlib.all;
entity crc8 is -- crc-8 generator, checker
generic (
INIT: slv8 := "00000000"); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv8 -- crc code
);
end crc8;
architecture syn of crc8 is
signal R_CRC : slv8 := INIT; -- state registers
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_CRC <= INIT;
else
if ENA = '1' then
R_CRC <= crc8_update(R_CRC, DI);
end if;
end if;
end if;
end process proc_regs;
CRC <= R_CRC;
end syn;
|
gpl-2.0
|
9b9b1e2bcbff3ad26af89aaa2aee5b1c
| 0.542186 | 3.61054 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_sequencer.vhd
| 1 | 90,523 |
-- $Id: pdp11_sequencer.vhd 556 2014-05-29 19:01:39Z mueller $
--
-- Copyright 2006-2014 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sequencer - syn
-- Description: pdp11: CPU sequencer
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2014.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
-- 2010-06-20 307 1.3.1 rename cpacc to cacc in vm_cntl_type
-- 2010-06-13 305 1.3 remove CPDIN_WE, CPDOUT_WE out ports; set
-- CNTL.cpdout_we instead of CPDOUT_WE
-- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait
-- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.2.6 BUGFIX: use is_dstkstack1246, stklim for mode=6
-- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode
-- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling
-- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug
-- 2008-12-13 176 1.2.2 BUGFIX: use is_pci in s_dstw_inc if DSTDEF='1'
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc; prevent stale DSRC
-- 2008-08-22 161 1.2 rename ubf_ -> ibf_; use iblib
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust; cp reset sets now
-- c_cpurust_reset; proper c_cpurust_vfail handling
-- 2008-04-27 140 1.1.8 BUGFIX: halt cpu in case of a vector fetch error
-- use cpursta to encode why cpu halts, remove cpufail
-- 2008-04-27 139 1.1.7 BUGFIX: correct bytop handling for address fetches;
-- BUGFIX: redo mtp flow; add fork_dsta fork and ddst
-- reload in s_opa_mtp_pop_w;
-- 2008-04-19 137 1.1.6 BUGFIX: fix loop state in s_rti_getpc_w
-- 2008-03-30 131 1.1.5 BUGFIX: inc/dec by 2 for byte mode -(sp),(sp)+
-- inc/dec by 2 for @(R)+ and @-(R) also for bytop's
-- 2008-03-02 121 1.1.4 remove snoopers; add waitsusp, redo WAIT handling
-- 2008-02-24 119 1.1.3 add lah,rps,wps command; revamp cp memory access
-- change WAIT logic, now also bails out on cp command
-- 2008-01-20 112 1.1.2 rename PRESET->BRESET
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_sequencer is -- CPU sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
CRESET : out slbit; -- console reset
BRESET : out slbit; -- ibus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
INT_ACK : out slbit; -- interrupt acknowledge
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_sequencer;
architecture syn of pdp11_sequencer is
constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));
constant cpuerr_ibf_illhlt : integer := 7;
constant cpuerr_ibf_adderr : integer := 6;
constant cpuerr_ibf_nxm : integer := 5;
constant cpuerr_ibf_iobto : integer := 4;
constant cpuerr_ibf_ysv : integer := 3;
constant cpuerr_ibf_rsv : integer := 2;
type state_type is (
s_idle,
s_cp_regread,
s_cp_rps,
s_cp_memr_w,
s_cp_memw_w,
s_ifetch,
s_ifetch_w,
s_idecode,
s_srcr_def,
s_srcr_def_w,
s_srcr_inc,
s_srcr_inc_w,
s_srcr_dec,
s_srcr_dec1,
s_srcr_ind,
s_srcr_ind1_w,
s_srcr_ind2,
s_srcr_ind2_w,
s_dstr_def,
s_dstr_def_w,
s_dstr_inc,
s_dstr_inc_w,
s_dstr_dec,
s_dstr_dec1,
s_dstr_ind,
s_dstr_ind1_w,
s_dstr_ind2,
s_dstr_ind2_w,
s_dstw_def,
s_dstw_def_w,
s_dstw_inc,
s_dstw_inc_w,
s_dstw_incdef_w,
s_dstw_dec,
s_dstw_dec1,
s_dstw_ind,
s_dstw_ind_w,
s_dstw_def246,
s_dsta_inc,
s_dsta_incdef_w,
s_dsta_dec,
s_dsta_dec1,
s_dsta_ind,
s_dsta_ind_w,
s_op_halt,
s_op_wait,
s_op_trap,
s_op_reset,
s_op_rts,
s_op_rts_pop,
s_op_rts_pop_w,
s_op_spl,
s_op_mcc,
s_op_br,
s_op_mark,
s_op_mark1,
s_op_mark_pop,
s_op_mark_pop_w,
s_op_sob,
s_op_sob1,
s_opg_gen,
s_opg_gen_rmw_w,
s_opg_mul,
s_opg_mul1,
s_opg_div,
s_opg_div_cn,
s_opg_div_cr,
s_opg_div_sq,
s_opg_div_sr,
s_opg_div_zero,
s_opg_ash,
s_opg_ash_cn,
s_opg_ashc,
s_opg_ashc_cn,
s_opg_ashc_wl,
s_opa_jsr,
s_opa_jsr1,
s_opa_jsr_push,
s_opa_jsr_push_w,
s_opa_jsr2,
s_opa_jmp,
s_opa_mtp,
s_opa_mtp_pop_w,
s_opa_mtp_reg,
s_opa_mtp_mem,
s_opa_mtp_mem_w,
s_opa_mfp_reg,
s_opa_mfp_mem,
s_opa_mfp_mem_w,
s_opa_mfp_dec,
s_opa_mfp_push,
s_opa_mfp_push_w,
s_trap_4,
s_trap_10,
s_trap_disp,
s_int_ext,
s_int_getpc,
s_int_getpc_w,
s_int_getps,
s_int_getps_w,
s_int_getsp,
s_int_decsp,
s_int_pushps,
s_int_pushps_w,
s_int_pushpc,
s_int_pushpc_w,
s_rti_getpc,
s_rti_getpc_w,
s_rti_getps,
s_rti_getps_w,
s_rti_newpc,
s_vmerr,
s_cpufail
);
signal R_STATE : state_type := s_idle; -- state register
signal N_STATE : state_type := s_idle;
signal R_STATUS : cpustat_type := cpustat_init;
signal N_STATUS : cpustat_type := cpustat_init;
signal R_CPUERR : cpuerr_type := cpuerr_init;
signal N_CPUERR : cpuerr_type := cpuerr_init;
signal R_IDSTAT : decode_stat_type := decode_stat_init;
signal N_IDSTAT : decode_stat_type := decode_stat_init;
signal R_VMSTAT : vm_stat_type := vm_stat_init;
signal IBSEL_CPUERR : slbit := '0';
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_cpuerr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_CPUERR
);
proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_CPUERR = '1' then
idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
idout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_status: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATUS <= cpustat_init;
R_CPUERR <= cpuerr_init;
R_IDSTAT <= decode_stat_init;
R_VMSTAT <= vm_stat_init;
else
R_STATUS <= N_STATUS;
R_CPUERR <= N_CPUERR;
R_IDSTAT <= N_IDSTAT;
R_VMSTAT <= VM_STAT;
end if;
end if;
end process proc_status;
proc_state: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATE <= s_idle;
else
R_STATE <= N_STATE;
end if;
end if;
end process proc_state;
proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL,
ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,
R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,
INT_PRI, INT_VECT)
variable nstate : state_type;
variable nstatus : cpustat_type := cpustat_init;
variable ncpuerr : cpuerr_type := cpuerr_init;
variable ncreset : slbit := '0';
variable nbreset : slbit := '0';
variable nintack : slbit := '0';
variable ndpcntl : dpath_cntl_type := dpath_cntl_init;
variable nvmcntl : vm_cntl_type := vm_cntl_init;
variable nidstat : decode_stat_type := decode_stat_init;
variable nmmumoni : mmu_moni_type := mmu_moni_init;
variable imemok : boolean;
variable bytop : slbit := '0'; -- local bytop access flag
variable macc : slbit := '0'; -- local modify access flag
variable lvector : slv9_2 := (others=>'0'); -- local trap/interrupt vector
variable brcode : slv4 := (others=>'0'); -- reduced br opcode (15,10-8)
variable brcond : slbit := '0'; -- br condition value
variable is_kmode : slbit := '0'; -- cmode is kernel mode
variable is_dstkstack1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
variable int_pending : slbit := '0'; -- an interrupt is pending
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
alias DSTDEF : slbit is IREG(3); -- dst register mode defered
alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
procedure do_memread_i(nstate : inout state_type;
ndpcntl : inout dpath_cntl_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type) is
begin
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nvmcntl.dspace := '0';
nvmcntl.req := '1';
ndpcntl.gpr_pcinc := '1'; -- (pc)++
nstate := wstate;
end procedure do_memread_i;
procedure do_memread_d(nstate : inout state_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type;
bytop : in slbit := '0';
macc : in slbit := '0';
is_pci : in slbit := '0') is
begin
nvmcntl.dspace := not is_pci; -- ispace if pc immediate modes
-- bytop := R_IDSTAT.is_bytop and not is_addr;
nvmcntl.bytop := bytop;
nvmcntl.macc := macc;
nvmcntl.req := '1';
nstate := wstate;
end procedure do_memread_d;
procedure do_memread_srcinc(nstate : inout state_type;
ndpcntl : inout dpath_cntl_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type;
nmmumoni : inout mmu_moni_type;
updt_sp : in slbit := '0') is
begin
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
if updt_sp = '1' then
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.gpr_adst := c_gpr_sp; -- update SP too
ndpcntl.gpr_we := '1';
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.req := '1';
nstate := wstate;
end procedure do_memread_srcinc;
procedure do_memwrite(nstate : inout state_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type;
macc : in slbit :='0') is
begin
nvmcntl.dspace := '1';
nvmcntl.bytop := R_IDSTAT.is_bytop;
nvmcntl.wacc := '1';
nvmcntl.macc := macc;
nvmcntl.req := '1';
nstate := wstate;
end procedure do_memwrite;
procedure do_memcheck(nstate : inout state_type;
nstatus : inout cpustat_type;
mok : out boolean) is
begin
nstate := nstate; -- dummy to add driver (vivado)
nstatus := nstatus; -- "
mok := false;
if VM_STAT.ack = '1' then
mok := true;
nstatus.trap_mmu := VM_STAT.trap_mmu;
if R_CPUERR.ysv = '0' then -- ysv trap when cpuerr not yet set
nstatus.trap_ysv := VM_STAT.trap_ysv;
end if;
elsif VM_STAT.err='1' or VM_STAT.fail='1' then
nstate := s_vmerr;
end if;
end procedure do_memcheck;
procedure do_const_opsize(ndpcntl : inout dpath_cntl_type;
bytop : in slbit;
isdef : in slbit;
regnum : in slv3) is
begin
ndpcntl := ndpcntl; -- dummy to add driver (vivado)
if bytop='0' or isdef='1' or
regnum=c_gpr_pc or regnum=c_gpr_sp then
ndpcntl.ounit_const := "000000010";
else
ndpcntl.ounit_const := "000000001";
end if;
end procedure do_const_opsize;
procedure do_fork_dstr(nstate : inout state_type;
idstat : in decode_stat_type) is
begin
case idstat.fork_dstr is
when c_fork_dstr_def => nstate := s_dstr_def;
when c_fork_dstr_inc => nstate := s_dstr_inc;
when c_fork_dstr_dec => nstate := s_dstr_dec;
when c_fork_dstr_ind => nstate := s_dstr_ind;
when others => nstate := s_cpufail;
end case;
end procedure do_fork_dstr;
procedure do_fork_opg(nstate : inout state_type;
idstat : in decode_stat_type) is
begin
case idstat.fork_opg is
when c_fork_opg_gen => nstate := s_opg_gen;
when c_fork_opg_wdef => nstate := s_dstw_def;
when c_fork_opg_winc => nstate := s_dstw_inc;
when c_fork_opg_wdec => nstate := s_dstw_dec;
when c_fork_opg_wind => nstate := s_dstw_ind;
when c_fork_opg_mul => nstate := s_opg_mul;
when c_fork_opg_div => nstate := s_opg_div;
when c_fork_opg_ash => nstate := s_opg_ash;
when c_fork_opg_ashc => nstate := s_opg_ashc;
when others => nstate := s_cpufail;
end case;
end procedure do_fork_opg;
procedure do_fork_opa(nstate : inout state_type;
idstat : in decode_stat_type) is
begin
case idstat.fork_opa is
when c_fork_opa_jmp => nstate := s_opa_jmp;
when c_fork_opa_jsr => nstate := s_opa_jsr;
when c_fork_opa_mtp => nstate := s_opa_mtp_mem;
when c_fork_opa_mfp_reg => nstate := s_opa_mfp_reg;
when c_fork_opa_mfp_mem => nstate := s_opa_mfp_mem;
when others => nstate := s_cpufail;
end case;
end procedure do_fork_opa;
procedure do_fork_next(nstate : inout state_type;
nstatus : inout cpustat_type;
nmmumoni : inout mmu_moni_type) is
begin
nmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
nstate := s_idle;
elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or
R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or
PSW.tflag='1' then
nstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then
nstate := s_ifetch;
else
nstate := s_idle;
end if;
end procedure do_fork_next;
procedure do_fork_next_pref(nstate : inout state_type;
nstatus : inout cpustat_type;
ndpcntl : inout dpath_cntl_type;
nvmcntl : inout vm_cntl_type;
nmmumoni : inout mmu_moni_type) is
begin
ndpcntl := ndpcntl; -- dummy to add driver (vivado)
nvmcntl := nvmcntl; -- "
nmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
nstate := s_idle;
elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or
R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or
PSW.tflag='1' then
nstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then
nvmcntl.req := '1';
ndpcntl.gpr_pcinc := '1';
nmmumoni.istart := '1';
nstate := s_ifetch_w;
else
nstate := s_idle;
end if;
end procedure do_fork_next_pref;
procedure do_start_int(nstate : inout state_type;
ndpcntl : inout dpath_cntl_type;
vector : in slv9_2) is
begin
ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
ndpcntl.dtmp_we := '1';
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := vector & "00"; -- vector
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- DSRC = vector
nstate := s_int_getpc;
end procedure do_start_int;
begin
nstate := R_STATE;
nstatus := R_STATUS;
ncpuerr := R_CPUERR;
nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait
ncreset := '0';
nbreset := '0';
nintack := '0';
nidstat := R_IDSTAT;
if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !
ncpuerr := cpuerr_init;
end if;
int_pending := '0';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
int_pending := '1';
end if;
imemok := false;
nmmumoni := mmu_moni_init;
nmmumoni.pc := PC;
macc := '0';
bytop := '0';
brcode := IREG(15) & IREG(10 downto 8);
brcond := '1';
is_kmode := '0';
is_dstkstack1246 := '0';
if PSW.cmode = c_psw_kmode then
is_kmode := '1';
if DSTREG = c_gpr_sp and
(DSTMODF="001" or DSTMODF="010" or
DSTMODF="100" or DSTMODF="110") then
is_dstkstack1246 := '1';
end if;
end if;
lvector := (others=>'0');
nvmcntl := vm_cntl_init;
nvmcntl.dspace := '1'; -- DEFAULT
nvmcntl.mode := PSW.cmode; -- DEFAULT
nvmcntl.intrsv := R_STATUS.do_intrsv; -- DEFAULT
ndpcntl := dpath_cntl_init;
ndpcntl.gpr_asrc := SRCREG; -- DEFAULT
ndpcntl.gpr_adst := DSTREG; -- DEFAULT
ndpcntl.gpr_mode := PSW.cmode; -- DEFAULT
ndpcntl.gpr_rset := PSW.rset; -- DEFAULT
ndpcntl.gpr_we := '0'; -- DEFAULT
ndpcntl.gpr_bytop := '0'; -- DEFAULT
ndpcntl.gpr_pcinc := '0'; -- DEFAULT
ndpcntl.psr_ccwe := '0'; -- DEFAULT
ndpcntl.psr_we := '0'; -- DEFAULT
ndpcntl.psr_func := "000"; -- DEFAULT
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '0';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '0';
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '0';
ndpcntl.ounit_asel := c_ounit_asel_ddst;
ndpcntl.ounit_azero := '0'; -- DEFAULT
ndpcntl.ounit_const := (others=>'0'); -- DEFAULT
ndpcntl.ounit_bsel := c_ounit_bsel_const;
ndpcntl.ounit_opsub := '0'; -- DEFAULT
ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC
ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC
ndpcntl.aunit_cimod := R_IDSTAT.aunit_cimod; -- STATIC
ndpcntl.aunit_cc1op := R_IDSTAT.aunit_cc1op; -- STATIC
ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC
ndpcntl.aunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.lunit_func := R_IDSTAT.lunit_func; -- STATIC
ndpcntl.lunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.munit_func := R_IDSTAT.munit_func; -- STATIC
ndpcntl.ireg_we := '0';
ndpcntl.cres_sel := R_IDSTAT.res_sel; -- DEFAULT
ndpcntl.dres_sel := c_dpath_res_ounit;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;
if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then
nstatus.cmdbusy := '1';
nstatus.cpfunc := CP_CNTL.func;
nstatus.cprnum := CP_CNTL.rnum;
end if;
if R_STATUS.cmdack = '1' then
nstatus.cmdack := '0';
nstatus.cmderr := '0';
nstatus.cmdmerr := '0';
end if;
case R_STATE is
-- idle and command port states ---------------------------------------------
-- Note: s_idle was entered from suspended WAIT when waitsusp='1'
-- --> all exits must check this and either return to s_op_wait
-- or abort the WAIT and set waitsusp='0'
when s_idle =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST (do mux early)
nstatus.cpustep := '0';
if R_STATUS.cmdbusy = '1' then
case R_STATUS.cpfunc is
when c_cpfunc_noop => -- noop : no operation --------
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_sta => -- sta : cpu start -----------
ncreset := '1';
nstatus.cmdack := '1';
nstatus.cpugo := '1';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_runs;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_sto => -- sto : cpu stop ------------
nstatus.cmdack := '1';
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_stop;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_cont => -- cont : cpu continue --------
nstatus.cmdack := '1';
nstatus.cpugo := '1';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_runs;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_step => -- step : cpu step ------------
nstatus.cmdack := '1';
nstatus.cpustep := '1';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_step;
nstatus.waitsusp := '0';
if int_pending = '1' then
nintack := '1';
nstatus.intvect := INT_VECT;
nstate := s_int_ext;
else
nstate := s_ifetch;
end if;
when c_cpfunc_rst => -- rst : cpu reset (soft) ----
ncreset := '1';
nstatus.cmdack := '1';
nstatus.cpugo := '0';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_reset;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_rreg => -- rreg : read register ------
ndpcntl.gpr_adst := R_STATUS.cprnum;
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_cp_regread;
when c_cpfunc_wreg => -- wreg : write register -----
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.gpr_adst := R_STATUS.cprnum;
ndpcntl.gpr_we := '1';
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rpsw => -- rpsw : read psw -----------
ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
ndpcntl.dtmp_we := '1';
nstate := s_cp_rps;
when c_cpfunc_wpsw => -- wpsw : write psw ----------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
ndpcntl.psr_we := '1'; -- load new PS
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rmem => -- rmem : read memory --------
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memr_w;
when c_cpfunc_wmem => -- wmem : write memory -------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
nvmcntl.wacc := '1'; -- write mem
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memw_w;
when others =>
nstatus.cmdack := '1';
nstatus.cmderr := '1';
nstate := s_idle;
end case;
elsif R_STATUS.waitsusp = '1' then
nstatus.waitsusp := '0';
nstate := s_op_wait;
elsif R_STATUS.cpugo = '1' then
if int_pending = '1' then
nintack := '1';
nstatus.intvect := INT_VECT;
nstate := s_int_ext;
else
nstate := s_ifetch;
end if;
end if;
when s_cp_regread =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_rps =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_memr_w =>
nstate := s_cp_memr_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.trap_ysv := '0'; -- suppress traps on console
nstatus.trap_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
when s_cp_memw_w =>
nstate := s_cp_memw_w;
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.trap_ysv := '0'; -- suppress traps on console
nstatus.trap_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
-- instruction fetch and decode ---------------------------------------------
when s_ifetch =>
nmmumoni.istart := '1'; -- do here; memread_i inc PC !
do_memread_i(nstate, ndpcntl, nvmcntl, s_ifetch_w);
when s_ifetch_w =>
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
when s_idecode =>
nidstat := ID_STAT; -- register decode status
if ID_STAT.force_srcsp = '1' then
ndpcntl.gpr_asrc := c_gpr_sp;
end if;
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nvmcntl.dspace := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
if ID_STAT.do_pref_dec='1' and PSW.tflag='0' and int_pending='0' and
R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1'
then
nvmcntl.req := '1';
ndpcntl.gpr_pcinc := '1'; -- (pc)++
nmmumoni.istart := '1';
nstatus.prefdone := '1';
end if;
if ID_STAT.do_fork_op = '1' then
case ID_STAT.fork_op is
when c_fork_op_halt => nstate := s_op_halt;
when c_fork_op_wait => nstate := s_op_wait;
when c_fork_op_rtti => nstate := s_rti_getpc;
when c_fork_op_trap => nstate := s_op_trap;
when c_fork_op_reset=> nstate := s_op_reset;
when c_fork_op_rts => nstate := s_op_rts;
when c_fork_op_spl => nstate := s_op_spl;
when c_fork_op_mcc => nstate := s_op_mcc;
when c_fork_op_br => nstate := s_op_br;
when c_fork_op_mark => nstate := s_op_mark;
when c_fork_op_sob => nstate := s_op_sob;
when c_fork_op_mtp => nstate := s_opa_mtp;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_srcr = '1' then
case ID_STAT.fork_srcr is
when c_fork_srcr_def => nstate := s_srcr_def;
when c_fork_srcr_inc => nstate := s_srcr_inc;
when c_fork_srcr_dec => nstate := s_srcr_dec;
when c_fork_srcr_ind => nstate := s_srcr_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, ID_STAT);
elsif ID_STAT.do_fork_dsta = '1' then
case ID_STAT.fork_dsta is -- 2nd dsta fork in s_opa_mtp_pop_w
when c_fork_dsta_def => do_fork_opa(nstate, ID_STAT);
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_opg = '1' then
do_fork_opg(nstate, ID_STAT);
elsif ID_STAT.is_res = '1' then
nstate := s_trap_10; -- do trap 10;
else
nstate := s_cpufail; -- catch mistakes here...
end if;
-- source read states -------------------------------------------------------
-- flows:
-- 1 (r) s_srcr_def req (r)
-- s_srcr_def_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 2 (r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 3 @(r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 4 -(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 5 @-(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 6 n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 7 @n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- s_srcr_def req @n(r)
-- s_srcr_def_w get @n(r)
-- -> do_fork_dstr or do_fork_opg
when s_srcr_def =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
do_memread_d(nstate, nvmcntl, s_srcr_def_w,
bytop=>R_IDSTAT.is_bytop,
is_pci=>R_IDSTAT.is_srcpcmode1);
when s_srcr_def_w =>
nstate := s_srcr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_srcr_inc =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w,
bytop=>bytop, is_pci=>R_IDSTAT.is_srcpc);
when s_srcr_inc_w =>
nstate := s_srcr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
when s_srcr_dec =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
nstate := s_srcr_dec1;
when s_srcr_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w, bytop=>bytop);
when s_srcr_ind =>
do_memread_i(nstate, ndpcntl, nvmcntl, s_srcr_ind1_w);
when s_srcr_ind1_w =>
nstate := s_srcr_ind1_w;
if R_IDSTAT.is_srcpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A = DSRC
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout; -- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.ddst_we := '1'; -- update DDST (to reload PC)
nstate := s_srcr_ind2;
end if;
when s_srcr_ind2 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_ind2_w, bytop=>bytop);
when s_srcr_ind2_w =>
nstate := s_srcr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
-- destination read states --------------------------------------------------
-- flows:
-- 1 (r) s_dstr_def req (r) (rmw if rmw op)
-- s_dstr_def_w get (r)
-- -> do_fork_opg
--
-- 2 (r)+ s_dstr_inc req (r); r+=s (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 3 @(r)+ s_dstr_inc req (r); r+=s
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 4 -(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r) (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 5 @-(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r)
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 6 n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r) (rmw if rmw op)
-- s_dstr_ind2_w get n(r)
-- -> do_fork_opg
--
-- 7 @n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r)
-- s_dstr_ind2_w get n(r)
-- s_dstr_def req @n(r) (rmw if rmw op)
-- s_dstr_def_w get @n(r)
-- -> do_fork_opg
when s_dstr_def =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memread_d(nstate, nvmcntl, s_dstr_def_w,
bytop=>R_IDSTAT.is_bytop, macc=>R_IDSTAT.is_rmwop);
when s_dstr_def_w =>
nstate := s_dstr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opg(nstate, R_IDSTAT);
end if;
when s_dstr_inc =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
bytop=>bytop, macc=>macc, is_pci=>R_IDSTAT.is_dstpc);
when s_dstr_inc_w =>
nstate := s_dstr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_dstr_dec =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstr_dec1;
when s_dstr_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
bytop=>bytop, macc=>macc);
when s_dstr_ind =>
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
when s_dstr_ind1_w =>
nstate := s_dstr_ind1_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstr_ind2;
end if;
when s_dstr_ind2 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
bytop=>bytop, macc=>macc);
when s_dstr_ind2_w =>
nstate := s_dstr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
-- destination write states -------------------------------------------------
-- flows:
-- 1 (r) s_dstw_def wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 2 (r)+ s_dstw_inc wreq (r) check kstack
-- s_dstw_inc_w ack (r); r+=s
-- -> do_fork_next
--
-- 3 @(r)+ s_dstw_inc rreq (r); r+=s
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 4 -(r) s_dstw_dec r-=s
-- s_dstw_dec1 wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 5 @-(r) s_dstw_dec r-=s
-- s_dstw_dec1 rreq (r)
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 6 n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 wreq n(r) check kstack
-- s_dstw_def_w ack n(r)
-- -> do_fork_next
--
-- 7 @n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 rreq n(r)
-- s_dstw_incdef_w get n(r)
-- s_dstw_def246 wreq @n(r)
-- s_dstw_def_w ack @n(r)
-- -> do_fork_next
when s_dstw_def =>
ndpcntl.psr_ccwe := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
nvmcntl.kstack := is_dstkstack1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
when s_dstw_def_w =>
nstate := s_dstw_def_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_dstw_inc =>
ndpcntl.psr_ccwe := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for else)
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG); --(...)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
if DSTDEF = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
nvmcntl.kstack := is_dstkstack1246;
do_memwrite(nstate, nvmcntl, s_dstw_inc_w);
nstatus.do_gprwe := '1';
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w,
is_pci=>R_IDSTAT.is_dstpc);
end if;
when s_dstw_inc_w =>
nstate := s_dstw_inc_w;
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
if R_STATUS.do_gprwe = '1' then
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
nmmumoni.trace_prev := '1'; -- ssr freeze of prev state
ndpcntl.gpr_we := '1'; -- update DST reg
end if;
nstatus.do_gprwe := '0';
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_dstw_incdef_w =>
nstate := s_dstw_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_def246;
end if;
when s_dstw_dec =>
ndpcntl.psr_ccwe := '1';
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstw_dec1;
when s_dstw_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if)
if DSTDEF = '0' then
nvmcntl.kstack := is_dstkstack1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
else
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w);
end if;
when s_dstw_ind =>
ndpcntl.psr_ccwe := '1';
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstw_ind_w);
when s_dstw_ind_w =>
nstate := s_dstw_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_dec1;
end if;
when s_dstw_def246 =>
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
-- destination address states -----------------------------------------------
-- flows:
-- 1 (r) -> do_fork_opa
--
-- 2 (r)+ s_dsta_inc r+=2
-- -> do_fork_opa
--
-- 3 @(r)+ s_dsta_inc req (r); r+=s
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 4 -(r) s_dsta_dec r-=s
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 5 @-(r) s_dsta_dec r-=s
-- s_dsta_dec1 req (r)
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 6 n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 7 @n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 req n(r)
-- s_dsta_incdef_w get n(r)
-- -> do_fork_opa
when s_dsta_inc =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then
do_fork_opa(nstate, R_IDSTAT);
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w,
is_pci=>R_IDSTAT.is_dstpc);
end if;
when s_dsta_incdef_w =>
nstate := s_dsta_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opa(nstate, R_IDSTAT);
end if;
when s_dsta_dec =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
nstate := s_dsta_dec1;
when s_dsta_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then -- check here used also by
do_fork_opa(nstate, R_IDSTAT); -- s_dsta_ind flow !!
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w);
end if;
when s_dsta_ind =>
do_memread_i(nstate, ndpcntl, nvmcntl, s_dsta_ind_w);
when s_dsta_ind_w =>
nstate := s_dsta_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dsta_dec1;
end if;
-- instruction operate states -----------------------------------------------
when s_op_halt => -- HALT
if is_kmode = '1' then -- if in kernel mode execute
nmmumoni.idone := '1';
nstatus.cpugo := '0';
nstatus.cpuhalt := '1';
nstatus.cpurust := c_cpurust_halt;
nstate := s_idle;
else -- otherwise trap
ncpuerr.illhlt := '1';
nstate := s_trap_4; -- trap 4 like 11/70
end if;
when s_op_wait => -- WAIT
nstate := s_op_wait; -- spin here
if is_kmode = '0' then -- but act as nop if not in kernel
nstate := s_idle;
elsif int_pending = '1' or -- bail out if pending interrupt
R_STATUS.cpustep='1' then -- or the instruction is only stepped
nstate := s_idle;
elsif R_STATUS.cmdbusy = '1' then -- suspend if a cp command is pending
nstatus.waitsusp := '1';
nstate := s_idle;
else
nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait
end if;
when s_op_trap => -- traps
lvector := "0000" & R_IDSTAT.trap_vec; -- vector
do_start_int(nstate, ndpcntl, lvector);
when s_op_reset => -- RESET
if is_kmode = '1' then -- if in kernel mode execute
nbreset := '1';
end if;
nstate := s_idle;
when s_op_rts => -- RTS
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with reg(dst)
nstate := s_op_rts_pop;
when s_op_rts_pop =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_rts_pop_w,
nmmumoni, updt_sp=>'1');
when s_op_rts_pop_w =>
nstate := s_op_rts_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gpr_adst := DSTREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R with (SP)+
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_op_spl => -- SPL
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wspl;
if is_kmode = '1' then -- active only in kernel mode
ndpcntl.psr_we := '1';
nstate := s_ifetch; -- unconditionally fetch next
-- instruction like a 11/70
-- no interrupt recognition !
else
do_fork_next(nstate, nstatus, nmmumoni); -- in non-kernel, noop
end if;
when s_op_mcc => -- CLx/SEx
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wcc;
ndpcntl.psr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_op_br => -- BR
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg8;-- OUNIT B = IREG8
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
-- note: cc are NZVC
case brcode(3 downto 1) is
when "000" => -- BR
brcond := '1';
when "001" => -- BNE/BEQ: if Z = x
brcond := PSW.cc(2);
when "010" => -- BGE/BLT: if N xor V = x
brcond := PSW.cc(3) xor PSW.cc(1);
when "011" => -- BGT/BLE: if Z or (N xor V) = x
brcond := PSW.cc(2) or (PSW.cc(3) xor PSW.cc(1));
when "100" => -- BPL/BMI: if N = x
brcond := PSW.cc(3);
when "101" => -- BHI/BLOS:if C or Z = x
brcond := PSW.cc(2) or PSW.cc(0);
when "110" => -- BVC/BVS: if V = x
brcond := PSW.cc(1);
when "111" => -- BCC/BCS: if C = x
brcond := PSW.cc(0);
when others => null;
end case;
ndpcntl.gpr_adst := c_gpr_pc;
if brcond = brcode(0) then -- this coding creates redundant code
ndpcntl.gpr_we := '1'; -- but synthesis optimizes this way !
do_fork_next(nstate, nstatus, nmmumoni);
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_op_mark => -- MARK
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
ndpcntl.gpr_adst := c_gpr_r5; -- fetch r5
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_op_mark1;
when s_op_mark1 =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with r5
nstate := s_op_mark_pop;
when s_op_mark_pop =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_mark_pop_w,
nmmumoni, updt_sp=>'1');
when s_op_mark_pop_w =>
nstate := s_op_mark_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gpr_adst := c_gpr_r5;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R5 with (sp)+
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_op_sob => -- SOB (dec)
-- comment fork_next_pref out (blog 2006-10-02) due to synthesis impact
--nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
--ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.dres_sel := R_IDSTAT.res_sel;
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
if DP_STAT.ccout_z = '0' then -- if z=0 branch, if z=1 fall thru
nstate := s_op_sob1;
else
--do_fork_next_pref(nstate, ndpcntl, nvmcntl, nmmumoni);
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_op_sob1 => -- SOB (br)
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_gen =>
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.gpr_bytop := R_IDSTAT.is_bytop;
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
if R_IDSTAT.op_mov = '1' then -- in case of MOV xx,R
ndpcntl.gpr_bytop := '0'; -- no bytop, do sign extend
end if;
ndpcntl.psr_ccwe := '1';
if R_IDSTAT.is_dstw_reg = '1' then
ndpcntl.gpr_we := '1';
end if;
if R_IDSTAT.is_rmwop = '1' then
do_memwrite(nstate, nvmcntl, s_opg_gen_rmw_w, macc=>'1');
else
if R_STATUS.prefdone = '1' then
nstatus.prefdone :='0';
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
else
if R_IDSTAT.is_dstw_pc = '1' then
nstate := s_idle;
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
end if;
end if;
when s_opg_gen_rmw_w =>
nstate := s_opg_gen_rmw_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_opg_mul => -- MUL (oper)
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.gpr_adst := SRCREG; -- write high order result
ndpcntl.gpr_we := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- capture high order part
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.dtmp_we := '1'; -- capture low order part
nstate := s_opg_mul1;
when s_opg_mul1 => -- MUL (write odd reg)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_div => -- DIV (load dd_low)
ndpcntl.munit_s_div := '1';
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
nstate := s_opg_div_cn;
when s_opg_div_cn => -- DIV (1st...16th cycle)
ndpcntl.munit_s_div_cn := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
nstate := s_opg_div_cn;
if DP_STAT.div_zero='1' or DP_STAT.div_ovfl='1' then
nstate := s_opg_div_zero;
else
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
end if;
if DP_STAT.shc_tc = '1' then
nstate := s_opg_div_cr;
end if;
when s_opg_div_cr => -- DIV (reminder correction)
ndpcntl.munit_s_div_cr := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
nstate := s_opg_div_sq;
when s_opg_div_sq => -- DIV (store quotient)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.gpr_we := '1';
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
nstate := s_opg_div_sr;
when s_opg_div_sr => -- DIV (store reminder)
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_div_zero => -- DIV (/0 or 0/ abort)
ndpcntl.psr_ccwe := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_ash => -- ASH (load shc)
ndpcntl.munit_s_ash := '1';
nstate := s_opg_ash_cn;
when s_opg_ash_cn => -- ASH (shift cycles)
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.munit_s_ash_cn := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nstate := s_opg_ash_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_opg_ashc => -- ASHC (load low, load shc)
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
ndpcntl.munit_s_ashc := '1';
nstate := s_opg_ashc_cn;
when s_opg_ashc_cn => -- ASHC (shift cycles)
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.munit_s_ashc_cn := '1';
nstate := s_opg_ashc_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
nstate := s_opg_ashc_wl;
end if;
when s_opg_ashc_wl => -- ASHC (write low)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
-- dsta mode operations -----------------------------------------------------
when s_opa_jsr =>
ndpcntl.gpr_asrc := c_gpr_sp; -- (for else)
ndpcntl.dsrc_sel := c_dpath_dsrc_src; -- DSRC = regfile (for else)
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_trap_10; -- trap 10 like 11/70
else
ndpcntl.dsrc_we := '1';
nstate := s_opa_jsr1;
end if;
when s_opa_jsr1 =>
ndpcntl.gpr_asrc := SRCREG;
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
ndpcntl.dtmp_we := '1';
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
ndpcntl.dsrc_we := '1'; -- update DDST
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_jsr_push;
when s_opa_jsr_push =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_jsr_push_w;
when s_opa_jsr_push_w =>
nstate := s_opa_jsr_push_w;
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R with PC
nstate := s_opa_jsr2;
end if;
when s_opa_jsr2 =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with dsta
do_fork_next(nstate, nstatus, nmmumoni);
when s_opa_jmp =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_trap_10; -- trap 10 like 11/70
else
ndpcntl.gpr_we := '1'; -- load PC with dsta
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_opa_mtp =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_opa_mtp_pop_w,
nmmumoni, updt_sp=>'1');
when s_opa_mtp_pop_w =>
nstate := s_opa_mtp_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dtmp_we := '1'; -- load DTMP
if R_IDSTAT.is_dstmode0 = '1' then -- handle register access
nstate := s_opa_mtp_reg;
else
case R_IDSTAT.fork_dsta is -- 2nd dsta fork in s_idecode
when c_fork_dsta_def => nstate := s_opa_mtp_mem;
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
end if;
end if;
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
ndpcntl.ddst_we := '1'; -- update DDST (needed for sp)
when s_opa_mtp_reg =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.gpr_mode := PSW.pmode; -- load reg in pmode
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opa_mtp_mem =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst;-- VA = DDST
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
nvmcntl.mode := PSW.pmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mtp_mem_w;
when s_opa_mtp_mem_w =>
nstate := s_opa_mtp_mem_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_opa_mfp_reg =>
ndpcntl.gpr_mode := PSW.pmode; -- fetch reg in pmode
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = reg(dst)
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
when s_opa_mfp_mem =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if PSW.cmode=c_psw_umode and -- if cm=pm=user then
PSW.cmode=c_psw_umode then -- MFPI works like it
nvmcntl.dspace := '1'; -- were MFPD
else
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
end if;
nvmcntl.mode := PSW.pmode;
nvmcntl.req := '1';
nstate := s_opa_mfp_mem_w;
when s_opa_mfp_mem_w =>
nstate := s_opa_mfp_mem_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
end if;
when s_opa_mfp_dec =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_mfp_push;
when s_opa_mfp_push =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mfp_push_w;
when s_opa_mfp_push_w =>
nstate := s_opa_mfp_push_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
-- trap and interrupt handling states ---------------------------------------
when s_trap_4 =>
lvector := "0000001"; -- vector (4)
do_start_int(nstate, ndpcntl, lvector);
when s_trap_10 =>
lvector := "0000010"; -- vector (10)
do_start_int(nstate, ndpcntl, lvector);
when s_trap_disp =>
if R_STATUS.trap_mmu = '1' then
nvmcntl.trap_done := '1'; -- mmu trap taken: set ssr0 trap bit
lvector := "0101010"; -- mmu trap: vector (250)
elsif R_STATUS.trap_ysv = '1' then
lvector := "0000001"; -- ysv trap: vector (4)
ncpuerr.ysv := '1';
else
lvector := "0000011"; -- trace trap: vector (14)
end if;
nstatus.trap_mmu := '0'; -- clear pending trap flags
nstatus.trap_ysv := '0'; --
do_start_int(nstate, ndpcntl, lvector);
when s_int_ext =>
lvector := R_STATUS.intvect; -- external vector
do_start_int(nstate, ndpcntl, lvector);
when s_int_getpc =>
nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_int_getpc_w, nmmumoni);
when s_int_getpc_w =>
nstate := s_int_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_int_getps;
end if;
when s_int_getps =>
nvmcntl.mode := c_psw_kmode; -- fetch PS from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_int_getps_w, nmmumoni);
when s_int_getps_w =>
nstate := s_int_getps_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.psr_func := c_psr_func_wint; -- interupt mode write
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.psr_we := '1'; -- store new PS
nstate := s_int_getsp;
end if;
when s_int_getsp =>
ndpcntl.gpr_asrc := c_gpr_sp;
ndpcntl.dsrc_we := '1'; -- DSRC = SP (in new mode)
nstate := s_int_decsp;
when s_int_decsp =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP too
nstate := s_int_pushps;
when s_int_pushps =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP (old PS)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_int_pushps_w;
when s_int_pushps_w =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.gpr_adst := c_gpr_sp;
nstate := s_int_pushps_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_we := '1'; -- update SP too
nstate := s_int_pushpc;
end if;
when s_int_pushpc =>
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_int_pushpc_w;
when s_int_pushpc_w =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
nstate := s_int_pushpc_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
nstatus.do_intrsv := '0'; -- signal end of rsv
ndpcntl.gpr_we := '1'; -- load new PC
do_fork_next(nstate, nstatus, nmmumoni); -- ???
end if;
-- return from trap or interrupt handling states ----------------------------
when s_rti_getpc =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getpc_w,
nmmumoni, updt_sp=>'1');
when s_rti_getpc_w =>
nstate := s_rti_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_rti_getps;
end if;
when s_rti_getps =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getps_w,
nmmumoni, updt_sp=>'1');
when s_rti_getps_w =>
nstate := s_rti_getps_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if is_kmode = '1' then -- if in kernel mode
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
else
ndpcntl.psr_func := c_psr_func_wrti; -- otherwise filter
end if;
if imemok then
ndpcntl.psr_we := '1'; -- load new PS
nstate := s_rti_newpc;
end if;
when s_rti_newpc =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load new PC
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
nstate := s_ifetch; -- force fetch
else -- otherwise RTI
do_fork_next(nstate, nstatus, nmmumoni);
end if;
-- exception abort states ---------------------------------------------------
when s_vmerr =>
nstate := s_cpufail;
-- setup for R_VMSTAT.err_rsv='1'
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gpr_adst := c_gpr_sp;
nstatus.trap_mmu :='0'; -- drop pending mmu trap
if R_VMSTAT.fail = '1' then -- vmbox failure
nstatus.cpugo := '0'; -- halt cpu
nstatus.cpurust := c_cpurust_vfail;
nstate := s_idle;
elsif R_STATUS.do_intrsv = '1' then -- double error
nstatus.cpugo := '0'; -- give up, HALT cpu
nstatus.cpurust := c_cpurust_recrsv;
nstate := s_idle;
elsif R_VMSTAT.err = '1' then -- normal vm errors
if R_VMSTAT.err_rsv = '1' then
nstatus.do_intrsv := '1'; -- signal start of rsv
ndpcntl.gpr_we := '1';
if R_VMSTAT.err_odd='1' or R_VMSTAT.err_mmu='1' then
ncpuerr.adderr := '1';
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
end if;
ncpuerr.rsv := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_odd = '1' then
ncpuerr.adderr := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_mmu = '1' then
lvector := "0101010"; -- vector (250)
do_start_int(nstate, ndpcntl, lvector);
end if;
end if;
when s_cpufail =>
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_sfail;
nstate := s_idle;
when others =>
nstate := s_cpufail; --!!! catch undefined states !!!
end case;
if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test
-- nstatus here !!
nstatus.cmdbusy := '0';
ndpcntl.cpdout_we := '1';
end if;
N_STATE <= nstate;
N_STATUS <= nstatus;
N_CPUERR <= ncpuerr;
N_IDSTAT <= nidstat;
CRESET <= ncreset;
BRESET <= nbreset;
INT_ACK <= nintack;
DP_CNTL <= ndpcntl;
VM_CNTL <= nvmcntl;
nmmumoni.regnum := ndpcntl.gpr_adst;
nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
MMU_MONI <= nmmumoni;
end process proc_next;
proc_cpstat : process (R_STATUS)
begin
CP_STAT <= cp_stat_init;
CP_STAT.cmdbusy <= R_STATUS.cmdbusy;
CP_STAT.cmdack <= R_STATUS.cmdack;
CP_STAT.cmderr <= R_STATUS.cmderr;
CP_STAT.cmdmerr <= R_STATUS.cmdmerr;
CP_STAT.cpugo <= R_STATUS.cpugo;
CP_STAT.cpustep <= R_STATUS.cpustep;
CP_STAT.cpuhalt <= R_STATUS.cpuhalt;
CP_STAT.cpuwait <= R_STATUS.cpuwait;
CP_STAT.cpurust <= R_STATUS.cpurust;
end process proc_cpstat;
end syn;
|
gpl-2.0
|
2ad3b2860ce369c4e6e7f053b2b344c8
| 0.489655 | 3.563477 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd
| 2 | 4,677 |
-- $Id: sys_tst_snhumanio_s3.vhd 419 2011-11-01 19:42:30Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_s3 - syn
-- Description: snhumanio tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- s3board/s3_sram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-18 410 13.1 O40d xc3s1000-4 149 211 - 143 t 11.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-10-15 416 1.0.1 remove O_CLKSYS top level port
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_s3 is -- top level
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end sys_tst_snhumanio_s3;
architecture syn of sys_tst_snhumanio_s3 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
|
gpl-2.0
|
09b447bdd6cca35e8c29864814286f50
| 0.495189 | 3.492905 | false | false | false | false |
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