repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
GOOD-Stuff/srio_test
|
srio_test.cache/ip/9df6841f69d5483f/fifo_generator_rx_inst_sim_netlist.vhdl
| 1 | 340,907 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:48:21 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => Q(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 2) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(1 downto 0) => B"00",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => din(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 4),
DOBDO(3 downto 0) => dout(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 6) => B"00000000000000000000000000",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_comb : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0055000000FFC0C0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => wr_rst_busy,
I4 => \out\,
I5 => E(0),
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg_0(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gcc0.gc0.count_d1_reg[10]\,
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
D(11 downto 0) <= \^d\(11 downto 0);
\gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(3),
O => \gc0.count[0]_i_2_n_0\
);
\gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(2),
O => \gc0.count[0]_i_3_n_0\
);
\gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(1),
O => \gc0.count[0]_i_4_n_0\
);
\gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^d\(0),
O => \gc0.count[0]_i_5_n_0\
);
\gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(7),
O => \gc0.count[4]_i_2_n_0\
);
\gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(6),
O => \gc0.count[4]_i_3_n_0\
);
\gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(5),
O => \gc0.count[4]_i_4_n_0\
);
\gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(4),
O => \gc0.count[4]_i_5_n_0\
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(11),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(10),
O => \gc0.count[8]_i_3_n_0\
);
\gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(9),
O => \gc0.count[8]_i_4_n_0\
);
\gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(8),
O => \gc0.count[8]_i_5_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(0),
Q => Q(0)
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(10),
Q => Q(10)
);
\gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(11),
Q => Q(11)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(1),
Q => Q(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(2),
Q => Q(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(3),
Q => Q(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(4),
Q => Q(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(5),
Q => Q(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(6),
Q => Q(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(7),
Q => Q(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(8),
Q => Q(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(9),
Q => Q(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
D => \gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^d\(0)
);
\gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gc0.count_reg[0]_i_1_n_4\,
O(2) => \gc0.count_reg[0]_i_1_n_5\,
O(1) => \gc0.count_reg[0]_i_1_n_6\,
O(0) => \gc0.count_reg[0]_i_1_n_7\,
S(3) => \gc0.count[0]_i_2_n_0\,
S(2) => \gc0.count[0]_i_3_n_0\,
S(1) => \gc0.count[0]_i_4_n_0\,
S(0) => \gc0.count[0]_i_5_n_0\
);
\gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_5\,
Q => \^d\(10)
);
\gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_4\,
Q => \^d\(11)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_6\,
Q => \^d\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_5\,
Q => \^d\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_4\,
Q => \^d\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_7\,
Q => \^d\(4)
);
\gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[4]_i_1_n_4\,
O(2) => \gc0.count_reg[4]_i_1_n_5\,
O(1) => \gc0.count_reg[4]_i_1_n_6\,
O(0) => \gc0.count_reg[4]_i_1_n_7\,
S(3) => \gc0.count[4]_i_2_n_0\,
S(2) => \gc0.count[4]_i_3_n_0\,
S(1) => \gc0.count[4]_i_4_n_0\,
S(0) => \gc0.count[4]_i_5_n_0\
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_6\,
Q => \^d\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_5\,
Q => \^d\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_4\,
Q => \^d\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_7\,
Q => \^d\(8)
);
\gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[8]_i_1_n_4\,
O(2) => \gc0.count_reg[8]_i_1_n_5\,
O(1) => \gc0.count_reg[8]_i_1_n_6\,
O(0) => \gc0.count_reg[8]_i_1_n_7\,
S(3) => \gc0.count[8]_i_2_n_0\,
S(2) => \gc0.count[8]_i_3_n_0\,
S(1) => \gc0.count[8]_i_4_n_0\,
S(0) => \gc0.count[8]_i_5_n_0\
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_6\,
Q => \^d\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gcc0.gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\gcc0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(3),
O => \gcc0.gc0.count[0]_i_2_n_0\
);
\gcc0.gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(2),
O => \gcc0.gc0.count[0]_i_3_n_0\
);
\gcc0.gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(1),
O => \gcc0.gc0.count[0]_i_4_n_0\
);
\gcc0.gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(7),
O => \gcc0.gc0.count[4]_i_2_n_0\
);
\gcc0.gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(6),
O => \gcc0.gc0.count[4]_i_3_n_0\
);
\gcc0.gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(5),
O => \gcc0.gc0.count[4]_i_4_n_0\
);
\gcc0.gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(4),
O => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(11),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(10),
O => \gcc0.gc0.count[8]_i_3_n_0\
);
\gcc0.gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(9),
O => \gcc0.gc0.count[8]_i_4_n_0\
);
\gcc0.gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(8),
O => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(10),
Q => \^q\(10)
);
\gcc0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(11),
Q => \^q\(11)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(5),
Q => \^q\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(6),
Q => \^q\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(7),
Q => \^q\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(8),
Q => \^q\(8)
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(9),
Q => \^q\(9)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gcc0.gc0.count_reg[0]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[0]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[0]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[0]_i_1_n_7\,
S(3) => \gcc0.gc0.count[0]_i_2_n_0\,
S(2) => \gcc0.gc0.count[0]_i_3_n_0\,
S(1) => \gcc0.gc0.count[0]_i_4_n_0\,
S(0) => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_5\,
Q => p_12_out(10)
);
\gcc0.gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_4\,
Q => p_12_out(11)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_6\,
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_5\,
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_4\,
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_7\,
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[4]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[4]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[4]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[4]_i_1_n_7\,
S(3) => \gcc0.gc0.count[4]_i_2_n_0\,
S(2) => \gcc0.gc0.count[4]_i_3_n_0\,
S(1) => \gcc0.gc0.count[4]_i_4_n_0\,
S(0) => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_6\,
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_5\,
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_4\,
Q => p_12_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_7\,
Q => p_12_out(8)
);
\gcc0.gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gcc0.gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[8]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[8]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[8]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[8]_i_1_n_7\,
S(3) => \gcc0.gc0.count[8]_i_2_n_0\,
S(2) => \gcc0.gc0.count[8]_i_3_n_0\,
S(1) => \gcc0.gc0.count[8]_i_4_n_0\,
S(0) => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_6\,
Q => p_12_out(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => D(0),
I2 => \^q\(1),
I3 => D(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => D(2),
I2 => \^q\(3),
I3 => D(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => D(4),
I2 => \^q\(5),
I3 => D(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => D(6),
I2 => \^q\(7),
I3 => D(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => D(8),
I2 => \^q\(9),
I3 => D(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => ram_empty_i_reg_3
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_0(5)
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => D(10),
I2 => \^q\(11),
I3 => D(11),
O => v1_reg(5)
);
\gmux.gm[5].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => p_12_out(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_1(5)
);
\gmux.gm[5].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => ram_empty_i_reg_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
\gc0.count_d1_reg[11]\ : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
v1_reg(5 downto 0) => v1_reg(5 downto 0)
);
\gc0.count_d1[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => \gc0.count_d1_reg[11]\
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[0]\(1) <= rd_rst_reg(2);
\gc0.count_reg[0]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_comb : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => \gcc0.gc0.count_d1_reg[11]\
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
E(0) => E(0),
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_comb => ram_full_comb,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
v1_reg_0(5 downto 0) => v1_reg_0(5 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(12 downto 4),
dout(8 downto 0) => dout(12 downto 4),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(21 downto 13),
dout(8 downto 0) => dout(21 downto 13),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(30 downto 22),
dout(8 downto 0) => dout(30 downto 22),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[4].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(39 downto 31),
dout(8 downto 0) => dout(39 downto 31),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[5].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(48 downto 40),
dout(8 downto 0) => dout(48 downto 40),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[6].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(57 downto 49),
dout(8 downto 0) => dout(57 downto 49),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[7].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(63 downto 58),
dout(5 downto 0) => dout(63 downto 58),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
clk => clk,
empty => empty,
\gc0.count_d1_reg[11]\ => \^e\(0),
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
ram_empty_fb_i_reg => \^e\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gcc0.gc0.count_d1_reg[11]\ : STD_LOGIC;
begin
\gcc0.gc0.count_d1_reg[11]\ <= \^gcc0.gc0.count_d1_reg[11]\;
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => E(0),
clk => clk,
full => full,
\gcc0.gc0.count_d1_reg[11]\ => \^gcc0.gc0.count_d1_reg[11]\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\,
\out\ => \out\,
v1_reg(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_0(5 downto 0) => \c1/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
ram_empty_i_reg_4 => ram_empty_i_reg_4,
ram_full_fb_i_reg => \^gcc0.gc0.count_d1_reg[11]\,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
v1_reg_0(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_1(5 downto 0) => \c1/v1_reg\(5 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_25\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_26\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_0_out(11 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.wr_n_26\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_23\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_24\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_25\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => rd_rst_i(2),
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\gcc0.gc0.count_d1_reg[11]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => wr_rst_i(1),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_22\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_23\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_24\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_25\,
ram_empty_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_26\,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\out\(0) => rd_rst_i(0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[0]\(1) => rd_rst_i(2),
\gc0.count_reg[0]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(11) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(11 downto 0) => NLW_U0_data_count_UNCONNECTED(11 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(11 downto 0) => B"000000000000",
prog_empty_thresh_assert(11 downto 0) => B"000000000000",
prog_empty_thresh_negate(11 downto 0) => B"000000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(11 downto 0) => B"000000000000",
prog_full_thresh_assert(11 downto 0) => B"000000000000",
prog_full_thresh_negate(11 downto 0) => B"000000000000",
rd_clk => '0',
rd_data_count(11 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(11 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(11 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(11 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
4cc5a9b7bce1c07701b5ffdf1ce072f6
| 0.68526 | 3.451279 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/decryption_mem/simulation/bmg_stim_gen.vhd
| 1 | 12,760 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((15 <= 15),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((15 <= 15),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(14 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(14 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ_REG(2-1);
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32768 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32768,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
gpl-3.0
|
b0da101d26a2aa607ed377eb69079370
| 0.523981 | 3.549374 | false | false | false | false |
freecores/w11
|
rtl/vlib/serport/serport_1clock.vhd
| 1 | 7,759 |
-- $Id: serport_1clock.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_1clock - syn
-- Description: serial port: serial port module, 1 clock domain
--
-- Dependencies: serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_1c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-23 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.memlib.all;
entity serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end serport_1clock;
architecture syn of serport_1clock is
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
RESET_INT <= RESET or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXFIFO_SIZE
);
TXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => open
);
-- receive back preasure
-- on if fifo more than 3/4 full
-- off if fifo less than 1/2 full
proc_rxok: process (CLK)
constant rxsize_rxok_off : slv3 := "011";
constant rxsize_rxok_on : slv3 := "010";
variable rxsize_msb : slv3 := "000";
begin
if rising_edge(CLK) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2);
if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
MONI.rxerr <= RXERR;
MONI.rxovr <= RXOVR;
MONI.rxact <= RXACT;
MONI.txact <= UART_TXBUSY;
MONI.abact <= ABACT;
MONI.abdone <= ABDONE;
MONI.rxok <= RXOK;
MONI.txok <= TXOK;
proc_abclkdiv: process (ABCLKDIV)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV;
end process proc_abclkdiv;
end syn;
|
gpl-2.0
|
fdbbb940871b27cb1ebb7dd2ce413e82
| 0.542853 | 3.783033 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/core/nn_constants_pkg.vhd
| 1 | 11,772 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : nn_constants_pkg.vhd
-- PROJECT : FPGA_NEURAL-Network
-- PACKAGE : NN_CONSTANTS_pkg
--=============================================================================
-- AUTORS(s) : Barbosa, F
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 10, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.NN_TYPES_pkg.all;
--=============================================================================
-- Package declaration for NN_TYPES_pkg
--=============================================================================
package NN_CONSTANTS_pkg is
constant A_SAMPLE_INPUT : ARRAY_OF_SFIXED := (
(to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE))
);
constant INPUT_LAYER_WEIGHTS_INSTANCE : INPUT_LAYER_WEIGHTS := (
(to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE))
);
constant HIDDEN_LAYER_WEIGHTS_INSTANCE : HIDDEN_LAYER_WEIGHTS := (
-- (to_sfixed(22.5922,U_SIZE,L_SIZE), to_sfixed(43.5699,U_SIZE,L_SIZE), to_sfixed(43.0207,U_SIZE,L_SIZE), to_sfixed(97.9748,U_SIZE,L_SIZE), to_sfixed(25.8065,U_SIZE,L_SIZE), to_sfixed(26.2212,U_SIZE,L_SIZE), to_sfixed(22.1747,U_SIZE,L_SIZE), to_sfixed(31.8778,U_SIZE,L_SIZE), to_sfixed(8.5516,U_SIZE,L_SIZE), to_sfixed(2.9220,U_SIZE,L_SIZE), to_sfixed(48.8609,U_SIZE,L_SIZE), to_sfixed(45.8849,U_SIZE,L_SIZE), to_sfixed(52.1136,U_SIZE,L_SIZE), to_sfixed(9.8712,U_SIZE,L_SIZE)),
-- (to_sfixed(17.0708,U_SIZE,L_SIZE), to_sfixed(31.1102,U_SIZE,L_SIZE), to_sfixed(18.4816,U_SIZE,L_SIZE), to_sfixed(43.8870,U_SIZE,L_SIZE), to_sfixed(40.8720,U_SIZE,L_SIZE), to_sfixed(60.2843,U_SIZE,L_SIZE), to_sfixed(11.7418,U_SIZE,L_SIZE), to_sfixed(42.4167,U_SIZE,L_SIZE), to_sfixed(26.2482,U_SIZE,L_SIZE), to_sfixed(92.8854,U_SIZE,L_SIZE), to_sfixed(57.8525,U_SIZE,L_SIZE), to_sfixed(96.3089,U_SIZE,L_SIZE), to_sfixed(23.1594,U_SIZE,L_SIZE), to_sfixed(26.1871,U_SIZE,L_SIZE)),
-- (to_sfixed(22.7664,U_SIZE,L_SIZE), to_sfixed(92.3380,U_SIZE,L_SIZE), to_sfixed(90.4881,U_SIZE,L_SIZE), to_sfixed(11.1119,U_SIZE,L_SIZE), to_sfixed(59.4896,U_SIZE,L_SIZE), to_sfixed(71.1216,U_SIZE,L_SIZE), to_sfixed(29.6676,U_SIZE,L_SIZE), to_sfixed(50.7858,U_SIZE,L_SIZE), to_sfixed(80.1015,U_SIZE,L_SIZE), to_sfixed(73.0331,U_SIZE,L_SIZE), to_sfixed(23.7284,U_SIZE,L_SIZE), to_sfixed(54.6806,U_SIZE,L_SIZE), to_sfixed(48.8898,U_SIZE,L_SIZE), to_sfixed(33.5357,U_SIZE,L_SIZE))
(to_sfixed(1.5122,U_SIZE,L_SIZE), to_sfixed(0.6097,U_SIZE,L_SIZE), to_sfixed(0.9763,U_SIZE,L_SIZE), to_sfixed(-0.8762,U_SIZE,L_SIZE), to_sfixed(0.1932,U_SIZE,L_SIZE), to_sfixed(0.0908,U_SIZE,L_SIZE), to_sfixed(0.4391,U_SIZE,L_SIZE), to_sfixed(-0.0864,U_SIZE,L_SIZE), to_sfixed(-0.5696,U_SIZE,L_SIZE), to_sfixed(0.5749,U_SIZE,L_SIZE), to_sfixed(-0.4827,U_SIZE,L_SIZE), to_sfixed(0.6270,U_SIZE,L_SIZE), to_sfixed(1.7584,U_SIZE,L_SIZE), to_sfixed(0.5553,U_SIZE,L_SIZE)),
(to_sfixed(1.0114,U_SIZE,L_SIZE), to_sfixed(0.9375,U_SIZE,L_SIZE), to_sfixed(0.3523,U_SIZE,L_SIZE), to_sfixed(0.4041,U_SIZE,L_SIZE), to_sfixed(1.5389,U_SIZE,L_SIZE), to_sfixed(-0.9106,U_SIZE,L_SIZE), to_sfixed(-2.2535,U_SIZE,L_SIZE), to_sfixed(-0.0119,U_SIZE,L_SIZE), to_sfixed(-0.7724,U_SIZE,L_SIZE), to_sfixed(2.9647,U_SIZE,L_SIZE), to_sfixed(-1.4867,U_SIZE,L_SIZE), to_sfixed(-2.3596,U_SIZE,L_SIZE), to_sfixed(0.8667,U_SIZE,L_SIZE), to_sfixed(-1.2566,U_SIZE,L_SIZE)),
(to_sfixed(-0.7440,U_SIZE,L_SIZE), to_sfixed(-0.2641,U_SIZE,L_SIZE), to_sfixed(-1.0074,U_SIZE,L_SIZE), to_sfixed(0.7037,U_SIZE,L_SIZE), to_sfixed(-0.0806,U_SIZE,L_SIZE), to_sfixed(0.1825,U_SIZE,L_SIZE), to_sfixed(-0.3537,U_SIZE,L_SIZE), to_sfixed(0.8026,U_SIZE,L_SIZE), to_sfixed(-0.4890,U_SIZE,L_SIZE), to_sfixed(0.2165,U_SIZE,L_SIZE), to_sfixed(0.1458,U_SIZE,L_SIZE), to_sfixed(-0.8806,U_SIZE,L_SIZE), to_sfixed(-1.3739,U_SIZE,L_SIZE), to_sfixed(0.5034,U_SIZE,L_SIZE))
);
constant OUTPUT_LAYER_WEIGHTS_INSTANCE : OUTPUT_LAYER_WEIGHTS := (
-- (to_sfixed(62.4060,U_SIZE,L_SIZE), to_sfixed(36.7437,U_SIZE,L_SIZE), to_sfixed(88.5168,U_SIZE,L_SIZE), to_sfixed(67.9728,U_SIZE,L_SIZE)),
-- (to_sfixed(67.9136,U_SIZE,L_SIZE), to_sfixed(98.7982,U_SIZE,L_SIZE), to_sfixed(91.3287,U_SIZE,L_SIZE), to_sfixed(13.6553,U_SIZE,L_SIZE)),
-- (to_sfixed(39.5515,U_SIZE,L_SIZE), to_sfixed(3.7739,U_SIZE,L_SIZE), to_sfixed(79.6184,U_SIZE,L_SIZE), to_sfixed(72.1227,U_SIZE,L_SIZE))
(to_sfixed(1.9494,U_SIZE,L_SIZE), to_sfixed(-2.3810,U_SIZE,L_SIZE), to_sfixed(-1.1301,U_SIZE,L_SIZE), to_sfixed(0.0489,U_SIZE,L_SIZE)),
(to_sfixed(-2.9926,U_SIZE,L_SIZE), to_sfixed(-2.1257,U_SIZE,L_SIZE), to_sfixed(1.5242,U_SIZE,L_SIZE), to_sfixed(-0.1979,U_SIZE,L_SIZE)),
(to_sfixed(-0.8011,U_SIZE,L_SIZE), to_sfixed(4.6621,U_SIZE,L_SIZE), to_sfixed(1.2713,U_SIZE,L_SIZE), to_sfixed(-0.2438,U_SIZE,L_SIZE))
);
constant FIXED_WEIGHTS_MATRIX_INSTANCE: FIXED_WEIGHTS_MATRIX
:= (
INPUT_LAYER => INPUT_LAYER_WEIGHTS_INSTANCE,
HIDDEN_LAYER => HIDDEN_LAYER_WEIGHTS_INSTANCE,
OUTPUT_LAYER => OUTPUT_LAYER_WEIGHTS_INSTANCE
);
end;
--=============================================================================
-- package body declaration
--=============================================================================
package body NN_CONSTANTS_pkg is
end package body;
|
gpl-3.0
|
544ebef70a7e58042f56307500b94525
| 0.634811 | 2.312316 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_mem70.vhd
| 2 | 6,381 |
-- $Id: pdp11_mem70.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mem70 - syn
-- Description: pdp11: 11/70 memory system registers
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mem70;
architecture syn of pdp11_mem70 is
constant ibaddr_loaddr : slv16 := slv(to_unsigned(8#177740#,16));
constant ibaddr_hiaddr : slv16 := slv(to_unsigned(8#177742#,16));
constant ibaddr_syserr : slv16 := slv(to_unsigned(8#177744#,16));
constant ibaddr_cntl : slv16 := slv(to_unsigned(8#177746#,16));
constant ibaddr_maint : slv16 := slv(to_unsigned(8#177750#,16));
constant ibaddr_hm : slv16 := slv(to_unsigned(8#177752#,16));
constant ibaddr_losize : slv16 := slv(to_unsigned(8#177760#,16));
constant ibaddr_hisize : slv16 := slv(to_unsigned(8#177762#,16));
subtype cntl_ibf_frep is integer range 5 downto 4;
subtype cntl_ibf_fmiss is integer range 3 downto 2;
constant cntl_ibf_disutrap : integer := 1;
constant cntl_ibf_distrap : integer := 0;
type regs_type is record -- state registers
ibsel_cr : slbit; -- ibus select cntl
ibsel_hm : slbit; -- ibus select hitmiss
ibsel_ls : slbit; -- ibus select losize
ibsel_nn : slbit; -- ibus select others
hm_data : slv6; -- hit/miss: data
cr_frep : slv2; -- cntl: force replacement bits
cr_fmiss : slv2; -- cntl: force miss bits
cr_disutrap: slbit; -- cntl: disable unibus trap
cr_distrap: slbit; -- cntl: disable traps
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- ibsel_*
(others=>'0'), -- hm_data
"00","00", -- cr_freq,_fmiss
'0','0' -- dis(u)trap
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel_cr := '0';
n.ibsel_hm := '0';
n.ibsel_ls := '0';
n.ibsel_nn := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
n.ibsel_cr := '1';
end if;
if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
n.ibsel_hm := '1';
end if;
if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
n.ibsel_ls := '1';
end if;
if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
IB_MREQ.addr=ibaddr_maint(12 downto 1) or
IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
n.ibsel_nn := '1';
end if;
end if;
-- ibus transactions
if r.ibsel_cr = '1' then
idout(cntl_ibf_frep) := r.cr_frep;
idout(cntl_ibf_fmiss) := r.cr_fmiss;
idout(cntl_ibf_disutrap) := r.cr_disutrap;
idout(cntl_ibf_distrap) := r.cr_distrap;
end if;
if r.ibsel_hm = '1' then
idout(r.hm_data'range) := r.hm_data;
end if;
if r.ibsel_ls = '1' then
idout := slv(to_unsigned(sys_conf_mem_losize,16));
end if;
if r.ibsel_cr='1' and ibw0='1' then
n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
end if;
if HM_ENA = '1' then
n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
r.ibsel_ls or r.ibsel_nn) and ibreq;
IB_SRES.busy <= '0';
end process proc_next;
CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
end syn;
|
gpl-2.0
|
7381701e7f112fcac8ab6deb52a47a04
| 0.551011 | 3.326903 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/tst_serlooplib.vhd
| 1 | 4,996 |
-- $Id: tst_serlooplib.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: tst_serlooplib
-- Description: Definitions for tst_serloop records and helpers
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-10-14 416 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.serportlib.all;
package tst_serlooplib is
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
end record hio_cntl_type;
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi
);
type hio_stat_type is record -- humanio status
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
end record hio_stat_type;
constant hio_stat_init : hio_stat_type := (
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0') -- txokcnt
);
-- -------------------------------------
component tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end component;
component tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
end package tst_serlooplib;
|
gpl-2.0
|
e852fe6e3de317aa9f39da668e489787
| 0.513211 | 4.409532 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/pezhman_mem/example_design/pezhman_mem_exdes.vhd
| 1 | 4,501 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pezhman_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY pezhman_mem_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END pezhman_mem_exdes;
ARCHITECTURE xilinx OF pezhman_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT pezhman_mem IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : pezhman_mem
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
8c5b10e1b77a98f7fc437cde9def63dd
| 0.556765 | 4.61641 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/decryption_mem/simulation/decryption_mem_synth.vhd
| 1 | 9,339 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: decryption_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY decryption_mem_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE decryption_mem_synth_ARCH OF decryption_mem_synth IS
COMPONENT decryption_mem_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
RSTB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
RSTB => RSTB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: decryption_mem_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
RSTB => RSTB,
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
gpl-3.0
|
0c5706bafa1400a609ea638754c5bd6c
| 0.548346 | 3.611369 | false | false | false | false |
freecores/w11
|
rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd
| 1 | 23,191 |
-- $Id: fx2_3fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_3fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 driver (3 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-15 453 13.3 O76x xc3s1200e-4 157 265 96 243 s 7.7/7.4
-- 2012-01-15 453 13.3 O76x xc3s1200e-4 156 259 96 238 s 7.9/7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-04 469 1.1 BUGFIX: redo rx logic, now properly pipelined
-- 2012-01-09 453 1.0 Initial version (derived from 2fifo_ic)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_3fifoctl_ic;
architecture syn of fx2_3fifoctl_ic is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_tx2fifo: slv2 := c_fifo_ep8;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe wait
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp, -- s_txdisp: write, dispatch
s_tx2prep0, -- s_tx2prep0: switch to tx2-fifo
s_tx2prep1, -- s_tx2prep1: fifo addr setup
s_tx2prep2, -- s_tx2prep2: wait for flags
s_tx2disp -- s_tx2disp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend 1 time out counter
pe2tocnt : slv(PETOWIDTH-1 downto 0); -- pktend 2 time out counter
pepend : slbit; -- pktend 1 pending
pe2pend : slbit; -- pktend 2 pending
rxpipe1 : slbit; -- read pipe 1: iob capture stage
rxpipe2 : slbit; -- read pipe 2: fifo write stage
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep8_sel : slbit; -- ep8 (tx2) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
moni_ep8_pf : slbit; -- ep8 (tx2) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
petocnt_init, -- pe2tocnt
'0','0', -- pepend,pe2pend
'0','0', -- rxpipe1, rxpipe2
ccnt_init, -- ccnt
'0','0','0', -- moni_ep(4|6|8)_sel
'0','0','0' -- moni_ep(4|6|8)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal FX2_DATA_DO : slv8 := (others=>'0');
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2FIFO_DO : slv8 := (others=>'0');
signal TX2FIFO_VAL : slbit := '0';
signal TX2FIFO_HOLD : slbit := '0';
signal TX2SIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2SIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
signal TX2BUSY_L : slbit := '0';
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1 and
TX2AFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL|TX2AFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => FX2_DATA_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
TX2FIFO : fifo_2c_dram -- output 2 fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TX2DATA,
ENA => TX2ENA,
BUSY => TX2BUSY_L,
DO => TX2FIFO_DO,
VAL => TX2FIFO_VAL,
HOLD => TX2FIFO_HOLD,
SIZEW => TX2SIZE_USR,
SIZER => TX2SIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS,
FX2_FLAG_N, TXFIFO_VAL, TX2FIFO_VAL,
TXFIFO_DO, TX2FIFO_DO,
RXSIZE_FX2, RXFIFO_BUSY, TXBUSY_L, TX2BUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable itx2fifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable idata_do : slv8 := (others=>'0');
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable sltx2ok : slbit := '0';
variable pipeok : slbit := '0';
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
itx2fifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
idata_do := TXFIFO_DO;
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
sltx2ok := FX2_FLAG_N(c_flag_tx2_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
n.rxpipe1 := '0';
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and RXFIFO_BUSY='0' then
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
elsif sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')then
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
end if;
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_txprep0; -- otherwise switch to tx flow
end if;
-- if chunk done and tx2 or pe2 pending and possible
elsif cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_tx2prep0;
end if;
-- if more rx to do and possible
elsif slrxok='1' and unsigned(RXSIZE_FX2)>3 then -- !thres must be >3!
islrd := '1';
cc_cnt := '1';
n.rxpipe1 := '1';
if pipeok='1' then
n.state := s_rxdisp; -- 1 cycle read
--n.state := s_rxprep2; -- 2 cycle read
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_idle; -- to idle
end if;
end if;
when s_rxpipe => -- s_rxpipe: read, pipe wait
isloe := '1';
n.state := s_rxprep2;
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and tx2 or pe2 pending and possible
if cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
n.state := s_tx2prep0;
-- if chunk done and rx pending and possible
elsif cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_do := TXFIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when s_tx2prep0 => -- s_tx2prep0: switch to tx2-fifo
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
when s_tx2prep1 => -- s_tx2prep1: fifo addr setup
cc_clr := '1';
n.state := s_tx2prep2;
when s_tx2prep2 => -- s_tx2prep2: wait for flags
n.state := s_tx2disp;
when s_tx2disp => -- s_tx2disp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if chunk done and tx or pe pending and possible
elsif cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')
then
n.state := s_txprep0;
-- if pktend 2 to do and possible
elsif sltx2ok = '1' and r.pe2pend = '1' then
ipktend := '1';
n.pe2pend := '0';
n.state := s_idle;
-- if more tx2 to do and possible
elsif sltx2ok = '1' and TX2FIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pe2pend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itx2fifo_hold := '0';
idata_do := TX2FIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_tx2disp; -- stream
else
n.state := s_tx2prep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
-- rx pipe handling
idata_cei := r.rxpipe1;
n.rxpipe2 := r.rxpipe1;
irxfifo_ena := r.rxpipe2;
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
if TX2FIFO_VAL = '1' then
n.pe2tocnt := (others=>'1');
else
if unsigned(r.pe2tocnt) /= 0 then
n.pe2tocnt := slv(unsigned(r.pe2tocnt) - 1);
if unsigned(r.pe2tocnt) = 1 then
n.pe2pend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
n.moni_ep8_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_tx2disp then
n.moni_ep8_sel := '1';
n.moni_ep8_pf := not FX2_FLAG_N(c_flag_prog);
end if;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
FX2_DATA_DO <= idata_do;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
TX2FIFO_HOLD <= itx2fifo_hold;
end process proc_next;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.fifo_ep8 <= R_REGS.moni_ep8_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.flag_ep8_full <= not FX2_FLAG_N(c_flag_tx2_ff);
R_MONI_C.flag_ep8_almost <= R_REGS.moni_ep8_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
R_MONI_S <= R_MONI_C;
end if;
end if;
end process proc_moni;
proc_almost: process (RXSIZE_USR, TXSIZE_USR, TX2SIZE_USR)
begin
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
if unsigned(TX2SIZE_USR) <= TX2AFULL_THRES then
TX2AFULL <= '1';
else
TX2AFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
TX2BUSY <= TX2BUSY_L;
MONI <= R_MONI_S;
end syn;
|
gpl-2.0
|
a6a15baad3d4ddf00d0b65fb6b126134
| 0.496011 | 3.32726 | false | false | false | false |
freecores/w11
|
rtl/vlib/simlib/simclk.vhd
| 1 | 2,376 |
-- $Id: simclk.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simclk - sim
-- Description: Clock generator for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-10 72 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit -- clock stop trigger
);
end entity simclk;
architecture sim of simclk is
begin
proc_clk: process
constant clock_halfperiod : time := PERIOD/2;
begin
CLK <= '0';
wait for OFFSET;
clk_loop: loop
CLK <= '1';
wait for clock_halfperiod;
CLK <= '0';
wait for PERIOD-clock_halfperiod;
exit clk_loop when CLK_STOP = '1';
end loop;
CLK <= '1'; -- final clock cycle for clk_sim
wait for clock_halfperiod;
CLK <= '0';
wait for PERIOD-clock_halfperiod;
wait; -- endless wait, simulator will stop
end process proc_clk;
end sim;
|
gpl-2.0
|
4d72a76dd407d466f473f9cd38267b0b
| 0.577441 | 3.914333 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/sigmoid/sigmoid_rom_pkg.vhd
| 1 | 2,266 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : sigmoid_rom_pkg.vhd
-- PROJECT : FPGA_NEURAL-Network
-- PACKAGE : SIGMOID_ROM_pkg
--=============================================================================
-- AUTORS(s) : Agostini, N
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 14, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.NN_TYPES_pkg.all;
--=============================================================================
-- Package declaration for SIGMOID_ROM_pkg
--=============================================================================
package SIGMOID_ROM_pkg is
constant VECTOR_SIZE : natural := 1024;
constant NUMBER_OF_BITS: natural :=10;
subtype INPUT_SFIXED is sfixed(1 downto L_SIZE);
type INPUT_ARRAY is array (natural range <>) of INPUT_SFIXED;
subtype TAN_SIG_VECTOR is INPUT_ARRAY(0 to (VECTOR_SIZE-1));
end;
--=============================================================================
-- package body declaration
--=============================================================================
package body SIGMOID_ROM_pkg is
end package body;
|
gpl-3.0
|
1f838a13525d788f173377a1bf67d266
| 0.473522 | 4.926087 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/iob_reg_i_gen.vhd
| 2 | 2,066 |
-- $Id: iob_reg_i_gen.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i_gen - syn
-- Description: Registered IOB, input only, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i_gen is -- registered IOB, input, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slv(DWIDTH-1 downto 0); -- input data
PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_i_gen;
architecture syn of iob_reg_i_gen is
signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INIT);
attribute iob : string;
attribute iob of R_DI : signal is "true";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
R_DI <= PAD;
end if;
end if;
end process proc_regs;
DI <= R_DI;
end syn;
|
gpl-2.0
|
36431aac4700dfd4ef17782c9cbcf0a2
| 0.576476 | 3.618214 | false | false | false | false |
superboy0712/MIPS
|
uart/baudGen.vhd
| 3 | 1,898 |
-----------------------------------------------------------------------------------------
-- baud rate generator for uart
--
-- this module has been changed to receive the baud rate dividing counter from registers.
-- the two registers should be calculated as follows:
-- first register:
-- baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
-- second register:
-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
--
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity baudGen is
port ( clr : in std_logic; -- global reset input
clk : in std_logic; -- global clock input
-- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
baudFreq : in std_logic_vector(11 downto 0); -- baud rate setting registers - see header description
-- baudLimit = clkFreq / gcd(clkFreq, 16 * baudRate) - baudFreq
baudLimit : in std_logic_vector(15 downto 0); -- baud rate setting registers - see header description
ce16 : out std_logic); -- baud rate multiplyed by 16
end baudGen;
architecture Behavioral of baudGen is
signal counter : std_logic_vector(15 downto 0);
begin
-- baud divider counter
-- clock divider output
process (clr, clk)
begin
if (clr = '1') then
counter <= (others => '0');
ce16 <= '0';
elsif (rising_edge(clk)) then
if (counter >= baudLimit) then
counter <= counter - baudLimit;
ce16 <= '1';
else
counter <= counter + baudFreq;
ce16 <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
29d64fdfdd694d621bb33d06de1c96f5
| 0.51844 | 4.403712 | false | false | false | false |
unhold/hdl
|
vhdl/vether/vether_tb.vhd
| 1 | 2,370 |
library std;
use std.textio.all;
library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
library work;
use work.tb_pack.all;
use work.vether.all;
entity vether_tb is
port (
tx_po,
tx_no : out std_ulogic;
led_no : out std_ulogic_vector(7 downto 0));
end;
architecture tb of vether_tb is
procedure write(filename : string; data : data_t) is
file f : text is out filename;
variable l : line;
begin
for i in data'range loop
write(l, to_hstring(data(i)));
writeline(f, l);
end loop;
end;
constant clk_freq : natural := 20_460e3;
signal clk : std_ulogic := '0';
signal stb, run, tx_p, tx_n, run_pulse : std_ulogic;
constant ref_frame : mac_t := (
x"00", x"10", x"A4", x"7B", x"EA", x"80", -- dst
x"00", x"12", x"34", x"56", x"78", x"90", -- src
x"08", x"00", -- ethertype
x"45", x"00", x"00", x"2E", x"B3", x"FE", x"00",
x"00", x"80", x"11", x"05", x"40", x"C0", x"A8", x"00", x"2C",
x"C0", x"A8", x"00", x"04", x"04", x"00", x"04", x"00", x"00",
x"1A", x"2D", x"E8", x"00", x"01", x"02", x"03", x"04", x"05",
x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E",
x"0F", x"10", x"11", -- data
x"B3", x"31", x"88", x"1B"); -- fcs
constant gen_frame : mac_t := to_mac(x"0010A47BEA80", x"001234567890", (
x"45", x"00", x"00", x"2E", x"B3", x"FE", x"00",
x"00", x"80", x"11", x"05", x"40", x"C0", x"A8", x"00", x"2C",
x"C0", x"A8", x"00", x"04", x"04", x"00", x"04", x"00", x"00",
x"1A", x"2D", x"E8", x"00", x"01", x"02", x"03", x"04", x"05",
x"06", x"07", x"08", x"09", x"0A", x"0B", x"0C", x"0D", x"0E",
x"0F", x"10", x"11"));
begin
process
begin
write("ref_frame.dat", ref_frame);
write("gen_frame.dat", gen_frame);
assert ref_frame = gen_frame report "frame mismatch";
wait;
end process;
clk_gen(clk, true, clk_freq);
stb_gen : entity work.stb_gen
generic map (
period_g => clk_freq) -- 1 sec
port map (
clk_i => clk,
stb_o => stb);
vether_tx : entity work.vether_tx
generic map (
clk_freq_g => clk_freq)
port map (
clk_i => clk,
stb_i => stb,
tx_po => tx_p,
tx_no => tx_n,
run_o => run);
run_pulse_gen : entity work.pulse_gen
generic map (
duration_g => clk_freq/10) -- 100 ms
port map (
clk_i => clk,
stb_i => run,
pulse_o => run_pulse);
led_no <= not ("00000" & tx_p & tx_n & run_pulse);
tx_po <= tx_p;
tx_no <= tx_n;
end;
|
gpl-3.0
|
c94fe4cb4d78a9da5dcbb7ac18f31b34
| 0.553165 | 2.106667 | false | false | false | false |
superboy0712/MIPS
|
HostComm.vhd
| 1 | 4,426 |
-- Part of TDT4255 Computer Design laboratory exercises
-- Group for Computer Architecture and Design
-- Department of Computer and Information Science
-- Norwegian University of Science and Technology
-- HostComm.vhd
-- A module which wraps some registers, address mapping logic and
-- a UART-to-register control interface to control TDT4255 exercises.
-- This particular variant is to be used for exercises 1 and 2, and
-- contains the following registers:
-- * Magic word (for identification) at address 0x4000. Always returns 0xCAFEC0DE.
-- * Processor enable register (1-bit) at address 0x0000
-- * Processor reset register (1-bit) at address 0x0001
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity HostComm is
port (
clk, reset : in std_logic;
-- interface towards the UART ports
UART_Rx : in std_logic;
UART_Tx : out std_logic;
-- interface towards the processor
proc_en, proc_rst : out std_logic;
-- interface towards the instruction memory
imem_data_in : in std_logic_vector(7 downto 0);
imem_data_out : out std_logic_vector(7 downto 0);
imem_addr : out std_logic_vector(9 downto 0);
imem_wr_en : out std_logic;
-- interface towards the data memory
dmem_data_in : in std_logic_vector(7 downto 0);
dmem_data_out : out std_logic_vector(7 downto 0);
dmem_addr : out std_logic_vector(9 downto 0);
dmem_wr_en : out std_logic
);
end HostComm;
architecture Behavioral of HostComm is
constant TDT4255_EX1_MAGIC : std_logic_vector(31 downto 0) := x"CAFEC0DE";
-- addresses for status/control registers
constant REG_ADDR_PROC_EN : std_logic_vector(15 downto 0) := x"0000";
constant REG_ADDR_PROC_RESET : std_logic_vector(15 downto 0) := x"0001";
-- addresses for the magic ID register
constant REG_ADDR_MAGIC0 : std_logic_vector(15 downto 0) := x"4000";
constant REG_ADDR_MAGIC1 : std_logic_vector(15 downto 0) := x"4001";
constant REG_ADDR_MAGIC2 : std_logic_vector(15 downto 0) := x"4002";
constant REG_ADDR_MAGIC3 : std_logic_vector(15 downto 0) := x"4003";
-- UART register control interface signals
signal regReadData, regWriteData : std_logic_vector(7 downto 0);
signal regAddress : std_logic_vector(15 downto 0);
signal regReadEnable, regWriteEnable : std_logic;
-- control/status registers
signal procResetSignal, procEnableSignal : std_logic;
begin
-- instantiate the UART register controller
UARTHandlerInst: entity work.uart2BusTop
-- 16 bits address width (for register addressing over UART)
generic map (AW => 16)
port map (
clr => reset, clk => clk, serIn => UART_Rx, serOut => UART_Tx,
intAccessGnt => '1', intRdData => regReadData, intWrData => regWriteData,
intAddress => regAddress, intWrite => regWriteEnable, intRead => regReadEnable
);
-- register read mux
regReadData <= dmem_data_in when regAddress(15 downto 14) = "10" else
imem_data_in when regAddress(15 downto 14) = "11" else
"0000000" & procEnableSignal when regAddress = REG_ADDR_PROC_EN else
"0000000" & procResetSignal when regAddress = REG_ADDR_PROC_RESET else
TDT4255_EX1_MAGIC(31 downto 24) when regAddress = REG_ADDR_MAGIC0 else
TDT4255_EX1_MAGIC(23 downto 16) when regAddress = REG_ADDR_MAGIC1 else
TDT4255_EX1_MAGIC(15 downto 8) when regAddress = REG_ADDR_MAGIC2 else
TDT4255_EX1_MAGIC(7 downto 0) when regAddress = REG_ADDR_MAGIC3 else
x"00";
-- instruction memory connections
imem_wr_en <= regWriteEnable and (regAddress(15) and regAddress(14)) and (not procEnableSignal);
imem_addr <= regAddress(9 downto 0);
imem_data_out <= regWriteData;
-- data memory connections
dmem_wr_en <= regWriteEnable and (regAddress(15) and (not regAddress(14))) and (not procEnableSignal);
dmem_addr <= regAddress(9 downto 0);
dmem_data_out <= regWriteData;
ControlRegs: process(clk, reset)
begin
if reset = '1' then
procResetSignal <= '0';
procEnableSignal <= '0';
elsif rising_edge(clk) then
-- implement the enable signal ctrl register
if regWriteEnable = '1' and regAddress = REG_ADDR_PROC_EN then
procEnableSignal <= regWriteData(0);
end if;
-- implement the reset signal ctrl register
if regWriteEnable = '1' and regAddress = REG_ADDR_PROC_RESET then
procResetSignal <= regWriteData(0);
end if;
end if;
end process;
proc_rst <= procResetSignal;
proc_en <= procEnableSignal;
end Behavioral;
|
mit
|
a32f7b5a3ad04f629087eaf000326d14
| 0.713737 | 3.42835 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd
| 1 | 9,653 |
-- $Id: sys_tst_rlink_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n3 - syn
-- Description: rlink tester design for nexys3
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc6slx16-2 752 1258 48 439 t 7.9
-- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-18 440 1.1.1 use [rt]xok for DSP_DP
-- 2011-12-11 438 1.1 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n3;
architecture syn of sys_tst_rlink_n3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-2.0
|
f763863ad6e3fa8f659b3246d17accb5
| 0.500052 | 3.19002 | false | false | false | false |
unhold/hdl
|
vhdl/example/function_pipeline_tb.08.vhd
| 1 | 1,472 |
entity function_pipeline_tb is
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture tb of function_pipeline_tb is
subtype my_datai_t is unsigned(3 downto 0);
subtype my_datao_t is unsigned(4 downto 0);
function fun(my_datai : my_datai_t) return my_datao_t is
begin
return resize(my_datai * 2 - 2, 5);
end function;
constant max_stages_c : natural := 3;
signal clk : bit;
signal datai : my_datai_t := (others => '0');
type my_datao_vec_t is array(natural range <>) of my_datao_t;
signal datao_op, datao_ip : my_datao_vec_t(0 to max_stages_c);
--psl default clock is rising_edge(clk);
begin
clk <= not clk after 1 ns;
process(clk)
begin
if rising_edge(clk) then
datai <= datai + 1;
end if;
end process;
gen_dut : for i in 0 to max_stages_c generate
dut_op : entity work.function_pipeline(output_pipeline)
generic map (
datai_t => my_datai_t,
datao_t => my_datao_t,
fun => fun,
stages_c => i)
port map (
clk_i => clk,
datai_i => datai,
datao_o => datao_op(i));
--psl assert next[i] (always datao_op(i) = fun(prev(datai, i)));
dut_ip : entity work.function_pipeline(input_pipeline)
generic map (
datai_t => my_datai_t,
datao_t => my_datao_t,
fun => fun,
stages_c => i)
port map (
clk_i => clk,
datai_i => datai,
datao_o => datao_ip(i));
--psl assert next[i] (always datao_ip(i) = fun(prev(datai, i)));
end generate;
end;
|
gpl-3.0
|
22b21fc8052a097ae2c5b7ffb4e311a6
| 0.630435 | 2.736059 | false | false | false | false |
unhold/hdl
|
vhdl/fifo.vhd
| 1 | 3,703 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rtl_pack.all;
entity fifo is
generic (
depth_order_g : positive;
data_width_g : positive;
prefill_g : natural := 0);
port (
a_reset_i : in std_ulogic := '0';
a_clock_i : in std_ulogic;
a_full_o : out std_ulogic;
a_write_i : in std_ulogic := '1';
a_data_i : in std_ulogic_vector(data_width_g-1 downto 0);
b_reset_i : in std_ulogic := '0';
b_clock_i : in std_ulogic;
b_read_i : in std_ulogic := '1';
b_empty_o : out std_ulogic;
b_prefill_reached_o : out std_ulogic;
b_data_o : out std_ulogic_vector(data_width_g-1 downto 0));
constant check_prefill : boolean := check(prefill_g < 2**depth_order_g);
end;
library ieee;
use ieee.numeric_std.all;
library work;
use work.greycode_pack.all;
architecture rtl of fifo is
constant sync_stages_c : positive := 2;
-- Compensate for sync and pipeline delay.
-- This assumes that fifo will be written continuously, once writing started.
constant b_prefill_c : natural := maximum(prefill_g - sync_stages_c - 1, 1);
subtype address_t is greycode_t(depth_order_g-1 downto 0);
signal a_write_address, b_read_address : address_t := (others => '0');
signal b_prefill_reached : std_ulogic := '0';
signal b_write_address, a_read_address : address_t;
signal a_full, b_empty : std_ulogic;
signal b_next_read_address : address_t;
signal b_next_prefill_reached : std_ulogic;
signal async_fill : integer range 0 to 2**depth_order_g-1;
begin
dual_port_ram : entity work.dual_port_ram
generic map (
address_width_g => depth_order_g,
data_width_g => data_width_g)
port map (
a_clock_i => a_clock_i,
a_address_i => a_write_address,
a_write_i => a_write_i,
a_data_i => a_data_i,
b_clock_i => b_clock_i,
b_address_i => b_next_read_address,
b_read_i => '1',
b_data_o => b_data_o);
a_full <= to_stdulogic(a_write_address + 1 = a_read_address);
a_full_o <= a_full;
a_write : process(a_reset_i, a_clock_i)
begin
if a_reset_i = '1' then
a_write_address <= (others => '0');
elsif rising_edge(a_clock_i) then
assert (a_write_i and a_full) = '0' report "fifo: write full fifo";
if (a_write_i and not a_full) = '1' then
a_write_address <= a_write_address + 1;
end if;
end if;
end process;
sync_write_address_a_b : entity work.sync
generic map (
width_g => depth_order_g,
stages_g => sync_stages_c,
reset_value_g => '0')
port map (
reset_i => b_reset_i,
clock_i => b_clock_i,
data_i => a_write_address,
data_o => b_write_address);
b_empty <= to_stdulogic(b_read_address = b_write_address) or not b_prefill_reached;
b_next_read_address <= b_read_address + 1 when (b_read_i and not b_empty) = '1' else b_read_address;
b_next_prefill_reached <= b_prefill_reached or to_stdulogic(to_integer(unsigned(to_binary(b_write_address))) >= b_prefill_c);
-- Cannot only use equal, because values may be lost in the sync.
b_empty_o <= b_empty;
b_prefill_reached_o <= b_prefill_reached;
b_read_sync : process(b_reset_i, b_clock_i)
begin
if b_reset_i = '1' then
b_read_address <= (others => '0');
b_prefill_reached <= to_stdulogic(prefill_g = 0);
elsif rising_edge(b_clock_i) then
b_read_address <= b_next_read_address;
b_prefill_reached <= b_next_prefill_reached;
end if;
end process;
sync_read_address_b_a : entity work.sync
generic map (
width_g => depth_order_g,
reset_value_g => '0')
port map (
reset_i => a_reset_i,
clock_i => a_clock_i,
data_i => b_read_address,
data_o => a_read_address);
async_fill <= (to_integer(unsigned(to_binary(a_write_address))) - to_integer(unsigned(to_binary(b_read_address)))) mod 2**depth_order_g;
end;
|
gpl-3.0
|
448c9f64d5f8d5a31a690241f9f0e00d
| 0.650014 | 2.602249 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd
| 1 | 3,994 |
-- $Id: tb_tst_serloop1_n3.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n3 - sim
-- Description: Test bench for sys_tst_serloop1_n3
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop1_n3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk
-- 2011-12-11 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_tst_serloop1_n3 is
end tb_tst_serloop1_n3;
architecture sim of tb_tst_serloop1_n3 is
signal CLK100 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100,
CLK_STOP => CLK_STOP
);
UUT : entity work.sys_tst_serloop1_n3
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_PPCM_CE_N => open,
O_PPCM_RST_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK100,
CLKH => CLK100,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
8f1cc016890e92504fe03472d6ae7480
| 0.531798 | 3.100932 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/ben_mem/simulation/bmg_stim_gen.vhd
| 1 | 13,011 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (32767 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"ben_mem.mif",
DEFAULT_DATA,
8,
32768);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>32768 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(14 DOWNTO 0) <= READ_ADDR(14 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ_REG(1);
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 32768 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
gpl-3.0
|
80310c22e0da3a8f00bd39113fe09480
| 0.529706 | 3.696307 | false | false | false | false |
superboy0712/MIPS
|
MIPS_PC_with_src_select.vhd
| 1 | 2,245 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:25:59 10/18/2014
-- Design Name:
-- Module Name: MIPS_PC_with_src_select - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MIPS_PC_with_src_select is
Port (
reset : in std_logic;
PC_en : in std_logic;
clk : in std_logic;
PCSrc : in STD_LOGIC;
Jump : in STD_LOGIC;
offeset_address : in STD_LOGIC_VECTOR (31 downto 0);
instruction : in STD_LOGIC_VECTOR(25 downto 0);
PC : out std_logic_vector (31 downto 0 ));
end MIPS_PC_with_src_select;
architecture Behavioral of MIPS_PC_with_src_select is
signal PC_register : signed( 31 DOWNTO 0 ) := ( others => '0');
signal branch_selector_outupt : std_logic_vector( 31 downto 0);
begin
process(tmp_PC)
begin
--initialization variable
--
if reset = '1' then tmp_PC := ( others => '0');
elsif reset = '0' and rising_edge(clk) then
if PC_en = '1' then
if PCSrc = '0' then branch_selector_outupt <= tmp_PC + 1;
elsif PCSrc = '1' then branch_selector_outupt <= tmp_PC + 1 + signed(offeset_address);
end if;
end if;
end if;
PC <= std_logic_vector(tmp_PC);
end process;
Jump_address_generator : process(instr_reg(25 downto 0))
-- to simplify, the 4msb always 0. becoz PC only 8bits
begin
Jump_address <= std_logic_vector(resize(unsigned(instr_reg(25 downto 0)), Jump_address'length));
end process;
PC_output_logic : process(PC_register, PCSrc, Jump, offeset_address, instruction)
begin
end process;
end Behavioral;
|
mit
|
c76363d4b2afc72a184839a6b7e70388
| 0.604009 | 3.391239 | false | false | false | false |
freecores/w11
|
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd
| 1 | 8,080 |
-- $Id: rlink_sp1c_fx2.vhd 525 2013-07-06 12:19:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c_fx2 - syn
-- Description: rlink_core8 + serport_1clock + fx2 combo
--
-- Dependencies: rlinklib/rlink_core8
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end entity rlink_sp1c_fx2;
architecture syn of rlink_sp1c_fx2 is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
begin
CORE : rlink_core8
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH,
CPREF => CPREF,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA,
P1_TXBUSY => FX2_TXBUSY
);
FX2CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => PETOWIDTH,
CCWIDTH => CCWIDTH,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
end syn;
|
gpl-2.0
|
6c7c0b4e29c60993c65838786611563c
| 0.527228 | 3.394958 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
libraries/std_logic_1164_additions.vhdl
| 2 | 70,414 |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-09-11 14:52:13-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.12 2007-09-11 14:52:13-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
gpl-3.0
|
0b8cf0f569a2bfdb76fd13902001ddc0
| 0.509955 | 3.844608 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rb_sres_or_3.vhd
| 2 | 2,697 |
-- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_3 - syn
-- Description: rbus result or, 3 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_3;
architecture syn of rb_sres_or_3 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack or
RB_SRES_3.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy or
RB_SRES_3.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err or
RB_SRES_3.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout or
RB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => RB_SRES_3,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
613f704d0433f181d0e0ac140e0b1537
| 0.53578 | 3.29304 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/ac429c869fe088c6/tx_axis_gen_sim_netlist.vhdl
| 1 | 196,900 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 20:11:26 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ tx_axis_gen_sim_netlist.vhdl
-- Design : tx_axis_gen
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem is
port (
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 64 downto 0 );
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1 downto 0) => din(33 downto 32),
DIC(1 downto 0) => din(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => p_0_out(33 downto 32),
DOC(1 downto 0) => p_0_out(35 downto 34),
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(37 downto 36),
DIB(1 downto 0) => din(39 downto 38),
DIC(1 downto 0) => din(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(37 downto 36),
DOB(1 downto 0) => p_0_out(39 downto 38),
DOC(1 downto 0) => p_0_out(41 downto 40),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(43 downto 42),
DIB(1 downto 0) => din(45 downto 44),
DIC(1 downto 0) => din(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(43 downto 42),
DOB(1 downto 0) => p_0_out(45 downto 44),
DOC(1 downto 0) => p_0_out(47 downto 46),
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(49 downto 48),
DIB(1 downto 0) => din(51 downto 50),
DIC(1 downto 0) => din(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(49 downto 48),
DOB(1 downto 0) => p_0_out(51 downto 50),
DOC(1 downto 0) => p_0_out(53 downto 52),
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(55 downto 54),
DIB(1 downto 0) => din(57 downto 56),
DIC(1 downto 0) => din(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(55 downto 54),
DOB(1 downto 0) => p_0_out(57 downto 56),
DOC(1 downto 0) => p_0_out(59 downto 58),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(61 downto 60),
DIB(1 downto 0) => din(63 downto 62),
DIC(1) => '0',
DIC(0) => din(64),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(61 downto 60),
DOB(1 downto 0) => p_0_out(63 downto 62),
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => p_0_out(64),
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => Q(3 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(0),
Q => \goreg_dm.dout_i_reg[64]\(0)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(10),
Q => \goreg_dm.dout_i_reg[64]\(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(11),
Q => \goreg_dm.dout_i_reg[64]\(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(12),
Q => \goreg_dm.dout_i_reg[64]\(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(13),
Q => \goreg_dm.dout_i_reg[64]\(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(14),
Q => \goreg_dm.dout_i_reg[64]\(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(15),
Q => \goreg_dm.dout_i_reg[64]\(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(16),
Q => \goreg_dm.dout_i_reg[64]\(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(17),
Q => \goreg_dm.dout_i_reg[64]\(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(18),
Q => \goreg_dm.dout_i_reg[64]\(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(19),
Q => \goreg_dm.dout_i_reg[64]\(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(1),
Q => \goreg_dm.dout_i_reg[64]\(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(20),
Q => \goreg_dm.dout_i_reg[64]\(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(21),
Q => \goreg_dm.dout_i_reg[64]\(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(22),
Q => \goreg_dm.dout_i_reg[64]\(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(23),
Q => \goreg_dm.dout_i_reg[64]\(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(24),
Q => \goreg_dm.dout_i_reg[64]\(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(25),
Q => \goreg_dm.dout_i_reg[64]\(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(26),
Q => \goreg_dm.dout_i_reg[64]\(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(27),
Q => \goreg_dm.dout_i_reg[64]\(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(28),
Q => \goreg_dm.dout_i_reg[64]\(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(29),
Q => \goreg_dm.dout_i_reg[64]\(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(2),
Q => \goreg_dm.dout_i_reg[64]\(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(30),
Q => \goreg_dm.dout_i_reg[64]\(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(31),
Q => \goreg_dm.dout_i_reg[64]\(31)
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(32),
Q => \goreg_dm.dout_i_reg[64]\(32)
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(33),
Q => \goreg_dm.dout_i_reg[64]\(33)
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(34),
Q => \goreg_dm.dout_i_reg[64]\(34)
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(35),
Q => \goreg_dm.dout_i_reg[64]\(35)
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(36),
Q => \goreg_dm.dout_i_reg[64]\(36)
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(37),
Q => \goreg_dm.dout_i_reg[64]\(37)
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(38),
Q => \goreg_dm.dout_i_reg[64]\(38)
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(39),
Q => \goreg_dm.dout_i_reg[64]\(39)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(3),
Q => \goreg_dm.dout_i_reg[64]\(3)
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(40),
Q => \goreg_dm.dout_i_reg[64]\(40)
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(41),
Q => \goreg_dm.dout_i_reg[64]\(41)
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(42),
Q => \goreg_dm.dout_i_reg[64]\(42)
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(43),
Q => \goreg_dm.dout_i_reg[64]\(43)
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(44),
Q => \goreg_dm.dout_i_reg[64]\(44)
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(45),
Q => \goreg_dm.dout_i_reg[64]\(45)
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(46),
Q => \goreg_dm.dout_i_reg[64]\(46)
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(47),
Q => \goreg_dm.dout_i_reg[64]\(47)
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(48),
Q => \goreg_dm.dout_i_reg[64]\(48)
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(49),
Q => \goreg_dm.dout_i_reg[64]\(49)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(4),
Q => \goreg_dm.dout_i_reg[64]\(4)
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(50),
Q => \goreg_dm.dout_i_reg[64]\(50)
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(51),
Q => \goreg_dm.dout_i_reg[64]\(51)
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(52),
Q => \goreg_dm.dout_i_reg[64]\(52)
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(53),
Q => \goreg_dm.dout_i_reg[64]\(53)
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(54),
Q => \goreg_dm.dout_i_reg[64]\(54)
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(55),
Q => \goreg_dm.dout_i_reg[64]\(55)
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(56),
Q => \goreg_dm.dout_i_reg[64]\(56)
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(57),
Q => \goreg_dm.dout_i_reg[64]\(57)
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(58),
Q => \goreg_dm.dout_i_reg[64]\(58)
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(59),
Q => \goreg_dm.dout_i_reg[64]\(59)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(5),
Q => \goreg_dm.dout_i_reg[64]\(5)
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(60),
Q => \goreg_dm.dout_i_reg[64]\(60)
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(61),
Q => \goreg_dm.dout_i_reg[64]\(61)
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(62),
Q => \goreg_dm.dout_i_reg[64]\(62)
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(63),
Q => \goreg_dm.dout_i_reg[64]\(63)
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(64),
Q => \goreg_dm.dout_i_reg[64]\(64)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(6),
Q => \goreg_dm.dout_i_reg[64]\(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(7),
Q => \goreg_dm.dout_i_reg[64]\(7)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(8),
Q => \goreg_dm.dout_i_reg[64]\(8)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_0_out(9),
Q => \goreg_dm.dout_i_reg[64]\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \gpr1.dout_i_reg[1]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EEFD8000"
)
port map (
I0 => curr_fwft_state(0),
I1 => \out\,
I2 => rd_en,
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_i,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_o_i,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00BF"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => curr_fwft_state(1),
I3 => \out\,
O => \gc0.count_reg[0]\(0)
);
\goreg_dm.dout_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpr1.dout_i[64]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00F7"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \out\,
O => E(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => \out\,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
p_2_out : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
almost_full : in STD_LOGIC;
p_7_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_rst_busy : in STD_LOGIC;
wr_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gaf.gaf0.ram_afull_i_i_3_n_0\ : STD_LOGIC;
signal \gwss.wsts/comp0\ : STD_LOGIC;
signal \gwss.wsts/comp1\ : STD_LOGIC;
signal \gwss.wsts/p_0_in\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_fb_i_i_3_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_3_n_0 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gaf.gaf0.ram_afull_i_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gcc0.gc1.gsym.count[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gcc0.gc1.gsym.count[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gcc0.gc1.gsym.count[3]_i_1\ : label is "soft_lutpair2";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gaf.gaf0.ram_afull_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00AA0000CCEE0CCC"
)
port map (
I0 => \gwss.wsts/p_0_in\,
I1 => almost_full,
I2 => \gwss.wsts/comp1\,
I3 => p_7_out,
I4 => E(0),
I5 => wr_rst_busy,
O => p_2_out
);
\gaf.gaf0.ram_afull_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gc0.count_d1_reg[3]\(3),
I1 => wr_pntr_plus2(3),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => wr_pntr_plus2(2),
I4 => \gaf.gaf0.ram_afull_i_i_3_n_0\,
O => \gwss.wsts/p_0_in\
);
\gaf.gaf0.ram_afull_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => wr_pntr_plus2(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => \gaf.gaf0.ram_afull_i_i_3_n_0\
);
\gcc0.gc1.gsym.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gcc0.gc1.gsym.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gcc0.gc1.gsym.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gcc0.gc1.gsym.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gcc0.gc1.gsym.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => p_12_out(0)
);
\gcc0.gc1.gsym.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => p_12_out(1)
);
\gcc0.gc1.gsym.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => p_12_out(2)
);
\gcc0.gc1.gsym.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => p_12_out(3)
);
\gcc0.gc1.gsym.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc1.gsym.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc1.gsym.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc1.gsym.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc1.gsym.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gcc0.gc1.gsym.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gcc0.gc1.gsym.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gcc0.gc1.gsym.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFC44FC"
)
port map (
I0 => \gwss.wsts/comp0\,
I1 => ram_empty_fb_i_reg,
I2 => ram_empty_fb_i_i_3_n_0,
I3 => wr_en,
I4 => \out\,
O => ram_empty_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gc0.count_d1_reg[3]\(3),
I1 => \^q\(3),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => \^q\(2),
I4 => ram_empty_fb_i_i_4_n_0,
O => \gwss.wsts/comp0\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"4100004100000000"
)
port map (
I0 => ram_empty_fb_i_i_5_n_0,
I1 => \^q\(2),
I2 => \gc0.count_reg[3]\(2),
I3 => \^q\(3),
I4 => \gc0.count_reg[3]\(3),
I5 => p_7_out,
O => ram_empty_fb_i_i_3_n_0
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => \^q\(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => ram_empty_fb_i_i_4_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => \gc0.count_reg[3]\(1),
I2 => \^q\(0),
I3 => \gc0.count_reg[3]\(0),
O => ram_empty_fb_i_i_5_n_0
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000800F8F0F8"
)
port map (
I0 => \gwss.wsts/comp1\,
I1 => wr_en,
I2 => \out\,
I3 => p_7_out,
I4 => \gwss.wsts/comp0\,
I5 => wr_rst_busy,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gc0.count_d1_reg[3]\(3),
I1 => p_12_out(3),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => p_12_out(2),
I4 => ram_full_fb_i_i_3_n_0,
O => \gwss.wsts/comp1\
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_12_out(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => p_12_out(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => ram_full_fb_i_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
p_2_out : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal p_15_out : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of p_15_out : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of \gaf.gaf0.ram_afull_i_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \gaf.gaf0.ram_afull_i_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \gaf.gaf0.ram_afull_i_reg\ : label is "no";
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
almost_full <= ram_afull_i;
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gaf.gaf0.ram_afull_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => p_2_out,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_afull_i
);
\gcc0.gc1.gsym.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => p_15_out
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
signal dout_i : STD_LOGIC_VECTOR ( 64 downto 0 );
begin
\gdm.dm_gen.dm\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem
port map (
AR(0) => AR(0),
E(0) => E(0),
EN => EN,
Q(3 downto 0) => Q(3 downto 0),
clk => clk,
din(64 downto 0) => din(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\goreg_dm.dout_i_reg[64]\(64 downto 0) => dout_i(64 downto 0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(32),
Q => dout(32)
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(33),
Q => dout(33)
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(34),
Q => dout(34)
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(35),
Q => dout(35)
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(36),
Q => dout(36)
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(37),
Q => dout(37)
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(38),
Q => dout(38)
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(39),
Q => dout(39)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(40),
Q => dout(40)
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(41),
Q => dout(41)
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(42),
Q => dout(42)
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(43),
Q => dout(43)
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(44),
Q => dout(44)
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(45),
Q => dout(45)
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(46),
Q => dout(46)
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(47),
Q => dout(47)
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(48),
Q => dout(48)
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(49),
Q => dout(49)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(50),
Q => dout(50)
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(51),
Q => dout(51)
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(52),
Q => dout(52)
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(53),
Q => dout(53)
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(54),
Q => dout(54)
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(55),
Q => dout(55)
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(56),
Q => dout(56)
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(57),
Q => dout(57)
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(58),
Q => dout(58)
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(59),
Q => dout(59)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(60),
Q => dout(60)
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(61),
Q => dout(61)
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(62),
Q => dout(62)
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(63),
Q => dout(63)
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(64),
Q => dout(64)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => dout_i(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_7_out : out STD_LOGIC;
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \^out\ : STD_LOGIC;
signal \^p_7_out\ : STD_LOGIC;
begin
\out\ <= \^out\;
p_7_out <= \^p_7_out\;
\gr1.gr1_int.rfwft\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft
port map (
AR(0) => AR(0),
E(0) => E(0),
clk => clk,
empty => empty,
\gc0.count_reg[0]\(0) => \^p_7_out\,
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
\out\ => \^out\,
rd_en => rd_en
);
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
AR(0) => AR(0),
clk => clk,
\out\ => \^out\,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^p_7_out\,
Q(3 downto 0) => Q(3 downto 0),
clk => clk,
\gpr1.dout_i_reg[1]\(3 downto 0) => \gpr1.dout_i_reg[1]\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_7_out : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^almost_full\ : STD_LOGIC;
signal \gwss.wsts_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
almost_full <= \^almost_full\;
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^e\(0),
almost_full => \^almost_full\,
clk => clk,
full => full,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\out\ => \gwss.wsts_n_0\,
p_2_out => p_2_out,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3 downto 0) => Q(3 downto 0),
almost_full => \^almost_full\,
clk => clk,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gc0.count_reg[3]\(3 downto 0) => \gc0.count_reg[3]\(3 downto 0),
\out\ => \gwss.wsts_n_0\,
p_2_out => p_2_out,
p_7_out => p_7_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_empty_i_reg => ram_empty_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_2_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(3 downto 0) => rd_pntr_plus1(3 downto 0),
clk => clk,
empty => empty,
\goreg_dm.dout_i_reg[64]\(0) => p_5_out,
\gpr1.dout_i_reg[1]\(3 downto 0) => p_0_out_0(3 downto 0),
\out\ => p_2_out,
p_7_out => p_7_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
Q(3 downto 0) => p_11_out(3 downto 0),
almost_full => almost_full,
clk => clk,
full => full,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gc0.count_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\out\ => rst_full_ff_i,
p_7_out => p_7_out,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
AR(0) => rd_rst_i(0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
EN => \gntv_or_sync_fifo.gl0.wr_n_2\,
Q(3 downto 0) => p_11_out(3 downto 0),
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_5_out
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
rst => rst,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
almost_full => almost_full,
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
almost_full => almost_full,
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 65;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 65;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 14;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
almost_full => almost_full,
clk => clk,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 64 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 64 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "tx_axis_gen,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 65;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 65;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 14;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => almost_full,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(4 downto 0) => NLW_U0_data_count_UNCONNECTED(4 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(64 downto 0) => din(64 downto 0),
dout(64 downto 0) => dout(64 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(3 downto 0) => B"0000",
prog_empty_thresh_assert(3 downto 0) => B"0000",
prog_empty_thresh_negate(3 downto 0) => B"0000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(3 downto 0) => B"0000",
prog_full_thresh_assert(3 downto 0) => B"0000",
prog_full_thresh_negate(3 downto 0) => B"0000",
rd_clk => '0',
rd_data_count(4 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(4 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(4 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(4 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
187e33eebc27089937d0c6ab2591818e
| 0.607344 | 2.841516 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/1307ce7a11e7d807/vio_0_sim_netlist.vhdl
| 1 | 549,685 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 10:23:02 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.vhdl
-- Design : vio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
port (
s_drdy_i : out STD_LOGIC;
in0 : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_en_reg[4]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\sl_oport_o[16]_INST_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_rst_o : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
\wr_en[4]_i_3\ : in STD_LOGIC;
\wr_en[4]_i_5\ : in STD_LOGIC;
\Bus_Data_out_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Probe_out_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
signal \Bus_data_out[0]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[10]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[11]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[12]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[13]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[14]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[15]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[1]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[2]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[3]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[4]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[5]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[6]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[7]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[8]_i_1_n_0\ : STD_LOGIC;
signal \Bus_data_out[9]_i_1_n_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal Hold_probe_in : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \data_info_probe_in__67\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^in0\ : STD_LOGIC;
signal int_cnt_rst : STD_LOGIC;
signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rd_en_p1 : STD_LOGIC;
signal rd_en_p2 : STD_LOGIC;
signal wr_control_reg : STD_LOGIC;
signal \wr_en[2]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_4_n_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_0\ : STD_LOGIC;
signal wr_probe_out_modified : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_8_p1 : STD_LOGIC;
signal xsdb_addr_8_p2 : STD_LOGIC;
signal xsdb_drdy_i_1_n_0 : STD_LOGIC;
signal xsdb_rd : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Bus_data_out[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of rd_en_p1_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair12";
begin
D(0) <= \^d\(0);
SR(0) <= \^sr\(0);
in0 <= \^in0\;
\wr_en_reg[4]_0\ <= \^wr_en_reg[4]_0\;
\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => Probe_out_reg(0),
I1 => \data_info_probe_in__67\(0),
I2 => xsdb_addr_8_p2,
O => \Bus_data_out[0]_i_1_n_0\
);
\Bus_data_out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF00AF000FC000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(0),
I1 => probe_out_modified(0),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => \^in0\,
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(0)
);
\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(10),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(10),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[10]_i_1_n_0\
);
\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(11),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(11),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[11]_i_1_n_0\
);
\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => xsdb_addr_2_0_p2(0),
I1 => probe_out_modified(12),
I2 => xsdb_addr_2_0_p2(1),
I3 => xsdb_addr_2_0_p2(2),
I4 => xsdb_addr_8_p2,
O => \Bus_data_out[12]_i_1_n_0\
);
\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => xsdb_addr_2_0_p2(0),
I1 => probe_out_modified(13),
I2 => xsdb_addr_2_0_p2(1),
I3 => xsdb_addr_2_0_p2(2),
I4 => xsdb_addr_8_p2,
O => \Bus_data_out[13]_i_1_n_0\
);
\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => xsdb_addr_2_0_p2(0),
I1 => probe_out_modified(14),
I2 => xsdb_addr_2_0_p2(1),
I3 => xsdb_addr_2_0_p2(2),
I4 => xsdb_addr_8_p2,
O => \Bus_data_out[14]_i_1_n_0\
);
\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => xsdb_addr_2_0_p2(0),
I1 => probe_out_modified(15),
I2 => xsdb_addr_2_0_p2(1),
I3 => xsdb_addr_2_0_p2(2),
I4 => xsdb_addr_8_p2,
O => \Bus_data_out[15]_i_1_n_0\
);
\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \data_info_probe_in__67\(1),
I1 => xsdb_addr_8_p2,
O => \Bus_data_out[1]_i_1_n_0\
);
\Bus_data_out[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A00F0F0F00C0C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(1),
I1 => probe_out_modified(1),
I2 => xsdb_addr_2_0_p2(2),
I3 => \^sr\(0),
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(1)
);
\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \data_info_probe_in__67\(2),
I1 => xsdb_addr_8_p2,
O => \Bus_data_out[2]_i_1_n_0\
);
\Bus_data_out[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A000000F00CFCF"
)
port map (
I0 => \Bus_Data_out_reg[11]\(2),
I1 => probe_out_modified(2),
I2 => xsdb_addr_2_0_p2(2),
I3 => int_cnt_rst,
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(2)
);
\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(3),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(3),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[3]_i_1_n_0\
);
\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(4),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(4),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[4]_i_1_n_0\
);
\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(5),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(5),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[5]_i_1_n_0\
);
\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(6),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(6),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[6]_i_1_n_0\
);
\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(7),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(7),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[7]_i_1_n_0\
);
\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(8),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(8),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[8]_i_1_n_0\
);
\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088300000"
)
port map (
I0 => \Bus_Data_out_reg[11]\(9),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(9),
I3 => xsdb_addr_2_0_p2(0),
I4 => xsdb_addr_2_0_p2(2),
I5 => xsdb_addr_8_p2,
O => \Bus_data_out[9]_i_1_n_0\
);
\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[0]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(0),
R => '0'
);
\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[10]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(10),
R => '0'
);
\bus_data_out_reg[11]_RnM\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[11]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(11),
R => '0'
);
\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[12]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(12),
R => '0'
);
\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[13]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(13),
R => '0'
);
\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[14]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(14),
R => '0'
);
\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[15]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(15),
R => '0'
);
\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[1]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(1),
R => '0'
);
\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[2]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(2),
R => '0'
);
\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[3]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(3),
R => '0'
);
\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[4]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(4),
R => '0'
);
\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[5]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(5),
R => '0'
);
\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[6]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(6),
R => '0'
);
\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[7]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(7),
R => '0'
);
\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[8]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(8),
R => '0'
);
\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \Bus_data_out[9]_i_1_n_0\,
Q => \sl_oport_o[16]_INST_0\(9),
R => '0'
);
Hold_probe_in_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(3),
Q => Hold_probe_in,
R => s_rst_o
);
clear_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(1),
Q => \^sr\(0),
R => s_rst_o
);
committ_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(0),
Q => \^in0\,
R => s_rst_o
);
int_cnt_rst_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(2),
Q => int_cnt_rst,
R => s_rst_o
);
\probe_in_reg[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Hold_probe_in,
O => E(0)
);
\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(0),
Q => probe_out_modified(0),
R => \^sr\(0)
);
\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(10),
Q => probe_out_modified(10),
R => \^sr\(0)
);
\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(11),
Q => probe_out_modified(11),
R => \^sr\(0)
);
\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(12),
Q => probe_out_modified(12),
R => \^sr\(0)
);
\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(13),
Q => probe_out_modified(13),
R => \^sr\(0)
);
\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(14),
Q => probe_out_modified(14),
R => \^sr\(0)
);
\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(15),
Q => probe_out_modified(15),
R => \^sr\(0)
);
\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(1),
Q => probe_out_modified(1),
R => \^sr\(0)
);
\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(2),
Q => probe_out_modified(2),
R => \^sr\(0)
);
\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(3),
Q => probe_out_modified(3),
R => \^sr\(0)
);
\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(4),
Q => probe_out_modified(4),
R => \^sr\(0)
);
\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(5),
Q => probe_out_modified(5),
R => \^sr\(0)
);
\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(6),
Q => probe_out_modified(6),
R => \^sr\(0)
);
\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(7),
Q => probe_out_modified(7),
R => \^sr\(0)
);
\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(8),
Q => probe_out_modified(8),
R => \^sr\(0)
);
\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(9),
Q => probe_out_modified(9),
R => \^sr\(0)
);
rd_en_p1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_rd
);
rd_en_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_rd,
Q => rd_en_p1,
R => s_rst_o
);
rd_en_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => rd_en_p1,
Q => rd_en_p2,
R => s_rst_o
);
\wr_en[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => s_daddr_o(2),
I3 => \^wr_en_reg[4]_0\,
I4 => s_daddr_o(0),
I5 => s_daddr_o(1),
O => \wr_en[2]_i_1_n_0\
);
\wr_en[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000800"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => \^wr_en_reg[4]_0\,
I3 => s_daddr_o(2),
I4 => s_daddr_o(0),
I5 => s_daddr_o(1),
O => \wr_en[4]_i_1_n_0\
);
\wr_en[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \wr_en[4]_i_3\,
I1 => \wr_en[4]_i_4_n_0\,
I2 => \wr_en[4]_i_5\,
I3 => s_daddr_o(5),
O => \^wr_en_reg[4]_0\
);
\wr_en[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(4),
I1 => s_daddr_o(3),
I2 => s_daddr_o(7),
I3 => s_daddr_o(6),
O => \wr_en[4]_i_4_n_0\
);
\wr_en_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[2]_i_1_n_0\,
Q => wr_control_reg,
R => '0'
);
\wr_en_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[4]_i_1_n_0\,
Q => wr_probe_out_modified,
R => '0'
);
\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(0),
Q => \^d\(0),
R => '0'
);
\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(1),
Q => xsdb_addr_2_0_p1(1),
R => '0'
);
\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(2),
Q => xsdb_addr_2_0_p1(2),
R => '0'
);
\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \^d\(0),
Q => xsdb_addr_2_0_p2(0),
R => '0'
);
\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(1),
Q => xsdb_addr_2_0_p2(1),
R => '0'
);
\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(2),
Q => xsdb_addr_2_0_p2(2),
R => '0'
);
xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(5),
Q => xsdb_addr_8_p1,
R => '0'
);
xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_8_p1,
Q => xsdb_addr_8_p2,
R => '0'
);
xsdb_drdy_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => rd_en_p2,
O => xsdb_drdy_i_1_n_0
);
xsdb_drdy_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_drdy_i_1_n_0,
Q => s_drdy_i,
R => s_rst_o
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC;
s_den_o : in STD_LOGIC;
s_dwe_o : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wr_en[4]_i_5\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
s_rst_o : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC;
signal Read_int : STD_LOGIC;
signal data_int_sync1 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of data_int_sync1 : signal is "true";
signal data_int_sync2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg of data_int_sync2 : signal is "true";
signal \dn_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[3]\ : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal probe_in_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true;
signal read_done : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of read_done : signal is "200";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of read_done : signal is "found";
signal read_done_i_1_n_0 : STD_LOGIC;
signal \up_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \up_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[1]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[2]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[3]\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes";
attribute RTL_MAX_FANOUT of read_done_reg : label is "found";
begin
\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(0),
Q => Q(0),
R => '0'
);
\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_in,
Q => Q(10),
R => '0'
);
\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[3]\,
Q => Q(11),
R => '0'
);
\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(1),
Q => Q(1),
R => '0'
);
\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(2),
Q => Q(2),
R => '0'
);
\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(3),
Q => Q(3),
R => '0'
);
\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[0]\,
Q => Q(4),
R => '0'
);
\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[1]\,
Q => Q(5),
R => '0'
);
\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[2]\,
Q => Q(6),
R => '0'
);
\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[3]\,
Q => Q(7),
R => '0'
);
\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[0]\,
Q => Q(8),
R => '0'
);
\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_6_in,
Q => Q(9),
R => '0'
);
Read_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
I2 => s_daddr_o(2),
I3 => s_daddr_o(1),
I4 => s_daddr_o(0),
I5 => \wr_en[4]_i_5\,
O => \DECODER_INST/rd_en_int_7\
);
Read_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \DECODER_INST/rd_en_int_7\,
Q => Read_int,
R => '0'
);
\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(0),
Q => data_int_sync1(0),
R => '0'
);
\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(1),
Q => data_int_sync1(1),
R => '0'
);
\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(2),
Q => data_int_sync1(2),
R => '0'
);
\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(3),
Q => data_int_sync1(3),
R => '0'
);
\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(0),
Q => data_int_sync2(0),
R => '0'
);
\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(1),
Q => data_int_sync2(1),
R => '0'
);
\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(2),
Q => data_int_sync2(2),
R => '0'
);
\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(3),
Q => data_int_sync2(3),
R => '0'
);
\dn_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[0]\,
I1 => data_int_sync1(0),
I2 => data_int_sync2(0),
O => \dn_activity[0]_i_1_n_0\
);
\dn_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_6_in,
I1 => data_int_sync1(1),
I2 => data_int_sync2(1),
O => \dn_activity[1]_i_1_n_0\
);
\dn_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_9_in,
I1 => data_int_sync1(2),
I2 => data_int_sync2(2),
O => \dn_activity[2]_i_1_n_0\
);
\dn_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[3]\,
I1 => data_int_sync1(3),
I2 => data_int_sync2(3),
O => \dn_activity[3]_i_1_n_0\
);
\dn_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[0]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[0]\,
R => read_done
);
\dn_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[1]_i_1_n_0\,
Q => p_6_in,
R => read_done
);
\dn_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[2]_i_1_n_0\,
Q => p_9_in,
R => read_done
);
\dn_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[3]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[3]\,
R => read_done
);
\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(0),
Q => probe_in_reg(0),
R => '0'
);
\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(1),
Q => probe_in_reg(1),
R => '0'
);
\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(2),
Q => probe_in_reg(2),
R => '0'
);
\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(3),
Q => probe_in_reg(3),
R => '0'
);
read_done_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Read_int,
I1 => read_done,
I2 => s_rst_o,
O => read_done_i_1_n_0
);
read_done_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => read_done_i_1_n_0,
Q => read_done,
R => '0'
);
\up_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[0]\,
I1 => data_int_sync2(0),
I2 => data_int_sync1(0),
O => \up_activity[0]_i_1_n_0\
);
\up_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[1]\,
I1 => data_int_sync2(1),
I2 => data_int_sync1(1),
O => \up_activity[1]_i_1_n_0\
);
\up_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[2]\,
I1 => data_int_sync2(2),
I2 => data_int_sync1(2),
O => \up_activity[2]_i_1_n_0\
);
\up_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[3]\,
I1 => data_int_sync2(3),
I2 => data_int_sync1(3),
O => \up_activity[3]_i_1_n_0\
);
\up_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[0]_i_1_n_0\,
Q => \up_activity_reg_n_0_[0]\,
R => read_done
);
\up_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[1]_i_1_n_0\,
Q => \up_activity_reg_n_0_[1]\,
R => read_done
);
\up_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[2]_i_1_n_0\,
Q => \up_activity_reg_n_0_[2]\,
R => read_done
);
\up_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[3]_i_1_n_0\,
Q => \up_activity_reg_n_0_[3]\,
R => read_done
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one is
port (
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
data_int : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
UNCONN_IN : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\G_PROBE_OUT[0].wr_probe_out_reg\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one is
signal \^data_int\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \data_int[0]_i_1_n_0\ : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Probe_out_reg[0]\ : label is "yes";
begin
data_int(0) <= \^data_int\(0);
\Probe_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \out\,
D => \^data_int\(0),
Q => probe_out0(0),
R => SR(0)
);
\data_int[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => Q(0),
I1 => \G_PROBE_OUT[0].wr_probe_out_reg\,
I2 => SR(0),
I3 => \^data_int\(0),
O => \data_int[0]_i_1_n_0\
);
\data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => UNCONN_IN,
CE => '1',
D => \data_int[0]_i_1_n_0\,
Q => \^data_int\(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one_0 is
port (
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
\Probe_out_reg[0]_0\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
UNCONN_IN : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\G_PROBE_OUT[1].wr_probe_out_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one_0 : entity is "vio_v3_0_13_probe_out_one";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one_0 is
signal \^probe_out_reg[0]_0\ : STD_LOGIC;
signal \data_int[0]_i_1__0_n_0\ : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Probe_out_reg[0]\ : label is "yes";
begin
\Probe_out_reg[0]_0\ <= \^probe_out_reg[0]_0\;
\Probe_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \out\,
D => \^probe_out_reg[0]_0\,
Q => probe_out1(0),
R => SR(0)
);
\data_int[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => Q(0),
I1 => \G_PROBE_OUT[1].wr_probe_out_reg\,
I2 => SR(0),
I3 => \^probe_out_reg[0]_0\,
O => \data_int[0]_i_1__0_n_0\
);
\data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => UNCONN_IN,
CE => '1',
D => \data_int[0]_i_1__0_n_0\,
Q => \^probe_out_reg[0]_0\,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
port (
s_rst_o : out STD_LOGIC;
s_dclk_o : out STD_LOGIC;
s_den_o : out STD_LOGIC;
s_dwe_o : out STD_LOGIC;
s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
s_drdy_i : in STD_LOGIC
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2013;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "kintex7";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
signal reg_do : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \reg_do[10]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[15]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[2]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[3]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[6]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[7]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[9]_i_1_n_0\ : STD_LOGIC;
signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
signal reg_drdy : STD_LOGIC;
signal reg_drdy_i_1_n_0 : STD_LOGIC;
signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
signal reg_test0 : STD_LOGIC;
signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \reg_do[10]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \reg_do[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair8";
begin
\^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4);
s_dclk_o <= \^sl_iport_i\(1);
s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21);
s_dwe_o <= \^sl_iport_i\(3);
s_rst_o <= \^sl_iport_i\(0);
\reg_do[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAFFFFAAAAAAAA"
)
port map (
I0 => \reg_do[5]_i_2_n_0\,
I1 => \^sl_iport_i\(4),
I2 => reg_test(0),
I3 => \^sl_iport_i\(6),
I4 => \^sl_iport_i\(5),
I5 => \^sl_iport_i\(8),
O => reg_do(0)
);
\reg_do[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \reg_do[8]_i_2_n_0\,
I2 => \^sl_iport_i\(4),
O => \reg_do[10]_i_1_n_0\
);
\reg_do[10]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(10),
O => \reg_do[10]_i_2_n_0\
);
\reg_do[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
O => \reg_do[15]_i_1_n_0\
);
\reg_do[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20220000"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \^sl_iport_i\(4),
I2 => reg_test(1),
I3 => \^sl_iport_i\(6),
I4 => \reg_do[1]_i_2_n_0\,
O => reg_do(1)
);
\reg_do[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \^sl_iport_i\(8),
I1 => \^sl_iport_i\(10),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(7),
I4 => \^sl_iport_i\(9),
O => \reg_do[1]_i_2_n_0\
);
\reg_do[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(2),
O => \reg_do[2]_i_1_n_0\
);
\reg_do[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(3),
O => \reg_do[3]_i_1_n_0\
);
\reg_do[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(4),
O => \reg_do[4]_i_1_n_0\
);
\reg_do[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800044"
)
port map (
I0 => \^sl_iport_i\(6),
I1 => \^sl_iport_i\(8),
I2 => reg_test(5),
I3 => \^sl_iport_i\(4),
I4 => \^sl_iport_i\(5),
I5 => \reg_do[5]_i_2_n_0\,
O => reg_do(5)
);
\reg_do[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFFFFC"
)
port map (
I0 => \^sl_iport_i\(7),
I1 => \^sl_iport_i\(8),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(9),
O => \reg_do[5]_i_2_n_0\
);
\reg_do[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(6),
O => \reg_do[6]_i_1_n_0\
);
\reg_do[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(7),
O => \reg_do[7]_i_1_n_0\
);
\reg_do[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F00"
)
port map (
I0 => reg_test(8),
I1 => \^sl_iport_i\(4),
I2 => \^sl_iport_i\(5),
I3 => \reg_do[8]_i_2_n_0\,
O => reg_do(8)
);
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \^sl_iport_i\(9),
I1 => \^sl_iport_i\(7),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(8),
I5 => \^sl_iport_i\(6),
O => \reg_do[8]_i_2_n_0\
);
\reg_do[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C008000"
)
port map (
I0 => reg_test(9),
I1 => \reg_do[1]_i_2_n_0\,
I2 => \^sl_iport_i\(6),
I3 => \^sl_iport_i\(5),
I4 => \^sl_iport_i\(4),
O => \reg_do[9]_i_1_n_0\
);
\reg_do_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(0),
Q => \reg_do_reg_n_0_[0]\,
R => '0'
);
\reg_do_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[10]_i_2_n_0\,
Q => \reg_do_reg_n_0_[10]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(11),
Q => \reg_do_reg_n_0_[11]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(12),
Q => \reg_do_reg_n_0_[12]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(13),
Q => \reg_do_reg_n_0_[13]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(14),
Q => \reg_do_reg_n_0_[14]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(15),
Q => \reg_do_reg_n_0_[15]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(1),
Q => \reg_do_reg_n_0_[1]\,
R => '0'
);
\reg_do_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[2]_i_1_n_0\,
Q => \reg_do_reg_n_0_[2]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[3]_i_1_n_0\,
Q => \reg_do_reg_n_0_[3]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[4]_i_1_n_0\,
Q => \reg_do_reg_n_0_[4]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(5),
Q => \reg_do_reg_n_0_[5]\,
R => '0'
);
\reg_do_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[6]_i_1_n_0\,
Q => \reg_do_reg_n_0_[6]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[7]_i_1_n_0\,
Q => \reg_do_reg_n_0_[7]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(8),
Q => \reg_do_reg_n_0_[8]\,
R => '0'
);
\reg_do_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[9]_i_1_n_0\,
Q => \reg_do_reg_n_0_[9]\,
S => \reg_do[10]_i_1_n_0\
);
reg_drdy_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => s_den_o_INST_0_i_1_n_0,
I2 => \^sl_iport_i\(12),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(14),
I5 => \^sl_iport_i\(0),
O => reg_drdy_i_1_n_0
);
reg_drdy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_drdy_i_1_n_0,
Q => reg_drdy,
R => '0'
);
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(3),
I1 => \^sl_iport_i\(2),
I2 => \^sl_iport_i\(14),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(12),
I5 => s_den_o_INST_0_i_1_n_0,
O => reg_test0
);
\reg_test_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(21),
Q => reg_test(0),
R => '0'
);
\reg_test_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(31),
Q => reg_test(10),
R => '0'
);
\reg_test_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(32),
Q => reg_test(11),
R => '0'
);
\reg_test_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(33),
Q => reg_test(12),
R => '0'
);
\reg_test_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(34),
Q => reg_test(13),
R => '0'
);
\reg_test_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(35),
Q => reg_test(14),
R => '0'
);
\reg_test_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(36),
Q => reg_test(15),
R => '0'
);
\reg_test_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(22),
Q => reg_test(1),
R => '0'
);
\reg_test_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(23),
Q => reg_test(2),
R => '0'
);
\reg_test_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(24),
Q => reg_test(3),
R => '0'
);
\reg_test_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(25),
Q => reg_test(4),
R => '0'
);
\reg_test_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(26),
Q => reg_test(5),
R => '0'
);
\reg_test_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(27),
Q => reg_test(6),
R => '0'
);
\reg_test_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(28),
Q => reg_test(7),
R => '0'
);
\reg_test_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(29),
Q => reg_test(8),
R => '0'
);
\reg_test_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(30),
Q => reg_test(9),
R => '0'
);
s_den_o_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAAAAAA"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => \^sl_iport_i\(14),
I2 => \^sl_iport_i\(13),
I3 => \^sl_iport_i\(12),
I4 => s_den_o_INST_0_i_1_n_0,
O => s_den_o
);
s_den_o_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(15),
I1 => \^sl_iport_i\(16),
I2 => \^sl_iport_i\(17),
I3 => \^sl_iport_i\(18),
I4 => \^sl_iport_i\(20),
I5 => \^sl_iport_i\(19),
O => s_den_o_INST_0_i_1_n_0
);
\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_drdy_i,
I1 => reg_drdy,
O => sl_oport_o(0)
);
\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[9]\,
I1 => s_do_i(9),
I2 => reg_drdy,
O => sl_oport_o(10)
);
\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[10]\,
I1 => s_do_i(10),
I2 => reg_drdy,
O => sl_oport_o(11)
);
\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[11]\,
I1 => s_do_i(11),
I2 => reg_drdy,
O => sl_oport_o(12)
);
\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[12]\,
I1 => s_do_i(12),
I2 => reg_drdy,
O => sl_oport_o(13)
);
\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[13]\,
I1 => s_do_i(13),
I2 => reg_drdy,
O => sl_oport_o(14)
);
\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[14]\,
I1 => s_do_i(14),
I2 => reg_drdy,
O => sl_oport_o(15)
);
\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[15]\,
I1 => s_do_i(15),
I2 => reg_drdy,
O => sl_oport_o(16)
);
\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[0]\,
I1 => s_do_i(0),
I2 => reg_drdy,
O => sl_oport_o(1)
);
\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[1]\,
I1 => s_do_i(1),
I2 => reg_drdy,
O => sl_oport_o(2)
);
\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[2]\,
I1 => s_do_i(2),
I2 => reg_drdy,
O => sl_oport_o(3)
);
\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[3]\,
I1 => s_do_i(3),
I2 => reg_drdy,
O => sl_oport_o(4)
);
\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[4]\,
I1 => s_do_i(4),
I2 => reg_drdy,
O => sl_oport_o(5)
);
\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[5]\,
I1 => s_do_i(5),
I2 => reg_drdy,
O => sl_oport_o(6)
);
\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[6]\,
I1 => s_do_i(6),
I2 => reg_drdy,
O => sl_oport_o(7)
);
\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[7]\,
I1 => s_do_i(7),
I2 => reg_drdy,
O => sl_oport_o(8)
);
\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[8]\,
I1 => s_do_i(8),
I2 => reg_drdy,
O => sl_oport_o(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_all is
port (
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
Probe_out_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\G_PROBE_OUT[1].wr_probe_out_reg[1]_0\ : out STD_LOGIC;
\G_PROBE_OUT[1].wr_probe_out_reg[1]_1\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
in0 : in STD_LOGIC;
clk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_den_o : in STD_LOGIC;
s_dwe_o : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_all;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_all is
signal Committ_1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Committ_1 : signal is "true";
signal Committ_2 : STD_LOGIC;
attribute async_reg of Committ_2 : signal is "true";
signal \DECODER_INST/xsdb_wr\ : STD_LOGIC;
signal \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ : STD_LOGIC;
signal \G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0\ : STD_LOGIC;
signal \G_PROBE_OUT[0].wr_probe_out_reg\ : STD_LOGIC;
signal \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\ : STD_LOGIC;
signal \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ : STD_LOGIC;
signal \G_PROBE_OUT[1].wr_probe_out_reg\ : STD_LOGIC;
signal \^g_probe_out[1].wr_probe_out_reg[1]_0\ : STD_LOGIC;
signal \^g_probe_out[1].wr_probe_out_reg[1]_1\ : STD_LOGIC;
signal data_int : STD_LOGIC_VECTOR ( 0 to 0 );
signal probe_out_mem_n_0 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of Committ_1_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of Committ_1_reg : label is "yes";
attribute ASYNC_REG_boolean of Committ_2_reg : label is std.standard.true;
attribute KEEP of Committ_2_reg : label is "yes";
begin
\G_PROBE_OUT[1].wr_probe_out_reg[1]_0\ <= \^g_probe_out[1].wr_probe_out_reg[1]_0\;
\G_PROBE_OUT[1].wr_probe_out_reg[1]_1\ <= \^g_probe_out[1].wr_probe_out_reg[1]_1\;
Committ_1_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => in0,
Q => Committ_1,
R => '0'
);
Committ_2_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => Committ_1,
Q => Committ_2,
R => '0'
);
\G_PROBE_OUT[0].PROBE_OUT0_INST\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one
port map (
\G_PROBE_OUT[0].wr_probe_out_reg\ => \G_PROBE_OUT[0].wr_probe_out_reg\,
Q(0) => Q(0),
SR(0) => SR(0),
UNCONN_IN => \out\,
clk => clk,
data_int(0) => data_int(0),
\out\ => Committ_2,
probe_out0(0) => probe_out0(0)
);
\G_PROBE_OUT[0].wr_probe_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \DECODER_INST/xsdb_wr\,
I1 => s_daddr_o(1),
I2 => \G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0\,
I3 => s_daddr_o(8),
I4 => s_daddr_o(2),
I5 => s_daddr_o(0),
O => \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\
);
\G_PROBE_OUT[0].wr_probe_out[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => \DECODER_INST/xsdb_wr\
);
\G_PROBE_OUT[0].wr_probe_out[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^g_probe_out[1].wr_probe_out_reg[1]_0\,
I1 => s_daddr_o(7),
I2 => s_daddr_o(6),
I3 => s_daddr_o(10),
I4 => s_daddr_o(9),
I5 => \^g_probe_out[1].wr_probe_out_reg[1]_1\,
O => \G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0\
);
\G_PROBE_OUT[0].wr_probe_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\,
Q => \G_PROBE_OUT[0].wr_probe_out_reg\,
R => '0'
);
\G_PROBE_OUT[1].PROBE_OUT0_INST\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_one_0
port map (
\G_PROBE_OUT[1].wr_probe_out_reg\ => \G_PROBE_OUT[1].wr_probe_out_reg\,
\Probe_out_reg[0]_0\ => \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\,
Q(0) => Q(0),
SR(0) => SR(0),
UNCONN_IN => \out\,
clk => clk,
\out\ => Committ_2,
probe_out1(0) => probe_out1(0)
);
\G_PROBE_OUT[1].wr_probe_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000020000000000"
)
port map (
I0 => \DECODER_INST/xsdb_wr\,
I1 => s_daddr_o(1),
I2 => \G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0\,
I3 => s_daddr_o(8),
I4 => s_daddr_o(2),
I5 => s_daddr_o(0),
O => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\
);
\G_PROBE_OUT[1].wr_probe_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\,
Q => \G_PROBE_OUT[1].wr_probe_out_reg\,
R => '0'
);
\Probe_out_reg_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => probe_out_mem_n_0,
Q => Probe_out_reg(0),
R => '0'
);
probe_out_mem: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\,
I1 => data_int(0),
I2 => D(0),
O => probe_out_mem_n_0
);
\wr_en[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_daddr_o(3),
I1 => s_daddr_o(15),
I2 => s_daddr_o(16),
I3 => s_daddr_o(5),
I4 => s_daddr_o(4),
O => \^g_probe_out[1].wr_probe_out_reg[1]_1\
);
\wr_en[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(12),
I1 => s_daddr_o(11),
I2 => s_daddr_o(14),
I3 => s_daddr_o(13),
O => \^g_probe_out[1].wr_probe_out_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 );
sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 33;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
signal \<const0>\ : STD_LOGIC;
signal Bus_Data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bus_di\ : STD_LOGIC;
signal DECODER_INST_n_4 : STD_LOGIC;
signal DECODER_INST_n_5 : STD_LOGIC;
signal PROBE_OUT_ALL_INST_n_3 : STD_LOGIC;
signal PROBE_OUT_ALL_INST_n_4 : STD_LOGIC;
signal Probe_out_reg : STD_LOGIC_VECTOR ( 0 to 0 );
signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
signal bus_clk : STD_LOGIC;
attribute DONT_TOUCH_boolean : boolean;
attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true;
signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC;
signal bus_den : STD_LOGIC;
signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_drdy : STD_LOGIC;
signal bus_dwe : STD_LOGIC;
signal bus_rst : STD_LOGIC;
signal clear : STD_LOGIC;
signal committ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2;
attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0;
attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2;
attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1;
attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013;
attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1;
attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0;
attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7";
attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33;
attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true;
begin
probe_out10(0) <= \<const0>\;
probe_out100(0) <= \<const0>\;
probe_out101(0) <= \<const0>\;
probe_out102(0) <= \<const0>\;
probe_out103(0) <= \<const0>\;
probe_out104(0) <= \<const0>\;
probe_out105(0) <= \<const0>\;
probe_out106(0) <= \<const0>\;
probe_out107(0) <= \<const0>\;
probe_out108(0) <= \<const0>\;
probe_out109(0) <= \<const0>\;
probe_out11(0) <= \<const0>\;
probe_out110(0) <= \<const0>\;
probe_out111(0) <= \<const0>\;
probe_out112(0) <= \<const0>\;
probe_out113(0) <= \<const0>\;
probe_out114(0) <= \<const0>\;
probe_out115(0) <= \<const0>\;
probe_out116(0) <= \<const0>\;
probe_out117(0) <= \<const0>\;
probe_out118(0) <= \<const0>\;
probe_out119(0) <= \<const0>\;
probe_out12(0) <= \<const0>\;
probe_out120(0) <= \<const0>\;
probe_out121(0) <= \<const0>\;
probe_out122(0) <= \<const0>\;
probe_out123(0) <= \<const0>\;
probe_out124(0) <= \<const0>\;
probe_out125(0) <= \<const0>\;
probe_out126(0) <= \<const0>\;
probe_out127(0) <= \<const0>\;
probe_out128(0) <= \<const0>\;
probe_out129(0) <= \<const0>\;
probe_out13(0) <= \<const0>\;
probe_out130(0) <= \<const0>\;
probe_out131(0) <= \<const0>\;
probe_out132(0) <= \<const0>\;
probe_out133(0) <= \<const0>\;
probe_out134(0) <= \<const0>\;
probe_out135(0) <= \<const0>\;
probe_out136(0) <= \<const0>\;
probe_out137(0) <= \<const0>\;
probe_out138(0) <= \<const0>\;
probe_out139(0) <= \<const0>\;
probe_out14(0) <= \<const0>\;
probe_out140(0) <= \<const0>\;
probe_out141(0) <= \<const0>\;
probe_out142(0) <= \<const0>\;
probe_out143(0) <= \<const0>\;
probe_out144(0) <= \<const0>\;
probe_out145(0) <= \<const0>\;
probe_out146(0) <= \<const0>\;
probe_out147(0) <= \<const0>\;
probe_out148(0) <= \<const0>\;
probe_out149(0) <= \<const0>\;
probe_out15(0) <= \<const0>\;
probe_out150(0) <= \<const0>\;
probe_out151(0) <= \<const0>\;
probe_out152(0) <= \<const0>\;
probe_out153(0) <= \<const0>\;
probe_out154(0) <= \<const0>\;
probe_out155(0) <= \<const0>\;
probe_out156(0) <= \<const0>\;
probe_out157(0) <= \<const0>\;
probe_out158(0) <= \<const0>\;
probe_out159(0) <= \<const0>\;
probe_out16(0) <= \<const0>\;
probe_out160(0) <= \<const0>\;
probe_out161(0) <= \<const0>\;
probe_out162(0) <= \<const0>\;
probe_out163(0) <= \<const0>\;
probe_out164(0) <= \<const0>\;
probe_out165(0) <= \<const0>\;
probe_out166(0) <= \<const0>\;
probe_out167(0) <= \<const0>\;
probe_out168(0) <= \<const0>\;
probe_out169(0) <= \<const0>\;
probe_out17(0) <= \<const0>\;
probe_out170(0) <= \<const0>\;
probe_out171(0) <= \<const0>\;
probe_out172(0) <= \<const0>\;
probe_out173(0) <= \<const0>\;
probe_out174(0) <= \<const0>\;
probe_out175(0) <= \<const0>\;
probe_out176(0) <= \<const0>\;
probe_out177(0) <= \<const0>\;
probe_out178(0) <= \<const0>\;
probe_out179(0) <= \<const0>\;
probe_out18(0) <= \<const0>\;
probe_out180(0) <= \<const0>\;
probe_out181(0) <= \<const0>\;
probe_out182(0) <= \<const0>\;
probe_out183(0) <= \<const0>\;
probe_out184(0) <= \<const0>\;
probe_out185(0) <= \<const0>\;
probe_out186(0) <= \<const0>\;
probe_out187(0) <= \<const0>\;
probe_out188(0) <= \<const0>\;
probe_out189(0) <= \<const0>\;
probe_out19(0) <= \<const0>\;
probe_out190(0) <= \<const0>\;
probe_out191(0) <= \<const0>\;
probe_out192(0) <= \<const0>\;
probe_out193(0) <= \<const0>\;
probe_out194(0) <= \<const0>\;
probe_out195(0) <= \<const0>\;
probe_out196(0) <= \<const0>\;
probe_out197(0) <= \<const0>\;
probe_out198(0) <= \<const0>\;
probe_out199(0) <= \<const0>\;
probe_out2(0) <= \<const0>\;
probe_out20(0) <= \<const0>\;
probe_out200(0) <= \<const0>\;
probe_out201(0) <= \<const0>\;
probe_out202(0) <= \<const0>\;
probe_out203(0) <= \<const0>\;
probe_out204(0) <= \<const0>\;
probe_out205(0) <= \<const0>\;
probe_out206(0) <= \<const0>\;
probe_out207(0) <= \<const0>\;
probe_out208(0) <= \<const0>\;
probe_out209(0) <= \<const0>\;
probe_out21(0) <= \<const0>\;
probe_out210(0) <= \<const0>\;
probe_out211(0) <= \<const0>\;
probe_out212(0) <= \<const0>\;
probe_out213(0) <= \<const0>\;
probe_out214(0) <= \<const0>\;
probe_out215(0) <= \<const0>\;
probe_out216(0) <= \<const0>\;
probe_out217(0) <= \<const0>\;
probe_out218(0) <= \<const0>\;
probe_out219(0) <= \<const0>\;
probe_out22(0) <= \<const0>\;
probe_out220(0) <= \<const0>\;
probe_out221(0) <= \<const0>\;
probe_out222(0) <= \<const0>\;
probe_out223(0) <= \<const0>\;
probe_out224(0) <= \<const0>\;
probe_out225(0) <= \<const0>\;
probe_out226(0) <= \<const0>\;
probe_out227(0) <= \<const0>\;
probe_out228(0) <= \<const0>\;
probe_out229(0) <= \<const0>\;
probe_out23(0) <= \<const0>\;
probe_out230(0) <= \<const0>\;
probe_out231(0) <= \<const0>\;
probe_out232(0) <= \<const0>\;
probe_out233(0) <= \<const0>\;
probe_out234(0) <= \<const0>\;
probe_out235(0) <= \<const0>\;
probe_out236(0) <= \<const0>\;
probe_out237(0) <= \<const0>\;
probe_out238(0) <= \<const0>\;
probe_out239(0) <= \<const0>\;
probe_out24(0) <= \<const0>\;
probe_out240(0) <= \<const0>\;
probe_out241(0) <= \<const0>\;
probe_out242(0) <= \<const0>\;
probe_out243(0) <= \<const0>\;
probe_out244(0) <= \<const0>\;
probe_out245(0) <= \<const0>\;
probe_out246(0) <= \<const0>\;
probe_out247(0) <= \<const0>\;
probe_out248(0) <= \<const0>\;
probe_out249(0) <= \<const0>\;
probe_out25(0) <= \<const0>\;
probe_out250(0) <= \<const0>\;
probe_out251(0) <= \<const0>\;
probe_out252(0) <= \<const0>\;
probe_out253(0) <= \<const0>\;
probe_out254(0) <= \<const0>\;
probe_out255(0) <= \<const0>\;
probe_out26(0) <= \<const0>\;
probe_out27(0) <= \<const0>\;
probe_out28(0) <= \<const0>\;
probe_out29(0) <= \<const0>\;
probe_out3(0) <= \<const0>\;
probe_out30(0) <= \<const0>\;
probe_out31(0) <= \<const0>\;
probe_out32(0) <= \<const0>\;
probe_out33(0) <= \<const0>\;
probe_out34(0) <= \<const0>\;
probe_out35(0) <= \<const0>\;
probe_out36(0) <= \<const0>\;
probe_out37(0) <= \<const0>\;
probe_out38(0) <= \<const0>\;
probe_out39(0) <= \<const0>\;
probe_out4(0) <= \<const0>\;
probe_out40(0) <= \<const0>\;
probe_out41(0) <= \<const0>\;
probe_out42(0) <= \<const0>\;
probe_out43(0) <= \<const0>\;
probe_out44(0) <= \<const0>\;
probe_out45(0) <= \<const0>\;
probe_out46(0) <= \<const0>\;
probe_out47(0) <= \<const0>\;
probe_out48(0) <= \<const0>\;
probe_out49(0) <= \<const0>\;
probe_out5(0) <= \<const0>\;
probe_out50(0) <= \<const0>\;
probe_out51(0) <= \<const0>\;
probe_out52(0) <= \<const0>\;
probe_out53(0) <= \<const0>\;
probe_out54(0) <= \<const0>\;
probe_out55(0) <= \<const0>\;
probe_out56(0) <= \<const0>\;
probe_out57(0) <= \<const0>\;
probe_out58(0) <= \<const0>\;
probe_out59(0) <= \<const0>\;
probe_out6(0) <= \<const0>\;
probe_out60(0) <= \<const0>\;
probe_out61(0) <= \<const0>\;
probe_out62(0) <= \<const0>\;
probe_out63(0) <= \<const0>\;
probe_out64(0) <= \<const0>\;
probe_out65(0) <= \<const0>\;
probe_out66(0) <= \<const0>\;
probe_out67(0) <= \<const0>\;
probe_out68(0) <= \<const0>\;
probe_out69(0) <= \<const0>\;
probe_out7(0) <= \<const0>\;
probe_out70(0) <= \<const0>\;
probe_out71(0) <= \<const0>\;
probe_out72(0) <= \<const0>\;
probe_out73(0) <= \<const0>\;
probe_out74(0) <= \<const0>\;
probe_out75(0) <= \<const0>\;
probe_out76(0) <= \<const0>\;
probe_out77(0) <= \<const0>\;
probe_out78(0) <= \<const0>\;
probe_out79(0) <= \<const0>\;
probe_out8(0) <= \<const0>\;
probe_out80(0) <= \<const0>\;
probe_out81(0) <= \<const0>\;
probe_out82(0) <= \<const0>\;
probe_out83(0) <= \<const0>\;
probe_out84(0) <= \<const0>\;
probe_out85(0) <= \<const0>\;
probe_out86(0) <= \<const0>\;
probe_out87(0) <= \<const0>\;
probe_out88(0) <= \<const0>\;
probe_out89(0) <= \<const0>\;
probe_out9(0) <= \<const0>\;
probe_out90(0) <= \<const0>\;
probe_out91(0) <= \<const0>\;
probe_out92(0) <= \<const0>\;
probe_out93(0) <= \<const0>\;
probe_out94(0) <= \<const0>\;
probe_out95(0) <= \<const0>\;
probe_out96(0) <= \<const0>\;
probe_out97(0) <= \<const0>\;
probe_out98(0) <= \<const0>\;
probe_out99(0) <= \<const0>\;
DECODER_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
port map (
\Bus_Data_out_reg[11]\(11 downto 0) => Bus_Data_out(11 downto 0),
D(0) => xsdb_addr_2_0_p1(0),
E(0) => DECODER_INST_n_5,
Probe_out_reg(0) => Probe_out_reg(0),
Q(15) => \bus_data_int_reg_n_0_[15]\,
Q(14) => \bus_data_int_reg_n_0_[14]\,
Q(13) => \bus_data_int_reg_n_0_[13]\,
Q(12) => \bus_data_int_reg_n_0_[12]\,
Q(11) => \bus_data_int_reg_n_0_[11]\,
Q(10) => \bus_data_int_reg_n_0_[10]\,
Q(9) => \bus_data_int_reg_n_0_[9]\,
Q(8) => \bus_data_int_reg_n_0_[8]\,
Q(7) => \bus_data_int_reg_n_0_[7]\,
Q(6) => \bus_data_int_reg_n_0_[6]\,
Q(5) => \bus_data_int_reg_n_0_[5]\,
Q(4) => \bus_data_int_reg_n_0_[4]\,
Q(3) => \bus_data_int_reg_n_0_[3]\,
Q(2) => \bus_data_int_reg_n_0_[2]\,
Q(1) => p_0_in,
Q(0) => \^bus_di\,
SR(0) => clear,
in0 => committ,
\out\ => bus_clk,
s_daddr_o(7 downto 3) => bus_addr(10 downto 6),
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\sl_oport_o[16]_INST_0\(15 downto 0) => bus_do(15 downto 0),
\wr_en[4]_i_3\ => PROBE_OUT_ALL_INST_n_4,
\wr_en[4]_i_5\ => PROBE_OUT_ALL_INST_n_3,
\wr_en_reg[4]_0\ => DECODER_INST_n_4
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
PROBE_IN_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
port map (
D(3) => probe_in3(0),
D(2) => probe_in2(0),
D(1) => probe_in1(0),
D(0) => probe_in0(0),
E(0) => DECODER_INST_n_5,
Q(11 downto 0) => Bus_Data_out(11 downto 0),
clk => clk,
\out\ => bus_clk,
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en[4]_i_5\ => DECODER_INST_n_4
);
PROBE_OUT_ALL_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_out_all
port map (
D(0) => xsdb_addr_2_0_p1(0),
\G_PROBE_OUT[1].wr_probe_out_reg[1]_0\ => PROBE_OUT_ALL_INST_n_3,
\G_PROBE_OUT[1].wr_probe_out_reg[1]_1\ => PROBE_OUT_ALL_INST_n_4,
Probe_out_reg(0) => Probe_out_reg(0),
Q(0) => \^bus_di\,
SR(0) => clear,
clk => clk,
in0 => committ,
\out\ => bus_clk,
probe_out0(0) => probe_out0(0),
probe_out1(0) => probe_out1(0),
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe
);
U_XSDB_SLAVE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
port map (
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_dclk_o => bus_clk,
s_den_o => bus_den,
s_di_o(15 downto 0) => bus_di(15 downto 0),
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
sl_iport_i(36 downto 0) => sl_iport0(36 downto 0),
sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
);
\bus_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(0),
Q => \^bus_di\,
R => '0'
);
\bus_data_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(10),
Q => \bus_data_int_reg_n_0_[10]\,
R => '0'
);
\bus_data_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(11),
Q => \bus_data_int_reg_n_0_[11]\,
R => '0'
);
\bus_data_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(12),
Q => \bus_data_int_reg_n_0_[12]\,
R => '0'
);
\bus_data_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(13),
Q => \bus_data_int_reg_n_0_[13]\,
R => '0'
);
\bus_data_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(14),
Q => \bus_data_int_reg_n_0_[14]\,
R => '0'
);
\bus_data_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(15),
Q => \bus_data_int_reg_n_0_[15]\,
R => '0'
);
\bus_data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(1),
Q => p_0_in,
R => '0'
);
\bus_data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(2),
Q => \bus_data_int_reg_n_0_[2]\,
R => '0'
);
\bus_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(3),
Q => \bus_data_int_reg_n_0_[3]\,
R => '0'
);
\bus_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(4),
Q => \bus_data_int_reg_n_0_[4]\,
R => '0'
);
\bus_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(5),
Q => \bus_data_int_reg_n_0_[5]\,
R => '0'
);
\bus_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(6),
Q => \bus_data_int_reg_n_0_[6]\,
R => '0'
);
\bus_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(7),
Q => \bus_data_int_reg_n_0_[7]\,
R => '0'
);
\bus_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(8),
Q => \bus_data_int_reg_n_0_[8]\,
R => '0'
);
\bus_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(9),
Q => \bus_data_int_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio_0,vio,{}";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of inst : label is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of inst : label is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of inst : label is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of inst : label is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of inst : label is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of inst : label is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of inst : label is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of inst : label is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of inst : label is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of inst : label is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of inst : label is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of inst : label is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of inst : label is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of inst : label is 2;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of inst : label is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of inst : label is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of inst : label is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of inst : label is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of inst : label is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of inst : label is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of inst : label is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of inst : label is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of inst : label is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of inst : label is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of inst : label is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of inst : label is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of inst : label is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of inst : label is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of inst : label is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of inst : label is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of inst : label is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of inst : label is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of inst : label is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of inst : label is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of inst : label is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of inst : label is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of inst : label is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of inst : label is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of inst : label is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of inst : label is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of inst : label is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of inst : label is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of inst : label is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of inst : label is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of inst : label is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of inst : label is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of inst : label is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of inst : label is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of inst : label is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of inst : label is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of inst : label is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of inst : label is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of inst : label is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of inst : label is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of inst : label is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of inst : label is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of inst : label is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of inst : label is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of inst : label is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of inst : label is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of inst : label is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of inst : label is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of inst : label is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of inst : label is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of inst : label is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of inst : label is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of inst : label is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of inst : label is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of inst : label is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of inst : label is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of inst : label is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of inst : label is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of inst : label is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of inst : label is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of inst : label is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of inst : label is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of inst : label is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of inst : label is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of inst : label is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of inst : label is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of inst : label is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of inst : label is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of inst : label is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of inst : label is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of inst : label is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of inst : label is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of inst : label is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of inst : label is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of inst : label is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of inst : label is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of inst : label is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of inst : label is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of inst : label is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of inst : label is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of inst : label is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of inst : label is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of inst : label is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of inst : label is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of inst : label is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of inst : label is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of inst : label is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of inst : label is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of inst : label is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of inst : label is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of inst : label is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of inst : label is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of inst : label is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of inst : label is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of inst : label is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of inst : label is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of inst : label is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of inst : label is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of inst : label is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of inst : label is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of inst : label is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of inst : label is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of inst : label is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of inst : label is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of inst : label is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of inst : label is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of inst : label is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of inst : label is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of inst : label is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of inst : label is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of inst : label is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of inst : label is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of inst : label is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of inst : label is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of inst : label is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of inst : label is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of inst : label is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of inst : label is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of inst : label is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of inst : label is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of inst : label is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of inst : label is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of inst : label is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of inst : label is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of inst : label is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of inst : label is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of inst : label is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of inst : label is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of inst : label is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of inst : label is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of inst : label is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of inst : label is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of inst : label is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of inst : label is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of inst : label is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of inst : label is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of inst : label is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of inst : label is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of inst : label is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of inst : label is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of inst : label is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of inst : label is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of inst : label is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of inst : label is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of inst : label is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of inst : label is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of inst : label is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of inst : label is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of inst : label is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of inst : label is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of inst : label is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of inst : label is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of inst : label is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of inst : label is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of inst : label is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of inst : label is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of inst : label is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of inst : label is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of inst : label is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of inst : label is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of inst : label is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of inst : label is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of inst : label is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of inst : label is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of inst : label is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of inst : label is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of inst : label is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of inst : label is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of inst : label is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of inst : label is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of inst : label is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of inst : label is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of inst : label is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of inst : label is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of inst : label is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of inst : label is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of inst : label is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of inst : label is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of inst : label is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of inst : label is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of inst : label is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of inst : label is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of inst : label is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of inst : label is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of inst : label is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of inst : label is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of inst : label is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of inst : label is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of inst : label is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of inst : label is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of inst : label is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of inst : label is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of inst : label is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of inst : label is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of inst : label is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of inst : label is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of inst : label is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of inst : label is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of inst : label is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of inst : label is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of inst : label is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of inst : label is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of inst : label is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of inst : label is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of inst : label is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of inst : label is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of inst : label is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of inst : label is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of inst : label is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of inst : label is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of inst : label is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of inst : label is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of inst : label is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of inst : label is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of inst : label is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of inst : label is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of inst : label is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of inst : label is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of inst : label is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of inst : label is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of inst : label is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of inst : label is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of inst : label is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of inst : label is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of inst : label is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of inst : label is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of inst : label is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of inst : label is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of inst : label is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of inst : label is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of inst : label is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of inst : label is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of inst : label is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of inst : label is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of inst : label is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of inst : label is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of inst : label is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of inst : label is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of inst : label is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of inst : label is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of inst : label is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of inst : label is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of inst : label is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of inst : label is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of inst : label is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of inst : label is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of inst : label is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of inst : label is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of inst : label is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of inst : label is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of inst : label is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of inst : label is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of inst : label is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of inst : label is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of inst : label is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of inst : label is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of inst : label is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of inst : label is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of inst : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of inst : label is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of inst : label is std.standard.true;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 2;
attribute syn_noprune : string;
attribute syn_noprune of inst : label is "1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
port map (
clk => clk,
probe_in0(0) => probe_in0(0),
probe_in1(0) => probe_in1(0),
probe_in10(0) => '0',
probe_in100(0) => '0',
probe_in101(0) => '0',
probe_in102(0) => '0',
probe_in103(0) => '0',
probe_in104(0) => '0',
probe_in105(0) => '0',
probe_in106(0) => '0',
probe_in107(0) => '0',
probe_in108(0) => '0',
probe_in109(0) => '0',
probe_in11(0) => '0',
probe_in110(0) => '0',
probe_in111(0) => '0',
probe_in112(0) => '0',
probe_in113(0) => '0',
probe_in114(0) => '0',
probe_in115(0) => '0',
probe_in116(0) => '0',
probe_in117(0) => '0',
probe_in118(0) => '0',
probe_in119(0) => '0',
probe_in12(0) => '0',
probe_in120(0) => '0',
probe_in121(0) => '0',
probe_in122(0) => '0',
probe_in123(0) => '0',
probe_in124(0) => '0',
probe_in125(0) => '0',
probe_in126(0) => '0',
probe_in127(0) => '0',
probe_in128(0) => '0',
probe_in129(0) => '0',
probe_in13(0) => '0',
probe_in130(0) => '0',
probe_in131(0) => '0',
probe_in132(0) => '0',
probe_in133(0) => '0',
probe_in134(0) => '0',
probe_in135(0) => '0',
probe_in136(0) => '0',
probe_in137(0) => '0',
probe_in138(0) => '0',
probe_in139(0) => '0',
probe_in14(0) => '0',
probe_in140(0) => '0',
probe_in141(0) => '0',
probe_in142(0) => '0',
probe_in143(0) => '0',
probe_in144(0) => '0',
probe_in145(0) => '0',
probe_in146(0) => '0',
probe_in147(0) => '0',
probe_in148(0) => '0',
probe_in149(0) => '0',
probe_in15(0) => '0',
probe_in150(0) => '0',
probe_in151(0) => '0',
probe_in152(0) => '0',
probe_in153(0) => '0',
probe_in154(0) => '0',
probe_in155(0) => '0',
probe_in156(0) => '0',
probe_in157(0) => '0',
probe_in158(0) => '0',
probe_in159(0) => '0',
probe_in16(0) => '0',
probe_in160(0) => '0',
probe_in161(0) => '0',
probe_in162(0) => '0',
probe_in163(0) => '0',
probe_in164(0) => '0',
probe_in165(0) => '0',
probe_in166(0) => '0',
probe_in167(0) => '0',
probe_in168(0) => '0',
probe_in169(0) => '0',
probe_in17(0) => '0',
probe_in170(0) => '0',
probe_in171(0) => '0',
probe_in172(0) => '0',
probe_in173(0) => '0',
probe_in174(0) => '0',
probe_in175(0) => '0',
probe_in176(0) => '0',
probe_in177(0) => '0',
probe_in178(0) => '0',
probe_in179(0) => '0',
probe_in18(0) => '0',
probe_in180(0) => '0',
probe_in181(0) => '0',
probe_in182(0) => '0',
probe_in183(0) => '0',
probe_in184(0) => '0',
probe_in185(0) => '0',
probe_in186(0) => '0',
probe_in187(0) => '0',
probe_in188(0) => '0',
probe_in189(0) => '0',
probe_in19(0) => '0',
probe_in190(0) => '0',
probe_in191(0) => '0',
probe_in192(0) => '0',
probe_in193(0) => '0',
probe_in194(0) => '0',
probe_in195(0) => '0',
probe_in196(0) => '0',
probe_in197(0) => '0',
probe_in198(0) => '0',
probe_in199(0) => '0',
probe_in2(0) => probe_in2(0),
probe_in20(0) => '0',
probe_in200(0) => '0',
probe_in201(0) => '0',
probe_in202(0) => '0',
probe_in203(0) => '0',
probe_in204(0) => '0',
probe_in205(0) => '0',
probe_in206(0) => '0',
probe_in207(0) => '0',
probe_in208(0) => '0',
probe_in209(0) => '0',
probe_in21(0) => '0',
probe_in210(0) => '0',
probe_in211(0) => '0',
probe_in212(0) => '0',
probe_in213(0) => '0',
probe_in214(0) => '0',
probe_in215(0) => '0',
probe_in216(0) => '0',
probe_in217(0) => '0',
probe_in218(0) => '0',
probe_in219(0) => '0',
probe_in22(0) => '0',
probe_in220(0) => '0',
probe_in221(0) => '0',
probe_in222(0) => '0',
probe_in223(0) => '0',
probe_in224(0) => '0',
probe_in225(0) => '0',
probe_in226(0) => '0',
probe_in227(0) => '0',
probe_in228(0) => '0',
probe_in229(0) => '0',
probe_in23(0) => '0',
probe_in230(0) => '0',
probe_in231(0) => '0',
probe_in232(0) => '0',
probe_in233(0) => '0',
probe_in234(0) => '0',
probe_in235(0) => '0',
probe_in236(0) => '0',
probe_in237(0) => '0',
probe_in238(0) => '0',
probe_in239(0) => '0',
probe_in24(0) => '0',
probe_in240(0) => '0',
probe_in241(0) => '0',
probe_in242(0) => '0',
probe_in243(0) => '0',
probe_in244(0) => '0',
probe_in245(0) => '0',
probe_in246(0) => '0',
probe_in247(0) => '0',
probe_in248(0) => '0',
probe_in249(0) => '0',
probe_in25(0) => '0',
probe_in250(0) => '0',
probe_in251(0) => '0',
probe_in252(0) => '0',
probe_in253(0) => '0',
probe_in254(0) => '0',
probe_in255(0) => '0',
probe_in26(0) => '0',
probe_in27(0) => '0',
probe_in28(0) => '0',
probe_in29(0) => '0',
probe_in3(0) => probe_in3(0),
probe_in30(0) => '0',
probe_in31(0) => '0',
probe_in32(0) => '0',
probe_in33(0) => '0',
probe_in34(0) => '0',
probe_in35(0) => '0',
probe_in36(0) => '0',
probe_in37(0) => '0',
probe_in38(0) => '0',
probe_in39(0) => '0',
probe_in4(0) => '0',
probe_in40(0) => '0',
probe_in41(0) => '0',
probe_in42(0) => '0',
probe_in43(0) => '0',
probe_in44(0) => '0',
probe_in45(0) => '0',
probe_in46(0) => '0',
probe_in47(0) => '0',
probe_in48(0) => '0',
probe_in49(0) => '0',
probe_in5(0) => '0',
probe_in50(0) => '0',
probe_in51(0) => '0',
probe_in52(0) => '0',
probe_in53(0) => '0',
probe_in54(0) => '0',
probe_in55(0) => '0',
probe_in56(0) => '0',
probe_in57(0) => '0',
probe_in58(0) => '0',
probe_in59(0) => '0',
probe_in6(0) => '0',
probe_in60(0) => '0',
probe_in61(0) => '0',
probe_in62(0) => '0',
probe_in63(0) => '0',
probe_in64(0) => '0',
probe_in65(0) => '0',
probe_in66(0) => '0',
probe_in67(0) => '0',
probe_in68(0) => '0',
probe_in69(0) => '0',
probe_in7(0) => '0',
probe_in70(0) => '0',
probe_in71(0) => '0',
probe_in72(0) => '0',
probe_in73(0) => '0',
probe_in74(0) => '0',
probe_in75(0) => '0',
probe_in76(0) => '0',
probe_in77(0) => '0',
probe_in78(0) => '0',
probe_in79(0) => '0',
probe_in8(0) => '0',
probe_in80(0) => '0',
probe_in81(0) => '0',
probe_in82(0) => '0',
probe_in83(0) => '0',
probe_in84(0) => '0',
probe_in85(0) => '0',
probe_in86(0) => '0',
probe_in87(0) => '0',
probe_in88(0) => '0',
probe_in89(0) => '0',
probe_in9(0) => '0',
probe_in90(0) => '0',
probe_in91(0) => '0',
probe_in92(0) => '0',
probe_in93(0) => '0',
probe_in94(0) => '0',
probe_in95(0) => '0',
probe_in96(0) => '0',
probe_in97(0) => '0',
probe_in98(0) => '0',
probe_in99(0) => '0',
probe_out0(0) => probe_out0(0),
probe_out1(0) => probe_out1(0),
probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0),
probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
);
end STRUCTURE;
|
mit
|
81f4ad9d5b7c0de0b1a098007c372645
| 0.70645 | 2.978983 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/decryption_mem/example_design/decryption_mem_prod.vhd
| 1 | 10,650 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: decryption_mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : decryption_mem.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : ASYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 32768
-- C_READ_DEPTH_A : 32768
-- C_ADDRA_WIDTH : 15
-- C_HAS_RSTB : 1
-- C_RST_PRIORITY_B : SR
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 32768
-- C_READ_DEPTH_B : 32768
-- C_ADDRB_WIDTH : 15
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 1
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 1
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY decryption_mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END decryption_mem_prod;
ARCHITECTURE xilinx OF decryption_mem_prod IS
COMPONENT decryption_mem_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
RSTB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : decryption_mem_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
RSTB => RSTB,
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
gpl-3.0
|
a4d8ed94821fe01e314e379bdf0189b7
| 0.480094 | 3.836455 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/Convolve.vhd
| 1 | 7,581 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/21/2016 02:04:20 PM
-- Design Name:
-- Module Name: Convolve - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library xil_defaultlib;
use xil_defaultlib.filter_input_fifo_1;
use work.the_filter_package.all;
entity Convolve is
Generic (
FILTERMATRIX : filtMASK := (0,0,0,0,1,0,0,0,0);
FILTER_SCALE : integer := 1;
IMG_WIDTH : positive := 640;
IMG_HEIGHT : positive := 480
);
Port (
CLK : in std_logic;
RST : in std_logic; -- low active
VALID_IN : in std_logic; -- high active
READY_IN : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic; -- high active
READY_OUT : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0)
);
end Convolve;
architecture Behavioral of Convolve is
-- ======================================================================
-- COMPONENTS
-- ======================================================================
component FILTER is
generic (
FILTERMATRIX : filtMASK := (0,0,0,0,1,0,0,0,0);
FILTER_SCALE : integer := 1;
IN_BITWIDTH : positive := 12;
OUT_BITWIDTH : positive := 16
);
port (
CLK : in std_logic;
RESET : in std_logic;
IMG_WIDTH : in integer := 1920;
IMG_HEIGHT : in integer := 1080;
DATA_IN : in std_logic_vector(IN_BITWIDTH-1 downto 0);
H_SYNC_IN : in std_logic;
V_SYNC_IN : in std_logic;
DATA_OUT : out std_logic_vector(OUT_BITWIDTH-1 downto 0);
H_SYNC_OUT : out std_logic; -- um zwei Takte verzoegert
V_SYNC_OUT : out std_logic;
VALID : inout std_logic
);
end component;
component filter_input_fifo_1 is
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
end component;
-- ======================================================================
-- SIGNALS | CONSTANTS
-- ======================================================================
signal ipt_fifo_ren : std_logic := '0';
signal ipt_fifo_full : std_logic;
signal input_fifo_rst : std_logic := '0';
signal ipt_fifo_out : std_logic_vector(31 downto 0);
signal ipt_fifo_data_count : std_logic_vector(11 DOWNTO 0);
signal filter_hsync : std_logic := '0';
signal filter_vsync : std_logic := '0';
signal filter_valid : std_logic;
signal filter_data_out : std_logic_vector(15 downto 0);
-- ======================================================================
-- FSM PARAMETERS
-- ======================================================================
type FILTER_type is ( FILTER_IDLE, FILTER_WORK, FILTER_STALL, FILTER_NLINE, FILTER_NIMG);
signal FILTER_state : FILTER_type := FILTER_IDLE;
signal filter_w_ctr : integer := 0; -- filter width counter
signal filter_h_ctr : integer := 0; -- filter height counter
begin
-- ======================================================================
-- COMPONENTS
-- ======================================================================
input_fifo : component filter_input_fifo_1
port map(
clk => CLK,
rst => RST or input_fifo_rst,
din => DATA_IN,
wr_en => VALID_IN,
rd_en => ipt_fifo_ren,
dout => ipt_fifo_out,
full => ipt_fifo_full,
empty => open,
data_count => ipt_fifo_data_count
);
READY_OUT <= NOT ipt_fifo_full AND READY_IN;
filter_unit : filter
generic map (
FILTERMATRIX => FILTERMATRIX,
FILTER_SCALE => FILTER_SCALE,
IN_BITWIDTH => 12,
OUT_BITWIDTH => 16
)
port map (
CLK => CLK,
RESET => RST,
IMG_WIDTH => IMG_WIDTH,
IMG_HEIGHT => IMG_HEIGHT,
DATA_IN => ipt_fifo_out(11 downto 0),
H_SYNC_IN => filter_hsync,
V_SYNC_IN => filter_vsync,
DATA_OUT => filter_data_out,
H_SYNC_OUT => open,
V_SYNC_OUT => open,
VALID => filter_valid
);
DATA_OUT <= (31 downto 16 => '0') & filter_data_out;
VALID_OUT <= filter_valid;
-- ======================================================================
-- PROCESSES
-- ======================================================================
FILTER_FSM : process( CLK )
begin
if RST = '1' then
FILTER_state <= FILTER_IDLE;
filter_hsync <= '0';
filter_vsync <= '0';
ipt_fifo_ren <= '0';
filter_w_ctr <= 0;
filter_h_ctr <= 0;
elsif(rising_edge(CLK)) then
case FILTER_state is
when FILTER_IDLE =>
input_fifo_rst <= '0';
filter_hsync <= '0';
filter_vsync <= '0';
--
if unsigned(ipt_fifo_data_count) >= IMG_WIDTH then
FILTER_state <= FILTER_WORK;
else
FILTER_state <= FILTER_IDLE;
end if;
when FILTER_WORK =>
ipt_fifo_ren <= '1';
filter_hsync <= '1';
filter_vsync <= '1';
filter_w_ctr <= filter_w_ctr + 1;
if filter_w_ctr = IMG_WIDTH then
filter_hsync <= '0';
ipt_fifo_ren <= '0';
filter_h_ctr <= filter_h_ctr + 1;
FILTER_state <= FILTER_STALL;
else
FILTER_state <= FILTER_WORK;
end if;
when FILTER_STALL =>
filter_w_ctr <= 0;
if filter_h_ctr = IMG_HEIGHT then
filter_vsync <= '0';
filter_h_ctr <= 0;
FILTER_state <= FILTER_NIMG;
else
FILTER_state <= FILTER_NLINE;
end if;
when FILTER_NLINE =>
if unsigned(ipt_fifo_data_count) >= IMG_WIDTH then
FILTER_state <= FILTER_WORK;
else
FILTER_state <= FILTER_NLINE;
end if;
when FILTER_NIMG =>
input_fifo_rst <= '1';
FILTER_state <= FILTER_IDLE;
when others =>
end case;
end if;
end process; -- FILTER_FSM
end Behavioral;
|
gpl-3.0
|
b9c31a5c17441154bae9a57df66fe984
| 0.419997 | 4.359402 | false | false | false | false |
superboy0712/MIPS
|
testbench/tb_MIPSProcessor.vhd
| 1 | 11,220 |
-- Part of TDT4255 Computer Design laboratory exercises
-- Group for Computer Architecture and Design
-- Department of Computer and Information Science
-- Norwegian University of Science and Technology
-- tb_MIPSProcessor.vhd
-- Testbench for the MIPSProcessor component
-- Instantiates data and instruction memory, fills them with some
-- test data, enables the processor, then checks the data memory
-- to see if the expected values have been written.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_MIPSProcessor IS
END tb_MIPSProcessor;
ARCHITECTURE behavior OF tb_MIPSProcessor IS
constant ADDR_WIDTH : integer := 8;
constant DATA_WIDTH : integer := 32;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal processor_enable : std_logic := '0';
signal imem_data_in : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
signal dmem_data_in : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
--multiplexed memory outputs
signal imem_address : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal dmem_address : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal dmem_data_out : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
signal dmem_write_enable : std_logic_vector(0 downto 0) := (others => '0');
-- driven only from processor
signal proc_imem_address : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal proc_dmem_data_out : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
signal proc_dmem_write_enable : std_logic_vector(0 downto 0) := (others => '0');
signal proc_dmem_address : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
-- driven only from testbench
signal imem_data_out : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
signal imem_write_enable : std_logic_vector(0 downto 0) := (others => '0');
signal tb_imem_address : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal tb_dmem_data_out : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
signal tb_dmem_write_enable : std_logic_vector(0 downto 0) := (others => '0');
signal tb_dmem_address : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the processor
Processor: entity work.MIPSProcessor(Behavioral) port map (
clk => clk, reset => reset,
processor_enable => processor_enable,
imem_data_in => imem_data_in,
imem_address => proc_imem_address,
dmem_data_in => dmem_data_in,
dmem_address => proc_dmem_address,
dmem_data_out => proc_dmem_data_out,
dmem_write_enable => proc_dmem_write_enable(0)
);
-- instantiate the instruction memory
InstrMem: entity work.DualPortMem port map (
clka => clk, clkb => clk,
wea => imem_write_enable,
dina => imem_data_out,
addra => imem_address, douta => imem_data_in,
-- plug unused memory port
web => "0", dinb => x"00", addrb => "0000000000"
);
-- instantiate the data memory
DataMem: entity work.DualPortMem port map (
clka => clk, clkb => clk,
wea => dmem_write_enable, dina => dmem_data_out,
addra => dmem_address, douta => dmem_data_in,
-- plug unused memory port
web => "0", dinb => x"00", addrb => "0000000000"
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
imem_address <= proc_imem_address when processor_enable = '1' else tb_imem_address;
dmem_address <= proc_dmem_address when processor_enable = '1' else tb_dmem_address;
dmem_data_out <= proc_dmem_data_out when processor_enable = '1' else tb_dmem_data_out;
dmem_write_enable <= proc_dmem_write_enable when processor_enable = '1' else tb_dmem_write_enable;
-- Stimulus process
stim_proc: process
-- helper procedures for filling instruction memory
procedure WriteInstructionWord(
instruction : in std_logic_vector(DATA_WIDTH-1 downto 0);
address : in unsigned(ADDR_WIDTH-1 downto 0)) is
begin
tb_imem_address <= std_logic_vector(address);
imem_data_out <= instruction;
imem_write_enable <= "1";
wait until rising_edge(clk);
imem_write_enable <= "0";
end WriteInstructionWord;
procedure FillInstructionMemory is
constant TEST_INSTRS : integer := 31;
type InstrData is array (0 to TEST_INSTRS-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
variable TestInstrData : InstrData := (
-- X"8C080000",
-- X"8C010001",
-- X"8C020002",
-- X"8C030003",
-- X"8C040004",
-- X"8C050005",
-- X"8C060006",
-- X"8C070007",
-- X"00221820",
-- X"8C0a000a",
-- X"AC010012",
-- X"AC020011",
-- X"AC030013",
-- X"AC040017",
-- X"AC050015",
-- X"AC060016",
-- X"AC070018",
-- X"AC080010",
-- X"AC090014"
-- "00000000010000110011100000100000", --add $3, $1, $2 /$3 = 30 + 29 = 61
-- "10101100000000110000000000000001"
-- X"8C010001",
-- X"AC020002",
-- X"8C030003",
-- X"AC040004",
-- X"8C050005",
-- X"AC060006",
-- X"8C070007",
-- X"AC010011",
-- X"8C020012",
-- X"AC030013",
-- X"8C040014",
-- X"AC050015",
-- X"8C060016",
-- X"AC070017"
X"8C010001", --lw $1, 1($0) /$1 = 2 load from data address 4
X"8C020002", --lw $2, 2($0) /$2 = 10 load from data address 8
X"00221820", --add $3, $1, $2 /$3 = 12
X"AC030014", --sw $3, 20($0) /Saving value 12 on data address 20
X"10000002", --beq $0, $0, 2 /Jumping to instruction adress +2*4 to : (current)4*4 + (offset)2*4 +4 = 28.
X"AC030003", --sw $3, 3($0) /SKIPPED (Saving value 12 on address 3)
X"AC030004", --sw $3, 4($0) /SKIPPED (Saving value 12 on address 4)
X"AC030018", --sw $3, 24($0) /Saving value 12 on data address 24 ---
X"AC030007", --sw $3, 7($0) /Saving value 12 on address 7
X"3C030006", --lui $3, 6 /$3 = 6 * 2^16 = 393216 = 0x60000
X"AC030008", --sw $3, 8($0) /Saving value 0x60000 on address 8
X"00231820", --add $3, $1, $3 /$3 = 393218 = 0x60002
X"AC030009", --sw $3, 9($0) /Saving 0x60002 on address 9
X"10400002", --beq $2, $0, 2 /No branch
X"0001982A", --slt $19, $0, $1 /$19 = 1
X"AC13000C", --sw $19, 12($0) /Saving 1 on address 12
X"08000013", --j 19 /jump to 19
X"AC030001", --sw $3, 1($0) /SKIPPED (Saving 0x60002 on address 1)
X"1000FFFD", --beq $0, $0, -3 /SKIPPED (Branch back three steps)
X"00622022", --sub $4, $3, $2 /$4 = 0x5FFF8
X"00822022", --sub $4, $4, $2 /$4 = 0x5FFEE
X"AC04000D", --sw $4, 13($0) /Saving value 0x5FFEE on address 13
X"00221820", --add $3, $1, $2 /$3 = 12
X"00432024", --and $4, $2, $3 /$4 = 1000 = 8
X"00432825", --or $5, $2, $3 /$5 = 1110 = 14
X"AC04000F", --sw $4, 15($0) /Saving value 8 on address 15
X"AC050010", --sw $5, 16($0) /Saving value 14 (= 0xE) on address 16
X"002A5020", --add $10, $1, $10 /add $1 to $ 10 and place in $10
X"1000FFFF", --beq $0, $0, -1 /Branch back one step to hold off code at this spot
X"AC050012",--sw $5, 18($0) /SHOULD NEVER HAPPEN (Saving value 14 (= 0xE) on address 18.)
X"AC050012" --sw $5, 18($0) /SHOULD NEVER HAPPEN (Saving value 14 (= 0xE) on address 18.)
);
begin
for i in 0 to TEST_INSTRS-1 loop
WriteInstructionWord(TestInstrData(i), to_unsigned(i, ADDR_WIDTH));---- WTF!!!!!!!
end loop;
end FillInstructionMemory;
-- helper procedures for filling data memory
procedure WriteDataWord(
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
address : in integer) is -- ADDRESS MUST BE A MULTIPLE OF 4!!! SINCE REGISTERS ARE ALL 32BITS. WHEN THEY WRITEBACK -SW- THEY WILL OVERWRITE THE NEXT 3 ADJACENT BYTES!!
begin
wait until falling_edge(clk);
tb_dmem_address <= std_logic_vector(to_unsigned(address, ADDR_WIDTH));
tb_dmem_data_out <= data;
wait until rising_edge(clk);
end WriteDataWord;
procedure FillDataMemory is
begin
wait until falling_edge(clk);
tb_dmem_write_enable <= "1";
-- for i in 0 to 31 loop
-- WriteDataWord(std_logic_vector(to_unsigned(31-i, 32)), i);
-- end loop;
WriteDataWord(x"00000002", 1); -- ADDRESS CHANGED TO 4
WriteDataWord(x"0000000A", 2); -- ADDRESS CHANGED TO 8
tb_dmem_write_enable <= "0";
end FillDataMemory;
-- helper procedures for checking the contents of data memory after
-- the processor has finished executing the tests
procedure CheckDataWord(
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
address : in integer) is
begin
wait until falling_edge(clk);
tb_dmem_address <= std_logic_vector(to_unsigned(address, ADDR_WIDTH));
tb_dmem_write_enable <= "0";
wait until rising_edge(clk);
wait for 0.1*clk_period;
assert data = dmem_data_in report "Expected data not found at datamem addr "
& integer'image(address) & " found = "
& integer'image(to_integer(unsigned(dmem_data_in)))
& " expected "
& integer'image(to_integer(unsigned(data)))
severity note;
assert data /= dmem_data_in report "Expected data found at datamem addr " & integer'image(address) severity note;
end CheckDataWord;
procedure CheckDataMemory is
begin
wait until processor_enable = '0';
--expected data memory contents, derived from program behavior
CheckDataWord(x"0000000C", 5);
CheckDataWord(x"0000000C", 6);
CheckDataWord(x"0000000C", 7);
CheckDataWord(x"00060000", 8);
CheckDataWord(x"00060002", 9);
CheckDataWord(x"00000001", 12);
CheckDataWord(x"0005FFEE", 13);
CheckDataWord(x"00000008", 15);
CheckDataWord(x"0000000E", 16);
-- CheckDataWord(std_logic_vector(to_unsigned(31,32)), 0);
-- CheckDataWord(std_logic_vector(to_unsigned(30,32)), 1);
-- CheckDataWord(std_logic_vector(to_unsigned(31,32)), 16);
-- CheckDataWord(std_logic_vector(to_unsigned(30,32)), 17);
-- CheckDataWord(std_logic_vector(to_unsigned(29,32)), 18);
-- CheckDataWord(std_logic_vector(to_unsigned(28,32)), 19);
-- CheckDataWord(std_logic_vector(to_unsigned(27,32)), 20);
-- CheckDataWord(std_logic_vector(to_unsigned(26,32)), 21);
-- CheckDataWord(std_logic_vector(to_unsigned(25,32)), 22);
-- CheckDataWord(std_logic_vector(to_unsigned(24,32)), 23);
-- CheckDataWord(std_logic_vector(to_unsigned(61,32)), 56);
-- CheckDataWord(std_logic_vector(to_unsigned(61,32)), 1);
end CheckDataMemory;
begin
-- hold reset state for 100 ns
reset <= '1';
wait for 100 ns;
reset <= '0';
processor_enable <= '0';
-- fill instruction and data mems with test data
FillInstructionMemory;
FillDataMemory;
wait for clk_period*10;
-- enable the processor
processor_enable <= '1';
-- execute for 200 cycles and stop
wait for clk_period*200;
processor_enable <= '0';
-- check the results
CheckDataMemory;
assert false report "end of simulation" severity failure;
wait;
end process;
END;
|
mit
|
d052b2e7ec9fc278d2eeee5e09c7b01d
| 0.634581 | 3.04065 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rb_sres_or_2.vhd
| 2 | 2,457 |
-- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_2 - syn
-- Description: rbus result or, 2 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_2;
architecture syn of rb_sres_or_2 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => rb_sres_init,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
b35319af39d335b9e1f42fc497785bf4
| 0.549451 | 3.280374 | false | false | false | false |
freecores/w11
|
rtl/vlib/genlib/clkdivce.vhd
| 2 | 3,472 |
-- $Id: clkdivce.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: clkgen - syn
-- Description: Generate usec and msec enable signals
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end clkdivce;
architecture syn of clkdivce is
type regs_type is record
ucnt : slv(CDUWIDTH-1 downto 0); -- usec clock divider counter
mcnt : slv10; -- msec clock divider counter
usec : slbit; -- usec pulse
msec : slbit; -- msec pulse
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(USECDIV-1,CDUWIDTH)),
slv(to_unsigned(MSECDIV-1,10)),
'0','0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024
report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " &
"USECDIV too large for given CDUWIDTH or MSECDIV>1024"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
n.usec := '0';
n.msec := '0';
n.ucnt := slv(unsigned(r.ucnt) - 1);
if unsigned(r.ucnt) = 0 then
n.usec := '1';
n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH));
n.mcnt := slv(unsigned(r.mcnt) - 1);
if unsigned(r.mcnt) = 0 then
n.msec := '1';
n.mcnt := slv(to_unsigned(MSECDIV-1,10));
end if;
end if;
N_REGS <= n;
CE_USEC <= r.usec;
CE_MSEC <= r.msec;
end process proc_next;
end syn;
|
gpl-2.0
|
ba8f208a52623cf1e627c42f8c5eb130
| 0.575461 | 3.705443 | false | false | false | false |
superboy0712/MIPS
|
pipeline files/IFID_register.vhd
| 1 | 954 |
library ieee;
use ieee.std_logic_1164.all;
entity IFID_register is
port(Clk, reset : in std_logic;
instruction_i, pc_i: in std_logic_vector(31 downto 0);
instruction_o, pc_o : out std_logic_vector(31 downto 0));
end IFID_register;
architecture IFID_register_a of IFID_register is
type tmp_array is array (0 to 1) of std_logic_vector(31 downto 0);
signal instruction_tmp, pc_tmp: tmp_array;
begin
process (Clk)
begin
if (reset = '1') then
instruction_tmp(0) <= (others => '0');
instruction_tmp(1) <= (others => '0');
pc_tmp(0) <= (others => '0');
pc_tmp(1) <= (others => '0');
elsif (rising_edge(clk)) then
instruction_tmp(0) <= instruction_tmp(1);
pc_tmp(0) <= pc_tmp(1);
instruction_tmp(1) <= instruction_i;
pc_tmp(1) <= pc_i;
end if;
end process;
instruction_o <= instruction_tmp(0);
pc_o <= pc_tmp(0);
end IFID_register_a;
|
mit
|
ad8976f0a7a9753d74403a69062c12fb
| 0.589099 | 2.935385 | false | false | false | false |
unhold/hdl
|
vhdl/gearbox.vhd
| 1 | 4,514 |
library ieee;
use ieee.std_logic_1164.all;
--! Higher order bits transfered first.
entity gearbox is
generic (
a_width_g : positive;
b_width_g : positive;
fifo_depth_order_g : positive);
port (
a_reset_i : in std_ulogic := '0';
a_clock_i : in std_ulogic;
a_data_i : in std_ulogic_vector(a_width_g-1 downto 0);
b_reset_i : in std_ulogic := '0';
b_clock_i : in std_ulogic;
b_data_o : out std_ulogic_vector(b_width_g-1 downto 0));
end;
library work;
use work.rtl_pack.all;
architecture rtl_fast of gearbox is
constant check_a_wider_b : boolean := check(a_width_g > b_width_g, "a>b");
signal b_fifo_read : std_ulogic;
signal b_fifo_prefill_reached : std_ulogic;
signal b_fifo_data : std_ulogic_vector(a_width_g-1 downto 0);
signal b_buffer : std_ulogic_vector(a_width_g+b_width_g-2 downto 0);
signal b_index : natural range 0 to a_width_g-1 := a_width_g - b_width_g;
begin
fifo : entity work.fifo
generic map (
depth_order_g => fifo_depth_order_g,
data_width_g => a_width_g,
prefill_g => 2**(fifo_depth_order_g-1) - 2 * b_width_g / a_width_g)
port map (
a_reset_i => a_reset_i,
a_clock_i => a_clock_i,
a_data_i => a_data_i,
b_reset_i => b_reset_i,
b_clock_i => b_clock_i,
b_read_i => b_fifo_read,
b_prefill_reached_o => b_fifo_prefill_reached,
b_data_o => b_fifo_data);
b_fifo_read <= to_stdulogic(b_index < b_width_g) and b_fifo_prefill_reached;
b_sync : process(b_reset_i, b_clock_i)
begin
if b_reset_i = '1' then
b_buffer <= (others => '-');
b_index <= a_width_g - b_width_g;
b_data_o <= (others => '0');
elsif rising_edge(b_clock_i) then
b_data_o <= b_buffer(b_index+b_width_g-1 downto b_index);
if b_fifo_read = '1' then
b_buffer(a_width_g-1 downto 0) <= b_fifo_data;
b_buffer(a_width_g+b_width_g-2 downto a_width_g) <= b_buffer(b_width_g-2 downto 0);
end if;
b_index <= (b_index - b_width_g) mod a_width_g;
end if;
end process;
end;
library work;
use work.rtl_pack.all;
architecture rtl_slow of gearbox is
constant check_b_wider_a : boolean := check(b_width_g > a_width_g, "b>a");
signal a_fifo_data : std_ulogic_vector(b_width_g-1 downto 0);
signal b_fifo_prefill_reached : std_ulogic;
signal a_fifo_write : std_ulogic := '0';
signal a_buffer : std_ulogic_vector(a_width_g+b_width_g-2 downto 0);
signal a_index : natural range 0 to b_width_g-1 := b_width_g - 1;
begin
fifo : entity work.fifo
generic map (
depth_order_g => fifo_depth_order_g,
data_width_g => b_width_g,
prefill_g => 2**(fifo_depth_order_g-1) - 2 * a_width_g / b_width_g)
port map (
a_reset_i => a_reset_i,
a_clock_i => a_clock_i,
a_write_i => a_fifo_write,
a_data_i => a_fifo_data,
b_reset_i => b_reset_i,
b_clock_i => b_clock_i,
b_read_i => b_fifo_prefill_reached,
b_prefill_reached_o => b_fifo_prefill_reached,
b_data_o => b_data_o);
a_fifo_data <= a_buffer(a_width_g+b_width_g-2 downto a_width_g-1);
a_sync : process(a_reset_i, a_clock_i)
begin
if a_reset_i = '1' then
a_fifo_write <= '0';
a_buffer <= (others => '-');
a_index <= b_width_g - 1;
elsif rising_edge(a_clock_i) then
if a_fifo_write = '1' then
a_buffer <= (others => '-');
if a_index /= b_width_g - 1 then
a_buffer(a_width_g+b_width_g-2 downto a_width_g+a_index)
<= a_buffer(a_width_g-2 downto a_width_g+a_index-b_width_g);
end if;
end if;
a_fifo_write <= to_stdulogic(a_index < a_width_g);
a_buffer(a_index+a_width_g-1 downto a_index) <= a_data_i;
a_index <= (a_index - a_width_g) mod b_width_g;
end if;
end process;
end;
library work;
use work.rtl_pack.all;
architecture rtl of gearbox is
constant check_a_nequal_b : boolean := check(a_width_g /= b_width_g, "a/=b");
begin
gen_fast : if a_width_g > b_width_g generate
gearbox_fast : entity work.gearbox(rtl_fast)
generic map (
a_width_g => a_width_g,
b_width_g => b_width_g,
fifo_depth_order_g => fifo_depth_order_g)
port map (
a_reset_i => a_reset_i,
a_clock_i => a_clock_i,
a_data_i => a_data_i,
b_reset_i => b_reset_i,
b_clock_i => b_clock_i,
b_data_o => b_data_o);
end generate;
gen_slow : if b_width_g > a_width_g generate
gearbox_slow : entity work.gearbox(rtl_slow)
generic map (
a_width_g => a_width_g,
b_width_g => b_width_g,
fifo_depth_order_g => fifo_depth_order_g)
port map (
a_reset_i => a_reset_i,
a_clock_i => a_clock_i,
a_data_i => a_data_i,
b_reset_i => b_reset_i,
b_clock_i => b_clock_i,
b_data_o => b_data_o);
end generate;
end;
|
gpl-3.0
|
37736655b49456993c87856b65f6ddc3
| 0.6214 | 2.326804 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
libraries/numeric_std_unsigned_c.vhdl
| 2 | 78,474 |
-- --------------------------------------------------------------------
-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)
--
-- This package overloaded the arithmetic operaters for
-- "STD_ULOGIC_VECTOR", and treats this vector like an
-- "UNSIGNED" from "numeric_std".
--
-- This is the updated (proposed) new package to be
-- balloted in January.
--
-- New subprograms are at the end of the package header
-- and the package body. These are to be revised, ID's
-- assigned, and voted into the ballot version.
--
-- Other changes will be noted here.
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- begin LCS-2006-130
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
-- size_res versions of these functions (Bugzilla 165)
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- end LCS-2006-130
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- size_res versions of these functions (Bugzilla 165)
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_LOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end package NUMERIC_STD_UNSIGNED;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT NUMERIC_STD_UNSIGNED package
-- This package body supplies a recommended implementation of these functions
-- Version: $Revision: 1.4 $
-- Date: $Date: 2009/08/26 19:56:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use work.numeric_std_additions.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
end package body NUMERIC_STD_UNSIGNED;
|
gpl-3.0
|
90230d032364bff7a46a7387ff563bd5
| 0.556171 | 4.005615 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/tb/tbd_rlink_direct.vhd
| 2 | 5,248 |
-- $Id: tbd_rlink_direct.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_rlink_direct - syn
-- Description: Wrapper for rlink_core to avoid records. It has a port
-- interface which will not be modified by xst synthesis
-- (no records, no generic port).
--
-- Dependencies: rlink_core
--
-- To test: rlink_core
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-11-24 92 8.1.03 I27 xc3s1000-4 143 309 0 166 s 7.64
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 148 320 0 - t 8.34
-- 2007-10-27 92 9.1 J30 xc3s1000-4 148 315 0 - t 8.34
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 302 0 162 s 7.65
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 138 306 0 - s 7.64
--
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-25 348 3.0.2 drop RL_FLUSH, add RL_MONI for rlink_core
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.2 add CP_FLUSH for rri_core, add CE_USEC
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch
-- name to switch core/serport
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
entity tbd_rlink_direct is -- rlink_core only tb design
-- generic: ATOWIDTH=5; ITOWIDTH=6
-- implements tbd_rlink_gen
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end entity tbd_rlink_direct;
architecture syn of tbd_rlink_direct is
signal RL_MONI : rl_moni_type := rl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
begin
RB_MREQ_aval <= RB_MREQ.aval;
RB_MREQ_re <= RB_MREQ.re;
RB_MREQ_we <= RB_MREQ.we;
RB_MREQ_initt<= RB_MREQ.init;
RB_MREQ_addr <= RB_MREQ.addr;
RB_MREQ_din <= RB_MREQ.din;
RB_SRES.ack <= RB_SRES_ack;
RB_SRES.busy <= RB_SRES_busy;
RB_SRES.err <= RB_SRES_err;
RB_SRES.dout <= RB_SRES_dout;
UUT : rlink_core
generic map (
ATOWIDTH => 5,
ITOWIDTH => 6)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
TXRXACT <= '0';
end syn;
|
gpl-2.0
|
9e8ae73710dafebc867c1b862826ac8d
| 0.534108 | 3.332063 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd
| 1 | 2,119 |
-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
constant sys_conf_fx2_type : string := "ic3";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
gpl-2.0
|
bde1802a34191b36fcbf72acd81da33b
| 0.652194 | 3.82491 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/pezhman_mem/example_design/pezhman_mem_prod.vhd
| 1 | 10,191 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: pezhman_mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : pezhman_mem.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 32768
-- C_READ_DEPTH_A : 32768
-- C_ADDRA_WIDTH : 15
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 32768
-- C_READ_DEPTH_B : 32768
-- C_ADDRB_WIDTH : 15
-- C_HAS_MEM_OUTPUT_REGS_A : 1
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 1
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY pezhman_mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END pezhman_mem_prod;
ARCHITECTURE xilinx OF pezhman_mem_prod IS
COMPONENT pezhman_mem_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : pezhman_mem_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
6b8fe64e6f4d31b28031e020efa3d5fa
| 0.482877 | 3.818284 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.srcs/sources_1/ip/fifo_generator_0/synth/fifo_generator_0.vhd
| 1 | 38,844 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_2;
USE fifo_generator_v13_1_2.fifo_generator_v13_1_2;
ENTITY fifo_generator_0 IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_2 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_v13_1_2,Vivado 2016.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_0_arch : ARCHITECTURE IS "fifo_generator_0,fifo_generator_v13_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_0,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0," &
"C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_" &
"FULL_THRESH_NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2," &
"C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_R" &
"USER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTA" &
"TION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WA" &
"CH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH" &
"_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL" &
"_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THR" &
"ESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_2
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_0_arch;
|
mit
|
0556451bd3ff2b867b187ec10af3b9f5
| 0.627562 | 2.910971 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/bpgenlib.vhd
| 1 | 8,643 |
-- $Id: bpgenlib.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: bpgenlib
-- Description: Generic Board/Part components
--
-- Dependencies: -
-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob
-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib
-- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus
-- 2011-11-16 426 1.0.6 now numeric_std clean
-- 2011-10-10 413 1.0.5 add sn_humanio_demu
-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
-- 2011-07-08 390 1.0.1 move in sn_(4x7segctl|humanio*) from s3boardlib
-- 2011-07-01 386 1.0 Initial version (with rs232_iob's and bp_swibtnled)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package bpgenlib is
component bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end component;
component bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end component;
component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_rs232_4l4l_iob is -- iob's for dual 4l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_CTS0_N : in slbit; -- pad-i: p0: clear to send (act. low)
O_RTS0_N : out slbit; -- pad-o: p0: request to send (act. low)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end component;
component sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
component sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
end package bpgenlib;
|
gpl-2.0
|
09ea99a9e2c33480ad3397dc02387517
| 0.507694 | 3.687287 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/bp_swibtnled.vhd
| 2 | 3,584 |
-- $Id: bp_swibtnled.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_swibtnled - syn
-- Description: Generic SWI, BTN and LED handling
--
-- Dependencies: xlib/iob_reg_i_gen
-- xlib/iob_reg_o_gen
-- genlib/debounce_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.0 Initial version, extracted from s3_humanio
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end bp_swibtnled;
architecture syn of bp_swibtnled is
signal RI_SWI : slv(SWIDTH-1 downto 0) := (others=>'0');
signal RI_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
begin
IOB_SWI : iob_reg_i_gen
generic map (DWIDTH => SWIDTH)
port map (CLK => CLK, CE => '1', DI => RI_SWI, PAD => I_SWI);
IOB_BTN : iob_reg_i_gen
generic map (DWIDTH => BWIDTH)
port map (CLK => CLK, CE => '1', DI => RI_BTN, PAD => I_BTN);
IOB_LED : iob_reg_o_gen
generic map (DWIDTH => LWIDTH)
port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
DEB: if DEBOUNCE generate
DEB_SWI : debounce_gen
generic map (
CWIDTH => 2,
CEDIV => 3,
DWIDTH => SWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE_INT => CE_MSEC,
DI => RI_SWI,
DO => SWI
);
DEB_BTN : debounce_gen
generic map (
CWIDTH => 2,
CEDIV => 3,
DWIDTH => BWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE_INT => CE_MSEC,
DI => RI_BTN,
DO => BTN
);
end generate DEB;
NODEB: if not DEBOUNCE generate
SWI <= RI_SWI;
BTN <= RI_BTN;
end generate NODEB;
end syn;
|
gpl-2.0
|
7f280ee18fb2e16fcacc56b0e4a2c096
| 0.531808 | 3.756813 | false | false | false | false |
freecores/w11
|
rtl/vlib/memlib/ram_1swar_1ar_gen.vhd
| 2 | 3,551 |
-- $Id: ram_1swar_1ar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_1ar_gen - syn
-- Description: Dual-Port RAM with with one synchronous write and two
-- asynchronius read ports (as distributed RAM).
-- The code is inspired by Xilinx example rams_09.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2010-06-03 ise 11.4 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm Comments
-- 4 16 - 32 16*RAM16X1D
-- 5 16 34 64 32*RAM16X1D
-- 6 16 68 128 64*RAM16X1D, 32*MUXF5
-- 7 16 136 256 128*RAM16X1D, 64*MUXF5, 32*MUXF6
-- 8 16 292 512 256*RAM16X1D,144*MUXF5, 64*MUXF6, 32*MUXF7
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- {same results as above for AW=4 and 6}
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_1swar_1ar_gen;
architecture syn of ram_1swar_1ar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDRA))) <= DI;
end if;
end if;
end process proc_clk;
DOA <= RAM(to_integer(unsigned(ADDRA)));
DOB <= RAM(to_integer(unsigned(ADDRB)));
end syn;
|
gpl-2.0
|
b151406eab50c96b9ac24325073a46ac
| 0.576739 | 3.353163 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/rlink_mon.vhd
| 1 | 4,763 |
-- $Id: rlink_mon.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon - sim
-- Description: rlink monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.2 now numeric_std clean
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rlinklib.all;
entity rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon;
architecture sim of rlink_mon is
begin
assert DWIDTH=8 or DWIDTH=9
report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
proc_moni: process
variable oline : line;
variable nbusy : integer := 0;
variable nhold : integer := 0;
procedure write_val(L: inout line;
data: in slv(DWIDTH-1 downto 0);
nwait: in integer;
txt1: in string;
txt2: in string) is
variable data9 : slv9 := (others=>'0');
begin
writetimestamp(L, CLK_CYCLE, txt1);
if DWIDTH = 9 then
write(L, data(data'left), right, 1);
else
write(L, string'(" "));
end if;
write(L, data(7 downto 0), right, 9);
if nwait > 0 then
write(L, txt2);
write(L, nwait);
end if;
if DWIDTH=9 and data(data'left)='1' then
-- a copy to data9 needed to allow following case construct
-- using data directly gives a 'subtype is not locally static' error
data9 := (others=>'0');
data9(data'range) := data;
write(L, string'(" comma"));
case data9 is
when c_rlink_dat_idle => write(L, string'(" idle"));
when c_rlink_dat_sop => write(L, string'(" sop"));
when c_rlink_dat_eop => write(L, string'(" eop"));
when c_rlink_dat_nak => write(L, string'(" nak"));
when c_rlink_dat_attn => write(L, string'(" attn"));
when others => null;
end case;
end if;
writeline(output, L);
end procedure write_val;
begin
loop
if ENA='0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RL_ENA = '1' then
if RL_BUSY = '1' then
nbusy := nbusy + 1;
else
write_val(oline, RL_DI, nbusy, ": rlrx ", " nbusy=");
nbusy := 0;
end if;
else
nbusy := 0;
end if;
if RL_VAL = '1' then
if RL_HOLD = '1' then
nhold := nhold + 1;
else
write_val(oline, RL_DO, nhold, ": rltx ", " nhold=");
nhold := 0;
end if;
else
nhold := 0;
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
f630ae66253f1f980d46eed150b4f146
| 0.535377 | 3.695112 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/3ba4d894d8c459ff/vio_0_sim_netlist.vhdl
| 1 | 538,818 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:32:27 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.vhdl
-- Design : vio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
port (
s_drdy_i : out STD_LOGIC;
\wr_en_reg[4]_0\ : out STD_LOGIC;
\wr_en_reg[4]_1\ : out STD_LOGIC;
\wr_en_reg[4]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_do_i : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_rst_o : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
\Bus_Data_out_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
signal Hold_probe_in : STD_LOGIC;
signal clear_int : STD_LOGIC;
signal committ_int : STD_LOGIC;
signal \data_info_probe_in__67\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_cnt_rst : STD_LOGIC;
signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rd_en_p1 : STD_LOGIC;
signal rd_en_p2 : STD_LOGIC;
signal wr_control_reg : STD_LOGIC;
signal \wr_en[2]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[2]_i_2_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_6_n_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_1\ : STD_LOGIC;
signal \^wr_en_reg[4]_2\ : STD_LOGIC;
signal wr_probe_out_modified : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_8_p1 : STD_LOGIC;
signal xsdb_addr_8_p2 : STD_LOGIC;
signal xsdb_drdy_i_1_n_0 : STD_LOGIC;
signal xsdb_rd : STD_LOGIC;
signal xsdb_wr : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Bus_data_out[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Bus_data_out[13]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[15]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wr_en[2]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \wr_en[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wr_en[4]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair14";
begin
\wr_en_reg[4]_0\ <= \^wr_en_reg[4]_0\;
\wr_en_reg[4]_1\ <= \^wr_en_reg[4]_1\;
\wr_en_reg[4]_2\ <= \^wr_en_reg[4]_2\;
\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF00AF000FC000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(0),
I1 => probe_out_modified(0),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => committ_int,
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(0)
);
\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(10),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(10),
O => \data_info_probe_in__67\(10)
);
\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(11),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(11),
O => \data_info_probe_in__67\(11)
);
\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(12),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(12)
);
\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(13),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(13)
);
\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(14),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(14)
);
\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(15),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(15)
);
\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0000FC0A00000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(1),
I1 => probe_out_modified(1),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => xsdb_addr_2_0_p2(0),
I5 => clear_int,
O => \data_info_probe_in__67\(1)
);
\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A000000F00CFCF"
)
port map (
I0 => \Bus_Data_out_reg[11]\(2),
I1 => probe_out_modified(2),
I2 => xsdb_addr_2_0_p2(2),
I3 => int_cnt_rst,
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(2)
);
\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(3),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(3),
O => \data_info_probe_in__67\(3)
);
\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(4),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(4),
O => \data_info_probe_in__67\(4)
);
\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(5),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(5),
O => \data_info_probe_in__67\(5)
);
\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(6),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(6),
O => \data_info_probe_in__67\(6)
);
\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(7),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(7),
O => \data_info_probe_in__67\(7)
);
\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(8),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(8),
O => \data_info_probe_in__67\(8)
);
\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(9),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(9),
O => \data_info_probe_in__67\(9)
);
\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(0),
Q => s_do_i(0),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(10),
Q => s_do_i(10),
R => xsdb_addr_8_p2
);
\bus_data_out_reg[11]_RnM\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(11),
Q => s_do_i(11),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(12),
Q => s_do_i(12),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(13),
Q => s_do_i(13),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(14),
Q => s_do_i(14),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(15),
Q => s_do_i(15),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(1),
Q => s_do_i(1),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(2),
Q => s_do_i(2),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(3),
Q => s_do_i(3),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(4),
Q => s_do_i(4),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(5),
Q => s_do_i(5),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(6),
Q => s_do_i(6),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(7),
Q => s_do_i(7),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(8),
Q => s_do_i(8),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(9),
Q => s_do_i(9),
R => xsdb_addr_8_p2
);
Hold_probe_in_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(3),
Q => Hold_probe_in,
R => s_rst_o
);
clear_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(1),
Q => clear_int,
R => s_rst_o
);
committ_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(0),
Q => committ_int,
R => s_rst_o
);
int_cnt_rst_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(2),
Q => int_cnt_rst,
R => s_rst_o
);
\probe_in_reg[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Hold_probe_in,
O => E(0)
);
\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(0),
Q => probe_out_modified(0),
R => clear_int
);
\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(10),
Q => probe_out_modified(10),
R => clear_int
);
\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(11),
Q => probe_out_modified(11),
R => clear_int
);
\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(12),
Q => probe_out_modified(12),
R => clear_int
);
\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(13),
Q => probe_out_modified(13),
R => clear_int
);
\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(14),
Q => probe_out_modified(14),
R => clear_int
);
\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(15),
Q => probe_out_modified(15),
R => clear_int
);
\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(1),
Q => probe_out_modified(1),
R => clear_int
);
\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(2),
Q => probe_out_modified(2),
R => clear_int
);
\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(3),
Q => probe_out_modified(3),
R => clear_int
);
\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(4),
Q => probe_out_modified(4),
R => clear_int
);
\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(5),
Q => probe_out_modified(5),
R => clear_int
);
\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(6),
Q => probe_out_modified(6),
R => clear_int
);
\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(7),
Q => probe_out_modified(7),
R => clear_int
);
\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(8),
Q => probe_out_modified(8),
R => clear_int
);
\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(9),
Q => probe_out_modified(9),
R => clear_int
);
rd_en_p1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_rd
);
rd_en_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_rd,
Q => rd_en_p1,
R => s_rst_o
);
rd_en_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => rd_en_p1,
Q => rd_en_p2,
R => s_rst_o
);
\wr_en[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => xsdb_wr,
I1 => s_daddr_o(2),
I2 => \^wr_en_reg[4]_0\,
I3 => \^wr_en_reg[4]_2\,
I4 => \^wr_en_reg[4]_1\,
I5 => \wr_en[2]_i_2_n_0\,
O => \wr_en[2]_i_1_n_0\
);
\wr_en[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[2]_i_2_n_0\
);
\wr_en[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => xsdb_wr,
I1 => \^wr_en_reg[4]_0\,
I2 => \^wr_en_reg[4]_2\,
I3 => \^wr_en_reg[4]_1\,
I4 => s_daddr_o(2),
I5 => \wr_en[4]_i_6_n_0\,
O => \wr_en[4]_i_1_n_0\
);
\wr_en[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_wr
);
\wr_en[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_daddr_o(15),
I1 => s_daddr_o(16),
I2 => s_daddr_o(13),
I3 => s_daddr_o(14),
I4 => s_daddr_o(4),
I5 => s_daddr_o(3),
O => \^wr_en_reg[4]_0\
);
\wr_en[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(6),
I1 => s_daddr_o(5),
I2 => s_daddr_o(8),
I3 => s_daddr_o(7),
O => \^wr_en_reg[4]_2\
);
\wr_en[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(10),
I1 => s_daddr_o(9),
I2 => s_daddr_o(12),
I3 => s_daddr_o(11),
O => \^wr_en_reg[4]_1\
);
\wr_en[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[4]_i_6_n_0\
);
\wr_en_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[2]_i_1_n_0\,
Q => wr_control_reg,
R => '0'
);
\wr_en_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[4]_i_1_n_0\,
Q => wr_probe_out_modified,
R => '0'
);
\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(0),
Q => xsdb_addr_2_0_p1(0),
R => '0'
);
\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(1),
Q => xsdb_addr_2_0_p1(1),
R => '0'
);
\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(2),
Q => xsdb_addr_2_0_p1(2),
R => '0'
);
\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(0),
Q => xsdb_addr_2_0_p2(0),
R => '0'
);
\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(1),
Q => xsdb_addr_2_0_p2(1),
R => '0'
);
\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(2),
Q => xsdb_addr_2_0_p2(2),
R => '0'
);
xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(8),
Q => xsdb_addr_8_p1,
R => '0'
);
xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_8_p1,
Q => xsdb_addr_8_p2,
R => '0'
);
xsdb_drdy_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => rd_en_p2,
O => xsdb_drdy_i_1_n_0
);
xsdb_drdy_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_drdy_i_1_n_0,
Q => s_drdy_i,
R => s_rst_o
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC;
\wr_en[4]_i_3\ : in STD_LOGIC;
\wr_en[4]_i_4\ : in STD_LOGIC;
\wr_en[4]_i_5\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
s_rst_o : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC;
signal Read_int : STD_LOGIC;
signal Read_int_i_2_n_0 : STD_LOGIC;
signal data_int_sync1 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of data_int_sync1 : signal is "true";
signal data_int_sync2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg of data_int_sync2 : signal is "true";
signal \dn_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[3]\ : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal probe_in_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true;
signal read_done : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of read_done : signal is "200";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of read_done : signal is "found";
signal read_done_i_1_n_0 : STD_LOGIC;
signal \up_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \up_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[1]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[2]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[3]\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes";
attribute RTL_MAX_FANOUT of read_done_reg : label is "found";
begin
\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(0),
Q => Q(0),
R => '0'
);
\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_in,
Q => Q(10),
R => '0'
);
\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[3]\,
Q => Q(11),
R => '0'
);
\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(1),
Q => Q(1),
R => '0'
);
\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(2),
Q => Q(2),
R => '0'
);
\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(3),
Q => Q(3),
R => '0'
);
\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[0]\,
Q => Q(4),
R => '0'
);
\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[1]\,
Q => Q(5),
R => '0'
);
\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[2]\,
Q => Q(6),
R => '0'
);
\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[3]\,
Q => Q(7),
R => '0'
);
\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[0]\,
Q => Q(8),
R => '0'
);
\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_6_in,
Q => Q(9),
R => '0'
);
Read_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => Read_int_i_2_n_0,
I1 => \wr_en[4]_i_3\,
I2 => \wr_en[4]_i_4\,
I3 => \wr_en[4]_i_5\,
O => \DECODER_INST/rd_en_int_7\
);
Read_int_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
I2 => s_daddr_o(2),
I3 => s_dwe_o,
I4 => s_den_o,
O => Read_int_i_2_n_0
);
Read_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \DECODER_INST/rd_en_int_7\,
Q => Read_int,
R => '0'
);
\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(0),
Q => data_int_sync1(0),
R => '0'
);
\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(1),
Q => data_int_sync1(1),
R => '0'
);
\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(2),
Q => data_int_sync1(2),
R => '0'
);
\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(3),
Q => data_int_sync1(3),
R => '0'
);
\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(0),
Q => data_int_sync2(0),
R => '0'
);
\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(1),
Q => data_int_sync2(1),
R => '0'
);
\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(2),
Q => data_int_sync2(2),
R => '0'
);
\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(3),
Q => data_int_sync2(3),
R => '0'
);
\dn_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[0]\,
I1 => data_int_sync1(0),
I2 => data_int_sync2(0),
O => \dn_activity[0]_i_1_n_0\
);
\dn_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_6_in,
I1 => data_int_sync1(1),
I2 => data_int_sync2(1),
O => \dn_activity[1]_i_1_n_0\
);
\dn_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_9_in,
I1 => data_int_sync1(2),
I2 => data_int_sync2(2),
O => \dn_activity[2]_i_1_n_0\
);
\dn_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[3]\,
I1 => data_int_sync1(3),
I2 => data_int_sync2(3),
O => \dn_activity[3]_i_1_n_0\
);
\dn_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[0]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[0]\,
R => read_done
);
\dn_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[1]_i_1_n_0\,
Q => p_6_in,
R => read_done
);
\dn_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[2]_i_1_n_0\,
Q => p_9_in,
R => read_done
);
\dn_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[3]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[3]\,
R => read_done
);
\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(0),
Q => probe_in_reg(0),
R => '0'
);
\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(1),
Q => probe_in_reg(1),
R => '0'
);
\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(2),
Q => probe_in_reg(2),
R => '0'
);
\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(3),
Q => probe_in_reg(3),
R => '0'
);
read_done_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Read_int,
I1 => read_done,
I2 => s_rst_o,
O => read_done_i_1_n_0
);
read_done_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => read_done_i_1_n_0,
Q => read_done,
R => '0'
);
\up_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[0]\,
I1 => data_int_sync2(0),
I2 => data_int_sync1(0),
O => \up_activity[0]_i_1_n_0\
);
\up_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[1]\,
I1 => data_int_sync2(1),
I2 => data_int_sync1(1),
O => \up_activity[1]_i_1_n_0\
);
\up_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[2]\,
I1 => data_int_sync2(2),
I2 => data_int_sync1(2),
O => \up_activity[2]_i_1_n_0\
);
\up_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[3]\,
I1 => data_int_sync2(3),
I2 => data_int_sync1(3),
O => \up_activity[3]_i_1_n_0\
);
\up_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[0]_i_1_n_0\,
Q => \up_activity_reg_n_0_[0]\,
R => read_done
);
\up_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[1]_i_1_n_0\,
Q => \up_activity_reg_n_0_[1]\,
R => read_done
);
\up_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[2]_i_1_n_0\,
Q => \up_activity_reg_n_0_[2]\,
R => read_done
);
\up_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[3]_i_1_n_0\,
Q => \up_activity_reg_n_0_[3]\,
R => read_done
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
port (
s_rst_o : out STD_LOGIC;
s_dclk_o : out STD_LOGIC;
s_den_o : out STD_LOGIC;
s_dwe_o : out STD_LOGIC;
s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
s_drdy_i : in STD_LOGIC
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2013;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "kintex7";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
signal reg_do : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \reg_do[10]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[15]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[2]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[3]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[6]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[7]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[9]_i_1_n_0\ : STD_LOGIC;
signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
signal reg_drdy : STD_LOGIC;
signal reg_drdy_i_1_n_0 : STD_LOGIC;
signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
signal reg_test0 : STD_LOGIC;
signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \reg_do[10]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \reg_do[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair8";
begin
\^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4);
s_dclk_o <= \^sl_iport_i\(1);
s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21);
s_dwe_o <= \^sl_iport_i\(3);
s_rst_o <= \^sl_iport_i\(0);
\reg_do[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAFFFFAAAAAAAA"
)
port map (
I0 => \reg_do[5]_i_2_n_0\,
I1 => \^sl_iport_i\(4),
I2 => reg_test(0),
I3 => \^sl_iport_i\(6),
I4 => \^sl_iport_i\(5),
I5 => \^sl_iport_i\(8),
O => reg_do(0)
);
\reg_do[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \reg_do[8]_i_2_n_0\,
I2 => \^sl_iport_i\(4),
O => \reg_do[10]_i_1_n_0\
);
\reg_do[10]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(10),
O => \reg_do[10]_i_2_n_0\
);
\reg_do[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
O => \reg_do[15]_i_1_n_0\
);
\reg_do[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20220000"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \^sl_iport_i\(4),
I2 => reg_test(1),
I3 => \^sl_iport_i\(6),
I4 => \reg_do[1]_i_2_n_0\,
O => reg_do(1)
);
\reg_do[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \^sl_iport_i\(8),
I1 => \^sl_iport_i\(10),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(7),
I4 => \^sl_iport_i\(9),
O => \reg_do[1]_i_2_n_0\
);
\reg_do[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(2),
O => \reg_do[2]_i_1_n_0\
);
\reg_do[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(3),
O => \reg_do[3]_i_1_n_0\
);
\reg_do[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(4),
O => \reg_do[4]_i_1_n_0\
);
\reg_do[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800044"
)
port map (
I0 => \^sl_iport_i\(6),
I1 => \^sl_iport_i\(8),
I2 => reg_test(5),
I3 => \^sl_iport_i\(4),
I4 => \^sl_iport_i\(5),
I5 => \reg_do[5]_i_2_n_0\,
O => reg_do(5)
);
\reg_do[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFFFFC"
)
port map (
I0 => \^sl_iport_i\(7),
I1 => \^sl_iport_i\(8),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(9),
O => \reg_do[5]_i_2_n_0\
);
\reg_do[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(6),
O => \reg_do[6]_i_1_n_0\
);
\reg_do[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(7),
O => \reg_do[7]_i_1_n_0\
);
\reg_do[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F00"
)
port map (
I0 => reg_test(8),
I1 => \^sl_iport_i\(4),
I2 => \^sl_iport_i\(5),
I3 => \reg_do[8]_i_2_n_0\,
O => reg_do(8)
);
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \^sl_iport_i\(9),
I1 => \^sl_iport_i\(7),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(8),
I5 => \^sl_iport_i\(6),
O => \reg_do[8]_i_2_n_0\
);
\reg_do[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C008000"
)
port map (
I0 => reg_test(9),
I1 => \reg_do[1]_i_2_n_0\,
I2 => \^sl_iport_i\(6),
I3 => \^sl_iport_i\(5),
I4 => \^sl_iport_i\(4),
O => \reg_do[9]_i_1_n_0\
);
\reg_do_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(0),
Q => \reg_do_reg_n_0_[0]\,
R => '0'
);
\reg_do_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[10]_i_2_n_0\,
Q => \reg_do_reg_n_0_[10]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(11),
Q => \reg_do_reg_n_0_[11]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(12),
Q => \reg_do_reg_n_0_[12]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(13),
Q => \reg_do_reg_n_0_[13]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(14),
Q => \reg_do_reg_n_0_[14]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(15),
Q => \reg_do_reg_n_0_[15]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(1),
Q => \reg_do_reg_n_0_[1]\,
R => '0'
);
\reg_do_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[2]_i_1_n_0\,
Q => \reg_do_reg_n_0_[2]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[3]_i_1_n_0\,
Q => \reg_do_reg_n_0_[3]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[4]_i_1_n_0\,
Q => \reg_do_reg_n_0_[4]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(5),
Q => \reg_do_reg_n_0_[5]\,
R => '0'
);
\reg_do_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[6]_i_1_n_0\,
Q => \reg_do_reg_n_0_[6]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[7]_i_1_n_0\,
Q => \reg_do_reg_n_0_[7]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(8),
Q => \reg_do_reg_n_0_[8]\,
R => '0'
);
\reg_do_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[9]_i_1_n_0\,
Q => \reg_do_reg_n_0_[9]\,
S => \reg_do[10]_i_1_n_0\
);
reg_drdy_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => s_den_o_INST_0_i_1_n_0,
I2 => \^sl_iport_i\(12),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(14),
I5 => \^sl_iport_i\(0),
O => reg_drdy_i_1_n_0
);
reg_drdy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_drdy_i_1_n_0,
Q => reg_drdy,
R => '0'
);
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(3),
I1 => \^sl_iport_i\(2),
I2 => \^sl_iport_i\(14),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(12),
I5 => s_den_o_INST_0_i_1_n_0,
O => reg_test0
);
\reg_test_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(21),
Q => reg_test(0),
R => '0'
);
\reg_test_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(31),
Q => reg_test(10),
R => '0'
);
\reg_test_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(32),
Q => reg_test(11),
R => '0'
);
\reg_test_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(33),
Q => reg_test(12),
R => '0'
);
\reg_test_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(34),
Q => reg_test(13),
R => '0'
);
\reg_test_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(35),
Q => reg_test(14),
R => '0'
);
\reg_test_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(36),
Q => reg_test(15),
R => '0'
);
\reg_test_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(22),
Q => reg_test(1),
R => '0'
);
\reg_test_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(23),
Q => reg_test(2),
R => '0'
);
\reg_test_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(24),
Q => reg_test(3),
R => '0'
);
\reg_test_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(25),
Q => reg_test(4),
R => '0'
);
\reg_test_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(26),
Q => reg_test(5),
R => '0'
);
\reg_test_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(27),
Q => reg_test(6),
R => '0'
);
\reg_test_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(28),
Q => reg_test(7),
R => '0'
);
\reg_test_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(29),
Q => reg_test(8),
R => '0'
);
\reg_test_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(30),
Q => reg_test(9),
R => '0'
);
s_den_o_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAAAAAA"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => \^sl_iport_i\(14),
I2 => \^sl_iport_i\(13),
I3 => \^sl_iport_i\(12),
I4 => s_den_o_INST_0_i_1_n_0,
O => s_den_o
);
s_den_o_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(15),
I1 => \^sl_iport_i\(16),
I2 => \^sl_iport_i\(17),
I3 => \^sl_iport_i\(18),
I4 => \^sl_iport_i\(20),
I5 => \^sl_iport_i\(19),
O => s_den_o_INST_0_i_1_n_0
);
\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_drdy_i,
I1 => reg_drdy,
O => sl_oport_o(0)
);
\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[9]\,
I1 => s_do_i(9),
I2 => reg_drdy,
O => sl_oport_o(10)
);
\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[10]\,
I1 => s_do_i(10),
I2 => reg_drdy,
O => sl_oport_o(11)
);
\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[11]\,
I1 => s_do_i(11),
I2 => reg_drdy,
O => sl_oport_o(12)
);
\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[12]\,
I1 => s_do_i(12),
I2 => reg_drdy,
O => sl_oport_o(13)
);
\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[13]\,
I1 => s_do_i(13),
I2 => reg_drdy,
O => sl_oport_o(14)
);
\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[14]\,
I1 => s_do_i(14),
I2 => reg_drdy,
O => sl_oport_o(15)
);
\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[15]\,
I1 => s_do_i(15),
I2 => reg_drdy,
O => sl_oport_o(16)
);
\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[0]\,
I1 => s_do_i(0),
I2 => reg_drdy,
O => sl_oport_o(1)
);
\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[1]\,
I1 => s_do_i(1),
I2 => reg_drdy,
O => sl_oport_o(2)
);
\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[2]\,
I1 => s_do_i(2),
I2 => reg_drdy,
O => sl_oport_o(3)
);
\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[3]\,
I1 => s_do_i(3),
I2 => reg_drdy,
O => sl_oport_o(4)
);
\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[4]\,
I1 => s_do_i(4),
I2 => reg_drdy,
O => sl_oport_o(5)
);
\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[5]\,
I1 => s_do_i(5),
I2 => reg_drdy,
O => sl_oport_o(6)
);
\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[6]\,
I1 => s_do_i(6),
I2 => reg_drdy,
O => sl_oport_o(7)
);
\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[7]\,
I1 => s_do_i(7),
I2 => reg_drdy,
O => sl_oport_o(8)
);
\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[8]\,
I1 => s_do_i(8),
I2 => reg_drdy,
O => sl_oport_o(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 );
sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 33;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
signal \<const0>\ : STD_LOGIC;
signal Bus_Data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal DECODER_INST_n_1 : STD_LOGIC;
signal DECODER_INST_n_2 : STD_LOGIC;
signal DECODER_INST_n_3 : STD_LOGIC;
signal DECODER_INST_n_4 : STD_LOGIC;
signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
signal bus_clk : STD_LOGIC;
attribute DONT_TOUCH_boolean : boolean;
attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true;
signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC;
signal bus_den : STD_LOGIC;
signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_drdy : STD_LOGIC;
signal bus_dwe : STD_LOGIC;
signal bus_rst : STD_LOGIC;
signal p_0_in : STD_LOGIC;
attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2;
attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0;
attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2;
attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1;
attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013;
attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1;
attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0;
attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7";
attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33;
attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true;
begin
probe_out0(0) <= \<const0>\;
probe_out1(0) <= \<const0>\;
probe_out10(0) <= \<const0>\;
probe_out100(0) <= \<const0>\;
probe_out101(0) <= \<const0>\;
probe_out102(0) <= \<const0>\;
probe_out103(0) <= \<const0>\;
probe_out104(0) <= \<const0>\;
probe_out105(0) <= \<const0>\;
probe_out106(0) <= \<const0>\;
probe_out107(0) <= \<const0>\;
probe_out108(0) <= \<const0>\;
probe_out109(0) <= \<const0>\;
probe_out11(0) <= \<const0>\;
probe_out110(0) <= \<const0>\;
probe_out111(0) <= \<const0>\;
probe_out112(0) <= \<const0>\;
probe_out113(0) <= \<const0>\;
probe_out114(0) <= \<const0>\;
probe_out115(0) <= \<const0>\;
probe_out116(0) <= \<const0>\;
probe_out117(0) <= \<const0>\;
probe_out118(0) <= \<const0>\;
probe_out119(0) <= \<const0>\;
probe_out12(0) <= \<const0>\;
probe_out120(0) <= \<const0>\;
probe_out121(0) <= \<const0>\;
probe_out122(0) <= \<const0>\;
probe_out123(0) <= \<const0>\;
probe_out124(0) <= \<const0>\;
probe_out125(0) <= \<const0>\;
probe_out126(0) <= \<const0>\;
probe_out127(0) <= \<const0>\;
probe_out128(0) <= \<const0>\;
probe_out129(0) <= \<const0>\;
probe_out13(0) <= \<const0>\;
probe_out130(0) <= \<const0>\;
probe_out131(0) <= \<const0>\;
probe_out132(0) <= \<const0>\;
probe_out133(0) <= \<const0>\;
probe_out134(0) <= \<const0>\;
probe_out135(0) <= \<const0>\;
probe_out136(0) <= \<const0>\;
probe_out137(0) <= \<const0>\;
probe_out138(0) <= \<const0>\;
probe_out139(0) <= \<const0>\;
probe_out14(0) <= \<const0>\;
probe_out140(0) <= \<const0>\;
probe_out141(0) <= \<const0>\;
probe_out142(0) <= \<const0>\;
probe_out143(0) <= \<const0>\;
probe_out144(0) <= \<const0>\;
probe_out145(0) <= \<const0>\;
probe_out146(0) <= \<const0>\;
probe_out147(0) <= \<const0>\;
probe_out148(0) <= \<const0>\;
probe_out149(0) <= \<const0>\;
probe_out15(0) <= \<const0>\;
probe_out150(0) <= \<const0>\;
probe_out151(0) <= \<const0>\;
probe_out152(0) <= \<const0>\;
probe_out153(0) <= \<const0>\;
probe_out154(0) <= \<const0>\;
probe_out155(0) <= \<const0>\;
probe_out156(0) <= \<const0>\;
probe_out157(0) <= \<const0>\;
probe_out158(0) <= \<const0>\;
probe_out159(0) <= \<const0>\;
probe_out16(0) <= \<const0>\;
probe_out160(0) <= \<const0>\;
probe_out161(0) <= \<const0>\;
probe_out162(0) <= \<const0>\;
probe_out163(0) <= \<const0>\;
probe_out164(0) <= \<const0>\;
probe_out165(0) <= \<const0>\;
probe_out166(0) <= \<const0>\;
probe_out167(0) <= \<const0>\;
probe_out168(0) <= \<const0>\;
probe_out169(0) <= \<const0>\;
probe_out17(0) <= \<const0>\;
probe_out170(0) <= \<const0>\;
probe_out171(0) <= \<const0>\;
probe_out172(0) <= \<const0>\;
probe_out173(0) <= \<const0>\;
probe_out174(0) <= \<const0>\;
probe_out175(0) <= \<const0>\;
probe_out176(0) <= \<const0>\;
probe_out177(0) <= \<const0>\;
probe_out178(0) <= \<const0>\;
probe_out179(0) <= \<const0>\;
probe_out18(0) <= \<const0>\;
probe_out180(0) <= \<const0>\;
probe_out181(0) <= \<const0>\;
probe_out182(0) <= \<const0>\;
probe_out183(0) <= \<const0>\;
probe_out184(0) <= \<const0>\;
probe_out185(0) <= \<const0>\;
probe_out186(0) <= \<const0>\;
probe_out187(0) <= \<const0>\;
probe_out188(0) <= \<const0>\;
probe_out189(0) <= \<const0>\;
probe_out19(0) <= \<const0>\;
probe_out190(0) <= \<const0>\;
probe_out191(0) <= \<const0>\;
probe_out192(0) <= \<const0>\;
probe_out193(0) <= \<const0>\;
probe_out194(0) <= \<const0>\;
probe_out195(0) <= \<const0>\;
probe_out196(0) <= \<const0>\;
probe_out197(0) <= \<const0>\;
probe_out198(0) <= \<const0>\;
probe_out199(0) <= \<const0>\;
probe_out2(0) <= \<const0>\;
probe_out20(0) <= \<const0>\;
probe_out200(0) <= \<const0>\;
probe_out201(0) <= \<const0>\;
probe_out202(0) <= \<const0>\;
probe_out203(0) <= \<const0>\;
probe_out204(0) <= \<const0>\;
probe_out205(0) <= \<const0>\;
probe_out206(0) <= \<const0>\;
probe_out207(0) <= \<const0>\;
probe_out208(0) <= \<const0>\;
probe_out209(0) <= \<const0>\;
probe_out21(0) <= \<const0>\;
probe_out210(0) <= \<const0>\;
probe_out211(0) <= \<const0>\;
probe_out212(0) <= \<const0>\;
probe_out213(0) <= \<const0>\;
probe_out214(0) <= \<const0>\;
probe_out215(0) <= \<const0>\;
probe_out216(0) <= \<const0>\;
probe_out217(0) <= \<const0>\;
probe_out218(0) <= \<const0>\;
probe_out219(0) <= \<const0>\;
probe_out22(0) <= \<const0>\;
probe_out220(0) <= \<const0>\;
probe_out221(0) <= \<const0>\;
probe_out222(0) <= \<const0>\;
probe_out223(0) <= \<const0>\;
probe_out224(0) <= \<const0>\;
probe_out225(0) <= \<const0>\;
probe_out226(0) <= \<const0>\;
probe_out227(0) <= \<const0>\;
probe_out228(0) <= \<const0>\;
probe_out229(0) <= \<const0>\;
probe_out23(0) <= \<const0>\;
probe_out230(0) <= \<const0>\;
probe_out231(0) <= \<const0>\;
probe_out232(0) <= \<const0>\;
probe_out233(0) <= \<const0>\;
probe_out234(0) <= \<const0>\;
probe_out235(0) <= \<const0>\;
probe_out236(0) <= \<const0>\;
probe_out237(0) <= \<const0>\;
probe_out238(0) <= \<const0>\;
probe_out239(0) <= \<const0>\;
probe_out24(0) <= \<const0>\;
probe_out240(0) <= \<const0>\;
probe_out241(0) <= \<const0>\;
probe_out242(0) <= \<const0>\;
probe_out243(0) <= \<const0>\;
probe_out244(0) <= \<const0>\;
probe_out245(0) <= \<const0>\;
probe_out246(0) <= \<const0>\;
probe_out247(0) <= \<const0>\;
probe_out248(0) <= \<const0>\;
probe_out249(0) <= \<const0>\;
probe_out25(0) <= \<const0>\;
probe_out250(0) <= \<const0>\;
probe_out251(0) <= \<const0>\;
probe_out252(0) <= \<const0>\;
probe_out253(0) <= \<const0>\;
probe_out254(0) <= \<const0>\;
probe_out255(0) <= \<const0>\;
probe_out26(0) <= \<const0>\;
probe_out27(0) <= \<const0>\;
probe_out28(0) <= \<const0>\;
probe_out29(0) <= \<const0>\;
probe_out3(0) <= \<const0>\;
probe_out30(0) <= \<const0>\;
probe_out31(0) <= \<const0>\;
probe_out32(0) <= \<const0>\;
probe_out33(0) <= \<const0>\;
probe_out34(0) <= \<const0>\;
probe_out35(0) <= \<const0>\;
probe_out36(0) <= \<const0>\;
probe_out37(0) <= \<const0>\;
probe_out38(0) <= \<const0>\;
probe_out39(0) <= \<const0>\;
probe_out4(0) <= \<const0>\;
probe_out40(0) <= \<const0>\;
probe_out41(0) <= \<const0>\;
probe_out42(0) <= \<const0>\;
probe_out43(0) <= \<const0>\;
probe_out44(0) <= \<const0>\;
probe_out45(0) <= \<const0>\;
probe_out46(0) <= \<const0>\;
probe_out47(0) <= \<const0>\;
probe_out48(0) <= \<const0>\;
probe_out49(0) <= \<const0>\;
probe_out5(0) <= \<const0>\;
probe_out50(0) <= \<const0>\;
probe_out51(0) <= \<const0>\;
probe_out52(0) <= \<const0>\;
probe_out53(0) <= \<const0>\;
probe_out54(0) <= \<const0>\;
probe_out55(0) <= \<const0>\;
probe_out56(0) <= \<const0>\;
probe_out57(0) <= \<const0>\;
probe_out58(0) <= \<const0>\;
probe_out59(0) <= \<const0>\;
probe_out6(0) <= \<const0>\;
probe_out60(0) <= \<const0>\;
probe_out61(0) <= \<const0>\;
probe_out62(0) <= \<const0>\;
probe_out63(0) <= \<const0>\;
probe_out64(0) <= \<const0>\;
probe_out65(0) <= \<const0>\;
probe_out66(0) <= \<const0>\;
probe_out67(0) <= \<const0>\;
probe_out68(0) <= \<const0>\;
probe_out69(0) <= \<const0>\;
probe_out7(0) <= \<const0>\;
probe_out70(0) <= \<const0>\;
probe_out71(0) <= \<const0>\;
probe_out72(0) <= \<const0>\;
probe_out73(0) <= \<const0>\;
probe_out74(0) <= \<const0>\;
probe_out75(0) <= \<const0>\;
probe_out76(0) <= \<const0>\;
probe_out77(0) <= \<const0>\;
probe_out78(0) <= \<const0>\;
probe_out79(0) <= \<const0>\;
probe_out8(0) <= \<const0>\;
probe_out80(0) <= \<const0>\;
probe_out81(0) <= \<const0>\;
probe_out82(0) <= \<const0>\;
probe_out83(0) <= \<const0>\;
probe_out84(0) <= \<const0>\;
probe_out85(0) <= \<const0>\;
probe_out86(0) <= \<const0>\;
probe_out87(0) <= \<const0>\;
probe_out88(0) <= \<const0>\;
probe_out89(0) <= \<const0>\;
probe_out9(0) <= \<const0>\;
probe_out90(0) <= \<const0>\;
probe_out91(0) <= \<const0>\;
probe_out92(0) <= \<const0>\;
probe_out93(0) <= \<const0>\;
probe_out94(0) <= \<const0>\;
probe_out95(0) <= \<const0>\;
probe_out96(0) <= \<const0>\;
probe_out97(0) <= \<const0>\;
probe_out98(0) <= \<const0>\;
probe_out99(0) <= \<const0>\;
DECODER_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
port map (
\Bus_Data_out_reg[11]\(11 downto 0) => Bus_Data_out(11 downto 0),
E(0) => DECODER_INST_n_4,
Q(15) => \bus_data_int_reg_n_0_[15]\,
Q(14) => \bus_data_int_reg_n_0_[14]\,
Q(13) => \bus_data_int_reg_n_0_[13]\,
Q(12) => \bus_data_int_reg_n_0_[12]\,
Q(11) => \bus_data_int_reg_n_0_[11]\,
Q(10) => \bus_data_int_reg_n_0_[10]\,
Q(9) => \bus_data_int_reg_n_0_[9]\,
Q(8) => \bus_data_int_reg_n_0_[8]\,
Q(7) => \bus_data_int_reg_n_0_[7]\,
Q(6) => \bus_data_int_reg_n_0_[6]\,
Q(5) => \bus_data_int_reg_n_0_[5]\,
Q(4) => \bus_data_int_reg_n_0_[4]\,
Q(3) => \bus_data_int_reg_n_0_[3]\,
Q(2) => \bus_data_int_reg_n_0_[2]\,
Q(1) => p_0_in,
Q(0) => \bus_data_int_reg_n_0_[0]\,
\out\ => bus_clk,
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_den_o => bus_den,
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en_reg[4]_0\ => DECODER_INST_n_1,
\wr_en_reg[4]_1\ => DECODER_INST_n_2,
\wr_en_reg[4]_2\ => DECODER_INST_n_3
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
PROBE_IN_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
port map (
D(3) => probe_in3(0),
D(2) => probe_in2(0),
D(1) => probe_in1(0),
D(0) => probe_in0(0),
E(0) => DECODER_INST_n_4,
Q(11 downto 0) => Bus_Data_out(11 downto 0),
clk => clk,
\out\ => bus_clk,
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en[4]_i_3\ => DECODER_INST_n_1,
\wr_en[4]_i_4\ => DECODER_INST_n_3,
\wr_en[4]_i_5\ => DECODER_INST_n_2
);
U_XSDB_SLAVE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
port map (
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_dclk_o => bus_clk,
s_den_o => bus_den,
s_di_o(15 downto 0) => bus_di(15 downto 0),
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
sl_iport_i(36 downto 0) => sl_iport0(36 downto 0),
sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
);
\bus_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(0),
Q => \bus_data_int_reg_n_0_[0]\,
R => '0'
);
\bus_data_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(10),
Q => \bus_data_int_reg_n_0_[10]\,
R => '0'
);
\bus_data_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(11),
Q => \bus_data_int_reg_n_0_[11]\,
R => '0'
);
\bus_data_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(12),
Q => \bus_data_int_reg_n_0_[12]\,
R => '0'
);
\bus_data_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(13),
Q => \bus_data_int_reg_n_0_[13]\,
R => '0'
);
\bus_data_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(14),
Q => \bus_data_int_reg_n_0_[14]\,
R => '0'
);
\bus_data_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(15),
Q => \bus_data_int_reg_n_0_[15]\,
R => '0'
);
\bus_data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(1),
Q => p_0_in,
R => '0'
);
\bus_data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(2),
Q => \bus_data_int_reg_n_0_[2]\,
R => '0'
);
\bus_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(3),
Q => \bus_data_int_reg_n_0_[3]\,
R => '0'
);
\bus_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(4),
Q => \bus_data_int_reg_n_0_[4]\,
R => '0'
);
\bus_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(5),
Q => \bus_data_int_reg_n_0_[5]\,
R => '0'
);
\bus_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(6),
Q => \bus_data_int_reg_n_0_[6]\,
R => '0'
);
\bus_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(7),
Q => \bus_data_int_reg_n_0_[7]\,
R => '0'
);
\bus_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(8),
Q => \bus_data_int_reg_n_0_[8]\,
R => '0'
);
\bus_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(9),
Q => \bus_data_int_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio_0,vio,{}";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_probe_out0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of inst : label is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of inst : label is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of inst : label is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of inst : label is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of inst : label is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of inst : label is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of inst : label is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of inst : label is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of inst : label is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of inst : label is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of inst : label is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of inst : label is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of inst : label is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of inst : label is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of inst : label is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of inst : label is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of inst : label is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of inst : label is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of inst : label is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of inst : label is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of inst : label is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of inst : label is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of inst : label is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of inst : label is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of inst : label is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of inst : label is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of inst : label is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of inst : label is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of inst : label is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of inst : label is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of inst : label is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of inst : label is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of inst : label is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of inst : label is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of inst : label is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of inst : label is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of inst : label is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of inst : label is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of inst : label is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of inst : label is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of inst : label is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of inst : label is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of inst : label is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of inst : label is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of inst : label is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of inst : label is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of inst : label is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of inst : label is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of inst : label is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of inst : label is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of inst : label is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of inst : label is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of inst : label is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of inst : label is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of inst : label is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of inst : label is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of inst : label is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of inst : label is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of inst : label is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of inst : label is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of inst : label is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of inst : label is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of inst : label is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of inst : label is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of inst : label is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of inst : label is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of inst : label is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of inst : label is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of inst : label is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of inst : label is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of inst : label is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of inst : label is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of inst : label is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of inst : label is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of inst : label is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of inst : label is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of inst : label is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of inst : label is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of inst : label is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of inst : label is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of inst : label is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of inst : label is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of inst : label is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of inst : label is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of inst : label is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of inst : label is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of inst : label is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of inst : label is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of inst : label is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of inst : label is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of inst : label is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of inst : label is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of inst : label is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of inst : label is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of inst : label is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of inst : label is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of inst : label is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of inst : label is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of inst : label is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of inst : label is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of inst : label is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of inst : label is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of inst : label is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of inst : label is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of inst : label is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of inst : label is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of inst : label is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of inst : label is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of inst : label is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of inst : label is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of inst : label is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of inst : label is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of inst : label is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of inst : label is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of inst : label is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of inst : label is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of inst : label is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of inst : label is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of inst : label is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of inst : label is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of inst : label is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of inst : label is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of inst : label is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of inst : label is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of inst : label is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of inst : label is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of inst : label is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of inst : label is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of inst : label is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of inst : label is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of inst : label is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of inst : label is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of inst : label is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of inst : label is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of inst : label is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of inst : label is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of inst : label is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of inst : label is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of inst : label is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of inst : label is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of inst : label is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of inst : label is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of inst : label is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of inst : label is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of inst : label is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of inst : label is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of inst : label is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of inst : label is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of inst : label is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of inst : label is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of inst : label is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of inst : label is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of inst : label is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of inst : label is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of inst : label is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of inst : label is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of inst : label is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of inst : label is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of inst : label is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of inst : label is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of inst : label is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of inst : label is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of inst : label is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of inst : label is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of inst : label is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of inst : label is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of inst : label is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of inst : label is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of inst : label is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of inst : label is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of inst : label is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of inst : label is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of inst : label is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of inst : label is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of inst : label is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of inst : label is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of inst : label is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of inst : label is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of inst : label is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of inst : label is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of inst : label is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of inst : label is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of inst : label is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of inst : label is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of inst : label is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of inst : label is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of inst : label is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of inst : label is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of inst : label is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of inst : label is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of inst : label is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of inst : label is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of inst : label is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of inst : label is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of inst : label is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of inst : label is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of inst : label is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of inst : label is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of inst : label is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of inst : label is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of inst : label is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of inst : label is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of inst : label is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of inst : label is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of inst : label is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of inst : label is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of inst : label is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of inst : label is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of inst : label is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of inst : label is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of inst : label is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of inst : label is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of inst : label is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of inst : label is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of inst : label is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of inst : label is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of inst : label is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of inst : label is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of inst : label is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of inst : label is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of inst : label is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of inst : label is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of inst : label is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of inst : label is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of inst : label is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of inst : label is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of inst : label is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of inst : label is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of inst : label is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of inst : label is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of inst : label is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of inst : label is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of inst : label is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of inst : label is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of inst : label is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of inst : label is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of inst : label is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of inst : label is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of inst : label is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of inst : label is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of inst : label is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of inst : label is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of inst : label is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of inst : label is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of inst : label is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of inst : label is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of inst : label is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of inst : label is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of inst : label is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of inst : label is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of inst : label is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of inst : label is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of inst : label is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of inst : label is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of inst : label is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of inst : label is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of inst : label is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of inst : label is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of inst : label is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of inst : label is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of inst : label is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of inst : label is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of inst : label is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of inst : label is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of inst : label is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of inst : label is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of inst : label is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of inst : label is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of inst : label is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of inst : label is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of inst : label is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of inst : label is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of inst : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of inst : label is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of inst : label is std.standard.true;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 0;
attribute syn_noprune : string;
attribute syn_noprune of inst : label is "1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
port map (
clk => clk,
probe_in0(0) => probe_in0(0),
probe_in1(0) => probe_in1(0),
probe_in10(0) => '0',
probe_in100(0) => '0',
probe_in101(0) => '0',
probe_in102(0) => '0',
probe_in103(0) => '0',
probe_in104(0) => '0',
probe_in105(0) => '0',
probe_in106(0) => '0',
probe_in107(0) => '0',
probe_in108(0) => '0',
probe_in109(0) => '0',
probe_in11(0) => '0',
probe_in110(0) => '0',
probe_in111(0) => '0',
probe_in112(0) => '0',
probe_in113(0) => '0',
probe_in114(0) => '0',
probe_in115(0) => '0',
probe_in116(0) => '0',
probe_in117(0) => '0',
probe_in118(0) => '0',
probe_in119(0) => '0',
probe_in12(0) => '0',
probe_in120(0) => '0',
probe_in121(0) => '0',
probe_in122(0) => '0',
probe_in123(0) => '0',
probe_in124(0) => '0',
probe_in125(0) => '0',
probe_in126(0) => '0',
probe_in127(0) => '0',
probe_in128(0) => '0',
probe_in129(0) => '0',
probe_in13(0) => '0',
probe_in130(0) => '0',
probe_in131(0) => '0',
probe_in132(0) => '0',
probe_in133(0) => '0',
probe_in134(0) => '0',
probe_in135(0) => '0',
probe_in136(0) => '0',
probe_in137(0) => '0',
probe_in138(0) => '0',
probe_in139(0) => '0',
probe_in14(0) => '0',
probe_in140(0) => '0',
probe_in141(0) => '0',
probe_in142(0) => '0',
probe_in143(0) => '0',
probe_in144(0) => '0',
probe_in145(0) => '0',
probe_in146(0) => '0',
probe_in147(0) => '0',
probe_in148(0) => '0',
probe_in149(0) => '0',
probe_in15(0) => '0',
probe_in150(0) => '0',
probe_in151(0) => '0',
probe_in152(0) => '0',
probe_in153(0) => '0',
probe_in154(0) => '0',
probe_in155(0) => '0',
probe_in156(0) => '0',
probe_in157(0) => '0',
probe_in158(0) => '0',
probe_in159(0) => '0',
probe_in16(0) => '0',
probe_in160(0) => '0',
probe_in161(0) => '0',
probe_in162(0) => '0',
probe_in163(0) => '0',
probe_in164(0) => '0',
probe_in165(0) => '0',
probe_in166(0) => '0',
probe_in167(0) => '0',
probe_in168(0) => '0',
probe_in169(0) => '0',
probe_in17(0) => '0',
probe_in170(0) => '0',
probe_in171(0) => '0',
probe_in172(0) => '0',
probe_in173(0) => '0',
probe_in174(0) => '0',
probe_in175(0) => '0',
probe_in176(0) => '0',
probe_in177(0) => '0',
probe_in178(0) => '0',
probe_in179(0) => '0',
probe_in18(0) => '0',
probe_in180(0) => '0',
probe_in181(0) => '0',
probe_in182(0) => '0',
probe_in183(0) => '0',
probe_in184(0) => '0',
probe_in185(0) => '0',
probe_in186(0) => '0',
probe_in187(0) => '0',
probe_in188(0) => '0',
probe_in189(0) => '0',
probe_in19(0) => '0',
probe_in190(0) => '0',
probe_in191(0) => '0',
probe_in192(0) => '0',
probe_in193(0) => '0',
probe_in194(0) => '0',
probe_in195(0) => '0',
probe_in196(0) => '0',
probe_in197(0) => '0',
probe_in198(0) => '0',
probe_in199(0) => '0',
probe_in2(0) => probe_in2(0),
probe_in20(0) => '0',
probe_in200(0) => '0',
probe_in201(0) => '0',
probe_in202(0) => '0',
probe_in203(0) => '0',
probe_in204(0) => '0',
probe_in205(0) => '0',
probe_in206(0) => '0',
probe_in207(0) => '0',
probe_in208(0) => '0',
probe_in209(0) => '0',
probe_in21(0) => '0',
probe_in210(0) => '0',
probe_in211(0) => '0',
probe_in212(0) => '0',
probe_in213(0) => '0',
probe_in214(0) => '0',
probe_in215(0) => '0',
probe_in216(0) => '0',
probe_in217(0) => '0',
probe_in218(0) => '0',
probe_in219(0) => '0',
probe_in22(0) => '0',
probe_in220(0) => '0',
probe_in221(0) => '0',
probe_in222(0) => '0',
probe_in223(0) => '0',
probe_in224(0) => '0',
probe_in225(0) => '0',
probe_in226(0) => '0',
probe_in227(0) => '0',
probe_in228(0) => '0',
probe_in229(0) => '0',
probe_in23(0) => '0',
probe_in230(0) => '0',
probe_in231(0) => '0',
probe_in232(0) => '0',
probe_in233(0) => '0',
probe_in234(0) => '0',
probe_in235(0) => '0',
probe_in236(0) => '0',
probe_in237(0) => '0',
probe_in238(0) => '0',
probe_in239(0) => '0',
probe_in24(0) => '0',
probe_in240(0) => '0',
probe_in241(0) => '0',
probe_in242(0) => '0',
probe_in243(0) => '0',
probe_in244(0) => '0',
probe_in245(0) => '0',
probe_in246(0) => '0',
probe_in247(0) => '0',
probe_in248(0) => '0',
probe_in249(0) => '0',
probe_in25(0) => '0',
probe_in250(0) => '0',
probe_in251(0) => '0',
probe_in252(0) => '0',
probe_in253(0) => '0',
probe_in254(0) => '0',
probe_in255(0) => '0',
probe_in26(0) => '0',
probe_in27(0) => '0',
probe_in28(0) => '0',
probe_in29(0) => '0',
probe_in3(0) => probe_in3(0),
probe_in30(0) => '0',
probe_in31(0) => '0',
probe_in32(0) => '0',
probe_in33(0) => '0',
probe_in34(0) => '0',
probe_in35(0) => '0',
probe_in36(0) => '0',
probe_in37(0) => '0',
probe_in38(0) => '0',
probe_in39(0) => '0',
probe_in4(0) => '0',
probe_in40(0) => '0',
probe_in41(0) => '0',
probe_in42(0) => '0',
probe_in43(0) => '0',
probe_in44(0) => '0',
probe_in45(0) => '0',
probe_in46(0) => '0',
probe_in47(0) => '0',
probe_in48(0) => '0',
probe_in49(0) => '0',
probe_in5(0) => '0',
probe_in50(0) => '0',
probe_in51(0) => '0',
probe_in52(0) => '0',
probe_in53(0) => '0',
probe_in54(0) => '0',
probe_in55(0) => '0',
probe_in56(0) => '0',
probe_in57(0) => '0',
probe_in58(0) => '0',
probe_in59(0) => '0',
probe_in6(0) => '0',
probe_in60(0) => '0',
probe_in61(0) => '0',
probe_in62(0) => '0',
probe_in63(0) => '0',
probe_in64(0) => '0',
probe_in65(0) => '0',
probe_in66(0) => '0',
probe_in67(0) => '0',
probe_in68(0) => '0',
probe_in69(0) => '0',
probe_in7(0) => '0',
probe_in70(0) => '0',
probe_in71(0) => '0',
probe_in72(0) => '0',
probe_in73(0) => '0',
probe_in74(0) => '0',
probe_in75(0) => '0',
probe_in76(0) => '0',
probe_in77(0) => '0',
probe_in78(0) => '0',
probe_in79(0) => '0',
probe_in8(0) => '0',
probe_in80(0) => '0',
probe_in81(0) => '0',
probe_in82(0) => '0',
probe_in83(0) => '0',
probe_in84(0) => '0',
probe_in85(0) => '0',
probe_in86(0) => '0',
probe_in87(0) => '0',
probe_in88(0) => '0',
probe_in89(0) => '0',
probe_in9(0) => '0',
probe_in90(0) => '0',
probe_in91(0) => '0',
probe_in92(0) => '0',
probe_in93(0) => '0',
probe_in94(0) => '0',
probe_in95(0) => '0',
probe_in96(0) => '0',
probe_in97(0) => '0',
probe_in98(0) => '0',
probe_in99(0) => '0',
probe_out0(0) => NLW_inst_probe_out0_UNCONNECTED(0),
probe_out1(0) => NLW_inst_probe_out1_UNCONNECTED(0),
probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0),
probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
);
end STRUCTURE;
|
mit
|
77a684055ddf69599fc71bcc2c077493
| 0.70964 | 2.992569 | false | false | false | false |
benreynwar/pyvivado
|
pyvivado/templates/jtag_testbench.vhd
| 1 | 7,759 |
-- -*- vhdl -*-
library ieee;
use ieee.std_logic_1164.all;
use work.axi_utils.all;
entity {{dut_name}}_jtag is
port (
clk_in_n: in std_logic;
clk_in_p: in std_logic{% if use_reset %};
reset: in std_logic{% endif %}
);
end entity;
architecture arch of {{dut_name}}_jtag is
-- Basic clk signals
signal clk: std_logic;{% if clk_b %}
signal clk_b: std_logic;{% endif %}
signal jtagtoaxi_clk: std_logic;
-- Axi signals
signal m2s: axi4lite_m2s;
signal s2m: axi4lite_s2m;
signal jtagtoaxim2s: axi4lite_m2s;
signal jtagtoaxis2m: axi4lite_s2m;
signal jtagtoaxi_breset: std_logic;
signal jtagtoaxi_reset: std_logic;
signal jtagtoaxi_resetn: std_logic;
signal breset_clk: std_logic;
signal breset_clk_b: std_logic;
signal reset_clk: std_logic;
signal reset_clk_b: std_logic;
signal resetn_clk: std_logic;
{% if not use_reset %}signal reset: std_logic;{% endif %}
component clk_wiz_0 port (
clk_in1_n: in std_logic;
clk_in1_p: in std_logic;
reset: in std_logic;
clk_out1: out std_logic;
clk_out2: out std_logic{% if clk_b %};
clk_out3: out std_logic{% endif %}
);
end component;
component jtag_axi_0 port (
aclk: in std_logic;
aresetn: in std_logic;
m_axi_araddr: out std_logic_vector(31 downto 0);
m_axi_arprot: out std_logic_vector(2 downto 0);
m_axi_arready: in std_logic;
m_axi_arvalid: out std_logic;
m_axi_awaddr: out std_logic_vector(31 downto 0);
m_axi_awprot: out std_logic_vector(2 downto 0);
m_axi_awready: in std_logic;
m_axi_awvalid: out std_logic;
m_axi_bready: out std_logic;
m_axi_bresp: in std_logic_vector(1 downto 0);
m_axi_bvalid: in std_logic;
m_axi_rdata: in std_logic_vector(31 downto 0);
m_axi_rready: out std_logic;
m_axi_rresp: in std_logic_vector(1 downto 0);
m_axi_rvalid: in std_logic;
m_axi_wdata: out std_logic_vector(31 downto 0);
m_axi_wready: in std_logic;
m_axi_wstrb: out std_logic_vector(3 downto 0);
m_axi_wvalid: out std_logic
);
end component;
component axi_clock_converter_0 port (
s_axi_aclk: in std_logic;
s_axi_aresetn: in std_logic;
s_axi_araddr: in std_logic_vector(31 downto 0);
s_axi_arprot: in std_logic_vector(2 downto 0);
s_axi_arready: out std_logic;
s_axi_arvalid: in std_logic;
s_axi_awaddr: in std_logic_vector(31 downto 0);
s_axi_awprot: in std_logic_vector(2 downto 0);
s_axi_awready: out std_logic;
s_axi_awvalid: in std_logic;
s_axi_bready: in std_logic;
s_axi_bresp: out std_logic_vector(1 downto 0);
s_axi_bvalid: out std_logic;
s_axi_rdata: out std_logic_vector(31 downto 0);
s_axi_rready: in std_logic;
s_axi_rresp: out std_logic_vector(1 downto 0);
s_axi_rvalid: out std_logic;
s_axi_wdata: in std_logic_vector(31 downto 0);
s_axi_wready: out std_logic;
s_axi_wstrb: in std_logic_vector(3 downto 0);
s_axi_wvalid: in std_logic;
m_axi_aclk: in std_logic;
m_axi_aresetn: in std_logic;
m_axi_araddr: out std_logic_vector(31 downto 0);
m_axi_arprot: out std_logic_vector(2 downto 0);
m_axi_arready: in std_logic;
m_axi_arvalid: out std_logic;
m_axi_awaddr: out std_logic_vector(31 downto 0);
m_axi_awprot: out std_logic_vector(2 downto 0);
m_axi_awready: in std_logic;
m_axi_awvalid: out std_logic;
m_axi_bready: out std_logic;
m_axi_bresp: in std_logic_vector(1 downto 0);
m_axi_bvalid: in std_logic;
m_axi_rdata: in std_logic_vector(31 downto 0);
m_axi_rready: out std_logic;
m_axi_rresp: in std_logic_vector(1 downto 0);
m_axi_rvalid: in std_logic;
m_axi_wdata: out std_logic_vector(31 downto 0);
m_axi_wready: in std_logic;
m_axi_wstrb: out std_logic_vector(3 downto 0);
m_axi_wvalid: out std_logic
);
end component;
begin
{% if not use_reset %}reset <= '0';{% endif %}
the_clock_wizard: clk_wiz_0
port map(
clk_in1_n => clk_in_n,
clk_in1_p => clk_in_p,
reset => reset,
clk_out1 => jtagtoaxi_clk,{% if clk_b %}
clk_out2 => clk_b,
clk_out3 => clk{% else %}
clk_out2 => clk{% endif %}
);
-- Create synchronous resets.
process(clk)
begin
if rising_edge(clk) then
breset_clk <= reset;
reset_clk <= breset_clk;
end if;
end process;
resetn_clk <= not reset_clk;
process(clk_b)
begin
if rising_edge(clk_b) then
breset_clk_b <= reset;
reset_clk_b <= breset_clk_b;
end if;
end process;
process(jtagtoaxi_clk)
begin
if rising_edge(jtagtoaxi_clk) then
jtagtoaxi_breset <= reset;
jtagtoaxi_reset <= jtagtoaxi_breset;
end if;
end process;
jtagtoaxi_resetn <= not jtagtoaxi_reset;
jtag_to_axi_master: jtag_axi_0
port map(
aclk => jtagtoaxi_clk,
aresetn => jtagtoaxi_resetn,
m_axi_araddr => jtagtoaxim2s.araddr,
m_axi_arprot => jtagtoaxim2s.arprot,
m_axi_arready => jtagtoaxis2m.arready,
m_axi_arvalid => jtagtoaxim2s.arvalid,
m_axi_awaddr => jtagtoaxim2s.awaddr,
m_axi_awprot => jtagtoaxim2s.awprot,
m_axi_awready => jtagtoaxis2m.awready,
m_axi_awvalid => jtagtoaxim2s.awvalid,
m_axi_bready => jtagtoaxim2s.bready,
m_axi_bresp => jtagtoaxis2m.bresp,
m_axi_bvalid => jtagtoaxis2m.bvalid,
m_axi_rdata => jtagtoaxis2m.rdata,
m_axi_rready => jtagtoaxim2s.rready,
m_axi_rresp => jtagtoaxis2m.rresp,
m_axi_rvalid => jtagtoaxis2m.rvalid,
m_axi_wdata => jtagtoaxim2s.wdata,
m_axi_wready => jtagtoaxis2m.wready,
m_axi_wstrb => jtagtoaxim2s.wstrb,
m_axi_wvalid => jtagtoaxim2s.wvalid
);
clock_domain_crossing: axi_clock_converter_0
port map (
s_axi_aclk => jtagtoaxi_clk,
s_axi_aresetn => jtagtoaxi_resetn,
s_axi_araddr => jtagtoaxim2s.araddr,
s_axi_arprot => jtagtoaxim2s.arprot,
s_axi_arready => jtagtoaxis2m.arready,
s_axi_arvalid => jtagtoaxim2s.arvalid,
s_axi_awaddr => jtagtoaxim2s.awaddr,
s_axi_awprot => jtagtoaxim2s.awprot,
s_axi_awready => jtagtoaxis2m.awready,
s_axi_awvalid => jtagtoaxim2s.awvalid,
s_axi_bready => jtagtoaxim2s.bready,
s_axi_bresp => jtagtoaxis2m.bresp,
s_axi_bvalid => jtagtoaxis2m.bvalid,
s_axi_rdata => jtagtoaxis2m.rdata,
s_axi_rready => jtagtoaxim2s.rready,
s_axi_rresp => jtagtoaxis2m.rresp,
s_axi_rvalid => jtagtoaxis2m.rvalid,
s_axi_wdata => jtagtoaxim2s.wdata,
s_axi_wready => jtagtoaxis2m.wready,
s_axi_wstrb => jtagtoaxim2s.wstrb,
s_axi_wvalid => jtagtoaxim2s.wvalid,
m_axi_aclk => clk,
m_axi_aresetn => resetn_clk,
m_axi_araddr => m2s.araddr,
m_axi_arprot => m2s.arprot,
m_axi_arready => s2m.arready,
m_axi_arvalid => m2s.arvalid,
m_axi_awaddr => m2s.awaddr,
m_axi_awprot => m2s.awprot,
m_axi_awready => s2m.awready,
m_axi_awvalid => m2s.awvalid,
m_axi_bready => m2s.bready,
m_axi_bresp => s2m.bresp,
m_axi_bvalid => s2m.bvalid,
m_axi_rdata => s2m.rdata,
m_axi_rready => m2s.rready,
m_axi_rresp => s2m.rresp,
m_axi_rvalid => s2m.rvalid,
m_axi_wdata => m2s.wdata,
m_axi_wready => s2m.wready,
m_axi_wstrb => m2s.wstrb,
m_axi_wvalid => m2s.wvalid
);
axi_wrapped_dut: entity work.{{dut_name}}
{% if dut_parameters %}
generic map(
{% for name, value in dut_parameters.items() %}
{{name}} => {{value}} {% if not loop.last %},{% endif %}
{% endfor %}
)
{% endif %}
port map (
clk => clk,
reset => reset_clk,{% if clk_b %}
clk_b => clk_b,{% endif %}
m2s => m2s,
s2m => s2m
);
end arch;
|
mit
|
77fe00ee05ce692384700386075bd2fe
| 0.620183 | 3.007364 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/2dd47188d6cdcfd2/vio_0_sim_netlist.vhdl
| 1 | 538,816 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 11:02:39 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.vhdl
-- Design : vio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
port (
s_drdy_i : out STD_LOGIC;
\wr_en_reg[4]_0\ : out STD_LOGIC;
\wr_en_reg[4]_1\ : out STD_LOGIC;
\wr_en_reg[4]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_do_i : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_rst_o : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
\Bus_Data_out_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
signal Hold_probe_in : STD_LOGIC;
signal clear_int : STD_LOGIC;
signal committ_int : STD_LOGIC;
signal \data_info_probe_in__67\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_cnt_rst : STD_LOGIC;
signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rd_en_p1 : STD_LOGIC;
signal rd_en_p2 : STD_LOGIC;
signal wr_control_reg : STD_LOGIC;
signal \wr_en[2]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[2]_i_2_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_6_n_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_1\ : STD_LOGIC;
signal \^wr_en_reg[4]_2\ : STD_LOGIC;
signal wr_probe_out_modified : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_8_p1 : STD_LOGIC;
signal xsdb_addr_8_p2 : STD_LOGIC;
signal xsdb_drdy_i_1_n_0 : STD_LOGIC;
signal xsdb_rd : STD_LOGIC;
signal xsdb_wr : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Bus_data_out[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Bus_data_out[13]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[15]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wr_en[2]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \wr_en[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wr_en[4]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair14";
begin
\wr_en_reg[4]_0\ <= \^wr_en_reg[4]_0\;
\wr_en_reg[4]_1\ <= \^wr_en_reg[4]_1\;
\wr_en_reg[4]_2\ <= \^wr_en_reg[4]_2\;
\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF00AF000FC000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(0),
I1 => probe_out_modified(0),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => committ_int,
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(0)
);
\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(10),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(10),
O => \data_info_probe_in__67\(10)
);
\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(11),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(11),
O => \data_info_probe_in__67\(11)
);
\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(12),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(12)
);
\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(13),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(13)
);
\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(14),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(14)
);
\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(15),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(15)
);
\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0000FC0A00000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(1),
I1 => probe_out_modified(1),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => xsdb_addr_2_0_p2(0),
I5 => clear_int,
O => \data_info_probe_in__67\(1)
);
\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A000000F00CFCF"
)
port map (
I0 => \Bus_Data_out_reg[11]\(2),
I1 => probe_out_modified(2),
I2 => xsdb_addr_2_0_p2(2),
I3 => int_cnt_rst,
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(2)
);
\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(3),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(3),
O => \data_info_probe_in__67\(3)
);
\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(4),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(4),
O => \data_info_probe_in__67\(4)
);
\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(5),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(5),
O => \data_info_probe_in__67\(5)
);
\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(6),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(6),
O => \data_info_probe_in__67\(6)
);
\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(7),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(7),
O => \data_info_probe_in__67\(7)
);
\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(8),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(8),
O => \data_info_probe_in__67\(8)
);
\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(9),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(9),
O => \data_info_probe_in__67\(9)
);
\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(0),
Q => s_do_i(0),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(10),
Q => s_do_i(10),
R => xsdb_addr_8_p2
);
\bus_data_out_reg[11]_RnM\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(11),
Q => s_do_i(11),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(12),
Q => s_do_i(12),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(13),
Q => s_do_i(13),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(14),
Q => s_do_i(14),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(15),
Q => s_do_i(15),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(1),
Q => s_do_i(1),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(2),
Q => s_do_i(2),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(3),
Q => s_do_i(3),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(4),
Q => s_do_i(4),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(5),
Q => s_do_i(5),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(6),
Q => s_do_i(6),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(7),
Q => s_do_i(7),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(8),
Q => s_do_i(8),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(9),
Q => s_do_i(9),
R => xsdb_addr_8_p2
);
Hold_probe_in_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(3),
Q => Hold_probe_in,
R => s_rst_o
);
clear_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(1),
Q => clear_int,
R => s_rst_o
);
committ_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(0),
Q => committ_int,
R => s_rst_o
);
int_cnt_rst_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(2),
Q => int_cnt_rst,
R => s_rst_o
);
\probe_in_reg[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Hold_probe_in,
O => E(0)
);
\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(0),
Q => probe_out_modified(0),
R => clear_int
);
\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(10),
Q => probe_out_modified(10),
R => clear_int
);
\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(11),
Q => probe_out_modified(11),
R => clear_int
);
\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(12),
Q => probe_out_modified(12),
R => clear_int
);
\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(13),
Q => probe_out_modified(13),
R => clear_int
);
\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(14),
Q => probe_out_modified(14),
R => clear_int
);
\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(15),
Q => probe_out_modified(15),
R => clear_int
);
\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(1),
Q => probe_out_modified(1),
R => clear_int
);
\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(2),
Q => probe_out_modified(2),
R => clear_int
);
\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(3),
Q => probe_out_modified(3),
R => clear_int
);
\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(4),
Q => probe_out_modified(4),
R => clear_int
);
\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(5),
Q => probe_out_modified(5),
R => clear_int
);
\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(6),
Q => probe_out_modified(6),
R => clear_int
);
\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(7),
Q => probe_out_modified(7),
R => clear_int
);
\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(8),
Q => probe_out_modified(8),
R => clear_int
);
\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(9),
Q => probe_out_modified(9),
R => clear_int
);
rd_en_p1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_rd
);
rd_en_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_rd,
Q => rd_en_p1,
R => s_rst_o
);
rd_en_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => rd_en_p1,
Q => rd_en_p2,
R => s_rst_o
);
\wr_en[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => xsdb_wr,
I1 => s_daddr_o(2),
I2 => \^wr_en_reg[4]_0\,
I3 => \^wr_en_reg[4]_2\,
I4 => \^wr_en_reg[4]_1\,
I5 => \wr_en[2]_i_2_n_0\,
O => \wr_en[2]_i_1_n_0\
);
\wr_en[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[2]_i_2_n_0\
);
\wr_en[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => xsdb_wr,
I1 => \^wr_en_reg[4]_0\,
I2 => \^wr_en_reg[4]_2\,
I3 => \^wr_en_reg[4]_1\,
I4 => s_daddr_o(2),
I5 => \wr_en[4]_i_6_n_0\,
O => \wr_en[4]_i_1_n_0\
);
\wr_en[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_wr
);
\wr_en[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_daddr_o(15),
I1 => s_daddr_o(16),
I2 => s_daddr_o(13),
I3 => s_daddr_o(14),
I4 => s_daddr_o(4),
I5 => s_daddr_o(3),
O => \^wr_en_reg[4]_0\
);
\wr_en[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(6),
I1 => s_daddr_o(5),
I2 => s_daddr_o(8),
I3 => s_daddr_o(7),
O => \^wr_en_reg[4]_2\
);
\wr_en[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(10),
I1 => s_daddr_o(9),
I2 => s_daddr_o(12),
I3 => s_daddr_o(11),
O => \^wr_en_reg[4]_1\
);
\wr_en[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[4]_i_6_n_0\
);
\wr_en_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[2]_i_1_n_0\,
Q => wr_control_reg,
R => '0'
);
\wr_en_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[4]_i_1_n_0\,
Q => wr_probe_out_modified,
R => '0'
);
\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(0),
Q => xsdb_addr_2_0_p1(0),
R => '0'
);
\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(1),
Q => xsdb_addr_2_0_p1(1),
R => '0'
);
\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(2),
Q => xsdb_addr_2_0_p1(2),
R => '0'
);
\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(0),
Q => xsdb_addr_2_0_p2(0),
R => '0'
);
\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(1),
Q => xsdb_addr_2_0_p2(1),
R => '0'
);
\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(2),
Q => xsdb_addr_2_0_p2(2),
R => '0'
);
xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(8),
Q => xsdb_addr_8_p1,
R => '0'
);
xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_8_p1,
Q => xsdb_addr_8_p2,
R => '0'
);
xsdb_drdy_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => rd_en_p2,
O => xsdb_drdy_i_1_n_0
);
xsdb_drdy_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_drdy_i_1_n_0,
Q => s_drdy_i,
R => s_rst_o
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC;
\wr_en[4]_i_3\ : in STD_LOGIC;
\wr_en[4]_i_4\ : in STD_LOGIC;
\wr_en[4]_i_5\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
s_rst_o : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC;
signal Read_int : STD_LOGIC;
signal Read_int_i_2_n_0 : STD_LOGIC;
signal data_int_sync1 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of data_int_sync1 : signal is "true";
signal data_int_sync2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg of data_int_sync2 : signal is "true";
signal \dn_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[3]\ : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal probe_in_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true;
signal read_done : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of read_done : signal is "200";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of read_done : signal is "found";
signal read_done_i_1_n_0 : STD_LOGIC;
signal \up_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \up_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[1]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[2]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[3]\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes";
attribute RTL_MAX_FANOUT of read_done_reg : label is "found";
begin
\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(0),
Q => Q(0),
R => '0'
);
\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_in,
Q => Q(10),
R => '0'
);
\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[3]\,
Q => Q(11),
R => '0'
);
\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(1),
Q => Q(1),
R => '0'
);
\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(2),
Q => Q(2),
R => '0'
);
\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(3),
Q => Q(3),
R => '0'
);
\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[0]\,
Q => Q(4),
R => '0'
);
\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[1]\,
Q => Q(5),
R => '0'
);
\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[2]\,
Q => Q(6),
R => '0'
);
\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[3]\,
Q => Q(7),
R => '0'
);
\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[0]\,
Q => Q(8),
R => '0'
);
\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_6_in,
Q => Q(9),
R => '0'
);
Read_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => Read_int_i_2_n_0,
I1 => \wr_en[4]_i_3\,
I2 => \wr_en[4]_i_4\,
I3 => \wr_en[4]_i_5\,
O => \DECODER_INST/rd_en_int_7\
);
Read_int_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
I2 => s_daddr_o(2),
I3 => s_dwe_o,
I4 => s_den_o,
O => Read_int_i_2_n_0
);
Read_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \DECODER_INST/rd_en_int_7\,
Q => Read_int,
R => '0'
);
\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(0),
Q => data_int_sync1(0),
R => '0'
);
\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(1),
Q => data_int_sync1(1),
R => '0'
);
\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(2),
Q => data_int_sync1(2),
R => '0'
);
\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(3),
Q => data_int_sync1(3),
R => '0'
);
\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(0),
Q => data_int_sync2(0),
R => '0'
);
\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(1),
Q => data_int_sync2(1),
R => '0'
);
\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(2),
Q => data_int_sync2(2),
R => '0'
);
\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(3),
Q => data_int_sync2(3),
R => '0'
);
\dn_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[0]\,
I1 => data_int_sync1(0),
I2 => data_int_sync2(0),
O => \dn_activity[0]_i_1_n_0\
);
\dn_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_6_in,
I1 => data_int_sync1(1),
I2 => data_int_sync2(1),
O => \dn_activity[1]_i_1_n_0\
);
\dn_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_9_in,
I1 => data_int_sync1(2),
I2 => data_int_sync2(2),
O => \dn_activity[2]_i_1_n_0\
);
\dn_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[3]\,
I1 => data_int_sync1(3),
I2 => data_int_sync2(3),
O => \dn_activity[3]_i_1_n_0\
);
\dn_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[0]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[0]\,
R => read_done
);
\dn_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[1]_i_1_n_0\,
Q => p_6_in,
R => read_done
);
\dn_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[2]_i_1_n_0\,
Q => p_9_in,
R => read_done
);
\dn_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[3]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[3]\,
R => read_done
);
\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(0),
Q => probe_in_reg(0),
R => '0'
);
\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(1),
Q => probe_in_reg(1),
R => '0'
);
\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(2),
Q => probe_in_reg(2),
R => '0'
);
\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(3),
Q => probe_in_reg(3),
R => '0'
);
read_done_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Read_int,
I1 => read_done,
I2 => s_rst_o,
O => read_done_i_1_n_0
);
read_done_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => read_done_i_1_n_0,
Q => read_done,
R => '0'
);
\up_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[0]\,
I1 => data_int_sync2(0),
I2 => data_int_sync1(0),
O => \up_activity[0]_i_1_n_0\
);
\up_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[1]\,
I1 => data_int_sync2(1),
I2 => data_int_sync1(1),
O => \up_activity[1]_i_1_n_0\
);
\up_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[2]\,
I1 => data_int_sync2(2),
I2 => data_int_sync1(2),
O => \up_activity[2]_i_1_n_0\
);
\up_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[3]\,
I1 => data_int_sync2(3),
I2 => data_int_sync1(3),
O => \up_activity[3]_i_1_n_0\
);
\up_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[0]_i_1_n_0\,
Q => \up_activity_reg_n_0_[0]\,
R => read_done
);
\up_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[1]_i_1_n_0\,
Q => \up_activity_reg_n_0_[1]\,
R => read_done
);
\up_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[2]_i_1_n_0\,
Q => \up_activity_reg_n_0_[2]\,
R => read_done
);
\up_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[3]_i_1_n_0\,
Q => \up_activity_reg_n_0_[3]\,
R => read_done
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
port (
s_rst_o : out STD_LOGIC;
s_dclk_o : out STD_LOGIC;
s_den_o : out STD_LOGIC;
s_dwe_o : out STD_LOGIC;
s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
s_drdy_i : in STD_LOGIC
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2013;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "kintex7";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
signal reg_do : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \reg_do[10]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[15]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[2]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[3]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[6]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[7]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[9]_i_1_n_0\ : STD_LOGIC;
signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
signal reg_drdy : STD_LOGIC;
signal reg_drdy_i_1_n_0 : STD_LOGIC;
signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
signal reg_test0 : STD_LOGIC;
signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \reg_do[10]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \reg_do[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair8";
begin
\^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4);
s_dclk_o <= \^sl_iport_i\(1);
s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21);
s_dwe_o <= \^sl_iport_i\(3);
s_rst_o <= \^sl_iport_i\(0);
\reg_do[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAFFFFAAAAAAAA"
)
port map (
I0 => \reg_do[5]_i_2_n_0\,
I1 => \^sl_iport_i\(4),
I2 => reg_test(0),
I3 => \^sl_iport_i\(6),
I4 => \^sl_iport_i\(5),
I5 => \^sl_iport_i\(8),
O => reg_do(0)
);
\reg_do[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \reg_do[8]_i_2_n_0\,
I2 => \^sl_iport_i\(4),
O => \reg_do[10]_i_1_n_0\
);
\reg_do[10]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(10),
O => \reg_do[10]_i_2_n_0\
);
\reg_do[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
O => \reg_do[15]_i_1_n_0\
);
\reg_do[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20220000"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \^sl_iport_i\(4),
I2 => reg_test(1),
I3 => \^sl_iport_i\(6),
I4 => \reg_do[1]_i_2_n_0\,
O => reg_do(1)
);
\reg_do[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \^sl_iport_i\(8),
I1 => \^sl_iport_i\(10),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(7),
I4 => \^sl_iport_i\(9),
O => \reg_do[1]_i_2_n_0\
);
\reg_do[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(2),
O => \reg_do[2]_i_1_n_0\
);
\reg_do[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(3),
O => \reg_do[3]_i_1_n_0\
);
\reg_do[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(4),
O => \reg_do[4]_i_1_n_0\
);
\reg_do[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800044"
)
port map (
I0 => \^sl_iport_i\(6),
I1 => \^sl_iport_i\(8),
I2 => reg_test(5),
I3 => \^sl_iport_i\(4),
I4 => \^sl_iport_i\(5),
I5 => \reg_do[5]_i_2_n_0\,
O => reg_do(5)
);
\reg_do[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFFFFC"
)
port map (
I0 => \^sl_iport_i\(7),
I1 => \^sl_iport_i\(8),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(9),
O => \reg_do[5]_i_2_n_0\
);
\reg_do[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(6),
O => \reg_do[6]_i_1_n_0\
);
\reg_do[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(7),
O => \reg_do[7]_i_1_n_0\
);
\reg_do[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F00"
)
port map (
I0 => reg_test(8),
I1 => \^sl_iport_i\(4),
I2 => \^sl_iport_i\(5),
I3 => \reg_do[8]_i_2_n_0\,
O => reg_do(8)
);
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \^sl_iport_i\(9),
I1 => \^sl_iport_i\(7),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(8),
I5 => \^sl_iport_i\(6),
O => \reg_do[8]_i_2_n_0\
);
\reg_do[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C008000"
)
port map (
I0 => reg_test(9),
I1 => \reg_do[1]_i_2_n_0\,
I2 => \^sl_iport_i\(6),
I3 => \^sl_iport_i\(5),
I4 => \^sl_iport_i\(4),
O => \reg_do[9]_i_1_n_0\
);
\reg_do_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(0),
Q => \reg_do_reg_n_0_[0]\,
R => '0'
);
\reg_do_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[10]_i_2_n_0\,
Q => \reg_do_reg_n_0_[10]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(11),
Q => \reg_do_reg_n_0_[11]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(12),
Q => \reg_do_reg_n_0_[12]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(13),
Q => \reg_do_reg_n_0_[13]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(14),
Q => \reg_do_reg_n_0_[14]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(15),
Q => \reg_do_reg_n_0_[15]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(1),
Q => \reg_do_reg_n_0_[1]\,
R => '0'
);
\reg_do_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[2]_i_1_n_0\,
Q => \reg_do_reg_n_0_[2]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[3]_i_1_n_0\,
Q => \reg_do_reg_n_0_[3]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[4]_i_1_n_0\,
Q => \reg_do_reg_n_0_[4]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(5),
Q => \reg_do_reg_n_0_[5]\,
R => '0'
);
\reg_do_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[6]_i_1_n_0\,
Q => \reg_do_reg_n_0_[6]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[7]_i_1_n_0\,
Q => \reg_do_reg_n_0_[7]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(8),
Q => \reg_do_reg_n_0_[8]\,
R => '0'
);
\reg_do_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[9]_i_1_n_0\,
Q => \reg_do_reg_n_0_[9]\,
S => \reg_do[10]_i_1_n_0\
);
reg_drdy_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => s_den_o_INST_0_i_1_n_0,
I2 => \^sl_iport_i\(12),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(14),
I5 => \^sl_iport_i\(0),
O => reg_drdy_i_1_n_0
);
reg_drdy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_drdy_i_1_n_0,
Q => reg_drdy,
R => '0'
);
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(3),
I1 => \^sl_iport_i\(2),
I2 => \^sl_iport_i\(14),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(12),
I5 => s_den_o_INST_0_i_1_n_0,
O => reg_test0
);
\reg_test_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(21),
Q => reg_test(0),
R => '0'
);
\reg_test_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(31),
Q => reg_test(10),
R => '0'
);
\reg_test_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(32),
Q => reg_test(11),
R => '0'
);
\reg_test_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(33),
Q => reg_test(12),
R => '0'
);
\reg_test_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(34),
Q => reg_test(13),
R => '0'
);
\reg_test_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(35),
Q => reg_test(14),
R => '0'
);
\reg_test_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(36),
Q => reg_test(15),
R => '0'
);
\reg_test_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(22),
Q => reg_test(1),
R => '0'
);
\reg_test_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(23),
Q => reg_test(2),
R => '0'
);
\reg_test_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(24),
Q => reg_test(3),
R => '0'
);
\reg_test_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(25),
Q => reg_test(4),
R => '0'
);
\reg_test_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(26),
Q => reg_test(5),
R => '0'
);
\reg_test_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(27),
Q => reg_test(6),
R => '0'
);
\reg_test_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(28),
Q => reg_test(7),
R => '0'
);
\reg_test_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(29),
Q => reg_test(8),
R => '0'
);
\reg_test_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(30),
Q => reg_test(9),
R => '0'
);
s_den_o_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAAAAAA"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => \^sl_iport_i\(14),
I2 => \^sl_iport_i\(13),
I3 => \^sl_iport_i\(12),
I4 => s_den_o_INST_0_i_1_n_0,
O => s_den_o
);
s_den_o_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(15),
I1 => \^sl_iport_i\(16),
I2 => \^sl_iport_i\(17),
I3 => \^sl_iport_i\(18),
I4 => \^sl_iport_i\(20),
I5 => \^sl_iport_i\(19),
O => s_den_o_INST_0_i_1_n_0
);
\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_drdy_i,
I1 => reg_drdy,
O => sl_oport_o(0)
);
\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[9]\,
I1 => s_do_i(9),
I2 => reg_drdy,
O => sl_oport_o(10)
);
\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[10]\,
I1 => s_do_i(10),
I2 => reg_drdy,
O => sl_oport_o(11)
);
\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[11]\,
I1 => s_do_i(11),
I2 => reg_drdy,
O => sl_oport_o(12)
);
\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[12]\,
I1 => s_do_i(12),
I2 => reg_drdy,
O => sl_oport_o(13)
);
\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[13]\,
I1 => s_do_i(13),
I2 => reg_drdy,
O => sl_oport_o(14)
);
\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[14]\,
I1 => s_do_i(14),
I2 => reg_drdy,
O => sl_oport_o(15)
);
\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[15]\,
I1 => s_do_i(15),
I2 => reg_drdy,
O => sl_oport_o(16)
);
\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[0]\,
I1 => s_do_i(0),
I2 => reg_drdy,
O => sl_oport_o(1)
);
\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[1]\,
I1 => s_do_i(1),
I2 => reg_drdy,
O => sl_oport_o(2)
);
\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[2]\,
I1 => s_do_i(2),
I2 => reg_drdy,
O => sl_oport_o(3)
);
\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[3]\,
I1 => s_do_i(3),
I2 => reg_drdy,
O => sl_oport_o(4)
);
\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[4]\,
I1 => s_do_i(4),
I2 => reg_drdy,
O => sl_oport_o(5)
);
\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[5]\,
I1 => s_do_i(5),
I2 => reg_drdy,
O => sl_oport_o(6)
);
\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[6]\,
I1 => s_do_i(6),
I2 => reg_drdy,
O => sl_oport_o(7)
);
\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[7]\,
I1 => s_do_i(7),
I2 => reg_drdy,
O => sl_oport_o(8)
);
\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[8]\,
I1 => s_do_i(8),
I2 => reg_drdy,
O => sl_oport_o(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 );
sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 33;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
signal \<const0>\ : STD_LOGIC;
signal Bus_Data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal DECODER_INST_n_1 : STD_LOGIC;
signal DECODER_INST_n_2 : STD_LOGIC;
signal DECODER_INST_n_3 : STD_LOGIC;
signal DECODER_INST_n_4 : STD_LOGIC;
signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
signal bus_clk : STD_LOGIC;
attribute DONT_TOUCH_boolean : boolean;
attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true;
signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC;
signal bus_den : STD_LOGIC;
signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_drdy : STD_LOGIC;
signal bus_dwe : STD_LOGIC;
signal bus_rst : STD_LOGIC;
signal p_0_in : STD_LOGIC;
attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2;
attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0;
attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2;
attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1;
attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013;
attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1;
attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0;
attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7";
attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33;
attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true;
begin
probe_out0(0) <= \<const0>\;
probe_out1(0) <= \<const0>\;
probe_out10(0) <= \<const0>\;
probe_out100(0) <= \<const0>\;
probe_out101(0) <= \<const0>\;
probe_out102(0) <= \<const0>\;
probe_out103(0) <= \<const0>\;
probe_out104(0) <= \<const0>\;
probe_out105(0) <= \<const0>\;
probe_out106(0) <= \<const0>\;
probe_out107(0) <= \<const0>\;
probe_out108(0) <= \<const0>\;
probe_out109(0) <= \<const0>\;
probe_out11(0) <= \<const0>\;
probe_out110(0) <= \<const0>\;
probe_out111(0) <= \<const0>\;
probe_out112(0) <= \<const0>\;
probe_out113(0) <= \<const0>\;
probe_out114(0) <= \<const0>\;
probe_out115(0) <= \<const0>\;
probe_out116(0) <= \<const0>\;
probe_out117(0) <= \<const0>\;
probe_out118(0) <= \<const0>\;
probe_out119(0) <= \<const0>\;
probe_out12(0) <= \<const0>\;
probe_out120(0) <= \<const0>\;
probe_out121(0) <= \<const0>\;
probe_out122(0) <= \<const0>\;
probe_out123(0) <= \<const0>\;
probe_out124(0) <= \<const0>\;
probe_out125(0) <= \<const0>\;
probe_out126(0) <= \<const0>\;
probe_out127(0) <= \<const0>\;
probe_out128(0) <= \<const0>\;
probe_out129(0) <= \<const0>\;
probe_out13(0) <= \<const0>\;
probe_out130(0) <= \<const0>\;
probe_out131(0) <= \<const0>\;
probe_out132(0) <= \<const0>\;
probe_out133(0) <= \<const0>\;
probe_out134(0) <= \<const0>\;
probe_out135(0) <= \<const0>\;
probe_out136(0) <= \<const0>\;
probe_out137(0) <= \<const0>\;
probe_out138(0) <= \<const0>\;
probe_out139(0) <= \<const0>\;
probe_out14(0) <= \<const0>\;
probe_out140(0) <= \<const0>\;
probe_out141(0) <= \<const0>\;
probe_out142(0) <= \<const0>\;
probe_out143(0) <= \<const0>\;
probe_out144(0) <= \<const0>\;
probe_out145(0) <= \<const0>\;
probe_out146(0) <= \<const0>\;
probe_out147(0) <= \<const0>\;
probe_out148(0) <= \<const0>\;
probe_out149(0) <= \<const0>\;
probe_out15(0) <= \<const0>\;
probe_out150(0) <= \<const0>\;
probe_out151(0) <= \<const0>\;
probe_out152(0) <= \<const0>\;
probe_out153(0) <= \<const0>\;
probe_out154(0) <= \<const0>\;
probe_out155(0) <= \<const0>\;
probe_out156(0) <= \<const0>\;
probe_out157(0) <= \<const0>\;
probe_out158(0) <= \<const0>\;
probe_out159(0) <= \<const0>\;
probe_out16(0) <= \<const0>\;
probe_out160(0) <= \<const0>\;
probe_out161(0) <= \<const0>\;
probe_out162(0) <= \<const0>\;
probe_out163(0) <= \<const0>\;
probe_out164(0) <= \<const0>\;
probe_out165(0) <= \<const0>\;
probe_out166(0) <= \<const0>\;
probe_out167(0) <= \<const0>\;
probe_out168(0) <= \<const0>\;
probe_out169(0) <= \<const0>\;
probe_out17(0) <= \<const0>\;
probe_out170(0) <= \<const0>\;
probe_out171(0) <= \<const0>\;
probe_out172(0) <= \<const0>\;
probe_out173(0) <= \<const0>\;
probe_out174(0) <= \<const0>\;
probe_out175(0) <= \<const0>\;
probe_out176(0) <= \<const0>\;
probe_out177(0) <= \<const0>\;
probe_out178(0) <= \<const0>\;
probe_out179(0) <= \<const0>\;
probe_out18(0) <= \<const0>\;
probe_out180(0) <= \<const0>\;
probe_out181(0) <= \<const0>\;
probe_out182(0) <= \<const0>\;
probe_out183(0) <= \<const0>\;
probe_out184(0) <= \<const0>\;
probe_out185(0) <= \<const0>\;
probe_out186(0) <= \<const0>\;
probe_out187(0) <= \<const0>\;
probe_out188(0) <= \<const0>\;
probe_out189(0) <= \<const0>\;
probe_out19(0) <= \<const0>\;
probe_out190(0) <= \<const0>\;
probe_out191(0) <= \<const0>\;
probe_out192(0) <= \<const0>\;
probe_out193(0) <= \<const0>\;
probe_out194(0) <= \<const0>\;
probe_out195(0) <= \<const0>\;
probe_out196(0) <= \<const0>\;
probe_out197(0) <= \<const0>\;
probe_out198(0) <= \<const0>\;
probe_out199(0) <= \<const0>\;
probe_out2(0) <= \<const0>\;
probe_out20(0) <= \<const0>\;
probe_out200(0) <= \<const0>\;
probe_out201(0) <= \<const0>\;
probe_out202(0) <= \<const0>\;
probe_out203(0) <= \<const0>\;
probe_out204(0) <= \<const0>\;
probe_out205(0) <= \<const0>\;
probe_out206(0) <= \<const0>\;
probe_out207(0) <= \<const0>\;
probe_out208(0) <= \<const0>\;
probe_out209(0) <= \<const0>\;
probe_out21(0) <= \<const0>\;
probe_out210(0) <= \<const0>\;
probe_out211(0) <= \<const0>\;
probe_out212(0) <= \<const0>\;
probe_out213(0) <= \<const0>\;
probe_out214(0) <= \<const0>\;
probe_out215(0) <= \<const0>\;
probe_out216(0) <= \<const0>\;
probe_out217(0) <= \<const0>\;
probe_out218(0) <= \<const0>\;
probe_out219(0) <= \<const0>\;
probe_out22(0) <= \<const0>\;
probe_out220(0) <= \<const0>\;
probe_out221(0) <= \<const0>\;
probe_out222(0) <= \<const0>\;
probe_out223(0) <= \<const0>\;
probe_out224(0) <= \<const0>\;
probe_out225(0) <= \<const0>\;
probe_out226(0) <= \<const0>\;
probe_out227(0) <= \<const0>\;
probe_out228(0) <= \<const0>\;
probe_out229(0) <= \<const0>\;
probe_out23(0) <= \<const0>\;
probe_out230(0) <= \<const0>\;
probe_out231(0) <= \<const0>\;
probe_out232(0) <= \<const0>\;
probe_out233(0) <= \<const0>\;
probe_out234(0) <= \<const0>\;
probe_out235(0) <= \<const0>\;
probe_out236(0) <= \<const0>\;
probe_out237(0) <= \<const0>\;
probe_out238(0) <= \<const0>\;
probe_out239(0) <= \<const0>\;
probe_out24(0) <= \<const0>\;
probe_out240(0) <= \<const0>\;
probe_out241(0) <= \<const0>\;
probe_out242(0) <= \<const0>\;
probe_out243(0) <= \<const0>\;
probe_out244(0) <= \<const0>\;
probe_out245(0) <= \<const0>\;
probe_out246(0) <= \<const0>\;
probe_out247(0) <= \<const0>\;
probe_out248(0) <= \<const0>\;
probe_out249(0) <= \<const0>\;
probe_out25(0) <= \<const0>\;
probe_out250(0) <= \<const0>\;
probe_out251(0) <= \<const0>\;
probe_out252(0) <= \<const0>\;
probe_out253(0) <= \<const0>\;
probe_out254(0) <= \<const0>\;
probe_out255(0) <= \<const0>\;
probe_out26(0) <= \<const0>\;
probe_out27(0) <= \<const0>\;
probe_out28(0) <= \<const0>\;
probe_out29(0) <= \<const0>\;
probe_out3(0) <= \<const0>\;
probe_out30(0) <= \<const0>\;
probe_out31(0) <= \<const0>\;
probe_out32(0) <= \<const0>\;
probe_out33(0) <= \<const0>\;
probe_out34(0) <= \<const0>\;
probe_out35(0) <= \<const0>\;
probe_out36(0) <= \<const0>\;
probe_out37(0) <= \<const0>\;
probe_out38(0) <= \<const0>\;
probe_out39(0) <= \<const0>\;
probe_out4(0) <= \<const0>\;
probe_out40(0) <= \<const0>\;
probe_out41(0) <= \<const0>\;
probe_out42(0) <= \<const0>\;
probe_out43(0) <= \<const0>\;
probe_out44(0) <= \<const0>\;
probe_out45(0) <= \<const0>\;
probe_out46(0) <= \<const0>\;
probe_out47(0) <= \<const0>\;
probe_out48(0) <= \<const0>\;
probe_out49(0) <= \<const0>\;
probe_out5(0) <= \<const0>\;
probe_out50(0) <= \<const0>\;
probe_out51(0) <= \<const0>\;
probe_out52(0) <= \<const0>\;
probe_out53(0) <= \<const0>\;
probe_out54(0) <= \<const0>\;
probe_out55(0) <= \<const0>\;
probe_out56(0) <= \<const0>\;
probe_out57(0) <= \<const0>\;
probe_out58(0) <= \<const0>\;
probe_out59(0) <= \<const0>\;
probe_out6(0) <= \<const0>\;
probe_out60(0) <= \<const0>\;
probe_out61(0) <= \<const0>\;
probe_out62(0) <= \<const0>\;
probe_out63(0) <= \<const0>\;
probe_out64(0) <= \<const0>\;
probe_out65(0) <= \<const0>\;
probe_out66(0) <= \<const0>\;
probe_out67(0) <= \<const0>\;
probe_out68(0) <= \<const0>\;
probe_out69(0) <= \<const0>\;
probe_out7(0) <= \<const0>\;
probe_out70(0) <= \<const0>\;
probe_out71(0) <= \<const0>\;
probe_out72(0) <= \<const0>\;
probe_out73(0) <= \<const0>\;
probe_out74(0) <= \<const0>\;
probe_out75(0) <= \<const0>\;
probe_out76(0) <= \<const0>\;
probe_out77(0) <= \<const0>\;
probe_out78(0) <= \<const0>\;
probe_out79(0) <= \<const0>\;
probe_out8(0) <= \<const0>\;
probe_out80(0) <= \<const0>\;
probe_out81(0) <= \<const0>\;
probe_out82(0) <= \<const0>\;
probe_out83(0) <= \<const0>\;
probe_out84(0) <= \<const0>\;
probe_out85(0) <= \<const0>\;
probe_out86(0) <= \<const0>\;
probe_out87(0) <= \<const0>\;
probe_out88(0) <= \<const0>\;
probe_out89(0) <= \<const0>\;
probe_out9(0) <= \<const0>\;
probe_out90(0) <= \<const0>\;
probe_out91(0) <= \<const0>\;
probe_out92(0) <= \<const0>\;
probe_out93(0) <= \<const0>\;
probe_out94(0) <= \<const0>\;
probe_out95(0) <= \<const0>\;
probe_out96(0) <= \<const0>\;
probe_out97(0) <= \<const0>\;
probe_out98(0) <= \<const0>\;
probe_out99(0) <= \<const0>\;
DECODER_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
port map (
\Bus_Data_out_reg[11]\(11 downto 0) => Bus_Data_out(11 downto 0),
E(0) => DECODER_INST_n_4,
Q(15) => \bus_data_int_reg_n_0_[15]\,
Q(14) => \bus_data_int_reg_n_0_[14]\,
Q(13) => \bus_data_int_reg_n_0_[13]\,
Q(12) => \bus_data_int_reg_n_0_[12]\,
Q(11) => \bus_data_int_reg_n_0_[11]\,
Q(10) => \bus_data_int_reg_n_0_[10]\,
Q(9) => \bus_data_int_reg_n_0_[9]\,
Q(8) => \bus_data_int_reg_n_0_[8]\,
Q(7) => \bus_data_int_reg_n_0_[7]\,
Q(6) => \bus_data_int_reg_n_0_[6]\,
Q(5) => \bus_data_int_reg_n_0_[5]\,
Q(4) => \bus_data_int_reg_n_0_[4]\,
Q(3) => \bus_data_int_reg_n_0_[3]\,
Q(2) => \bus_data_int_reg_n_0_[2]\,
Q(1) => p_0_in,
Q(0) => \bus_data_int_reg_n_0_[0]\,
\out\ => bus_clk,
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_den_o => bus_den,
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en_reg[4]_0\ => DECODER_INST_n_1,
\wr_en_reg[4]_1\ => DECODER_INST_n_2,
\wr_en_reg[4]_2\ => DECODER_INST_n_3
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
PROBE_IN_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
port map (
D(3) => probe_in3(0),
D(2) => probe_in2(0),
D(1) => probe_in1(0),
D(0) => probe_in0(0),
E(0) => DECODER_INST_n_4,
Q(11 downto 0) => Bus_Data_out(11 downto 0),
clk => clk,
\out\ => bus_clk,
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en[4]_i_3\ => DECODER_INST_n_1,
\wr_en[4]_i_4\ => DECODER_INST_n_3,
\wr_en[4]_i_5\ => DECODER_INST_n_2
);
U_XSDB_SLAVE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
port map (
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_dclk_o => bus_clk,
s_den_o => bus_den,
s_di_o(15 downto 0) => bus_di(15 downto 0),
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
sl_iport_i(36 downto 0) => sl_iport0(36 downto 0),
sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
);
\bus_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(0),
Q => \bus_data_int_reg_n_0_[0]\,
R => '0'
);
\bus_data_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(10),
Q => \bus_data_int_reg_n_0_[10]\,
R => '0'
);
\bus_data_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(11),
Q => \bus_data_int_reg_n_0_[11]\,
R => '0'
);
\bus_data_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(12),
Q => \bus_data_int_reg_n_0_[12]\,
R => '0'
);
\bus_data_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(13),
Q => \bus_data_int_reg_n_0_[13]\,
R => '0'
);
\bus_data_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(14),
Q => \bus_data_int_reg_n_0_[14]\,
R => '0'
);
\bus_data_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(15),
Q => \bus_data_int_reg_n_0_[15]\,
R => '0'
);
\bus_data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(1),
Q => p_0_in,
R => '0'
);
\bus_data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(2),
Q => \bus_data_int_reg_n_0_[2]\,
R => '0'
);
\bus_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(3),
Q => \bus_data_int_reg_n_0_[3]\,
R => '0'
);
\bus_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(4),
Q => \bus_data_int_reg_n_0_[4]\,
R => '0'
);
\bus_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(5),
Q => \bus_data_int_reg_n_0_[5]\,
R => '0'
);
\bus_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(6),
Q => \bus_data_int_reg_n_0_[6]\,
R => '0'
);
\bus_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(7),
Q => \bus_data_int_reg_n_0_[7]\,
R => '0'
);
\bus_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(8),
Q => \bus_data_int_reg_n_0_[8]\,
R => '0'
);
\bus_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(9),
Q => \bus_data_int_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio_0,vio,{}";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_probe_out0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of inst : label is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of inst : label is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of inst : label is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of inst : label is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of inst : label is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of inst : label is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of inst : label is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of inst : label is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of inst : label is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of inst : label is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of inst : label is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of inst : label is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of inst : label is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of inst : label is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of inst : label is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of inst : label is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of inst : label is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of inst : label is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of inst : label is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of inst : label is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of inst : label is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of inst : label is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of inst : label is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of inst : label is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of inst : label is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of inst : label is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of inst : label is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of inst : label is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of inst : label is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of inst : label is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of inst : label is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of inst : label is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of inst : label is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of inst : label is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of inst : label is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of inst : label is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of inst : label is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of inst : label is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of inst : label is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of inst : label is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of inst : label is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of inst : label is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of inst : label is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of inst : label is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of inst : label is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of inst : label is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of inst : label is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of inst : label is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of inst : label is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of inst : label is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of inst : label is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of inst : label is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of inst : label is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of inst : label is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of inst : label is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of inst : label is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of inst : label is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of inst : label is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of inst : label is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of inst : label is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of inst : label is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of inst : label is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of inst : label is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of inst : label is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of inst : label is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of inst : label is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of inst : label is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of inst : label is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of inst : label is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of inst : label is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of inst : label is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of inst : label is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of inst : label is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of inst : label is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of inst : label is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of inst : label is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of inst : label is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of inst : label is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of inst : label is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of inst : label is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of inst : label is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of inst : label is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of inst : label is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of inst : label is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of inst : label is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of inst : label is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of inst : label is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of inst : label is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of inst : label is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of inst : label is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of inst : label is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of inst : label is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of inst : label is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of inst : label is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of inst : label is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of inst : label is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of inst : label is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of inst : label is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of inst : label is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of inst : label is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of inst : label is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of inst : label is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of inst : label is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of inst : label is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of inst : label is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of inst : label is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of inst : label is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of inst : label is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of inst : label is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of inst : label is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of inst : label is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of inst : label is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of inst : label is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of inst : label is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of inst : label is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of inst : label is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of inst : label is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of inst : label is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of inst : label is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of inst : label is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of inst : label is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of inst : label is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of inst : label is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of inst : label is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of inst : label is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of inst : label is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of inst : label is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of inst : label is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of inst : label is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of inst : label is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of inst : label is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of inst : label is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of inst : label is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of inst : label is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of inst : label is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of inst : label is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of inst : label is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of inst : label is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of inst : label is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of inst : label is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of inst : label is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of inst : label is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of inst : label is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of inst : label is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of inst : label is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of inst : label is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of inst : label is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of inst : label is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of inst : label is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of inst : label is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of inst : label is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of inst : label is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of inst : label is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of inst : label is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of inst : label is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of inst : label is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of inst : label is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of inst : label is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of inst : label is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of inst : label is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of inst : label is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of inst : label is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of inst : label is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of inst : label is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of inst : label is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of inst : label is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of inst : label is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of inst : label is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of inst : label is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of inst : label is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of inst : label is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of inst : label is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of inst : label is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of inst : label is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of inst : label is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of inst : label is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of inst : label is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of inst : label is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of inst : label is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of inst : label is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of inst : label is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of inst : label is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of inst : label is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of inst : label is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of inst : label is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of inst : label is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of inst : label is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of inst : label is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of inst : label is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of inst : label is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of inst : label is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of inst : label is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of inst : label is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of inst : label is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of inst : label is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of inst : label is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of inst : label is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of inst : label is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of inst : label is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of inst : label is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of inst : label is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of inst : label is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of inst : label is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of inst : label is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of inst : label is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of inst : label is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of inst : label is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of inst : label is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of inst : label is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of inst : label is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of inst : label is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of inst : label is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of inst : label is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of inst : label is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of inst : label is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of inst : label is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of inst : label is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of inst : label is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of inst : label is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of inst : label is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of inst : label is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of inst : label is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of inst : label is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of inst : label is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of inst : label is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of inst : label is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of inst : label is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of inst : label is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of inst : label is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of inst : label is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of inst : label is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of inst : label is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of inst : label is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of inst : label is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of inst : label is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of inst : label is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of inst : label is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of inst : label is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of inst : label is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of inst : label is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of inst : label is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of inst : label is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of inst : label is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of inst : label is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of inst : label is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of inst : label is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of inst : label is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of inst : label is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of inst : label is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of inst : label is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of inst : label is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of inst : label is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of inst : label is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of inst : label is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of inst : label is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of inst : label is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of inst : label is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of inst : label is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of inst : label is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of inst : label is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of inst : label is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of inst : label is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of inst : label is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of inst : label is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of inst : label is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of inst : label is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of inst : label is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of inst : label is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of inst : label is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of inst : label is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of inst : label is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of inst : label is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of inst : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of inst : label is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of inst : label is std.standard.true;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 0;
attribute syn_noprune : string;
attribute syn_noprune of inst : label is "1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
port map (
clk => clk,
probe_in0(0) => probe_in0(0),
probe_in1(0) => probe_in1(0),
probe_in10(0) => '0',
probe_in100(0) => '0',
probe_in101(0) => '0',
probe_in102(0) => '0',
probe_in103(0) => '0',
probe_in104(0) => '0',
probe_in105(0) => '0',
probe_in106(0) => '0',
probe_in107(0) => '0',
probe_in108(0) => '0',
probe_in109(0) => '0',
probe_in11(0) => '0',
probe_in110(0) => '0',
probe_in111(0) => '0',
probe_in112(0) => '0',
probe_in113(0) => '0',
probe_in114(0) => '0',
probe_in115(0) => '0',
probe_in116(0) => '0',
probe_in117(0) => '0',
probe_in118(0) => '0',
probe_in119(0) => '0',
probe_in12(0) => '0',
probe_in120(0) => '0',
probe_in121(0) => '0',
probe_in122(0) => '0',
probe_in123(0) => '0',
probe_in124(0) => '0',
probe_in125(0) => '0',
probe_in126(0) => '0',
probe_in127(0) => '0',
probe_in128(0) => '0',
probe_in129(0) => '0',
probe_in13(0) => '0',
probe_in130(0) => '0',
probe_in131(0) => '0',
probe_in132(0) => '0',
probe_in133(0) => '0',
probe_in134(0) => '0',
probe_in135(0) => '0',
probe_in136(0) => '0',
probe_in137(0) => '0',
probe_in138(0) => '0',
probe_in139(0) => '0',
probe_in14(0) => '0',
probe_in140(0) => '0',
probe_in141(0) => '0',
probe_in142(0) => '0',
probe_in143(0) => '0',
probe_in144(0) => '0',
probe_in145(0) => '0',
probe_in146(0) => '0',
probe_in147(0) => '0',
probe_in148(0) => '0',
probe_in149(0) => '0',
probe_in15(0) => '0',
probe_in150(0) => '0',
probe_in151(0) => '0',
probe_in152(0) => '0',
probe_in153(0) => '0',
probe_in154(0) => '0',
probe_in155(0) => '0',
probe_in156(0) => '0',
probe_in157(0) => '0',
probe_in158(0) => '0',
probe_in159(0) => '0',
probe_in16(0) => '0',
probe_in160(0) => '0',
probe_in161(0) => '0',
probe_in162(0) => '0',
probe_in163(0) => '0',
probe_in164(0) => '0',
probe_in165(0) => '0',
probe_in166(0) => '0',
probe_in167(0) => '0',
probe_in168(0) => '0',
probe_in169(0) => '0',
probe_in17(0) => '0',
probe_in170(0) => '0',
probe_in171(0) => '0',
probe_in172(0) => '0',
probe_in173(0) => '0',
probe_in174(0) => '0',
probe_in175(0) => '0',
probe_in176(0) => '0',
probe_in177(0) => '0',
probe_in178(0) => '0',
probe_in179(0) => '0',
probe_in18(0) => '0',
probe_in180(0) => '0',
probe_in181(0) => '0',
probe_in182(0) => '0',
probe_in183(0) => '0',
probe_in184(0) => '0',
probe_in185(0) => '0',
probe_in186(0) => '0',
probe_in187(0) => '0',
probe_in188(0) => '0',
probe_in189(0) => '0',
probe_in19(0) => '0',
probe_in190(0) => '0',
probe_in191(0) => '0',
probe_in192(0) => '0',
probe_in193(0) => '0',
probe_in194(0) => '0',
probe_in195(0) => '0',
probe_in196(0) => '0',
probe_in197(0) => '0',
probe_in198(0) => '0',
probe_in199(0) => '0',
probe_in2(0) => probe_in2(0),
probe_in20(0) => '0',
probe_in200(0) => '0',
probe_in201(0) => '0',
probe_in202(0) => '0',
probe_in203(0) => '0',
probe_in204(0) => '0',
probe_in205(0) => '0',
probe_in206(0) => '0',
probe_in207(0) => '0',
probe_in208(0) => '0',
probe_in209(0) => '0',
probe_in21(0) => '0',
probe_in210(0) => '0',
probe_in211(0) => '0',
probe_in212(0) => '0',
probe_in213(0) => '0',
probe_in214(0) => '0',
probe_in215(0) => '0',
probe_in216(0) => '0',
probe_in217(0) => '0',
probe_in218(0) => '0',
probe_in219(0) => '0',
probe_in22(0) => '0',
probe_in220(0) => '0',
probe_in221(0) => '0',
probe_in222(0) => '0',
probe_in223(0) => '0',
probe_in224(0) => '0',
probe_in225(0) => '0',
probe_in226(0) => '0',
probe_in227(0) => '0',
probe_in228(0) => '0',
probe_in229(0) => '0',
probe_in23(0) => '0',
probe_in230(0) => '0',
probe_in231(0) => '0',
probe_in232(0) => '0',
probe_in233(0) => '0',
probe_in234(0) => '0',
probe_in235(0) => '0',
probe_in236(0) => '0',
probe_in237(0) => '0',
probe_in238(0) => '0',
probe_in239(0) => '0',
probe_in24(0) => '0',
probe_in240(0) => '0',
probe_in241(0) => '0',
probe_in242(0) => '0',
probe_in243(0) => '0',
probe_in244(0) => '0',
probe_in245(0) => '0',
probe_in246(0) => '0',
probe_in247(0) => '0',
probe_in248(0) => '0',
probe_in249(0) => '0',
probe_in25(0) => '0',
probe_in250(0) => '0',
probe_in251(0) => '0',
probe_in252(0) => '0',
probe_in253(0) => '0',
probe_in254(0) => '0',
probe_in255(0) => '0',
probe_in26(0) => '0',
probe_in27(0) => '0',
probe_in28(0) => '0',
probe_in29(0) => '0',
probe_in3(0) => probe_in3(0),
probe_in30(0) => '0',
probe_in31(0) => '0',
probe_in32(0) => '0',
probe_in33(0) => '0',
probe_in34(0) => '0',
probe_in35(0) => '0',
probe_in36(0) => '0',
probe_in37(0) => '0',
probe_in38(0) => '0',
probe_in39(0) => '0',
probe_in4(0) => '0',
probe_in40(0) => '0',
probe_in41(0) => '0',
probe_in42(0) => '0',
probe_in43(0) => '0',
probe_in44(0) => '0',
probe_in45(0) => '0',
probe_in46(0) => '0',
probe_in47(0) => '0',
probe_in48(0) => '0',
probe_in49(0) => '0',
probe_in5(0) => '0',
probe_in50(0) => '0',
probe_in51(0) => '0',
probe_in52(0) => '0',
probe_in53(0) => '0',
probe_in54(0) => '0',
probe_in55(0) => '0',
probe_in56(0) => '0',
probe_in57(0) => '0',
probe_in58(0) => '0',
probe_in59(0) => '0',
probe_in6(0) => '0',
probe_in60(0) => '0',
probe_in61(0) => '0',
probe_in62(0) => '0',
probe_in63(0) => '0',
probe_in64(0) => '0',
probe_in65(0) => '0',
probe_in66(0) => '0',
probe_in67(0) => '0',
probe_in68(0) => '0',
probe_in69(0) => '0',
probe_in7(0) => '0',
probe_in70(0) => '0',
probe_in71(0) => '0',
probe_in72(0) => '0',
probe_in73(0) => '0',
probe_in74(0) => '0',
probe_in75(0) => '0',
probe_in76(0) => '0',
probe_in77(0) => '0',
probe_in78(0) => '0',
probe_in79(0) => '0',
probe_in8(0) => '0',
probe_in80(0) => '0',
probe_in81(0) => '0',
probe_in82(0) => '0',
probe_in83(0) => '0',
probe_in84(0) => '0',
probe_in85(0) => '0',
probe_in86(0) => '0',
probe_in87(0) => '0',
probe_in88(0) => '0',
probe_in89(0) => '0',
probe_in9(0) => '0',
probe_in90(0) => '0',
probe_in91(0) => '0',
probe_in92(0) => '0',
probe_in93(0) => '0',
probe_in94(0) => '0',
probe_in95(0) => '0',
probe_in96(0) => '0',
probe_in97(0) => '0',
probe_in98(0) => '0',
probe_in99(0) => '0',
probe_out0(0) => NLW_inst_probe_out0_UNCONNECTED(0),
probe_out1(0) => NLW_inst_probe_out1_UNCONNECTED(0),
probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0),
probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
);
end STRUCTURE;
|
mit
|
6a2029e87bb8a3de8f6f85e8c030ff3b
| 0.709641 | 2.992574 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/serial/rs_232.vhd
| 1 | 3,316 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : rs_232.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : rs_232
-- ARCHITECTURE : structure
--=============================================================================
-- AUTORS(s) : Barbosa, F
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : NOV 29, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for rs_232
--=============================================================================
entity rs_232 is
port (
-- async receiver/transmitter com ports
clk : in std_logic;
txStart : in std_logic;
txData : in std_logic_vector(7 downto 0);
rxD : in std_logic;
rxReady : out std_logic;
rxData : out std_logic_vector(7 downto 0);
txBusy : out std_logic;
txD : out std_logic
);
end rs_232;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture structure of rs_232 is
component async_receiver
port (
clk : in std_logic;
RxD : in std_logic;
RxD_data : out std_logic_vector(7 downto 0);
RxD_data_ready : out std_logic
);
end component;
component async_transmitter
port (
clk : in std_logic;
TxD_start : in std_logic;
TxD_data : in std_logic_vector(7 downto 0);
TxD : out std_logic;
TxD_busy : out std_logic
);
end component;
--=============================================================================
-- architecture begin
--=============================================================================
begin
receiver : async_receiver
port map (
clk => clk,
RxD => rxD,
RxD_data => rxData,
RxD_data_ready => rxReady
);
transmitter : async_transmitter
port map (
clk => clk,
TxD_start => txStart,
TxD_data => txData,
TxD => txD,
TxD_busy => txBusy
);
end structure;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
f259b459185f8f2bd3c1f700205b45fa
| 0.4424 | 4.240409 | false | false | false | false |
unhold/hdl
|
vhdl/codec_8b10b_pack.vhd
| 1 | 5,185 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package codec_8b10b_pack is
subtype b8_t is std_ulogic_vector(7 downto 0);
subtype b10_t is std_ulogic_vector(9 downto 0);
type rd_t is (undef, plus1, minus1);
procedure data_8b10b(
b8_i : in b8_t;
rd_i : in rd_t;
b10_o : out b10_t;
rd_o : out rd_t);
end;
package body codec_8b10b_pack is
type rd_change_t is (undef, minus2, unchanged, plus2);
function to_rd_change(n : integer) return rd_change_t is
begin
case n is
when -2 => return minus2;
when 0 => return unchanged;
when 2 => return plus2;
when others => return undef;
end case;
end;
function "+"(rd : rd_t; rd_change : rd_change_t) return rd_t is
begin
case rd_change is
when unchanged => return rd;
when minus2 =>
if rd = plus1 then return minus1;
else return undef;
end if;
when plus2 =>
if rd = minus1 then return plus1;
else return undef;
end if;
when undef => return undef;
end case;
end;
function rd_change(d : std_ulogic_vector) return rd_change_t is
variable n : integer;
begin
n := 0;
for i in d'range loop
case to_x01(d(i)) is
when '0' => n := n - 1;
when '1' => n := n + 1;
when others =>
return undef;
end case;
end loop;
return to_rd_change(n);
end;
subtype b5_t is std_ulogic_vector(4 downto 0);
subtype b6_t is std_ulogic_vector(5 downto 0);
type code_5b6b_t is array(0 to 1) of b6_t;
type table_5b6b_t is array(0 to 31) of code_5b6b_t;
constant table_5b6b : table_5b6b_t := (
0 => (0 => "100111", 1 => "011000"),
1 => (0 => "011101", 1 => "100010"),
2 => (0 => "101101", 1 => "010010"),
3 => (0 => "110001", 1 => "110001"),
4 => (0 => "110101", 1 => "001010"),
5 => (0 => "101001", 1 => "101001"),
6 => (0 => "011001", 1 => "011001"),
7 => (0 => "111000", 1 => "000111"),
8 => (0 => "111001", 1 => "000110"),
9 => (0 => "100101", 1 => "100101"),
10 => (0 => "010101", 1 => "010101"),
11 => (0 => "110100", 1 => "110100"),
12 => (0 => "001101", 1 => "001101"),
13 => (0 => "101100", 1 => "101100"),
14 => (0 => "011100", 1 => "011100"),
15 => (0 => "010111", 1 => "101000"),
16 => (0 => "011011", 1 => "100100"),
17 => (0 => "100011", 1 => "100011"),
18 => (0 => "010011", 1 => "010011"),
19 => (0 => "110010", 1 => "110010"),
20 => (0 => "001011", 1 => "001011"),
21 => (0 => "101010", 1 => "101010"),
22 => (0 => "011010", 1 => "011010"),
23 => (0 => "111010", 1 => "000101"),
24 => (0 => "110011", 1 => "001100"),
25 => (0 => "100110", 1 => "100110"),
26 => (0 => "010110", 1 => "010110"),
27 => (0 => "110110", 1 => "001001"),
28 => (0 => "001110", 1 => "001110"),
29 => (0 => "101110", 1 => "010001"),
30 => (0 => "011110", 1 => "100001"),
31 => (0 => "101011", 1 => "010100"));
procedure data_5b6b(
b5_i : in b5_t;
rd_i : in rd_t;
b6_o : out b6_t;
rd_o : out rd_t) is
variable b6 : b6_t;
begin
case rd_i is
when minus1 => b6 := table_5b6b(to_integer(unsigned(b5_i)))(0);
when plus1 => b6 := table_5b6b(to_integer(unsigned(b5_i)))(1);
when others =>
b6_o := (others => 'X');
rd_o := undef;
return;
end case;
b6_o := b6;
rd_o := rd_i + rd_change(b6);
end;
function data_6b5b(b6_i : in b6_t) return b5_t is
begin
for i in table_5b6b'range loop
if b6_i = table_5b6b(i)(0) or b6_i = table_5b6b(i)(1) then
return b5_t(to_unsigned(i, 5));
end if;
end loop;
return (others => 'X');
end;
subtype b3_t is std_ulogic_vector(2 downto 0);
subtype b4_t is std_ulogic_vector(3 downto 0);
type code_3b4b_t is array(0 to 1) of b4_t;
type table_3b4b_t is array(0 to 7) of code_3b4b_t;
constant table_3b4b : table_3b4b_t := (
0 => (0 => "1011", 1 => "0100"),
1 => (0 => "1001", 1 => "1001"),
2 => (0 => "0101", 1 => "0101"),
3 => (0 => "1100", 1 => "0011"),
4 => (0 => "1101", 1 => "0010"),
5 => (0 => "1010", 1 => "1010"),
6 => (0 => "0110", 1 => "0110"),
-- 7 is a special case, handle in code
7 => (0 => "XXXX", 1 => "XXXX"));
procedure data_3b4b(
b3_i : in b3_t;
b6_i : in b6_t;
rd_i : in rd_t;
b4_o : out b4_t;
rd_o : out rd_t) is
variable b4 : b4_t;
begin
b4 := (others => 'X');
if not is_x(b3_i) then
case rd_i is
when minus1 =>
if b3_i = "111" then
case b6_i(0) is
when '0' => b4 := "1110";
when '1' => b4 := "0111";
when others => null;
end case;
else
b4 := table_3b4b(to_integer(unsigned(b3_i)))(0);
end if;
when plus1 =>
if b3_i = "111" then
case b6_i(0) is
when '0' => b4 := "1000";
when '1' => b4 := "0001";
when others => null;
end case;
else
b4 := table_3b4b(to_integer(unsigned(b3_i)))(1);
end if;
when others => null;
end case;
end if;
b4_o := b4;
rd_o := rd_i + rd_change(b4);
end procedure;
procedure data_8b10b(
b8_i : in b8_t;
rd_i : in rd_t;
b10_o : out b10_t;
rd_o : out rd_t) is
variable b6 : b6_t;
variable b4 : b4_t;
variable rd : rd_t;
begin
data_5b6b(b8_i(4 downto 0), rd_i, b6, rd);
data_3b4b(b8_i(7 downto 5), b6, rd, b4, rd_o);
b10_o := b6 & b4;
end;
end;
|
gpl-3.0
|
935cb251f7db108b15275061d55900f1
| 0.523819 | 2.383908 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.srcs/sources_1/ip/fifo_generator_rx_inst/fifo_generator_rx_inst_sim_netlist.vhdl
| 1 | 336,266 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:48:22 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/fifo_generator_rx_inst/fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_generator_rx_inst_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => Q(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 2) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(1 downto 0) => B"00",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => din(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 4),
DOBDO(3 downto 0) => dout(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 6) => B"00000000000000000000000000",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare is
port (
ram_full_comb : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare : entity is "compare";
end fifo_generator_rx_inst_compare;
architecture STRUCTURE of fifo_generator_rx_inst_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0055000000FFC0C0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => wr_rst_busy,
I4 => \out\,
I5 => E(0),
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare_3 : entity is "compare";
end fifo_generator_rx_inst_compare_3;
architecture STRUCTURE of fifo_generator_rx_inst_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg_0(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare_4 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare_4 : entity is "compare";
end fifo_generator_rx_inst_compare_4;
architecture STRUCTURE of fifo_generator_rx_inst_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gcc0.gc0.count_d1_reg[10]\,
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_compare_5 : entity is "compare";
end fifo_generator_rx_inst_compare_5;
architecture STRUCTURE of fifo_generator_rx_inst_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_generator_rx_inst_rd_bin_cntr;
architecture STRUCTURE of fifo_generator_rx_inst_rd_bin_cntr is
signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
D(11 downto 0) <= \^d\(11 downto 0);
\gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(3),
O => \gc0.count[0]_i_2_n_0\
);
\gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(2),
O => \gc0.count[0]_i_3_n_0\
);
\gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(1),
O => \gc0.count[0]_i_4_n_0\
);
\gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^d\(0),
O => \gc0.count[0]_i_5_n_0\
);
\gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(7),
O => \gc0.count[4]_i_2_n_0\
);
\gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(6),
O => \gc0.count[4]_i_3_n_0\
);
\gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(5),
O => \gc0.count[4]_i_4_n_0\
);
\gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(4),
O => \gc0.count[4]_i_5_n_0\
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(11),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(10),
O => \gc0.count[8]_i_3_n_0\
);
\gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(9),
O => \gc0.count[8]_i_4_n_0\
);
\gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(8),
O => \gc0.count[8]_i_5_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(0),
Q => Q(0)
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(10),
Q => Q(10)
);
\gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(11),
Q => Q(11)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(1),
Q => Q(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(2),
Q => Q(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(3),
Q => Q(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(4),
Q => Q(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(5),
Q => Q(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(6),
Q => Q(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(7),
Q => Q(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(8),
Q => Q(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(9),
Q => Q(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
D => \gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^d\(0)
);
\gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gc0.count_reg[0]_i_1_n_4\,
O(2) => \gc0.count_reg[0]_i_1_n_5\,
O(1) => \gc0.count_reg[0]_i_1_n_6\,
O(0) => \gc0.count_reg[0]_i_1_n_7\,
S(3) => \gc0.count[0]_i_2_n_0\,
S(2) => \gc0.count[0]_i_3_n_0\,
S(1) => \gc0.count[0]_i_4_n_0\,
S(0) => \gc0.count[0]_i_5_n_0\
);
\gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_5\,
Q => \^d\(10)
);
\gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_4\,
Q => \^d\(11)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_6\,
Q => \^d\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_5\,
Q => \^d\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_4\,
Q => \^d\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_7\,
Q => \^d\(4)
);
\gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[4]_i_1_n_4\,
O(2) => \gc0.count_reg[4]_i_1_n_5\,
O(1) => \gc0.count_reg[4]_i_1_n_6\,
O(0) => \gc0.count_reg[4]_i_1_n_7\,
S(3) => \gc0.count[4]_i_2_n_0\,
S(2) => \gc0.count[4]_i_3_n_0\,
S(1) => \gc0.count[4]_i_4_n_0\,
S(0) => \gc0.count[4]_i_5_n_0\
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_6\,
Q => \^d\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_5\,
Q => \^d\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_4\,
Q => \^d\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_7\,
Q => \^d\(8)
);
\gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[8]_i_1_n_4\,
O(2) => \gc0.count_reg[8]_i_1_n_5\,
O(1) => \gc0.count_reg[8]_i_1_n_6\,
O(0) => \gc0.count_reg[8]_i_1_n_7\,
S(3) => \gc0.count[8]_i_2_n_0\,
S(2) => \gc0.count[8]_i_3_n_0\,
S(1) => \gc0.count[8]_i_4_n_0\,
S(0) => \gc0.count[8]_i_5_n_0\
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_6\,
Q => \^d\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff_0;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff_1;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_generator_rx_inst_synchronizer_ff_2;
architecture STRUCTURE of fifo_generator_rx_inst_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_generator_rx_inst_wr_bin_cntr;
architecture STRUCTURE of fifo_generator_rx_inst_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gcc0.gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\gcc0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(3),
O => \gcc0.gc0.count[0]_i_2_n_0\
);
\gcc0.gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(2),
O => \gcc0.gc0.count[0]_i_3_n_0\
);
\gcc0.gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(1),
O => \gcc0.gc0.count[0]_i_4_n_0\
);
\gcc0.gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(7),
O => \gcc0.gc0.count[4]_i_2_n_0\
);
\gcc0.gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(6),
O => \gcc0.gc0.count[4]_i_3_n_0\
);
\gcc0.gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(5),
O => \gcc0.gc0.count[4]_i_4_n_0\
);
\gcc0.gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(4),
O => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(11),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(10),
O => \gcc0.gc0.count[8]_i_3_n_0\
);
\gcc0.gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(9),
O => \gcc0.gc0.count[8]_i_4_n_0\
);
\gcc0.gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(8),
O => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(10),
Q => \^q\(10)
);
\gcc0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(11),
Q => \^q\(11)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(5),
Q => \^q\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(6),
Q => \^q\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(7),
Q => \^q\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(8),
Q => \^q\(8)
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(9),
Q => \^q\(9)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gcc0.gc0.count_reg[0]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[0]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[0]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[0]_i_1_n_7\,
S(3) => \gcc0.gc0.count[0]_i_2_n_0\,
S(2) => \gcc0.gc0.count[0]_i_3_n_0\,
S(1) => \gcc0.gc0.count[0]_i_4_n_0\,
S(0) => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_5\,
Q => p_12_out(10)
);
\gcc0.gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_4\,
Q => p_12_out(11)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_6\,
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_5\,
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_4\,
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_7\,
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[4]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[4]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[4]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[4]_i_1_n_7\,
S(3) => \gcc0.gc0.count[4]_i_2_n_0\,
S(2) => \gcc0.gc0.count[4]_i_3_n_0\,
S(1) => \gcc0.gc0.count[4]_i_4_n_0\,
S(0) => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_6\,
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_5\,
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_4\,
Q => p_12_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_7\,
Q => p_12_out(8)
);
\gcc0.gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gcc0.gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[8]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[8]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[8]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[8]_i_1_n_7\,
S(3) => \gcc0.gc0.count[8]_i_2_n_0\,
S(2) => \gcc0.gc0.count[8]_i_3_n_0\,
S(1) => \gcc0.gc0.count[8]_i_4_n_0\,
S(0) => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_6\,
Q => p_12_out(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => D(0),
I2 => \^q\(1),
I3 => D(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => D(2),
I2 => \^q\(3),
I3 => D(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => D(4),
I2 => \^q\(5),
I3 => D(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => D(6),
I2 => \^q\(7),
I3 => D(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => D(8),
I2 => \^q\(9),
I3 => D(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => ram_empty_i_reg_3
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_0(5)
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => D(10),
I2 => \^q\(11),
I3 => D(11),
O => v1_reg(5)
);
\gmux.gm[5].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => p_12_out(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_1(5)
);
\gmux.gm[5].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => ram_empty_i_reg_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_generator_rx_inst_blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_rx_inst_blk_mem_gen_prim_wrapper
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
\gc0.count_d1_reg[11]\ : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_rd_status_flags_ss : entity is "rd_status_flags_ss";
end fifo_generator_rx_inst_rd_status_flags_ss;
architecture STRUCTURE of fifo_generator_rx_inst_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c1: entity work.fifo_generator_rx_inst_compare_4
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.fifo_generator_rx_inst_compare_5
port map (
comp1 => comp1,
v1_reg(5 downto 0) => v1_reg(5 downto 0)
);
\gc0.count_d1[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => \gc0.count_d1_reg[11]\
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_generator_rx_inst_reset_blk_ramfifo;
architecture STRUCTURE of fifo_generator_rx_inst_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[0]\(1) <= rd_rst_reg(2);
\gc0.count_reg[0]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.fifo_generator_rx_inst_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_wr_status_flags_ss : entity is "wr_status_flags_ss";
end fifo_generator_rx_inst_wr_status_flags_ss;
architecture STRUCTURE of fifo_generator_rx_inst_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_comb : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => \gcc0.gc0.count_d1_reg[11]\
);
c0: entity work.fifo_generator_rx_inst_compare
port map (
E(0) => E(0),
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_comb => ram_full_comb,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
c1: entity work.fifo_generator_rx_inst_compare_3
port map (
comp1 => comp1,
v1_reg_0(5 downto 0) => v1_reg_0(5 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_generator_rx_inst_blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_rx_inst_blk_mem_gen_prim_width
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(12 downto 4),
dout(8 downto 0) => dout(12 downto 4),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[2].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(21 downto 13),
dout(8 downto 0) => dout(21 downto 13),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[3].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(30 downto 22),
dout(8 downto 0) => dout(30 downto 22),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[4].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(39 downto 31),
dout(8 downto 0) => dout(39 downto 31),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[5].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(48 downto 40),
dout(8 downto 0) => dout(48 downto 40),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[6].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(57 downto 49),
dout(8 downto 0) => dout(57 downto 49),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[7].ram.r\: entity work.\fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(63 downto 58),
dout(5 downto 0) => dout(63 downto 58),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_rd_logic : entity is "rd_logic";
end fifo_generator_rx_inst_rd_logic;
architecture STRUCTURE of fifo_generator_rx_inst_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.fifo_generator_rx_inst_rd_status_flags_ss
port map (
clk => clk,
empty => empty,
\gc0.count_d1_reg[11]\ => \^e\(0),
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
rpntr: entity work.fifo_generator_rx_inst_rd_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
ram_empty_fb_i_reg => \^e\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_wr_logic : entity is "wr_logic";
end fifo_generator_rx_inst_wr_logic;
architecture STRUCTURE of fifo_generator_rx_inst_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gcc0.gc0.count_d1_reg[11]\ : STD_LOGIC;
begin
\gcc0.gc0.count_d1_reg[11]\ <= \^gcc0.gc0.count_d1_reg[11]\;
\gwss.wsts\: entity work.fifo_generator_rx_inst_wr_status_flags_ss
port map (
E(0) => E(0),
clk => clk,
full => full,
\gcc0.gc0.count_d1_reg[11]\ => \^gcc0.gc0.count_d1_reg[11]\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\,
\out\ => \out\,
v1_reg(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_0(5 downto 0) => \c1/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.fifo_generator_rx_inst_wr_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
ram_empty_i_reg_4 => ram_empty_i_reg_4,
ram_full_fb_i_reg => \^gcc0.gc0.count_d1_reg[11]\,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
v1_reg_0(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_1(5 downto 0) => \c1/v1_reg\(5 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_generator_rx_inst_blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_rx_inst_blk_mem_gen_generic_cstr
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth : entity is "blk_mem_gen_v8_3_4_synth";
end fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_rx_inst_blk_mem_gen_top
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_blk_mem_gen_v8_3_4 : entity is "blk_mem_gen_v8_3_4";
end fifo_generator_rx_inst_blk_mem_gen_v8_3_4;
architecture STRUCTURE of fifo_generator_rx_inst_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_memory : entity is "memory";
end fifo_generator_rx_inst_memory;
architecture STRUCTURE of fifo_generator_rx_inst_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.fifo_generator_rx_inst_blk_mem_gen_v8_3_4
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_generator_rx_inst_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_25\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_26\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_rx_inst_rd_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_0_out(11 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.wr_n_26\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_23\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_24\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_25\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => rd_rst_i(2),
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_rx_inst_wr_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\gcc0.gc0.count_d1_reg[11]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => wr_rst_i(1),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_22\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_23\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_24\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_25\,
ram_empty_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_26\,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_rx_inst_memory
port map (
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\out\(0) => rd_rst_i(0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.fifo_generator_rx_inst_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[0]\(1) => rd_rst_i(2),
\gc0.count_reg[0]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_top : entity is "fifo_generator_top";
end fifo_generator_rx_inst_fifo_generator_top;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_rx_inst_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_v13_1_2_synth : entity is "fifo_generator_v13_1_2_synth";
end fifo_generator_rx_inst_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_rx_inst_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_rx_inst_fifo_generator_v13_1_2 : entity is "fifo_generator_v13_1_2";
end fifo_generator_rx_inst_fifo_generator_v13_1_2;
architecture STRUCTURE of fifo_generator_rx_inst_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(11) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_rx_inst_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_rx_inst is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_rx_inst : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_rx_inst : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_rx_inst : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_rx_inst : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end fifo_generator_rx_inst;
architecture STRUCTURE of fifo_generator_rx_inst is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.fifo_generator_rx_inst_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(11 downto 0) => NLW_U0_data_count_UNCONNECTED(11 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(11 downto 0) => B"000000000000",
prog_empty_thresh_assert(11 downto 0) => B"000000000000",
prog_empty_thresh_negate(11 downto 0) => B"000000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(11 downto 0) => B"000000000000",
prog_full_thresh_assert(11 downto 0) => B"000000000000",
prog_full_thresh_negate(11 downto 0) => B"000000000000",
rd_clk => '0',
rd_data_count(11 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(11 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(11 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(11 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
fb2c4b9078112df2db9d94355915597a
| 0.683453 | 3.483034 | false | false | false | false |
Vadman97/ImageAES
|
des/DES/ipcore_dir/constants_mem/simulation/constants_mem_tb.vhd
| 1 | 4,520 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: constants_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY constants_mem_tb IS
END ENTITY;
ARCHITECTURE constants_mem_tb_ARCH OF constants_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
constants_mem_synth_inst:ENTITY work.constants_mem_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
987f65340aeb756786d012fe3b34e0f1
| 0.603097 | 4.448819 | false | false | false | false |
freecores/w11
|
rtl/vlib/genlib/gray_cnt_4.vhd
| 2 | 3,355 |
-- $Id: gray_cnt_4.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_4 - syn
-- Description: 4 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 4 4 365MHz/ 2.76ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end entity gray_cnt_4;
architecture syn of gray_cnt_4 is
signal R_DATA : slv4 := (others=>'0');
signal N_DATA : slv4 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
-- inferred. For 4 bit the coding was 'Gray', but see remarks in
-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "0000" => N_DATA <= "0001"; -- 0
when "0001" => N_DATA <= "0011"; -- 1
when "0011" => N_DATA <= "0010"; -- 2
when "0010" => N_DATA <= "0110"; -- 3
when "0110" => N_DATA <= "0111"; -- 4
when "0111" => N_DATA <= "0101"; -- 5
when "0101" => N_DATA <= "0100"; -- 6
when "0100" => N_DATA <= "1100"; -- 7
when "1100" => N_DATA <= "1101"; -- 8
when "1101" => N_DATA <= "1111"; -- 9
when "1111" => N_DATA <= "1110"; -- 10
when "1110" => N_DATA <= "1010"; -- 11
when "1010" => N_DATA <= "1011"; -- 12
when "1011" => N_DATA <= "1001"; -- 13
when "1001" => N_DATA <= "1000"; -- 14
when "1000" => N_DATA <= "0000"; -- 15
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
|
gpl-2.0
|
83e165dfd677dcf4cae6bdfb276633ce
| 0.530253 | 3.406091 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd
| 1 | 7,606 |
-- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n3 - syn
-- Description: Tester serial link for nexys3 (serport_1clock case)
--
-- Dependencies: genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop1_n3;
architecture syn of sys_tst_serloop1_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 8,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
gpl-2.0
|
8b9d451f94ab812cdd6cfc50a8b8f1ac
| 0.491586 | 3.337429 | false | false | false | false |
freecores/w11
|
rtl/ibus/ib_intmap.vhd
| 2 | 5,517 |
-- $Id: ib_intmap.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_intmap - syn
-- Description: pdp11: external interrupt mapper
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_intmap is -- external interrupt mapper
generic (
INTMAP : intmap_array_type := intmap_array_init);
port (
EI_REQ : in slv16_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end ib_intmap;
architecture syn of ib_intmap is
signal EI_LINE : slv4 := (others=>'0'); -- external interrupt line
type intp_type is array (15 downto 0) of slv3;
type intv_type is array (15 downto 0) of slv9;
constant conf_intp : intp_type :=
(slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
);
constant conf_intv : intv_type :=
(slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
);
-- attribute PRIORITY_EXTRACT : string;
-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
begin
EI_LINE <= "1111" when EI_REQ(15)='1' else
"1110" when EI_REQ(14)='1' else
"1101" when EI_REQ(13)='1' else
"1100" when EI_REQ(12)='1' else
"1011" when EI_REQ(11)='1' else
"1010" when EI_REQ(10)='1' else
"1001" when EI_REQ( 9)='1' else
"1000" when EI_REQ( 8)='1' else
"0111" when EI_REQ( 7)='1' else
"0110" when EI_REQ( 6)='1' else
"0101" when EI_REQ( 5)='1' else
"0100" when EI_REQ( 4)='1' else
"0011" when EI_REQ( 3)='1' else
"0010" when EI_REQ( 2)='1' else
"0001" when EI_REQ( 1)='1' else
"0000";
proc_intmap : process (EI_LINE, EI_ACKM)
variable iline : integer := 0;
variable iei_ack : slv16 := (others=>'0');
begin
iline := to_integer(unsigned(EI_LINE));
iei_ack := (others=>'0');
if EI_ACKM = '1' then
iei_ack(iline) := '1';
end if;
EI_ACK <= iei_ack(EI_ACK'range);
EI_PRI <= conf_intp(iline);
EI_VECT <= conf_intv(iline)(8 downto 2);
end process proc_intmap;
end syn;
|
gpl-2.0
|
fbd37839e286cf9f181fda2d660d5bce
| 0.551568 | 3.247204 | false | false | false | false |
superboy0712/MIPS
|
datapath.vhd
| 1 | 1,252 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity reg_file is
generic(
constant width : natural := 32;
constant depth : natural := 32
);
port(
clk : in std_logic;
wr_en : in std_logic;
-- input
rd_reg_num1 : in std_logic_vector( 4 downto 0);
rd_reg_num2 : in std_logic_vector( 4 downto 0);
wr_reg_num : in std_logic_vector( 4 downto 0);
wr_data : in std_logic_vector( width - 1 downto 0);
-- output
rd_data1 : out std_logic_vector( width - 1 downto 0);
rd_data2 : out std_logic_vector( width - 1 downto 0)
);
end reg_file;
architecture behavioral of reg_file is
-- an array of size 32, width 32
type reg_array is array( 0 to 31 ) of std_logic_vector ( 31 downto 0 );
signal reg_file : reg_array := (others =>(others => '0'));
begin
write1 : process(clk)
begin
if rising_edge(clk) then
if wr_en = '1' then
if to_integer(unsigned(wr_reg_num)) /= 0 then
reg_file(to_integer(unsigned(wr_reg_num))) <= wr_data;
end if;
end if;
end if;
end process;
rd_data1 <= reg_file(to_integer(unsigned(rd_reg_num1)));
rd_data2 <= reg_file(to_integer(unsigned(rd_reg_num2)));
end behavioral;
|
mit
|
a21f8d31e10c73d72c7b50bd16ee8497
| 0.607029 | 2.813483 | false | false | false | false |
unhold/hdl
|
vhdl/sync.vhd
| 1 | 869 |
library ieee;
use ieee.std_logic_1164.all;
entity sync is
generic (
width_g : positive := 1;
stages_g : positive := 2;
reset_value_g : std_ulogic := '-');
port (
reset_i : in std_ulogic := '0';
clock_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g-1 downto 0);
data_o : out std_ulogic_vector(width_g-1 downto 0) := (others => reset_value_g));
end;
architecture rtl of sync is
type sync_t is array(stages_g-2 downto 0) of std_ulogic_vector(width_g-1 downto 0);
signal sync_r : sync_t := (others => (others => reset_value_g));
begin
process(reset_i, clock_i)
begin
if reset_i = '1' then
sync_r <= (others => (others => reset_value_g));
data_o <= (others => reset_value_g);
elsif rising_edge(clock_i) then
sync_r <= sync_r(sync_r'high-1 downto sync_r'low) & data_i;
data_o <= sync_r(sync_r'high);
end if;
end process;
end;
|
gpl-3.0
|
ae61f429148b87a60f27ca56554082ff
| 0.635213 | 2.601796 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/ben_mem/example_design/ben_mem_exdes.vhd
| 1 | 4,477 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ben_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ben_mem_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ben_mem_exdes;
ARCHITECTURE xilinx OF ben_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ben_mem IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ben_mem
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
8c225271bbc1ee47a76a02f86a643fee
| 0.554389 | 4.591795 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_vmbox.vhd
| 2 | 24,725 |
-- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_vmbox - syn
-- Description: pdp11: virtual memory
--
-- Dependencies: pdp11_mmu
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.6.3 now numeric_std clean
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
-- from CP_ADDR; now all ibr handling via vmbox
-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
-- 2008-01-05 110 1.1.3 update snooper.
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
-- all status into regs_type. add intbus HOLD support.
-- 2007-12-30 108 1.1.1 use ubf_byte[01]
-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
-- 2nd port was unused, connected ADDR caused slow net
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end pdp11_vmbox;
architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 5; -- size of access timeout counter
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request
s_mem_w, -- s_mem_w: check mmu, wait for memory
s_ib_w, -- s_ib_w: wait for ibus
s_ib_wend, -- s_ib_wend: ibus write completion
s_ib_rend, -- s_ib_rend: ibus read completion
s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
s_fail, -- s_fail: vmbox fatal error catcher
s_errrsv, -- s_errrsv: red stack violation
s_errib -- s_errib: ibus error handler
);
type regs_type is record -- state registers
state : state_type; -- state
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
kstack : slbit; -- access through kernel stack
ysv : slbit; -- yellow stack violation detected
vaok : slbit; -- virtual address valid (from MMU)
trap_mmu : slbit; -- mmu trace trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibdout : slv16; -- ibus dout register
end record regs_type;
constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
s_idle, -- state
'0','0','0','0', -- wacc,macc,cacc,bytop
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
signal MMU_STAT : mmu_stat_type := mmu_stat_init;
signal PADDRH : slv16 := (others=>'0');
signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
signal UBMAP_MREQ : slbit := '0';
signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
begin
MMU : pdp11_mmu
port map (
CLK => CLK,
CRESET => CRESET,
BRESET => BRESET,
CNTL => MMU_CNTL,
VADDR => VM_ADDR,
MONI => MMU_MONI,
STAT => MMU_STAT,
PADDRH => PADDRH,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMU
);
UBMAP : pdp11_ubmap
port map (
CLK => CLK,
MREQ => UBMAP_MREQ,
ADDR_UB => CP_ADDR.addr(17 downto 1),
ADDR_PM => UBMAP_ADDR_PM,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_UBMAP
);
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
IB_SRES_3 => IB_SRES_MMU,
IB_SRES_4 => IB_SRES_UBMAP,
IB_SRES_OR => IB_SRES_INT
);
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
IB_SRES_OR => IB_SRES
);
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_SLIM = '1' then
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
proc_slim: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
end if;
end if;
end process proc_slim;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
IB_SRES, UBMAP_ADDR_PM,
EM_SRES, MMU_STAT, PADDRH)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
variable iubmap_mreq : slbit := '0';
variable paddr_mmu : slbit := '0';
variable paddr_sel : slv2 := "00";
constant c_paddr_sel_vmaddr : slv2 := "00";
constant c_paddr_sel_rpaddr : slv2 := "01";
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
begin
r := R_REGS;
n := R_REGS;
n.state := s_fail;
ivm_stat := vm_stat_init;
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if VM_ADDR(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
iubmap_mreq :='0';
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
-- and overwritten in s_idle_mw_mem
paddr_sel := "00";
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
paddr_mmu := '0';
paddr_sel := c_paddr_sel_vmaddr;
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
paddr_sel := c_paddr_sel_ubmap;
else
paddr_sel := c_paddr_sel_cacc;
end if;
end if;
end if;
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
is_stackyellow := '0';
is_stackred := '0';
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
is_stackyellow := '1';
if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
is_stackred := '1';
end if;
end if;
if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
is_stackred := '1';
end if;
immu_cntl.wacc := VM_CNTL.wacc;
immu_cntl.macc := VM_CNTL.macc;
immu_cntl.cacc := VM_CNTL.cacc;
immu_cntl.dspace := VM_CNTL.dspace;
immu_cntl.mode := VM_CNTL.mode;
immu_cntl.trap_done := VM_CNTL.trap_done;
case r.state is
when s_idle => -- s_idle: wait for vm_cntl request --
n.state := s_idle;
iubmap_mreq := '1'; -- activate ubmap always in s_idle
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.cacc := VM_CNTL.cacc;
n.bytop := VM_CNTL.bytop;
n.kstack := VM_CNTL.kstack;
n.ysv := '0';
n.vaok := MMU_STAT.vaok;
n.trap_mmu := MMU_STAT.trap;
n.mdin := iem_mreq.din;
-- n.paddr assignment handled separately in 'if state=s_idle' at the
-- end.
immu_cntl.req := '1';
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
n.state := s_fail;
elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
is_stackred='1' then
n.state := s_errrsv;
else
iem_mreq.req := '1';
iem_mreq.we := VM_CNTL.wacc;
if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
n.ysv := is_stackyellow;
end if;
n.state := s_mem_w;
end if;
end if;
when s_mem_w => -- s_mem_w: check mmu, wait for memory
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
ivm_stat.err := '1';
ivm_stat.err_odd := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
elsif r.vaok = '0' then -- MMU abort ?
ivm_stat.err := '1';
ivm_stat.err_mmu := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
n.ibbe := "11";
if r.cacc = '1' then -- console access ?
n.ibbe := CP_ADDR.be;
else -- cpu access ?
if r.bytop = '1' then
if r.paddr(0) = '0' then
n.ibbe(1) := '0';
else
n.ibbe(0) := '0';
end if;
end if;
end if;
n.ibrmw := r.macc;
n.state := s_ib_w;
else
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
ivm_stat.err := '1';
ivm_stat.err_nxm := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
ivm_stat.ack := '1';
ivm_stat.trap_ysv := r.ysv;
ivm_stat.trap_mmu := r.trap_mmu;
if r.macc='1' and r.wacc='0' then
n.state := s_idle_mw_mem;
else
n.state := s_idle;
end if;
else
n.state := s_mem_w; -- keep waiting
end if;
end if;
end if;
end if;
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
iib_aval := '1'; -- declare ibus addr valid
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
end if;
when s_ib_wend => -- s_ib_wend: ibus write completion --
ivm_stat.ack := '1';
n.state := s_idle;
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
end if;
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
end if;
end if;
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
n.state := s_idle_mw_mem;
paddr_mmu := '0';
paddr_sel := c_paddr_sel_rpaddr;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if r.paddr(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.bytop := VM_CNTL.bytop;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
iem_mreq.req := '1';
iem_mreq.we := '1';
n.state := s_mem_mw_w;
end if;
end if;
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
if EM_SRES.ack_w = '1' then
ivm_stat.ack := '1';
n.state := s_idle;
else
n.state := s_mem_mw_w; -- keep waiting
end if;
when s_fail => -- s_fail: vmbox fatal error catcher
ivm_stat.fail := '1';
n.state := s_idle;
when s_errrsv => -- s_errrsv: red stack violation -----
ivm_stat.err := '1';
ivm_stat.err_rsv := '1';
n.state := s_idle;
when s_errib => -- s_errib: ibus error handler -------
ivm_stat.err := '1';
ivm_stat.err_iobto := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
n.state := s_idle;
when others => null;
end case;
if r.bytop='1' and r.paddr(0)='1' then
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
end if;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
ipaddr := (others=>'0');
if paddr_mmu = '1' then
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
ipaddr(21 downto 6) := PADDRH;
if MMU_STAT.ena_22bit = '0' then
ipaddr(21 downto 18) := (others=>'0');
end if;
else
case paddr_sel is
when c_paddr_sel_vmaddr =>
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
when c_paddr_sel_rpaddr =>
ipaddr := r.paddr;
when c_paddr_sel_cacc =>
ipaddr := CP_ADDR.addr & '0';
if CP_ADDR.ena_22bit = '0' then
ipaddr(21 downto 16) := (others=>'0');
end if;
when c_paddr_sel_ubmap =>
ipaddr := UBMAP_ADDR_PM & '0';
when others => null;
end case;
end if;
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
N_REGS <= n;
UBMAP_MREQ <= iubmap_mreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_DOUT <= ivm_dout;
VM_STAT <= ivm_stat;
MMU_CNTL <= immu_cntl;
EM_MREQ <= iem_mreq;
end process proc_next;
IB_MREQ_M <= IB_MREQ; -- external drive master port
DM_STAT_VM.ibmreq <= IB_MREQ;
DM_STAT_VM.ibsres <= IB_SRES;
end syn;
|
gpl-2.0
|
7cb6749fbbc4c0146d5f08313763a647
| 0.483357 | 3.483866 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd
| 1 | 6,088 |
-- $Id: tst_fx2loop_hiomap.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage
-- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3) -- unused --
-- (2) -- unused --
-- (1) -- unused --
-- (0) reset state [!! decoded by top level design !!]
--
-- SWI(7:5) select display
-- (4) -- unused --
-- (3) throttle
-- (2) tx2blast
-- (1:0) mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
--
-- LED(7) MONI.fifo_ep4
-- (6) MONI.fifo_ep6
-- (5) MONI.fifo_ep8
-- (4) MONI.flag_ep4_empty
-- (3) MONI.flag_ep4_almost
-- (2) MONI.flag_ep6_full
-- (1) MONI.flag_ep6_almost
-- (0) rxsecnt > 0 (sequence error)
--
-- DSP data as selected by SWI(7:5)
-- 000 -> rxsecnt
-- 001 -> -- unused -- (display ffff)
-- 010 -> rxcnt.l
-- 011 -> rxcnt.h
-- 100 -> txcnt.l
-- 101 -> txcnt.h
-- 110 -> tx2cnt.l
-- 111 -> tx2cnt.h
--
-- DP(3) FX2_TXBUSY (shows tx back preasure)
-- (2) FX2_MONI.slwr (shows tx activity)
-- (1) FX2_RXHOLD (shows rx back preasure)
-- (0) FX2_MONI.slrd (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
-- ----------------------------------------------------------------------------
entity tst_fx2loop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_fx2loop_hiomap;
architecture syn of tst_fx2loop_hiomap is
type regs_type is record
dspdat : slv16; -- display data
dummy : slbit; -- <remove when 2nd signal added...>
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- dspdat
'0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- setup tester controls
icntl.mode := SWI(1 downto 0);
icntl.tx2blast := SWI(2);
icntl.throttle := SWI(3);
-- setup leds
iled(7) := FX2_MONI.fifo_ep4;
iled(6) := FX2_MONI.fifo_ep6;
iled(5) := FX2_MONI.fifo_ep8;
iled(4) := FX2_MONI.flag_ep4_empty;
iled(3) := FX2_MONI.flag_ep4_almost;
iled(2) := FX2_MONI.flag_ep6_full;
iled(1) := FX2_MONI.flag_ep6_almost;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if;
-- setup display data
case SWI(7 downto 5) is
when "000" => idat := HIO_STAT.rxsecnt;
when "001" => idat := (others=>'1');
when "010" => idat := HIO_STAT.rxcnt(15 downto 0);
when "011" => idat := HIO_STAT.rxcnt(31 downto 16);
when "100" => idat := HIO_STAT.txcnt(15 downto 0);
when "101" => idat := HIO_STAT.txcnt(31 downto 16);
when "110" => idat := HIO_STAT.tx2cnt(15 downto 0);
when "111" => idat := HIO_STAT.tx2cnt(31 downto 16);
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := HIO_STAT.txbusy; -- tx back preasure
idp(2) := FX2_MONI.slwr; -- tx activity
idp(1) := HIO_STAT.rxhold; -- rx back preasure
idp(0) := FX2_MONI.slrd; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;
|
gpl-2.0
|
efa2501b6804e09cc76018af9c85b29d
| 0.512976 | 3.403018 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd
| 1 | 13,584 |
-- $Id: sys_tst_rlink_cuff_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_n3 - syn
-- Description: rlink tester design for nexys3 with fx2 interface
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-01-04 469 13.3 O76d xc6slx16-2 ??? ???? ??? ???? p ??.? ic2/ 50
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_rlink_cuff_n2
-- and sys_tst_fx2loop_n3
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_n3 is -- top level
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_n3;
architecture syn of sys_tst_rlink_cuff_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
gpl-2.0
|
3b9d4029b1289af8f56177d1b180db83
| 0.497939 | 3.124914 | false | false | false | false |
unhold/hdl
|
vhdl/clk_div.vhd
| 1 | 674 |
library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
generic (
period_g : in positive);
port (
rst_i : in std_ulogic := '0';
clk_i : in std_ulogic;
clk_o : out std_ulogic);
begin
assert period_g >= 2 and period_g mod 2 = 0
report "clk_div: invalid period_g";
end;
architecture rtl of clk_div is
signal clk : std_ulogic := '0';
signal cnt : natural range 0 to period_g/2 - 1 := 0;
begin
process(rst_i, clk_i)
begin
if rst_i = '1' then
clk <= '0';
cnt <= 0;
elsif rising_edge(clk_i) then
if cnt = period_g/2 - 1 then
clk <= not clk;
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end process;
clk_o <= clk;
end;
|
gpl-3.0
|
16952b7b069395f22a414e2352d45f1e
| 0.596439 | 2.524345 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_sys70.vhd
| 2 | 3,917 |
-- $Id: pdp11_sys70.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sys70 - syn
-- Description: pdp11: 11/70 system registers
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.1 use iblib
-- 2008-04-20 137 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
use work.iblib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_sys70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_sys70;
architecture syn of pdp11_sys70 is
constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16));
constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16));
type regs_type is record -- state registers
ibsel_mbrk : slbit; -- ibus select mbrk
ibsel_sysid : slbit; -- ibus select sysid
mbrk : slv8; -- status of mbrk register
end record regs_type;
constant regs_init : regs_type := (
'0','0', -- ibsel_*
mbrk=>(others=>'0') -- mbrk
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel_mbrk := '0';
n.ibsel_sysid := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then
n.ibsel_mbrk := '1';
end if;
if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then
n.ibsel_sysid := '1';
end if;
end if;
-- ibus transactions
if r.ibsel_mbrk = '1' then
idout(r.mbrk'range) := r.mbrk;
end if;
if r.ibsel_sysid = '1' then
idout := slv(to_unsigned(8#123456#,16));
end if;
if r.ibsel_mbrk='1' and ibw0='1' then
n.mbrk := IB_MREQ.din(n.mbrk'range);
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq;
IB_SRES.busy <= '0';
end process proc_next;
end syn;
|
gpl-2.0
|
ac5069bf468af3e47ff7e296c5d84a83
| 0.550421 | 3.466372 | false | false | false | false |
freecores/w11
|
rtl/ibus/ibdr_sdreg.vhd
| 2 | 4,849 |
-- $Id: ibdr_sdreg.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_sdreg - syn
-- Description: ibus dev(rem): Switch/Display register
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 34 40 0 30 s 4.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 32 39 0 29 s 2.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.1 now numeric_std clean
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2008-08-22 161 1.0.4 use iblib
-- 2008-04-18 136 1.0.3 use RESET. Switch/Display not cleared by console
-- reset or reset instruction, only by cpu_reset
-- 2008-01-20 112 1.0.2 use BRESET
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- reorganize code, all in state_type/proc_next
-- 2007-12-31 108 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
-- fixed address: 177570
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DISPREG : out slv16 -- display register
);
end ibdr_sdreg;
architecture syn of ibdr_sdreg is
constant ibaddr_sdreg : slv16 := slv(to_unsigned(8#177570#,16));
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
sreg : slv16; -- switch register
dreg : slv16; -- display register
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- sreg
(others=>'0') -- dreg
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_sdreg(12 downto 1) then
n.ibsel := '1';
end if;
-- ibus output driver
if r.ibsel = '1' then
if IB_MREQ.racc = '0' then
idout := r.sreg; -- cpu will read switch register
else
idout := r.dreg; -- rri will read display register
end if;
end if;
-- ibus write transactions
if r.ibsel='1' and IB_MREQ.we='1' then
if IB_MREQ.racc = '0' then -- cpu will write display register
if IB_MREQ.be1 = '1' then
n.dreg(ibf_byte1) := IB_MREQ.din(ibf_byte1);
end if;
if IB_MREQ.be0 = '1' then
n.dreg(ibf_byte0) := IB_MREQ.din(ibf_byte0);
end if;
else -- rri will write switch register
n.sreg := IB_MREQ.din; -- byte write not supported
end if;
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
DISPREG <= r.dreg;
end process proc_next;
end syn;
|
gpl-2.0
|
5196b00a39d04bc3bcf0d79e8fd05f5d
| 0.529388 | 3.589193 | false | false | false | false |
superboy0712/MIPS
|
uart/uart2BusTop.vhd
| 1 | 3,489 |
-- UART2Bus system for controlling registers over UART
-- http://opencores.org/project,uart2bus
-----------------------------------------------------------------------------------------
-- uart to internal bus top module
--
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart2BusTop_pkg.all;
entity uart2BusTop is
generic ( AW : integer := 8);
port ( -- global signals
clr : in STD_LOGIC; -- global reset input
clk : in STD_LOGIC; -- global clock input
-- uart serial signals
serIn : in STD_LOGIC; -- serial data input
serOut : out STD_LOGIC; -- serial data output
-- internal bus to register file
intAccessReq : out std_logic; --
intAccessGnt : in std_logic; --
intRdData : in STD_LOGIC_VECTOR (7 downto 0); -- data read from register file
intAddress : out STD_LOGIC_VECTOR (AW - 1 downto 0); -- address bus to register file
intWrData : out STD_LOGIC_VECTOR (7 downto 0); -- write data to register file
intWrite : out STD_LOGIC; -- write control to register file
intRead : out STD_LOGIC); -- read control to register file
end uart2BusTop;
architecture Behavioral of uart2BusTop is
-- baud rate configuration, see baudGen.vhd for more details.
-- baud rate generator parameters for 115200 baud on 25MHz clock
--constant baudFreq : std_logic_vector(11 downto 0) := x"480";
--constant baudLimit : std_logic_vector(15 downto 0) := x"3889";
-- parameters for 24 MHz clock
constant baudFreq : std_logic_vector(11 downto 0) := x"030";
constant baudLimit : std_logic_vector(15 downto 0) := x"0241";
signal txData : std_logic_vector(7 downto 0); -- data byte to transmit
signal newTxData : std_logic; -- asserted to indicate that there is a new data byte for transmission
signal txBusy : std_logic; -- signs that transmitter is busy
signal rxData : std_logic_vector(7 downto 0); -- data byte received
signal newRxData : std_logic; -- signs that a new byte was received
begin
-- uart top module instance
ut : uartTop
port map (
clr => clr,
clk => clk,
serIn => serIn,
txData => txData,
newTxData => newTxData,
baudFreq => baudFreq,
baudLimit => baudLimit,
serOut => serOut,
txBusy => txBusy,
rxData => rxData,
newRxData => newRxData,
baudClk => open);
-- uart parser instance
up : uartParser
generic map (
AW => AW)
port map (
clr => clr,
clk => clk,
txBusy => txBusy,
rxData => rxData,
newRxData => newRxData,
intRdData => intRdData,
txData => txData,
newTxData => newTxData,
intReq => intAccessReq,
intGnt => intAccessGnt,
intAddress => intAddress,
intWrData => intWrData,
intWrite => intWrite,
intRead => intRead);
end Behavioral;
|
mit
|
c424c3c18d3cdeed80f7e590e084f889
| 0.511608 | 4.948936 | false | false | false | false |
quicky2000/top_test_image_controler_640_480_1b
|
image_generator.vhd
| 1 | 2,675 |
--
-- This file is part of top_test_image_controler_640_480_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity image_generator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
addr : out STD_LOGIC_VECTOR (18 downto 0);
write_enable : out STD_LOGIC;
data : out STD_LOGIC);
end image_generator;
architecture Behavioral of image_generator is
begin
process(clk,rst)
constant x_max : positive := 639;
constant y_max : positive := 479;
variable x_write : natural range 0 to x_max := 0;
variable y_write : natural range 0 to y_max := 0;
variable address : natural range 0 to 307199 := 0;
begin
if rst = '1' then
write_enable <= '0';
addr <= (others => '0');
data <= '0';
elsif rising_edge(clk) then
if std_logic_vector(to_unsigned(x_write,3)) = "000" or std_logic_vector(to_unsigned(y_write,3)) = "000" then
write_enable <= '1';
addr <= std_logic_vector(to_unsigned(address,19));
data <= '1';
else
write_enable <= '0';
addr <= (others => '0');
data <= '0';
end if;
-- Address management
if address /= 307199 then
address := address + 1;
else
address := 0;
end if; -- addr max
-- Coordinate management
if x_write /= x_max then
x_write := x_write + 1;
else --xmax
x_write := 0;
if y_write /= y_max then
y_write := y_write + 1;
else
y_write := 0;
end if; --ymax
end if; -- xmax
end if;-- clock rising edge
end process;
end Behavioral;
|
gpl-3.0
|
25c043487e8fa5c46291ab76ac8fd9f4
| 0.621308 | 3.757022 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/rlinklib.vhd
| 1 | 13,570 |
-- $Id: rlinklib.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2007-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rlinklib
-- Description: Definitions for rlink interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.3; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 3.3.2 add rlb_moni record definition
-- 2012-12-29 466 3.3.1 add rlink_rlbmux
-- 2011-12-23 444 3.3 CLK_CYCLE now integer
-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces
-- 2011-12-09 437 3.2 add rlink_core8
-- 2011-11-18 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- new rlink_serport interface;
-- rename rlink_core_serport->rlink_base_serport
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 rename: [cd]crc->[cd]err, ioto->rbnak, ioerr->rberr
-- 2010-12-04 343 3.0 move rbus components to rbus/rblib; renames
-- rri_ -> rlink and c_rri -> c_rlink;
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport
-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- 2010-05-01 285 2.1.3 remove rri_rb_rpcompat, now obsolete
-- 2010-04-18 279 2.1.2 rri_core_serport: drop RTSFBUF generic
-- 2010-04-10 275 2.1.1 add rri_core_serport
-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core, rri_serport;
-- CE_USEC, RTSFLUSH, CTS_N, RTS_N for rri_serport
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
-- 2008-08-22 161 1.3 renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
-- 2008-02-16 116 1.2.1 added rri_wreg(rw|w|r)_3
-- 2008-01-20 113 1.2 added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
-- 2007-11-24 98 1.1 added RP_IINT for rri_core.
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.serportlib.all;
package rlinklib is
constant c_rlink_cpref : slv4 := "1000"; -- default comma prefix
constant c_rlink_ncomm : positive := 4; -- number commas (sop,eop,nak,attn)
constant c_rlink_dat_idle : slv9 := "100000000";
constant c_rlink_dat_sop : slv9 := "100000001";
constant c_rlink_dat_eop : slv9 := "100000010";
constant c_rlink_dat_nak : slv9 := "100000011";
constant c_rlink_dat_attn : slv9 := "100000100";
constant c_rlink_cmd_rreg : slv3 := "000";
constant c_rlink_cmd_rblk : slv3 := "001";
constant c_rlink_cmd_wreg : slv3 := "010";
constant c_rlink_cmd_wblk : slv3 := "011";
constant c_rlink_cmd_stat : slv3 := "100";
constant c_rlink_cmd_attn : slv3 := "101";
constant c_rlink_cmd_init : slv3 := "110";
constant c_rlink_iint_rbf_anena: integer := 15; -- anena flag
constant c_rlink_iint_rbf_itoena: integer := 14; -- itoena flag
subtype c_rlink_iint_rbf_itoval is integer range 7 downto 0; -- itoval value
subtype c_rlink_cmd_rbf_seq is integer range 7 downto 3; -- sequence number
subtype c_rlink_cmd_rbf_code is integer range 2 downto 0; -- command code
subtype c_rlink_stat_rbf_stat is integer range 7 downto 5; -- ext status bits
constant c_rlink_stat_rbf_attn: integer := 4; -- attention flags set
constant c_rlink_stat_rbf_cerr: integer := 3; -- command error
constant c_rlink_stat_rbf_derr: integer := 2; -- data error
constant c_rlink_stat_rbf_rbnak: integer := 1; -- rbus no ack or timeout
constant c_rlink_stat_rbf_rberr: integer := 0; -- rbus err bit set
type rl_moni_type is record -- rlink_core monitor port
eop : slbit; -- eop send in last cycle
attn : slbit; -- attn send in last cycle
lamp : slbit; -- attn (lam) pending
end record rl_moni_type;
constant rl_moni_init : rl_moni_type :=
('0','0','0'); -- eop,attn,lamp
type rlb_moni_type is record -- rlink 8b monitor port
rxval : slbit; -- data in valid
rxhold : slbit; -- data in hold
txena : slbit; -- data out enable
txbusy : slbit; -- data out busy
end record rlb_moni_type;
constant rlb_moni_init : rlb_moni_type :=
('0','0','0','0'); -- rxval,rxhold,txena,txbusy
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.
constant rbaddr_rlink_serport : slv8 := slv(to_unsigned(2#11111110#,8));
-- this definition logically belongs into the 'for test benches' section'
-- must be here because it is needed as generic default in rlink_core8
-- simbus sb_cntl field usage for rlink
constant sbcntl_sbf_rlmon : integer := 15;
component rlink_core is -- rlink core with 9bit iface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6); -- idle timeout counter width
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
component rlink_aif is -- rlink, abstract interface
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
RESET : in slbit :='0'; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit := '0' -- rlink 9b: data hold
);
end component;
component rlink_core8 is -- rlink core with 8bit iface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
RESET : in slbit; -- reset
RLB_DI : in slv8; -- rlink 8b: data in
RLB_ENA : in slbit; -- rlink 8b: data enable
RLB_BUSY : out slbit; -- rlink 8b: data busy
RLB_DO : out slv8; -- rlink 8b: data out
RLB_VAL : out slbit; -- rlink 8b: data valid
RLB_HOLD : in slbit; -- rlink 8b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
component rlink_rlbmux is -- rlink rlb multiplexer
port (
SEL : in slbit; -- port select (0:RLB<->P0; 1:RLB<->P1)
RLB_DI : out slv8; -- rlb: data in
RLB_ENA : out slbit; -- rlb: data enable
RLB_BUSY : in slbit; -- rlb: data busy
RLB_DO : in slv8; -- rlb: data out
RLB_VAL : in slbit; -- rlb: data valid
RLB_HOLD : out slbit; -- rlb: data hold
P0_RXDATA : in slv8; -- p0: rx data
P0_RXVAL : in slbit; -- p0: rx valid
P0_RXHOLD : out slbit; -- p0: rx hold
P0_TXDATA : out slv8; -- p0: tx data
P0_TXENA : out slbit; -- p0: tx enable
P0_TXBUSY : in slbit; -- p0: tx busy
P1_RXDATA : in slv8; -- p1: rx data
P1_RXVAL : in slbit; -- p1: rx valid
P1_RXHOLD : out slbit; -- p1: rx hold
P1_TXDATA : out slv8; -- p1: tx data
P1_TXENA : out slbit; -- p1: tx enable
P1_TXBUSY : in slbit -- p1: tx busy
);
end component;
--
-- core + concrete_interface combo's
--
component rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end component;
component rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end component;
end package rlinklib;
|
gpl-2.0
|
d0cc2fb85397381edd75564dacab3313
| 0.54591 | 3.612886 | false | false | false | false |
Vadman97/ImageAES
|
des/DES/ipcore_dir/constants_mem/simulation/constants_mem_synth (Vadim-Laptop's conflicted copy 2017-04-27).vhd
| 1 | 6,855 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: constants_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY constants_mem_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE constants_mem_synth_ARCH OF constants_mem_synth IS
COMPONENT constants_mem_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: constants_mem_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
247ead8390f096d02889dfaeec102911
| 0.581619 | 3.81257 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd
| 1 | 7,257 |
-- $Id: sys_tst_serloop_s3.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop_s3 - syn
-- Description: Tester serial link for s3board
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- s3board/s3_sram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-16 426 13.1 O40d xc3s1000-4 424 602 64 476 t 13.6
-- 2011-11-13 425 13.1 O40d xc3s1000-4 421 586 64 466 t 13.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-12 423 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop_s3 is -- top level
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop_s3;
architecture syn of sys_tst_serloop_s3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
|
gpl-2.0
|
ce55e2cdbce7c56ad8850df5a60ee88c
| 0.496348 | 3.310675 | false | false | false | false |
freecores/w11
|
rtl/vlib/comlib/cdata2byte.vhd
| 2 | 4,382 |
-- $Id: cdata2byte.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: cdata2byte - syn
-- Description: 9 bit comma,data to Byte stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity cdata2byte is -- 9bit comma,data -> byte stream
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv9; -- input data; bit 8 = comma flag
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end cdata2byte;
architecture syn of cdata2byte is
type state_type is (
s_idle,
s_data,
s_comma,
s_escape,
s_edata
);
type regs_type is record
data : slv8; -- current data
state : state_type; -- state
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),
s_idle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert NCOMM <= 14
report "assert(NCOMM <= 14)"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, HOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ido : slv8 := (others=>'0');
variable ival : slbit := '0';
variable ibusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ido := r.data;
ival := '0';
ibusy := '1';
case r.state is
when s_idle =>
ibusy := '0';
if ENA = '1' then
n.data := DI(7 downto 0);
n.state := s_data;
if DI(8) = '1' then
n.state := s_comma;
else
if DI(7 downto 4)=CPREF and
(DI(3 downto 0)="1111" or
unsigned(DI(3 downto 0))<=NCOMM) then
n.state := s_escape;
end if;
end if;
end if;
when s_data =>
ival := '1';
if HOLD = '0' then
n.state := s_idle;
end if;
when s_comma =>
ido := CPREF & r.data(3 downto 0);
ival := '1';
if HOLD = '0' then
n.state := s_idle;
end if;
when s_escape =>
ido := CPREF & "1111";
ival := '1';
if HOLD = '0' then
n.state := s_edata;
end if;
when s_edata =>
ido := (not CPREF) & r.data(3 downto 0);
ival := '1';
if HOLD = '0' then
n.state := s_idle;
end if;
when others => null;
end case;
N_REGS <= n;
DO <= ido;
VAL <= ival;
BUSY <= ibusy;
end process proc_next;
end syn;
|
gpl-2.0
|
e7001d19a57d5b4bb299eda493b8590e
| 0.501597 | 3.72619 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
libraries/fixed_synth.vhdl
| 2 | 29,041 |
-- Synthesis test for the fixed point math package
-- This test is designed to be synthesizable and exercise much of the package.
-- Created for vhdl-200x by David Bishop ([email protected])
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:49:35-04 $
-- Version $Id: fixed_synth.vhdl,v 1.1 2006-06-08 10:49:35-04 l435385 Exp $
-- --------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
entity fixed_synth is
port (
in1, in2 : in STD_LOGIC_VECTOR (15 downto 0); -- inputs
out1 : out STD_LOGIC_VECTOR (15 downto 0); -- output
cmd : in STD_LOGIC_VECTOR (3 downto 0);
clk, rst_n : in STD_ULOGIC); -- clk and reset
end entity fixed_synth;
architecture rtl of fixed_synth is
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
type cmd_type is array (1 to 15) of STD_ULOGIC_VECTOR (cmd'range); -- cmd
signal cmdarray : cmd_type; -- command pipeline
type cry_type is array (0 to 4) of sfixed16; -- arrays
signal outarray0, outarray1, outarray2, outarray3, outarray4,
outarray5, outarray6, outarray7, outarray8, outarray9, outarray10,
outarray11, outarray12, outarray13, outarray14, outarray15 : sfixed16;
signal in1reg3, in2reg3 : sfixed16; -- register stages
begin -- architecture rtl
-- purpose: "0000" test the "+" operator
cmd0reg : process (clk, rst_n) is
variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto
SFixed_low(7, -8, '+', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray0 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray0 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1pin2 := in1array(3) + in2array(3);
outarray(0) := resize (in1pin2, outarray(0));
end if;
end process cmd0reg;
-- purpose: "0001" test the "-" operator
cmd1reg : process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
variable in1min2 : sfixed (SFixed_high(in1array(0), '-', in2array(0)) downto
SFixed_low(in1array(0), '-', in2array(0)));
-- variable in1min2 : sfixed (SFixed_high(7, -8, '-', 7, -8) downto
-- SFixed_low(7, -8, '-', 7, -8));
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray1 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray1 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := in1array(3) - in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd1reg;
-- purpose: "0010" test the "*" operator
cmd2reg : process (clk, rst_n) is
-- variable in1min2 : sfixed (SFixed_high(in1reg3, '*', in2reg3) downto
-- SFixed_low(in1reg3, '*', in2reg3));
variable in1min2 : sfixed (SFixed_high(7, -8, '*', 7, -8) downto
SFixed_low(7, -8, '*', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray2 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray2 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := in1array(3) * in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd2reg;
-- purpose: "0011" test the "/" operator
cmd3reg : process (clk, rst_n) is
variable in1min2 : sfixed (SFixed_high(in1reg3'high, in1reg3'low,
'/', in2reg3'high, in2reg3'low)
downto
SFixed_low(in1reg3'high, in1reg3'low,
'/', in2reg3'high, in2reg3'low));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd3reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray3 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := to_sfixed(1, in2array(0));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray3 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := to_sfixed(1, in2array(0));
else
in2array(0) := in2reg3;
end if;
in1min2 := in1array(3) / in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd3reg;
-- purpose: "0100" test the "+" operator
cmd4reg : process (clk, rst_n) is
variable in1pin2 : ufixed (uFixed_high(7, -8, '+', 7, -8) downto
uFixed_low(7, -8, '+', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray4 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray4 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1pin2 := ufixed(in1array(3)) + ufixed(in2array(3));
outarray(0) := sfixed (resize (in1pin2, outarray4'high, outarray4'low));
end if;
end process cmd4reg;
-- purpose: "0101" test the "-" operator
cmd5reg : process (clk, rst_n) is
variable in1min2 : ufixed (uFixed_high(7, -8, '-', 7, -8) downto
uFixed_low(7, -8, '-', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray5 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray5 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := ufixed(in1array(3)) - ufixed(in2array(3));
outarray(0) := sfixed(resize (in1min2, outarray5'high, outarray5'low));
end if;
end process cmd5reg;
-- purpose: "0110" test the "*" operator
cmd6reg : process (clk, rst_n) is
variable in1min2 : ufixed (uFixed_high(7, -8, '*', 7, -8) downto
uFixed_low(7, -8, '*', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray6 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray6 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
in1min2 := ufixed(in1array(3)) * ufixed(in2array(3));
outarray(0) := sfixed(resize (in1min2, outarray6'high, outarray6'low));
end if;
end process cmd6reg;
-- purpose: "0111" test the "/" operator
cmd7reg : process (clk, rst_n) is
variable in1min2 : ufixed (uFixed_high(7, -8, '/', 7, -8) downto
uFixed_low(7, -8, '/', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray7 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := sfixed(to_ufixed(1, in2reg3'high, in2reg3'low));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray7 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := sfixed(to_ufixed(1, in2reg3'high, in2reg3'low));
else
in2array(0) := in2reg3;
end if;
in1min2 := ufixed(in1array(3)) / ufixed(in2array(3));
outarray(0) := sfixed(resize (in1min2, outarray7'high, outarray7'low));
end if;
end process cmd7reg;
-- purpose: "1000" test the resize test
cmd8reg : process (clk, rst_n) is
variable tmpfp71, tmpfp72 : sfixed7; -- 8 bit fp number
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray8 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray8 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
-- Resize test Convert inputs into two 8 bit numbers
tmpfp71 := resize (in1array(3), tmpfp71'high, tmpfp71'low,
fixed_wrap, fixed_truncate);
tmpfp72 := resize (in2array(3), tmpfp72'high, tmpfp72'low,
fixed_saturate, fixed_round);
outarray(0) := (others => '0');
fx1 : for i in tmpfp71'range loop
outarray(0)(i+4) := tmpfp71(i);
end loop fx1;
fx2 : for i in tmpfp72'range loop
outarray(0)(i-4) := tmpfp72(i);
end loop fx2;
end if;
end process cmd8reg;
-- purpose: "1001" test the to_signed/unsigned test
cmd9reg : process (clk, rst_n) is
variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp
variable tmpsig : SIGNED (7 downto 0); -- signed number
variable tmpuns : UNSIGNED (15 downto 0); -- unsigned number
variable tmpint : INTEGER;
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray9 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray9 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));
if (tmp = "00") then
-- Signed to sfixed and back
tmpsig := to_signed (in1array(3), tmpsig'length);
outarray(0) := to_sfixed (tmpsig, outarray(0));
elsif (tmp = "01") then
-- unsigned to ufixed and back
tmpuns := to_unsigned (ufixed(in1array(3)), tmpuns'length);
outarray(0) := sfixed(to_ufixed (tmpuns, outarray(0)'high,
outarray(0)'low));
elsif (tmp = "10") then
tmpint := to_integer (in1array(3));
outarray(0) := to_sfixed (tmpint, outarray(0));
else
tmpint := to_integer (ufixed(in1array(3)));
outarray(0) := sfixed(to_ufixed (tmpint, outarray(0)'high,
outarray(0)'low));
end if;
end if;
end process cmd9reg;
-- purpose: "1010" test the reciprocal, abs, - test
cmd10reg : process (clk, rst_n) is
variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp
variable in1recip : sfixed (-in1reg3'low+1 downto -in1reg3'high);
variable uin1recip : ufixed (-in1reg3'low downto -in1reg3'high-1);
variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto
SFixed_low(7, -8, '+', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray10 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := to_sfixed(1, in1reg3);
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray10 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
if (in1reg3 = 0) then
in1array(0) := to_sfixed(1, in1reg3);
else
in1array(0) := in1reg3;
end if;
in2array(0) := in2reg3;
tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));
if (tmp = "00") then
in1recip := reciprocal (in1array(3));
outarray(0) := resize (in1recip, outarray(0)'high,
outarray(0)'low);
elsif (tmp = "01") then
uin1recip := reciprocal (ufixed(in1array(3)));
outarray(0) := sfixed(resize (uin1recip, outarray(0)'high,
outarray(0)'low));
elsif (tmp = "10") then
-- abs
in1pin2 := abs(in1array(3));
outarray(0) := resize (in1pin2,
outarray(0)'high,
outarray(0)'low);
else
-- -
in1pin2 := - in1array(3);
outarray(0) := resize (in1pin2,
outarray(0)'high,
outarray(0)'low);
end if;
end if;
end process cmd10reg;
-- purpose: "1011" test the mod operator
cmd11reg : process (clk, rst_n) is
variable in1min2 : sfixed (SFixed_high(7, -8, 'M', 7, -8) downto
SFixed_low(7, -8, 'm', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray11 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := to_sfixed(1, in2array(0));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray11 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := to_sfixed(1, in2array(0));
else
in2array(0) := in2reg3;
end if;
in1min2 := in1array(3) mod in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd11reg;
-- purpose: "1100" test the rem operator
cmd12reg : process (clk, rst_n) is
variable in1min2 : sfixed (SFixed_high(7, -8, 'R', 7, -8) downto
SFixed_low(7, -8, 'r', 7, -8));
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray12 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := to_sfixed(1, in2array(0));
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray12 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
if (in2reg3 = 0) then
in2array(0) := to_sfixed(1, in2array(0));
else
in2array(0) := in2reg3;
end if;
in1min2 := in1array(3) rem in2array(3);
outarray(0) := resize (in1min2, outarray(0));
end if;
end process cmd12reg;
-- purpose: "1101" test the srl operator
cmd13reg : process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray13 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray13 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
outarray(0) := in1array(3) srl to_integer(in2array(3));
end if;
end process cmd13reg;
-- purpose: "1110" test the sra operator
cmd14reg : process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray14 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray14 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
outarray(0) := in1array(3) sra to_integer(in2array(3));
end if;
end process cmd14reg;
-- purpose: "1111" test the sra operator
cmd15reg : process (clk, rst_n) is
constant match_data : sfixed16 := "01HL----10HL----"; -- for ?= command
variable outarray : cry_type; -- array for output
variable in1array, in2array : cry_type; -- array for input
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outarray15 <= (others => '0');
jrloop : for j in 0 to 4 loop
outarray (j) := (others => '0');
in1array (j) := (others => '0');
in2array (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outarray15 <= outarray(4);
jcloop : for j in 4 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
j1loop : for j in 3 downto 1 loop
in1array (j) := in1array(j-1);
end loop j1loop;
j2loop : for j in 3 downto 1 loop
in2array (j) := in2array(j-1);
end loop j2loop;
in1array(0) := in1reg3;
in2array(0) := in2reg3;
-- compare test
if (in1array(3) = in2array(3)) then
outarray(0)(-8) := '1';
else
outarray(0)(-8) := '0';
end if;
if (in1array(3) /= in2array(3)) then
outarray(0)(-7) := '1';
else
outarray(0)(-7) := '0';
end if;
if (in1array(3) < in2array(3)) then
outarray(0)(-6) := '1';
else
outarray(0)(-6) := '0';
end if;
if (in1array(3) > in2array(3)) then
outarray(0)(-5) := '1';
else
outarray(0)(-5) := '0';
end if;
if (in1array(3) <= in2array(3)) then
outarray(0)(-4) := '1';
else
outarray(0)(-4) := '0';
end if;
if (in1array(3) >= in2array(3)) then
outarray(0)(-3) := '1';
else
outarray(0)(-3) := '0';
end if;
if (in1array(3) = 45) then
outarray(0)(-2) := '1';
else
outarray(0)(-2) := '0';
end if;
if (in1array(3) = 3.125) then
outarray(0)(-1) := '1';
else
outarray(0)(-1) := '0';
end if;
-- add integer and real
outarray(0)(0) := \?=\ (in1array(3), in2array(3) + 45);
if (in1array(3) = in2array(3) + 3.125) then
outarray(0)(1) := '1';
else
outarray(0)(1) := '0';
end if;
if (std_match (in1array(3), match_data)) then
outarray(0)(2) := '1';
else
outarray(0)(2) := '0';
end if;
outarray(0)(3) := nor_reduce (in1array(3) or in2array(3));
outarray(0)(4) := xnor_reduce (in1array(3) xor in2array(3));
outarray(0)(5) := nand_reduce (not in1array(3));
outarray(0)(6) := or_reduce ('1' and ufixed(in1array(3)));
if find_leftmost(in1array(3), '1') = 3 then
outarray(0)(7) := '1';
else
outarray(0)(7) := '0';
end if;
end if;
end process cmd15reg;
-- purpose: register the inputs and the outputs
-- type : sequential
-- inputs : clk, rst_n, in1, in2
-- outputs: out1
cmdreg : process (clk, rst_n) is
variable outreg : sfixed16; -- register stages
variable in1reg, in2reg : sfixed16; -- register stages
variable in1reg2, in2reg2 : sfixed16; -- register stages
begin -- process mulreg
if rst_n = '0' then -- asynchronous reset (active low)
in1reg := (others => '0');
in2reg := (others => '0');
in1reg2 := (others => '0');
in2reg2 := (others => '0');
in1reg3 <= (others => '0');
in2reg3 <= (others => '0');
out1 <= (others => '0');
outreg := (others => '0');
rcloop : for i in 1 to 15 loop
cmdarray (i) <= (others => '0');
end loop rcloop;
elsif rising_edge(clk) then -- rising clock edge
out1 <= to_slv (outreg);
outregc : case cmdarray (13) is
when "0000" => outreg := outarray0;
when "0001" => outreg := outarray1;
when "0010" => outreg := outarray2;
when "0011" => outreg := outarray3;
when "0100" => outreg := outarray4;
when "0101" => outreg := outarray5;
when "0110" => outreg := outarray6;
when "0111" => outreg := outarray7;
when "1000" => outreg := outarray8;
when "1001" => outreg := outarray9;
when "1010" => outreg := outarray10;
when "1011" => outreg := outarray11;
when "1100" => outreg := outarray12;
when "1101" => outreg := outarray13;
when "1110" => outreg := outarray14;
when "1111" => outreg := outarray15;
when others => null;
end case outregc;
cmdpipe : for i in 15 downto 3 loop
cmdarray (i) <= cmdarray (i-1);
end loop cmdpipe;
cmdarray (2) <= STD_ULOGIC_VECTOR(cmd);
in1reg3 <= in1reg2;
in2reg3 <= in2reg2;
in1reg2 := in1reg;
in2reg2 := in2reg;
in1reg := to_sfixed (in1, in1reg);
in2reg := to_sfixed (in2, in2reg);
end if;
end process cmdreg;
end architecture rtl;
|
gpl-3.0
|
0c1596c4ea3868a310d54a52399cd4a6
| 0.530664 | 3.361616 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd
| 1 | 10,219 |
-- $Id: sn_humanio_demu_rbus.vhd 472 2013-01-06 14:39:10Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_demu_rbus - syn
-- Description: sn_humanio_demu with rbus interceptor
--
-- Dependencies: bpgen/sn_humanio_demu
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2013-01-06 472 13.3 O76xd xc3s1000-4 160 136 0 124 s 6.1 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-06 472 1.0 Initial version (cloned from sn_humanio_rbus
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register and BTN access
-- x:08 btn r/w/- r: return hio BTN status
-- w: ored with hio BTN to drive BTN
-- 3 dsp_en r/w/- if 1 display data will be driven by rbus
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
-- 1 led_en r/w/- if 1 LED will be driven by rri
-- 0 swi_en r/w/- if 1 SWI will be driven by rri
--
-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- bbbbbb10 led r/w/- Interface to LED and DSP_DP
-- 15:12 dp r/w/- r: returns DSP_DP status
-- w: will drive display dp's when dp_en=1
-- 7:00 led r/w/- r: returns LED status
-- w: will drive led's when led_en=1
--
-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status
-- w: will drive DSP_DAT when dsp_en=1
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end sn_humanio_demu_rbus;
architecture syn of sn_humanio_demu_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv8; -- rbus swi
btn : slv4; -- rbus btn
led : slv8; -- rbus led
dsp_dat : slv16; -- rbus dsp_dat
dsp_dp : slv4; -- rbus dsp_dp
ledin : slv8; -- led from design
swieff : slv8; -- effective swi
btneff : slv4; -- effective btn
ledeff : slv8; -- effective led
dpeff : slv4; -- effective dsp_dp
dateff : slv16; -- effective dsp_dat
swi_en : slbit; -- enable: swi from rbus
led_en : slbit; -- enable: led from rbus
dsp_en : slbit; -- enable: dsp_dat from rbus
dp_en : slbit; -- enable: dsp_dp from rbus
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- swi
(others=>'0'), -- btn
(others=>'0'), -- led
(others=>'0'), -- dsp_dat
(others=>'0'), -- dsp_dp
(others=>'0'), -- ledin
(others=>'0'), -- swieff
(others=>'0'), -- btneff
(others=>'0'), -- ledeff
(others=>'0'), -- dpeff
(others=>'0'), -- dateff
'0','0','0','0' -- (swi|led|dsp|dp)_en
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
subtype cntl_rbf_btn is integer range 11 downto 8;
constant cntl_rbf_dsp_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
subtype led_rbf_dp is integer range 15 downto 12;
subtype led_rbf_led is integer range 7 downto 0;
constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/-
constant rbaddr_swi: slv2 := "01"; -- 1 r/w/-
constant rbaddr_led: slv2 := "10"; -- 2 r/w/-
constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/-
signal HIO_SWI : slv8 := (others=>'0');
signal HIO_BTN : slv4 := (others=>'0');
signal HIO_LED : slv8 := (others=>'0');
signal HIO_DSP_DAT : slv16 := (others=>'0');
signal HIO_DSP_DP : slv4 := (others=>'0');
begin
HIO : sn_humanio_demu
generic map (
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => HIO_SWI,
BTN => HIO_BTN,
LED => HIO_LED,
DSP_DAT => HIO_DSP_DAT,
DSP_DP => HIO_DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- input register for LED signal
n.ledin := LED;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_btn) := HIO_BTN;
irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(cntl_rbf_btn);
n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
end if;
when rbaddr_swi =>
irb_dout(HIO_SWI'range) := HIO_SWI;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_led =>
irb_dout(led_rbf_dp) := HIO_DSP_DP;
irb_dout(led_rbf_led) := r.ledin;
if RB_MREQ.we = '1' then
n.dsp_dp := RB_MREQ.din(led_rbf_dp);
n.led := RB_MREQ.din(led_rbf_led);
end if;
when rbaddr_dsp =>
irb_dout := HIO_DSP_DAT;
if RB_MREQ.we = '1' then
n.dsp_dat := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
n.btneff := HIO_BTN or r.btn;
if r.swi_en = '0' then
n.swieff := HIO_SWI;
else
n.swieff := r.swi;
end if;
if r.led_en = '0' then
n.ledeff := r.ledin;
else
n.ledeff := r.led;
end if;
if r.dp_en = '0' then
n.dpeff := DSP_DP;
else
n.dpeff := r.dsp_dp;
end if;
if r.dsp_en = '0' then
n.dateff := DSP_DAT;
else
n.dateff := r.dsp_dat;
end if;
N_REGS <= n;
BTN <= R_REGS.btneff;
SWI <= R_REGS.swieff;
HIO_LED <= R_REGS.ledeff;
HIO_DSP_DP <= R_REGS.dpeff;
HIO_DSP_DAT <= R_REGS.dateff;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
|
gpl-2.0
|
71c0ce86dfddc2e92adaeaa8b66657d1
| 0.471083 | 3.518939 | false | false | false | false |
freecores/w11
|
rtl/vlib/simlib/simlib.vhd
| 1 | 28,220 |
-- $Id: simlib.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simlib - sim
-- Description: Support routines for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 drop CLK_CYCLE from simclk,simclkv; use integer for
-- simclkcnt(CLK_CYCLE),writetimestamp(clkcyc);
-- 2011-11-18 427 1.3.8 now numeric_std clean
-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm
-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
-- 2007-12-27 106 1.3.3 added simclk2v
-- 2007-12-15 101 1.3.2 add read_ea(time), readtagval[_ea](std_logic)
-- 2007-10-12 88 1.3.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-28 76 1.3 added writehex and writegen
-- 2007-08-10 72 1.2.2 remove entity simclk, put into separate source
-- 2007-08-03 71 1.2.1 readgen, readtagval, readtagval2: add base arg
-- 2007-07-29 70 1.2 readtagval2: add tag=- support; add readword_ea,
-- readoptchar, writetimestamp
-- 2007-07-28 69 1.1.1 rename readrest -> testempty; add readgen
-- use readgen in readtagval() and readtagval2()
-- 2007-07-22 68 1.1 add readrest, readtagval, readtagval2
-- 2007-06-30 62 1.0.1 remove clock_period ect constant defs
-- 2007-06-14 56 1.0 Initial version (renamed from pdp11_sim.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
package simlib is
constant null_char : character := character'val(0); -- '\0'
constant null_string : string(1 to 1) := (others=>null_char); -- "\0"
procedure readwhite( -- read over white space
L: inout line); -- line
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer:= 2); -- default base
procedure readcomment(
L: inout line;
good: out boolean);
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean);
procedure readword(
L: inout line;
name: out string;
good: out boolean);
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean);
procedure readempty(
L: inout line);
procedure testempty(
L: inout line;
good: out boolean);
procedure testempty_ea(
L: inout line);
procedure read_ea(
L: inout line;
value: out integer);
procedure read_ea(
L: inout line;
value: out time);
procedure read_ea(
L: inout line;
value: out std_logic);
procedure read_ea(
L: inout line;
value: out std_logic_vector);
procedure readoct_ea(
L: inout line;
value: out std_logic_vector);
procedure readhex_ea(
L: inout line;
value: out std_logic_vector);
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer:= 2);
procedure readword_ea(
L: inout line;
name: out string);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic);
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2);
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:= 2); -- default base
procedure writetimestamp(
L: inout line;
clkcyc: in integer;
str : in string := null_string);
-- ----------------------------------------------------------------------------
component simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit -- clock stop trigger
);
end component;
component simclkv is -- test bench clock generator
-- with variable periods
port (
CLK : out slbit; -- clock
CLK_PERIOD : in time; -- clock period
CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit -- clock stop trigger
);
end component;
component simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out integer -- clock cycle number
);
end component;
end package simlib;
-- ----------------------------------------------------------------------------
package body simlib is
procedure readwhite( -- read over white space
L: inout line) is -- line
variable ch : character;
begin
while L'length>0 loop
ch := L(L'left);
exit when (ch/=' ' and ch/=HT);
read(L,ch);
end loop;
end procedure readwhite;
-- -------------------------------------
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(2 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readoct called with ascending range"
severity failure;
assert value'length<=32
report "readoct called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "000";
when '1' => nibble := "001";
when '2' => nibble := "010";
when '3' => nibble := "011";
when '4' => nibble := "100";
when '5' => nibble := "101";
when '6' => nibble := "110";
when '7' => nibble := "111";
when 'u'|'U' => nibble := "UUU";
when 'x'|'X' => nibble := "XXX";
when 'z'|'Z' => nibble := "ZZZ";
when '-' => nibble := "---";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 3) := sum(sum'left-3 downto 0);
sum(2 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readoct;
-- -------------------------------------
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readhex called with ascending range"
severity failure;
assert value'length<=32
report "readhex called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "0000";
when '1' => nibble := "0001";
when '2' => nibble := "0010";
when '3' => nibble := "0011";
when '4' => nibble := "0100";
when '5' => nibble := "0101";
when '6' => nibble := "0110";
when '7' => nibble := "0111";
when '8' => nibble := "1000";
when '9' => nibble := "1001";
when 'a'|'A' => nibble := "1010";
when 'b'|'B' => nibble := "1011";
when 'c'|'C' => nibble := "1100";
when 'd'|'D' => nibble := "1101";
when 'e'|'E' => nibble := "1110";
when 'f'|'F' => nibble := "1111";
when 'u'|'U' => nibble := "UUUU";
when 'x'|'X' => nibble := "XXXX";
when 'z'|'Z' => nibble := "ZZZZ";
when '-' => nibble := "----";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 4) := sum(sum'left-4 downto 0);
sum(3 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readhex;
-- -------------------------------------
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer := 2) is -- default base
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable lbase : integer; -- local base
variable cbase : integer; -- current base
variable ok : boolean;
variable ivalue : integer;
variable ichar : character;
begin
assert not value'ascending(1)
report "readgen called with ascending range"
severity failure;
assert value'length<=32
report "readgen called with value'length > 32"
severity failure;
assert base=2 or base=8 or base=10 or base=16
report "readgen base not 2,8,10, or 16"
severity failure;
readwhite(L);
cbase := base;
lbase := 0;
ok := true;
if L'length >= 2 then
if L(L'left+1) = '"' then
case L(L'left) is
when 'b'|'B' => lbase := 2;
when 'o'|'O' => lbase := 8;
when 'd'|'D' => lbase := 10;
when 'x'|'X' => lbase := 16;
when others => ok := false;
end case;
end if;
if lbase /= 0 then
read(L, ichar);
read(L, ichar);
cbase := lbase;
end if;
end if;
if ok then
case cbase is
when 2 => read(L, value, ok);
when 8 => readoct(L, value, ok);
when 16 => readhex(L, value, ok);
when 10 =>
read(L, ivalue, ok);
-- the following if allows to enter negative integers, e.g. -1 for all-1
if ivalue >= 0 then
value := slv(to_unsigned(ivalue, value'length));
else
value := slv(to_signed(ivalue, value'length));
end if;
when others => null;
end case;
end if;
if ok and lbase/=0 then
if L'length>0 and L(L'left)='"' then
read(L, ichar);
else
ok := false;
end if;
end if;
good := ok;
end procedure readgen;
-- -------------------------------------
procedure readcomment(
L: inout line;
good: out boolean) is
variable ichar : character;
begin
readwhite(L);
good := true;
if L'length > 0 then
good := false;
if L(L'left) = '#' then
good := true;
elsif L(L'left) = 'C' then
good := true;
writeline(output, L);
end if;
end if;
end procedure readcomment;
-- -------------------------------------
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean) is
begin
for i in name'range loop
name(i) := ' ';
end loop;
good := false;
if L'length>0 and L(L'left)='.' then
readword(L, name, good);
end if;
end procedure readdotcomm;
-- -------------------------------------
procedure readword(
L: inout line;
name: out string;
good: out boolean) is
variable ichar : character;
variable ind : integer;
begin
assert name'ascending(1)
report "readword called with descending range for name"
severity failure;
readwhite(L);
for i in name'range loop
name(i) := ' ';
end loop;
ind := name'left;
while L'length>0 and ind<=name'right loop
ichar := L(L'left);
exit when ichar=' ' or ichar=',' or ichar='|';
read(L,ichar);
name(ind) := ichar;
ind := ind + 1;
end loop;
good := ind /= name'left; -- ok if one non-blank found
end procedure readword;
-- -------------------------------------
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean) is
variable ichar : character;
begin
good := false;
if L'length > 0 then
if L(L'left) = char then
read(L, ichar);
good := true;
end if;
end if;
end procedure readoptchar;
-- -------------------------------------
procedure readempty(
L: inout line) is
variable ch : character;
begin
while L'length>0 loop -- anything left ?
read(L,ch); -- read and discard it
end loop;
end procedure readempty;
-- -------------------------------------
procedure testempty(
L: inout line;
good: out boolean) is
begin
readwhite(L); -- discard white space
good := true; -- good if now empty
if L'length > 0 then -- anything left ?
good := false; -- assume bad
if L'length >= 2 and -- check for "--"
L(L'left)='-' and L(L'left+1)='-' then
good := true; -- in that case comment -> good
end if;
end if;
end procedure testempty;
-- -------------------------------------
procedure testempty_ea(
L: inout line) is
variable ok : boolean := false;
begin
testempty(L, ok);
assert ok report "extra chars in """ & L.all & """" severity failure;
end procedure testempty_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out integer) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(integer) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out time) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(time) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure readoct_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readoct(L, value, ok);
assert ok report "readoct() conversion error in """ &
L.all & """" severity failure;
end procedure readoct_ea;
-- -------------------------------------
procedure readhex_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readhex(L, value, ok);
assert ok report "readhex() conversion error in """ &
L.all & """" severity failure;
end procedure readhex_ea;
-- -------------------------------------
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer := 2) is
variable ok : boolean := false;
begin
readgen(L, value, ok, base);
assert ok report "readgen() conversion error in """ &
L.all & """" severity failure;
end procedure readgen_ea;
-- -------------------------------------
procedure readword_ea(
L: inout line;
name: out string) is
variable ok : boolean := false;
begin
readword(L, name, ok);
assert ok report "readword() read error in """ &
L.all & """" severity failure;
end procedure readword_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
for i in val'range loop
val(i) := '0';
end loop;
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
readgen(L, val, good, base);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok, base);
assert ok report "readtagval(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
val := '0';
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
read(L, val, good);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok);
assert ok report "readtagval(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable imatch : boolean;
variable igood : boolean;
variable ichar : character;
variable ok : boolean;
begin
readwhite(L);
for i in val1'range loop -- zero val1
val1(i) := '0';
end loop;
for i in val2'range loop -- zero val2
val2(i) := '0';
end loop;
igood := true;
imatch := false;
if L'length > tag'length then -- check for tag
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then -- if found
read(L, itag); -- remove tag
read(L, ichar); -- remove =
igood := false;
readoptchar(L, '-', ok); -- check for tag=-
if ok then
for i in val2'range loop -- set mask to all 1 (ignore)
val2(i) := '1';
end loop;
igood := true;
else -- here if tag=bit[,bit]
readgen(L, val1, igood, base); -- read val1
if igood then
readoptchar(L, ',', ok); -- check(and remove) ,
if ok then
readgen(L, val2, igood, base); -- and read val2
end if;
end if;
end if;
end if;
end if;
match := imatch;
good := igood;
end procedure readtagval2;
-- -------------------------------------
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval2(L, tag, match, val1, val2, ok, base);
assert ok report "readtagval2() conversion error in """ &
L.all & """" severity failure;
end procedure readtagval2_ea;
-- -------------------------------------
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(2 downto 0);
variable ochar : character;
begin
assert not value'ascending(1)
report "writeoct called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+2)/3;
iwidth := nbit mod 3;
if iwidth = 0 then
iwidth := 3;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for i in nibble'range loop
case nibble(i) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- i
if ochar = ' ' then
write(L,to_integer(unsigned(nibble)));
else
write(L,ochar);
end if;
iwidth := 3;
ioffset := ioffset - 3;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writeoct;
-- -------------------------------------
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(3 downto 0);
variable ochar : character;
variable hextab : string(1 to 16) := "0123456789abcdef";
begin
assert not value'ascending(1)
report "writehex called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+3)/4;
iwidth := nbit mod 4;
if iwidth = 0 then
iwidth := 4;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "0000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for i in nibble'range loop
case nibble(i) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- i
if ochar = ' ' then
write(L,hextab(to_integer(unsigned(nibble))+1));
else
write(L,ochar);
end if;
iwidth := 4;
ioffset := ioffset - 4;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writehex;
-- -------------------------------------
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:=2) is -- default base
begin
case base is
when 2 => write(L, value, justified, field);
when 8 => writeoct(L, value, justified, field);
when 16 => writehex(L, value, justified, field);
when others => report "writegen base not 2,8, or 16"
severity failure;
end case;
end procedure writegen;
-- -------------------------------------
procedure writetimestamp(
L: inout line;
clkcyc: in integer;
str: in string := null_string) is
variable t_nsec : integer := 0;
variable t_psec : integer := 0;
variable t_dnsec : integer := 0;
begin
t_nsec := now / 1 ns;
t_psec := (now - t_nsec * 1 ns) / 1 ps;
t_dnsec := t_psec/100;
-- write(L, now, right, 12);
write(L, t_nsec, right, 8);
write(L,'.');
write(L, t_dnsec, right, 1);
write(L, string'(" ns"));
write(L, clkcyc, right, 7);
if str /= null_string then
write(L, str);
end if;
end procedure writetimestamp;
end package body simlib;
|
gpl-2.0
|
d5fef210389e03878d9e9ddb1113b9b3
| 0.539157 | 3.811453 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/top.vhd
| 1 | 4,926 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : top.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : top
-- ARCHITECTURE : structure
--=============================================================================
-- AUTORS(s) : Agostini, N; Barbosa, F
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : NOV 28, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for top
--=============================================================================
entity top is
port (
-- async receiver/transmitter com ports
CLOCK_50 : in std_logic;
UART_RXD : in std_logic;
UART_TXD : out std_logic;
LEDR : out std_logic_vector (17 downto 0)
);
end top;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture structure of top is
signal rxReady : std_logic;
signal rxData : std_logic_vector(7 downto 0);
signal txBusy : std_logic;
signal txStart : std_logic;
signal txData : std_logic_vector(7 downto 0);
signal NN_start : std_logic; -- 0 - stop / 1 - start neural net
signal NN_sample : std_logic_vector (7 downto 0);
signal NN_result : std_logic_vector (1 downto 0);
signal NN_expected : std_logic_vector (1 downto 0);
signal NN_ready : std_logic;
component rs_232
port (
clk : in std_logic;
txStart : in std_logic;
txData : in std_logic_vector(7 downto 0);
rxD : in std_logic;
rxReady : out std_logic;
rxData : out std_logic_vector(7 downto 0);
txBusy : out std_logic;
txD : out std_logic
);
end component;
component controller
port (
-- async receiver/transmitter com ports
clk : in std_logic;
rxReady : in std_logic;
rxData : in std_logic_vector(7 downto 0); -- command string (character)
txBusy : in std_logic;
txStart : out std_logic;
txData : out std_logic_vector(7 downto 0);
-- LEDs (for debugging)
leds : out std_logic_vector (17 downto 0);
-- control ports
NN_start : out std_logic;
NN_sample : out std_logic_vector (7 downto 0);
NN_result : in std_logic_vector (1 downto 0);
NN_expected : in std_logic_vector (1 downto 0);
NN_ready : in std_logic
);
end component;
component NN_INSTANCE
port (
clk : in std_logic;
NN_start : in std_logic;
NN_sample : in std_logic_vector (7 downto 0);
NN_result : out std_logic_vector (1 downto 0);
NN_expected : out std_logic_vector (1 downto 0);
NN_ready : out std_logic
);
end component;
--=============================================================================
-- architecture begin
--=============================================================================
begin
serial_interface : rs_232
port map (
clk => CLOCK_50,
txStart => txStart,
txData => txData,
rxD => UART_RXD,
rxReady => rxReady,
rxData => rxData,
txBusy => txBusy,
txD => UART_TXD
);
control_block : controller
port map (
clk => CLOCK_50,
rxReady => rxReady,
rxData => rxData,
txBusy => txBusy,
txStart => txStart,
txData => txData,
leds => LEDR,
NN_start => NN_start,
NN_sample => NN_sample,
NN_result => NN_result,
NN_expected => NN_expected,
NN_ready => NN_ready
);
neural_net : NN_INSTANCE
port map (
clk => CLOCK_50,
NN_start => NN_start,
NN_sample => NN_sample,
NN_result => NN_result,
NN_expected => NN_expected,
NN_ready => NN_ready
);
end structure;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
0cb6de1bf3de7e14aef14c8c7e5c89f9
| 0.503857 | 3.526127 | false | false | false | false |
unhold/hdl
|
vhdl/vether/vether_xo2.vendor.vhd
| 1 | 1,831 |
library ieee;
use ieee.std_logic_1164.all;
library machxo2;
use machxo2.components;
entity vether_xo2 is
port (
tx_po,
tx_no : out std_ulogic;
led_no : out std_ulogic_vector(7 downto 0));
end;
architecture tbd of vether_xo2 is
attribute frequency_pin_clkos : string;
attribute frequency_pin_clkos of pll : label is "19.950000";
attribute frequency_pin_clki : string;
attribute frequency_pin_clki of pll : label is "133.000000";
attribute icp_current : string;
attribute icp_current of pll : label is "9";
attribute lpf_resistor : string;
attribute lpf_resistor of pll : label is "72";
constant clk_freq : natural := 19_950e3;
signal clk133, clk, lock, rst, stb, run, tx_p, tx_n, run_pulse : std_ulogic;
begin
osc : component machxo2.components.osch
generic map (
nom_freq => "133.0")
port map (
stdby => '0',
osc => clk133);
pll : component machxo2.components.ehxpllj
generic map (
clki_div => 16,
clkfb_div => 3,
clkop_div => 20,
clkos_div => 25,
clkop_cphase => 19,
clkos_cphase => 24,
clkos2_enable => "DISABLED",
clkos3_enable => "DISABLED",
feedbk_path => "INT_DIVA")
port map (
clki => clk133,
clkos => clk,
lock => lock);
rst <= not lock;
stb_gen : entity work.stb_gen
generic map (
period_g => clk_freq) -- 1 sec
port map (
rst_i => rst,
clk_i => clk,
stb_o => stb);
vether_tx : entity work.vether_tx
generic map (
clk_freq_g => clk_freq)
port map (
rst_i => rst,
clk_i => clk,
stb_i => stb,
tx_po => tx_p,
tx_no => tx_n,
run_o => run);
run_pulse_gen : entity work.pulse_gen
generic map (
duration_g => clk_freq/10) -- 100 ms
port map (
rst_i => rst,
clk_i => clk,
stb_i => run,
pulse_o => run_pulse);
led_no <= not ("00000" & tx_p & tx_n & run_pulse);
tx_po <= tx_p;
tx_no <= tx_n;
end;
|
gpl-3.0
|
0a187d1ccfb312b5b9d5bedc3a9aabd3
| 0.622064 | 2.665211 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/bp_rs232_2line_iob.vhd
| 2 | 2,279 |
-- $Id: bp_rs232_2line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2line_iob - syn
-- Description: iob's for 2 line rs232 (RXD,TXD only)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 Moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_int)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end bp_rs232_2line_iob;
architecture syn of bp_rs232_2line_iob is
begin
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
end syn;
|
gpl-2.0
|
49ec94729090c93d98154004c0cb269f
| 0.538394 | 3.663987 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/sigmoid/sigmoid_rom.vhd
| 1 | 36,954 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- if not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : SIGMOID_ROM.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : SIGMOID_ROM
-- ARCHITECTURE : rtl
--=============================================================================
-- AUTORS(s) : Agostini, N;
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 14, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- is the to unsigned really required????
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.NN_TYPES_pkg.all;
use work.SIGMOID_ROM_pkg.all;
--=============================================================================
-- Entity declaration for SIGMOID_ROM
--=============================================================================
entity SIGMOID_ROM is
port (
clk : in std_logic;
X_VALUE : in std_logic_vector ((NUMBER_OF_BITS-1) downto 0);
Y_VALUE : out CONSTRAINED_SFIXED
);
end SIGMOID_ROM;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture RTL of SIGMOID_ROM is
-- Constants
-- This constant has 1024 values
constant TAN_SIG : TAN_SIG_VECTOR := (
to_sfixed(-0.9951,1,L_SIZE),
to_sfixed(-0.9950,1,L_SIZE),
to_sfixed(-0.9949,1,L_SIZE),
to_sfixed(-0.9949,1,L_SIZE),
to_sfixed(-0.9948,1,L_SIZE),
to_sfixed(-0.9948,1,L_SIZE),
to_sfixed(-0.9947,1,L_SIZE),
to_sfixed(-0.9946,1,L_SIZE),
to_sfixed(-0.9946,1,L_SIZE),
to_sfixed(-0.9945,1,L_SIZE),
to_sfixed(-0.9944,1,L_SIZE),
to_sfixed(-0.9944,1,L_SIZE),
to_sfixed(-0.9943,1,L_SIZE),
to_sfixed(-0.9942,1,L_SIZE),
to_sfixed(-0.9942,1,L_SIZE),
to_sfixed(-0.9941,1,L_SIZE),
to_sfixed(-0.9940,1,L_SIZE),
to_sfixed(-0.9940,1,L_SIZE),
to_sfixed(-0.9939,1,L_SIZE),
to_sfixed(-0.9938,1,L_SIZE),
to_sfixed(-0.9938,1,L_SIZE),
to_sfixed(-0.9937,1,L_SIZE),
to_sfixed(-0.9936,1,L_SIZE),
to_sfixed(-0.9935,1,L_SIZE),
to_sfixed(-0.9935,1,L_SIZE),
to_sfixed(-0.9934,1,L_SIZE),
to_sfixed(-0.9933,1,L_SIZE),
to_sfixed(-0.9932,1,L_SIZE),
to_sfixed(-0.9931,1,L_SIZE),
to_sfixed(-0.9931,1,L_SIZE),
to_sfixed(-0.9930,1,L_SIZE),
to_sfixed(-0.9929,1,L_SIZE),
to_sfixed(-0.9928,1,L_SIZE),
to_sfixed(-0.9927,1,L_SIZE),
to_sfixed(-0.9926,1,L_SIZE),
to_sfixed(-0.9926,1,L_SIZE),
to_sfixed(-0.9925,1,L_SIZE),
to_sfixed(-0.9924,1,L_SIZE),
to_sfixed(-0.9923,1,L_SIZE),
to_sfixed(-0.9922,1,L_SIZE),
to_sfixed(-0.9921,1,L_SIZE),
to_sfixed(-0.9920,1,L_SIZE),
to_sfixed(-0.9919,1,L_SIZE),
to_sfixed(-0.9918,1,L_SIZE),
to_sfixed(-0.9917,1,L_SIZE),
to_sfixed(-0.9916,1,L_SIZE),
to_sfixed(-0.9915,1,L_SIZE),
to_sfixed(-0.9914,1,L_SIZE),
to_sfixed(-0.9913,1,L_SIZE),
to_sfixed(-0.9912,1,L_SIZE),
to_sfixed(-0.9911,1,L_SIZE),
to_sfixed(-0.9910,1,L_SIZE),
to_sfixed(-0.9909,1,L_SIZE),
to_sfixed(-0.9908,1,L_SIZE),
to_sfixed(-0.9907,1,L_SIZE),
to_sfixed(-0.9906,1,L_SIZE),
to_sfixed(-0.9905,1,L_SIZE),
to_sfixed(-0.9904,1,L_SIZE),
to_sfixed(-0.9903,1,L_SIZE),
to_sfixed(-0.9902,1,L_SIZE),
to_sfixed(-0.9900,1,L_SIZE),
to_sfixed(-0.9899,1,L_SIZE),
to_sfixed(-0.9898,1,L_SIZE),
to_sfixed(-0.9897,1,L_SIZE),
to_sfixed(-0.9896,1,L_SIZE),
to_sfixed(-0.9894,1,L_SIZE),
to_sfixed(-0.9893,1,L_SIZE),
to_sfixed(-0.9892,1,L_SIZE),
to_sfixed(-0.9891,1,L_SIZE),
to_sfixed(-0.9889,1,L_SIZE),
to_sfixed(-0.9888,1,L_SIZE),
to_sfixed(-0.9887,1,L_SIZE),
to_sfixed(-0.9885,1,L_SIZE),
to_sfixed(-0.9884,1,L_SIZE),
to_sfixed(-0.9883,1,L_SIZE),
to_sfixed(-0.9881,1,L_SIZE),
to_sfixed(-0.9880,1,L_SIZE),
to_sfixed(-0.9879,1,L_SIZE),
to_sfixed(-0.9877,1,L_SIZE),
to_sfixed(-0.9876,1,L_SIZE),
to_sfixed(-0.9874,1,L_SIZE),
to_sfixed(-0.9873,1,L_SIZE),
to_sfixed(-0.9871,1,L_SIZE),
to_sfixed(-0.9870,1,L_SIZE),
to_sfixed(-0.9868,1,L_SIZE),
to_sfixed(-0.9867,1,L_SIZE),
to_sfixed(-0.9865,1,L_SIZE),
to_sfixed(-0.9864,1,L_SIZE),
to_sfixed(-0.9862,1,L_SIZE),
to_sfixed(-0.9860,1,L_SIZE),
to_sfixed(-0.9859,1,L_SIZE),
to_sfixed(-0.9857,1,L_SIZE),
to_sfixed(-0.9855,1,L_SIZE),
to_sfixed(-0.9854,1,L_SIZE),
to_sfixed(-0.9852,1,L_SIZE),
to_sfixed(-0.9850,1,L_SIZE),
to_sfixed(-0.9848,1,L_SIZE),
to_sfixed(-0.9847,1,L_SIZE),
to_sfixed(-0.9845,1,L_SIZE),
to_sfixed(-0.9843,1,L_SIZE),
to_sfixed(-0.9841,1,L_SIZE),
to_sfixed(-0.9839,1,L_SIZE),
to_sfixed(-0.9838,1,L_SIZE),
to_sfixed(-0.9836,1,L_SIZE),
to_sfixed(-0.9834,1,L_SIZE),
to_sfixed(-0.9832,1,L_SIZE),
to_sfixed(-0.9830,1,L_SIZE),
to_sfixed(-0.9828,1,L_SIZE),
to_sfixed(-0.9826,1,L_SIZE),
to_sfixed(-0.9824,1,L_SIZE),
to_sfixed(-0.9822,1,L_SIZE),
to_sfixed(-0.9820,1,L_SIZE),
to_sfixed(-0.9817,1,L_SIZE),
to_sfixed(-0.9815,1,L_SIZE),
to_sfixed(-0.9813,1,L_SIZE),
to_sfixed(-0.9811,1,L_SIZE),
to_sfixed(-0.9809,1,L_SIZE),
to_sfixed(-0.9807,1,L_SIZE),
to_sfixed(-0.9804,1,L_SIZE),
to_sfixed(-0.9802,1,L_SIZE),
to_sfixed(-0.9800,1,L_SIZE),
to_sfixed(-0.9797,1,L_SIZE),
to_sfixed(-0.9795,1,L_SIZE),
to_sfixed(-0.9793,1,L_SIZE),
to_sfixed(-0.9790,1,L_SIZE),
to_sfixed(-0.9788,1,L_SIZE),
to_sfixed(-0.9785,1,L_SIZE),
to_sfixed(-0.9783,1,L_SIZE),
to_sfixed(-0.9780,1,L_SIZE),
to_sfixed(-0.9778,1,L_SIZE),
to_sfixed(-0.9775,1,L_SIZE),
to_sfixed(-0.9772,1,L_SIZE),
to_sfixed(-0.9770,1,L_SIZE),
to_sfixed(-0.9767,1,L_SIZE),
to_sfixed(-0.9764,1,L_SIZE),
to_sfixed(-0.9762,1,L_SIZE),
to_sfixed(-0.9759,1,L_SIZE),
to_sfixed(-0.9756,1,L_SIZE),
to_sfixed(-0.9753,1,L_SIZE),
to_sfixed(-0.9750,1,L_SIZE),
to_sfixed(-0.9748,1,L_SIZE),
to_sfixed(-0.9745,1,L_SIZE),
to_sfixed(-0.9742,1,L_SIZE),
to_sfixed(-0.9739,1,L_SIZE),
to_sfixed(-0.9736,1,L_SIZE),
to_sfixed(-0.9732,1,L_SIZE),
to_sfixed(-0.9729,1,L_SIZE),
to_sfixed(-0.9726,1,L_SIZE),
to_sfixed(-0.9723,1,L_SIZE),
to_sfixed(-0.9720,1,L_SIZE),
to_sfixed(-0.9717,1,L_SIZE),
to_sfixed(-0.9713,1,L_SIZE),
to_sfixed(-0.9710,1,L_SIZE),
to_sfixed(-0.9707,1,L_SIZE),
to_sfixed(-0.9703,1,L_SIZE),
to_sfixed(-0.9700,1,L_SIZE),
to_sfixed(-0.9696,1,L_SIZE),
to_sfixed(-0.9693,1,L_SIZE),
to_sfixed(-0.9689,1,L_SIZE),
to_sfixed(-0.9686,1,L_SIZE),
to_sfixed(-0.9682,1,L_SIZE),
to_sfixed(-0.9678,1,L_SIZE),
to_sfixed(-0.9674,1,L_SIZE),
to_sfixed(-0.9671,1,L_SIZE),
to_sfixed(-0.9667,1,L_SIZE),
to_sfixed(-0.9663,1,L_SIZE),
to_sfixed(-0.9659,1,L_SIZE),
to_sfixed(-0.9655,1,L_SIZE),
to_sfixed(-0.9651,1,L_SIZE),
to_sfixed(-0.9647,1,L_SIZE),
to_sfixed(-0.9643,1,L_SIZE),
to_sfixed(-0.9639,1,L_SIZE),
to_sfixed(-0.9635,1,L_SIZE),
to_sfixed(-0.9630,1,L_SIZE),
to_sfixed(-0.9626,1,L_SIZE),
to_sfixed(-0.9622,1,L_SIZE),
to_sfixed(-0.9618,1,L_SIZE),
to_sfixed(-0.9613,1,L_SIZE),
to_sfixed(-0.9609,1,L_SIZE),
to_sfixed(-0.9604,1,L_SIZE),
to_sfixed(-0.9600,1,L_SIZE),
to_sfixed(-0.9595,1,L_SIZE),
to_sfixed(-0.9590,1,L_SIZE),
to_sfixed(-0.9585,1,L_SIZE),
to_sfixed(-0.9581,1,L_SIZE),
to_sfixed(-0.9576,1,L_SIZE),
to_sfixed(-0.9571,1,L_SIZE),
to_sfixed(-0.9566,1,L_SIZE),
to_sfixed(-0.9561,1,L_SIZE),
to_sfixed(-0.9556,1,L_SIZE),
to_sfixed(-0.9551,1,L_SIZE),
to_sfixed(-0.9546,1,L_SIZE),
to_sfixed(-0.9540,1,L_SIZE),
to_sfixed(-0.9535,1,L_SIZE),
to_sfixed(-0.9530,1,L_SIZE),
to_sfixed(-0.9524,1,L_SIZE),
to_sfixed(-0.9519,1,L_SIZE),
to_sfixed(-0.9513,1,L_SIZE),
to_sfixed(-0.9508,1,L_SIZE),
to_sfixed(-0.9502,1,L_SIZE),
to_sfixed(-0.9496,1,L_SIZE),
to_sfixed(-0.9491,1,L_SIZE),
to_sfixed(-0.9485,1,L_SIZE),
to_sfixed(-0.9479,1,L_SIZE),
to_sfixed(-0.9473,1,L_SIZE),
to_sfixed(-0.9467,1,L_SIZE),
to_sfixed(-0.9461,1,L_SIZE),
to_sfixed(-0.9455,1,L_SIZE),
to_sfixed(-0.9448,1,L_SIZE),
to_sfixed(-0.9442,1,L_SIZE),
to_sfixed(-0.9436,1,L_SIZE),
to_sfixed(-0.9429,1,L_SIZE),
to_sfixed(-0.9423,1,L_SIZE),
to_sfixed(-0.9416,1,L_SIZE),
to_sfixed(-0.9409,1,L_SIZE),
to_sfixed(-0.9403,1,L_SIZE),
to_sfixed(-0.9396,1,L_SIZE),
to_sfixed(-0.9389,1,L_SIZE),
to_sfixed(-0.9382,1,L_SIZE),
to_sfixed(-0.9375,1,L_SIZE),
to_sfixed(-0.9368,1,L_SIZE),
to_sfixed(-0.9360,1,L_SIZE),
to_sfixed(-0.9353,1,L_SIZE),
to_sfixed(-0.9346,1,L_SIZE),
to_sfixed(-0.9338,1,L_SIZE),
to_sfixed(-0.9331,1,L_SIZE),
to_sfixed(-0.9323,1,L_SIZE),
to_sfixed(-0.9315,1,L_SIZE),
to_sfixed(-0.9308,1,L_SIZE),
to_sfixed(-0.9300,1,L_SIZE),
to_sfixed(-0.9292,1,L_SIZE),
to_sfixed(-0.9284,1,L_SIZE),
to_sfixed(-0.9276,1,L_SIZE),
to_sfixed(-0.9267,1,L_SIZE),
to_sfixed(-0.9259,1,L_SIZE),
to_sfixed(-0.9251,1,L_SIZE),
to_sfixed(-0.9242,1,L_SIZE),
to_sfixed(-0.9234,1,L_SIZE),
to_sfixed(-0.9225,1,L_SIZE),
to_sfixed(-0.9216,1,L_SIZE),
to_sfixed(-0.9207,1,L_SIZE),
to_sfixed(-0.9198,1,L_SIZE),
to_sfixed(-0.9189,1,L_SIZE),
to_sfixed(-0.9180,1,L_SIZE),
to_sfixed(-0.9171,1,L_SIZE),
to_sfixed(-0.9161,1,L_SIZE),
to_sfixed(-0.9152,1,L_SIZE),
to_sfixed(-0.9142,1,L_SIZE),
to_sfixed(-0.9133,1,L_SIZE),
to_sfixed(-0.9123,1,L_SIZE),
to_sfixed(-0.9113,1,L_SIZE),
to_sfixed(-0.9103,1,L_SIZE),
to_sfixed(-0.9093,1,L_SIZE),
to_sfixed(-0.9083,1,L_SIZE),
to_sfixed(-0.9072,1,L_SIZE),
to_sfixed(-0.9062,1,L_SIZE),
to_sfixed(-0.9051,1,L_SIZE),
to_sfixed(-0.9041,1,L_SIZE),
to_sfixed(-0.9030,1,L_SIZE),
to_sfixed(-0.9019,1,L_SIZE),
to_sfixed(-0.9008,1,L_SIZE),
to_sfixed(-0.8997,1,L_SIZE),
to_sfixed(-0.8986,1,L_SIZE),
to_sfixed(-0.8975,1,L_SIZE),
to_sfixed(-0.8963,1,L_SIZE),
to_sfixed(-0.8952,1,L_SIZE),
to_sfixed(-0.8940,1,L_SIZE),
to_sfixed(-0.8928,1,L_SIZE),
to_sfixed(-0.8916,1,L_SIZE),
to_sfixed(-0.8904,1,L_SIZE),
to_sfixed(-0.8892,1,L_SIZE),
to_sfixed(-0.8879,1,L_SIZE),
to_sfixed(-0.8867,1,L_SIZE),
to_sfixed(-0.8854,1,L_SIZE),
to_sfixed(-0.8842,1,L_SIZE),
to_sfixed(-0.8829,1,L_SIZE),
to_sfixed(-0.8816,1,L_SIZE),
to_sfixed(-0.8803,1,L_SIZE),
to_sfixed(-0.8789,1,L_SIZE),
to_sfixed(-0.8776,1,L_SIZE),
to_sfixed(-0.8762,1,L_SIZE),
to_sfixed(-0.8749,1,L_SIZE),
to_sfixed(-0.8735,1,L_SIZE),
to_sfixed(-0.8721,1,L_SIZE),
to_sfixed(-0.8707,1,L_SIZE),
to_sfixed(-0.8693,1,L_SIZE),
to_sfixed(-0.8678,1,L_SIZE),
to_sfixed(-0.8664,1,L_SIZE),
to_sfixed(-0.8649,1,L_SIZE),
to_sfixed(-0.8634,1,L_SIZE),
to_sfixed(-0.8619,1,L_SIZE),
to_sfixed(-0.8604,1,L_SIZE),
to_sfixed(-0.8589,1,L_SIZE),
to_sfixed(-0.8573,1,L_SIZE),
to_sfixed(-0.8558,1,L_SIZE),
to_sfixed(-0.8542,1,L_SIZE),
to_sfixed(-0.8526,1,L_SIZE),
to_sfixed(-0.8510,1,L_SIZE),
to_sfixed(-0.8494,1,L_SIZE),
to_sfixed(-0.8477,1,L_SIZE),
to_sfixed(-0.8461,1,L_SIZE),
to_sfixed(-0.8444,1,L_SIZE),
to_sfixed(-0.8427,1,L_SIZE),
to_sfixed(-0.8410,1,L_SIZE),
to_sfixed(-0.8393,1,L_SIZE),
to_sfixed(-0.8375,1,L_SIZE),
to_sfixed(-0.8358,1,L_SIZE),
to_sfixed(-0.8340,1,L_SIZE),
to_sfixed(-0.8322,1,L_SIZE),
to_sfixed(-0.8304,1,L_SIZE),
to_sfixed(-0.8286,1,L_SIZE),
to_sfixed(-0.8267,1,L_SIZE),
to_sfixed(-0.8249,1,L_SIZE),
to_sfixed(-0.8230,1,L_SIZE),
to_sfixed(-0.8211,1,L_SIZE),
to_sfixed(-0.8192,1,L_SIZE),
to_sfixed(-0.8172,1,L_SIZE),
to_sfixed(-0.8153,1,L_SIZE),
to_sfixed(-0.8133,1,L_SIZE),
to_sfixed(-0.8113,1,L_SIZE),
to_sfixed(-0.8093,1,L_SIZE),
to_sfixed(-0.8073,1,L_SIZE),
to_sfixed(-0.8052,1,L_SIZE),
to_sfixed(-0.8031,1,L_SIZE),
to_sfixed(-0.8011,1,L_SIZE),
to_sfixed(-0.7990,1,L_SIZE),
to_sfixed(-0.7968,1,L_SIZE),
to_sfixed(-0.7947,1,L_SIZE),
to_sfixed(-0.7925,1,L_SIZE),
to_sfixed(-0.7903,1,L_SIZE),
to_sfixed(-0.7881,1,L_SIZE),
to_sfixed(-0.7859,1,L_SIZE),
to_sfixed(-0.7836,1,L_SIZE),
to_sfixed(-0.7814,1,L_SIZE),
to_sfixed(-0.7791,1,L_SIZE),
to_sfixed(-0.7767,1,L_SIZE),
to_sfixed(-0.7744,1,L_SIZE),
to_sfixed(-0.7721,1,L_SIZE),
to_sfixed(-0.7697,1,L_SIZE),
to_sfixed(-0.7673,1,L_SIZE),
to_sfixed(-0.7649,1,L_SIZE),
to_sfixed(-0.7624,1,L_SIZE),
to_sfixed(-0.7599,1,L_SIZE),
to_sfixed(-0.7575,1,L_SIZE),
to_sfixed(-0.7550,1,L_SIZE),
to_sfixed(-0.7524,1,L_SIZE),
to_sfixed(-0.7499,1,L_SIZE),
to_sfixed(-0.7473,1,L_SIZE),
to_sfixed(-0.7447,1,L_SIZE),
to_sfixed(-0.7421,1,L_SIZE),
to_sfixed(-0.7394,1,L_SIZE),
to_sfixed(-0.7368,1,L_SIZE),
to_sfixed(-0.7341,1,L_SIZE),
to_sfixed(-0.7314,1,L_SIZE),
to_sfixed(-0.7286,1,L_SIZE),
to_sfixed(-0.7259,1,L_SIZE),
to_sfixed(-0.7231,1,L_SIZE),
to_sfixed(-0.7203,1,L_SIZE),
to_sfixed(-0.7174,1,L_SIZE),
to_sfixed(-0.7146,1,L_SIZE),
to_sfixed(-0.7117,1,L_SIZE),
to_sfixed(-0.7088,1,L_SIZE),
to_sfixed(-0.7059,1,L_SIZE),
to_sfixed(-0.7029,1,L_SIZE),
to_sfixed(-0.6999,1,L_SIZE),
to_sfixed(-0.6969,1,L_SIZE),
to_sfixed(-0.6939,1,L_SIZE),
to_sfixed(-0.6909,1,L_SIZE),
to_sfixed(-0.6878,1,L_SIZE),
to_sfixed(-0.6847,1,L_SIZE),
to_sfixed(-0.6816,1,L_SIZE),
to_sfixed(-0.6784,1,L_SIZE),
to_sfixed(-0.6752,1,L_SIZE),
to_sfixed(-0.6720,1,L_SIZE),
to_sfixed(-0.6688,1,L_SIZE),
to_sfixed(-0.6656,1,L_SIZE),
to_sfixed(-0.6623,1,L_SIZE),
to_sfixed(-0.6590,1,L_SIZE),
to_sfixed(-0.6557,1,L_SIZE),
to_sfixed(-0.6523,1,L_SIZE),
to_sfixed(-0.6489,1,L_SIZE),
to_sfixed(-0.6455,1,L_SIZE),
to_sfixed(-0.6421,1,L_SIZE),
to_sfixed(-0.6386,1,L_SIZE),
to_sfixed(-0.6351,1,L_SIZE),
to_sfixed(-0.6316,1,L_SIZE),
to_sfixed(-0.6281,1,L_SIZE),
to_sfixed(-0.6245,1,L_SIZE),
to_sfixed(-0.6210,1,L_SIZE),
to_sfixed(-0.6173,1,L_SIZE),
to_sfixed(-0.6137,1,L_SIZE),
to_sfixed(-0.6100,1,L_SIZE),
to_sfixed(-0.6063,1,L_SIZE),
to_sfixed(-0.6026,1,L_SIZE),
to_sfixed(-0.5989,1,L_SIZE),
to_sfixed(-0.5951,1,L_SIZE),
to_sfixed(-0.5913,1,L_SIZE),
to_sfixed(-0.5875,1,L_SIZE),
to_sfixed(-0.5836,1,L_SIZE),
to_sfixed(-0.5798,1,L_SIZE),
to_sfixed(-0.5759,1,L_SIZE),
to_sfixed(-0.5719,1,L_SIZE),
to_sfixed(-0.5680,1,L_SIZE),
to_sfixed(-0.5640,1,L_SIZE),
to_sfixed(-0.5600,1,L_SIZE),
to_sfixed(-0.5560,1,L_SIZE),
to_sfixed(-0.5519,1,L_SIZE),
to_sfixed(-0.5478,1,L_SIZE),
to_sfixed(-0.5437,1,L_SIZE),
to_sfixed(-0.5395,1,L_SIZE),
to_sfixed(-0.5354,1,L_SIZE),
to_sfixed(-0.5312,1,L_SIZE),
to_sfixed(-0.5270,1,L_SIZE),
to_sfixed(-0.5227,1,L_SIZE),
to_sfixed(-0.5185,1,L_SIZE),
to_sfixed(-0.5142,1,L_SIZE),
to_sfixed(-0.5098,1,L_SIZE),
to_sfixed(-0.5055,1,L_SIZE),
to_sfixed(-0.5011,1,L_SIZE),
to_sfixed(-0.4967,1,L_SIZE),
to_sfixed(-0.4923,1,L_SIZE),
to_sfixed(-0.4878,1,L_SIZE),
to_sfixed(-0.4833,1,L_SIZE),
to_sfixed(-0.4788,1,L_SIZE),
to_sfixed(-0.4743,1,L_SIZE),
to_sfixed(-0.4698,1,L_SIZE),
to_sfixed(-0.4652,1,L_SIZE),
to_sfixed(-0.4606,1,L_SIZE),
to_sfixed(-0.4560,1,L_SIZE),
to_sfixed(-0.4513,1,L_SIZE),
to_sfixed(-0.4466,1,L_SIZE),
to_sfixed(-0.4419,1,L_SIZE),
to_sfixed(-0.4372,1,L_SIZE),
to_sfixed(-0.4324,1,L_SIZE),
to_sfixed(-0.4277,1,L_SIZE),
to_sfixed(-0.4229,1,L_SIZE),
to_sfixed(-0.4180,1,L_SIZE),
to_sfixed(-0.4132,1,L_SIZE),
to_sfixed(-0.4083,1,L_SIZE),
to_sfixed(-0.4034,1,L_SIZE),
to_sfixed(-0.3985,1,L_SIZE),
to_sfixed(-0.3936,1,L_SIZE),
to_sfixed(-0.3886,1,L_SIZE),
to_sfixed(-0.3836,1,L_SIZE),
to_sfixed(-0.3786,1,L_SIZE),
to_sfixed(-0.3736,1,L_SIZE),
to_sfixed(-0.3685,1,L_SIZE),
to_sfixed(-0.3635,1,L_SIZE),
to_sfixed(-0.3584,1,L_SIZE),
to_sfixed(-0.3532,1,L_SIZE),
to_sfixed(-0.3481,1,L_SIZE),
to_sfixed(-0.3429,1,L_SIZE),
to_sfixed(-0.3378,1,L_SIZE),
to_sfixed(-0.3326,1,L_SIZE),
to_sfixed(-0.3273,1,L_SIZE),
to_sfixed(-0.3221,1,L_SIZE),
to_sfixed(-0.3168,1,L_SIZE),
to_sfixed(-0.3116,1,L_SIZE),
to_sfixed(-0.3063,1,L_SIZE),
to_sfixed(-0.3009,1,L_SIZE),
to_sfixed(-0.2956,1,L_SIZE),
to_sfixed(-0.2902,1,L_SIZE),
to_sfixed(-0.2849,1,L_SIZE),
to_sfixed(-0.2795,1,L_SIZE),
to_sfixed(-0.2741,1,L_SIZE),
to_sfixed(-0.2686,1,L_SIZE),
to_sfixed(-0.2632,1,L_SIZE),
to_sfixed(-0.2577,1,L_SIZE),
to_sfixed(-0.2522,1,L_SIZE),
to_sfixed(-0.2468,1,L_SIZE),
to_sfixed(-0.2412,1,L_SIZE),
to_sfixed(-0.2357,1,L_SIZE),
to_sfixed(-0.2302,1,L_SIZE),
to_sfixed(-0.2246,1,L_SIZE),
to_sfixed(-0.2190,1,L_SIZE),
to_sfixed(-0.2135,1,L_SIZE),
to_sfixed(-0.2079,1,L_SIZE),
to_sfixed(-0.2023,1,L_SIZE),
to_sfixed(-0.1966,1,L_SIZE),
to_sfixed(-0.1910,1,L_SIZE),
to_sfixed(-0.1853,1,L_SIZE),
to_sfixed(-0.1797,1,L_SIZE),
to_sfixed(-0.1740,1,L_SIZE),
to_sfixed(-0.1683,1,L_SIZE),
to_sfixed(-0.1626,1,L_SIZE),
to_sfixed(-0.1569,1,L_SIZE),
to_sfixed(-0.1512,1,L_SIZE),
to_sfixed(-0.1454,1,L_SIZE),
to_sfixed(-0.1397,1,L_SIZE),
to_sfixed(-0.1340,1,L_SIZE),
to_sfixed(-0.1282,1,L_SIZE),
to_sfixed(-0.1224,1,L_SIZE),
to_sfixed(-0.1167,1,L_SIZE),
to_sfixed(-0.1109,1,L_SIZE),
to_sfixed(-0.1051,1,L_SIZE),
to_sfixed(-0.0993,1,L_SIZE),
to_sfixed(-0.0935,1,L_SIZE),
to_sfixed(-0.0877,1,L_SIZE),
to_sfixed(-0.0818,1,L_SIZE),
to_sfixed(-0.0760,1,L_SIZE),
to_sfixed(-0.0702,1,L_SIZE),
to_sfixed(-0.0644,1,L_SIZE),
to_sfixed(-0.0585,1,L_SIZE),
to_sfixed(-0.0527,1,L_SIZE),
to_sfixed(-0.0468,1,L_SIZE),
to_sfixed(-0.0410,1,L_SIZE),
to_sfixed(-0.0351,1,L_SIZE),
to_sfixed(-0.0293,1,L_SIZE),
to_sfixed(-0.0234,1,L_SIZE),
to_sfixed(-0.0176,1,L_SIZE),
to_sfixed(-0.0117,1,L_SIZE),
to_sfixed(-0.0059,1,L_SIZE),
to_sfixed(0.0000,1,L_SIZE),
to_sfixed(0.0059,1,L_SIZE),
to_sfixed(0.0117,1,L_SIZE),
to_sfixed(0.0176,1,L_SIZE),
to_sfixed(0.0234,1,L_SIZE),
to_sfixed(0.0293,1,L_SIZE),
to_sfixed(0.0351,1,L_SIZE),
to_sfixed(0.0410,1,L_SIZE),
to_sfixed(0.0468,1,L_SIZE),
to_sfixed(0.0527,1,L_SIZE),
to_sfixed(0.0585,1,L_SIZE),
to_sfixed(0.0644,1,L_SIZE),
to_sfixed(0.0702,1,L_SIZE),
to_sfixed(0.0760,1,L_SIZE),
to_sfixed(0.0818,1,L_SIZE),
to_sfixed(0.0877,1,L_SIZE),
to_sfixed(0.0935,1,L_SIZE),
to_sfixed(0.0993,1,L_SIZE),
to_sfixed(0.1051,1,L_SIZE),
to_sfixed(0.1109,1,L_SIZE),
to_sfixed(0.1167,1,L_SIZE),
to_sfixed(0.1224,1,L_SIZE),
to_sfixed(0.1282,1,L_SIZE),
to_sfixed(0.1340,1,L_SIZE),
to_sfixed(0.1397,1,L_SIZE),
to_sfixed(0.1454,1,L_SIZE),
to_sfixed(0.1512,1,L_SIZE),
to_sfixed(0.1569,1,L_SIZE),
to_sfixed(0.1626,1,L_SIZE),
to_sfixed(0.1683,1,L_SIZE),
to_sfixed(0.1740,1,L_SIZE),
to_sfixed(0.1797,1,L_SIZE),
to_sfixed(0.1853,1,L_SIZE),
to_sfixed(0.1910,1,L_SIZE),
to_sfixed(0.1966,1,L_SIZE),
to_sfixed(0.2023,1,L_SIZE),
to_sfixed(0.2079,1,L_SIZE),
to_sfixed(0.2135,1,L_SIZE),
to_sfixed(0.2190,1,L_SIZE),
to_sfixed(0.2246,1,L_SIZE),
to_sfixed(0.2302,1,L_SIZE),
to_sfixed(0.2357,1,L_SIZE),
to_sfixed(0.2412,1,L_SIZE),
to_sfixed(0.2468,1,L_SIZE),
to_sfixed(0.2522,1,L_SIZE),
to_sfixed(0.2577,1,L_SIZE),
to_sfixed(0.2632,1,L_SIZE),
to_sfixed(0.2686,1,L_SIZE),
to_sfixed(0.2741,1,L_SIZE),
to_sfixed(0.2795,1,L_SIZE),
to_sfixed(0.2849,1,L_SIZE),
to_sfixed(0.2902,1,L_SIZE),
to_sfixed(0.2956,1,L_SIZE),
to_sfixed(0.3009,1,L_SIZE),
to_sfixed(0.3063,1,L_SIZE),
to_sfixed(0.3116,1,L_SIZE),
to_sfixed(0.3168,1,L_SIZE),
to_sfixed(0.3221,1,L_SIZE),
to_sfixed(0.3273,1,L_SIZE),
to_sfixed(0.3326,1,L_SIZE),
to_sfixed(0.3378,1,L_SIZE),
to_sfixed(0.3429,1,L_SIZE),
to_sfixed(0.3481,1,L_SIZE),
to_sfixed(0.3532,1,L_SIZE),
to_sfixed(0.3584,1,L_SIZE),
to_sfixed(0.3635,1,L_SIZE),
to_sfixed(0.3685,1,L_SIZE),
to_sfixed(0.3736,1,L_SIZE),
to_sfixed(0.3786,1,L_SIZE),
to_sfixed(0.3836,1,L_SIZE),
to_sfixed(0.3886,1,L_SIZE),
to_sfixed(0.3936,1,L_SIZE),
to_sfixed(0.3985,1,L_SIZE),
to_sfixed(0.4034,1,L_SIZE),
to_sfixed(0.4083,1,L_SIZE),
to_sfixed(0.4132,1,L_SIZE),
to_sfixed(0.4180,1,L_SIZE),
to_sfixed(0.4229,1,L_SIZE),
to_sfixed(0.4277,1,L_SIZE),
to_sfixed(0.4324,1,L_SIZE),
to_sfixed(0.4372,1,L_SIZE),
to_sfixed(0.4419,1,L_SIZE),
to_sfixed(0.4466,1,L_SIZE),
to_sfixed(0.4513,1,L_SIZE),
to_sfixed(0.4560,1,L_SIZE),
to_sfixed(0.4606,1,L_SIZE),
to_sfixed(0.4652,1,L_SIZE),
to_sfixed(0.4698,1,L_SIZE),
to_sfixed(0.4743,1,L_SIZE),
to_sfixed(0.4788,1,L_SIZE),
to_sfixed(0.4833,1,L_SIZE),
to_sfixed(0.4878,1,L_SIZE),
to_sfixed(0.4923,1,L_SIZE),
to_sfixed(0.4967,1,L_SIZE),
to_sfixed(0.5011,1,L_SIZE),
to_sfixed(0.5055,1,L_SIZE),
to_sfixed(0.5098,1,L_SIZE),
to_sfixed(0.5142,1,L_SIZE),
to_sfixed(0.5185,1,L_SIZE),
to_sfixed(0.5227,1,L_SIZE),
to_sfixed(0.5270,1,L_SIZE),
to_sfixed(0.5312,1,L_SIZE),
to_sfixed(0.5354,1,L_SIZE),
to_sfixed(0.5395,1,L_SIZE),
to_sfixed(0.5437,1,L_SIZE),
to_sfixed(0.5478,1,L_SIZE),
to_sfixed(0.5519,1,L_SIZE),
to_sfixed(0.5560,1,L_SIZE),
to_sfixed(0.5600,1,L_SIZE),
to_sfixed(0.5640,1,L_SIZE),
to_sfixed(0.5680,1,L_SIZE),
to_sfixed(0.5719,1,L_SIZE),
to_sfixed(0.5759,1,L_SIZE),
to_sfixed(0.5798,1,L_SIZE),
to_sfixed(0.5836,1,L_SIZE),
to_sfixed(0.5875,1,L_SIZE),
to_sfixed(0.5913,1,L_SIZE),
to_sfixed(0.5951,1,L_SIZE),
to_sfixed(0.5989,1,L_SIZE),
to_sfixed(0.6026,1,L_SIZE),
to_sfixed(0.6063,1,L_SIZE),
to_sfixed(0.6100,1,L_SIZE),
to_sfixed(0.6137,1,L_SIZE),
to_sfixed(0.6173,1,L_SIZE),
to_sfixed(0.6210,1,L_SIZE),
to_sfixed(0.6245,1,L_SIZE),
to_sfixed(0.6281,1,L_SIZE),
to_sfixed(0.6316,1,L_SIZE),
to_sfixed(0.6351,1,L_SIZE),
to_sfixed(0.6386,1,L_SIZE),
to_sfixed(0.6421,1,L_SIZE),
to_sfixed(0.6455,1,L_SIZE),
to_sfixed(0.6489,1,L_SIZE),
to_sfixed(0.6523,1,L_SIZE),
to_sfixed(0.6557,1,L_SIZE),
to_sfixed(0.6590,1,L_SIZE),
to_sfixed(0.6623,1,L_SIZE),
to_sfixed(0.6656,1,L_SIZE),
to_sfixed(0.6688,1,L_SIZE),
to_sfixed(0.6720,1,L_SIZE),
to_sfixed(0.6752,1,L_SIZE),
to_sfixed(0.6784,1,L_SIZE),
to_sfixed(0.6816,1,L_SIZE),
to_sfixed(0.6847,1,L_SIZE),
to_sfixed(0.6878,1,L_SIZE),
to_sfixed(0.6909,1,L_SIZE),
to_sfixed(0.6939,1,L_SIZE),
to_sfixed(0.6969,1,L_SIZE),
to_sfixed(0.6999,1,L_SIZE),
to_sfixed(0.7029,1,L_SIZE),
to_sfixed(0.7059,1,L_SIZE),
to_sfixed(0.7088,1,L_SIZE),
to_sfixed(0.7117,1,L_SIZE),
to_sfixed(0.7146,1,L_SIZE),
to_sfixed(0.7174,1,L_SIZE),
to_sfixed(0.7203,1,L_SIZE),
to_sfixed(0.7231,1,L_SIZE),
to_sfixed(0.7259,1,L_SIZE),
to_sfixed(0.7286,1,L_SIZE),
to_sfixed(0.7314,1,L_SIZE),
to_sfixed(0.7341,1,L_SIZE),
to_sfixed(0.7368,1,L_SIZE),
to_sfixed(0.7394,1,L_SIZE),
to_sfixed(0.7421,1,L_SIZE),
to_sfixed(0.7447,1,L_SIZE),
to_sfixed(0.7473,1,L_SIZE),
to_sfixed(0.7499,1,L_SIZE),
to_sfixed(0.7524,1,L_SIZE),
to_sfixed(0.7550,1,L_SIZE),
to_sfixed(0.7575,1,L_SIZE),
to_sfixed(0.7599,1,L_SIZE),
to_sfixed(0.7624,1,L_SIZE),
to_sfixed(0.7649,1,L_SIZE),
to_sfixed(0.7673,1,L_SIZE),
to_sfixed(0.7697,1,L_SIZE),
to_sfixed(0.7721,1,L_SIZE),
to_sfixed(0.7744,1,L_SIZE),
to_sfixed(0.7767,1,L_SIZE),
to_sfixed(0.7791,1,L_SIZE),
to_sfixed(0.7814,1,L_SIZE),
to_sfixed(0.7836,1,L_SIZE),
to_sfixed(0.7859,1,L_SIZE),
to_sfixed(0.7881,1,L_SIZE),
to_sfixed(0.7903,1,L_SIZE),
to_sfixed(0.7925,1,L_SIZE),
to_sfixed(0.7947,1,L_SIZE),
to_sfixed(0.7968,1,L_SIZE),
to_sfixed(0.7990,1,L_SIZE),
to_sfixed(0.8011,1,L_SIZE),
to_sfixed(0.8031,1,L_SIZE),
to_sfixed(0.8052,1,L_SIZE),
to_sfixed(0.8073,1,L_SIZE),
to_sfixed(0.8093,1,L_SIZE),
to_sfixed(0.8113,1,L_SIZE),
to_sfixed(0.8133,1,L_SIZE),
to_sfixed(0.8153,1,L_SIZE),
to_sfixed(0.8172,1,L_SIZE),
to_sfixed(0.8192,1,L_SIZE),
to_sfixed(0.8211,1,L_SIZE),
to_sfixed(0.8230,1,L_SIZE),
to_sfixed(0.8249,1,L_SIZE),
to_sfixed(0.8267,1,L_SIZE),
to_sfixed(0.8286,1,L_SIZE),
to_sfixed(0.8304,1,L_SIZE),
to_sfixed(0.8322,1,L_SIZE),
to_sfixed(0.8340,1,L_SIZE),
to_sfixed(0.8358,1,L_SIZE),
to_sfixed(0.8375,1,L_SIZE),
to_sfixed(0.8393,1,L_SIZE),
to_sfixed(0.8410,1,L_SIZE),
to_sfixed(0.8427,1,L_SIZE),
to_sfixed(0.8444,1,L_SIZE),
to_sfixed(0.8461,1,L_SIZE),
to_sfixed(0.8477,1,L_SIZE),
to_sfixed(0.8494,1,L_SIZE),
to_sfixed(0.8510,1,L_SIZE),
to_sfixed(0.8526,1,L_SIZE),
to_sfixed(0.8542,1,L_SIZE),
to_sfixed(0.8558,1,L_SIZE),
to_sfixed(0.8573,1,L_SIZE),
to_sfixed(0.8589,1,L_SIZE),
to_sfixed(0.8604,1,L_SIZE),
to_sfixed(0.8619,1,L_SIZE),
to_sfixed(0.8634,1,L_SIZE),
to_sfixed(0.8649,1,L_SIZE),
to_sfixed(0.8664,1,L_SIZE),
to_sfixed(0.8678,1,L_SIZE),
to_sfixed(0.8693,1,L_SIZE),
to_sfixed(0.8707,1,L_SIZE),
to_sfixed(0.8721,1,L_SIZE),
to_sfixed(0.8735,1,L_SIZE),
to_sfixed(0.8749,1,L_SIZE),
to_sfixed(0.8762,1,L_SIZE),
to_sfixed(0.8776,1,L_SIZE),
to_sfixed(0.8789,1,L_SIZE),
to_sfixed(0.8803,1,L_SIZE),
to_sfixed(0.8816,1,L_SIZE),
to_sfixed(0.8829,1,L_SIZE),
to_sfixed(0.8842,1,L_SIZE),
to_sfixed(0.8854,1,L_SIZE),
to_sfixed(0.8867,1,L_SIZE),
to_sfixed(0.8879,1,L_SIZE),
to_sfixed(0.8892,1,L_SIZE),
to_sfixed(0.8904,1,L_SIZE),
to_sfixed(0.8916,1,L_SIZE),
to_sfixed(0.8928,1,L_SIZE),
to_sfixed(0.8940,1,L_SIZE),
to_sfixed(0.8952,1,L_SIZE),
to_sfixed(0.8963,1,L_SIZE),
to_sfixed(0.8975,1,L_SIZE),
to_sfixed(0.8986,1,L_SIZE),
to_sfixed(0.8997,1,L_SIZE),
to_sfixed(0.9008,1,L_SIZE),
to_sfixed(0.9019,1,L_SIZE),
to_sfixed(0.9030,1,L_SIZE),
to_sfixed(0.9041,1,L_SIZE),
to_sfixed(0.9051,1,L_SIZE),
to_sfixed(0.9062,1,L_SIZE),
to_sfixed(0.9072,1,L_SIZE),
to_sfixed(0.9083,1,L_SIZE),
to_sfixed(0.9093,1,L_SIZE),
to_sfixed(0.9103,1,L_SIZE),
to_sfixed(0.9113,1,L_SIZE),
to_sfixed(0.9123,1,L_SIZE),
to_sfixed(0.9133,1,L_SIZE),
to_sfixed(0.9142,1,L_SIZE),
to_sfixed(0.9152,1,L_SIZE),
to_sfixed(0.9161,1,L_SIZE),
to_sfixed(0.9171,1,L_SIZE),
to_sfixed(0.9180,1,L_SIZE),
to_sfixed(0.9189,1,L_SIZE),
to_sfixed(0.9198,1,L_SIZE),
to_sfixed(0.9207,1,L_SIZE),
to_sfixed(0.9216,1,L_SIZE),
to_sfixed(0.9225,1,L_SIZE),
to_sfixed(0.9234,1,L_SIZE),
to_sfixed(0.9242,1,L_SIZE),
to_sfixed(0.9251,1,L_SIZE),
to_sfixed(0.9259,1,L_SIZE),
to_sfixed(0.9267,1,L_SIZE),
to_sfixed(0.9276,1,L_SIZE),
to_sfixed(0.9284,1,L_SIZE),
to_sfixed(0.9292,1,L_SIZE),
to_sfixed(0.9300,1,L_SIZE),
to_sfixed(0.9308,1,L_SIZE),
to_sfixed(0.9315,1,L_SIZE),
to_sfixed(0.9323,1,L_SIZE),
to_sfixed(0.9331,1,L_SIZE),
to_sfixed(0.9338,1,L_SIZE),
to_sfixed(0.9346,1,L_SIZE),
to_sfixed(0.9353,1,L_SIZE),
to_sfixed(0.9360,1,L_SIZE),
to_sfixed(0.9368,1,L_SIZE),
to_sfixed(0.9375,1,L_SIZE),
to_sfixed(0.9382,1,L_SIZE),
to_sfixed(0.9389,1,L_SIZE),
to_sfixed(0.9396,1,L_SIZE),
to_sfixed(0.9403,1,L_SIZE),
to_sfixed(0.9409,1,L_SIZE),
to_sfixed(0.9416,1,L_SIZE),
to_sfixed(0.9423,1,L_SIZE),
to_sfixed(0.9429,1,L_SIZE),
to_sfixed(0.9436,1,L_SIZE),
to_sfixed(0.9442,1,L_SIZE),
to_sfixed(0.9448,1,L_SIZE),
to_sfixed(0.9455,1,L_SIZE),
to_sfixed(0.9461,1,L_SIZE),
to_sfixed(0.9467,1,L_SIZE),
to_sfixed(0.9473,1,L_SIZE),
to_sfixed(0.9479,1,L_SIZE),
to_sfixed(0.9485,1,L_SIZE),
to_sfixed(0.9491,1,L_SIZE),
to_sfixed(0.9496,1,L_SIZE),
to_sfixed(0.9502,1,L_SIZE),
to_sfixed(0.9508,1,L_SIZE),
to_sfixed(0.9513,1,L_SIZE),
to_sfixed(0.9519,1,L_SIZE),
to_sfixed(0.9524,1,L_SIZE),
to_sfixed(0.9530,1,L_SIZE),
to_sfixed(0.9535,1,L_SIZE),
to_sfixed(0.9540,1,L_SIZE),
to_sfixed(0.9546,1,L_SIZE),
to_sfixed(0.9551,1,L_SIZE),
to_sfixed(0.9556,1,L_SIZE),
to_sfixed(0.9561,1,L_SIZE),
to_sfixed(0.9566,1,L_SIZE),
to_sfixed(0.9571,1,L_SIZE),
to_sfixed(0.9576,1,L_SIZE),
to_sfixed(0.9581,1,L_SIZE),
to_sfixed(0.9585,1,L_SIZE),
to_sfixed(0.9590,1,L_SIZE),
to_sfixed(0.9595,1,L_SIZE),
to_sfixed(0.9600,1,L_SIZE),
to_sfixed(0.9604,1,L_SIZE),
to_sfixed(0.9609,1,L_SIZE),
to_sfixed(0.9613,1,L_SIZE),
to_sfixed(0.9618,1,L_SIZE),
to_sfixed(0.9622,1,L_SIZE),
to_sfixed(0.9626,1,L_SIZE),
to_sfixed(0.9630,1,L_SIZE),
to_sfixed(0.9635,1,L_SIZE),
to_sfixed(0.9639,1,L_SIZE),
to_sfixed(0.9643,1,L_SIZE),
to_sfixed(0.9647,1,L_SIZE),
to_sfixed(0.9651,1,L_SIZE),
to_sfixed(0.9655,1,L_SIZE),
to_sfixed(0.9659,1,L_SIZE),
to_sfixed(0.9663,1,L_SIZE),
to_sfixed(0.9667,1,L_SIZE),
to_sfixed(0.9671,1,L_SIZE),
to_sfixed(0.9674,1,L_SIZE),
to_sfixed(0.9678,1,L_SIZE),
to_sfixed(0.9682,1,L_SIZE),
to_sfixed(0.9686,1,L_SIZE),
to_sfixed(0.9689,1,L_SIZE),
to_sfixed(0.9693,1,L_SIZE),
to_sfixed(0.9696,1,L_SIZE),
to_sfixed(0.9700,1,L_SIZE),
to_sfixed(0.9703,1,L_SIZE),
to_sfixed(0.9707,1,L_SIZE),
to_sfixed(0.9710,1,L_SIZE),
to_sfixed(0.9713,1,L_SIZE),
to_sfixed(0.9717,1,L_SIZE),
to_sfixed(0.9720,1,L_SIZE),
to_sfixed(0.9723,1,L_SIZE),
to_sfixed(0.9726,1,L_SIZE),
to_sfixed(0.9729,1,L_SIZE),
to_sfixed(0.9732,1,L_SIZE),
to_sfixed(0.9736,1,L_SIZE),
to_sfixed(0.9739,1,L_SIZE),
to_sfixed(0.9742,1,L_SIZE),
to_sfixed(0.9745,1,L_SIZE),
to_sfixed(0.9748,1,L_SIZE),
to_sfixed(0.9750,1,L_SIZE),
to_sfixed(0.9753,1,L_SIZE),
to_sfixed(0.9756,1,L_SIZE),
to_sfixed(0.9759,1,L_SIZE),
to_sfixed(0.9762,1,L_SIZE),
to_sfixed(0.9764,1,L_SIZE),
to_sfixed(0.9767,1,L_SIZE),
to_sfixed(0.9770,1,L_SIZE),
to_sfixed(0.9772,1,L_SIZE),
to_sfixed(0.9775,1,L_SIZE),
to_sfixed(0.9778,1,L_SIZE),
to_sfixed(0.9780,1,L_SIZE),
to_sfixed(0.9783,1,L_SIZE),
to_sfixed(0.9785,1,L_SIZE),
to_sfixed(0.9788,1,L_SIZE),
to_sfixed(0.9790,1,L_SIZE),
to_sfixed(0.9793,1,L_SIZE),
to_sfixed(0.9795,1,L_SIZE),
to_sfixed(0.9797,1,L_SIZE),
to_sfixed(0.9800,1,L_SIZE),
to_sfixed(0.9802,1,L_SIZE),
to_sfixed(0.9804,1,L_SIZE),
to_sfixed(0.9807,1,L_SIZE),
to_sfixed(0.9809,1,L_SIZE),
to_sfixed(0.9811,1,L_SIZE),
to_sfixed(0.9813,1,L_SIZE),
to_sfixed(0.9815,1,L_SIZE),
to_sfixed(0.9817,1,L_SIZE),
to_sfixed(0.9820,1,L_SIZE),
to_sfixed(0.9822,1,L_SIZE),
to_sfixed(0.9824,1,L_SIZE),
to_sfixed(0.9826,1,L_SIZE),
to_sfixed(0.9828,1,L_SIZE),
to_sfixed(0.9830,1,L_SIZE),
to_sfixed(0.9832,1,L_SIZE),
to_sfixed(0.9834,1,L_SIZE),
to_sfixed(0.9836,1,L_SIZE),
to_sfixed(0.9838,1,L_SIZE),
to_sfixed(0.9839,1,L_SIZE),
to_sfixed(0.9841,1,L_SIZE),
to_sfixed(0.9843,1,L_SIZE),
to_sfixed(0.9845,1,L_SIZE),
to_sfixed(0.9847,1,L_SIZE),
to_sfixed(0.9848,1,L_SIZE),
to_sfixed(0.9850,1,L_SIZE),
to_sfixed(0.9852,1,L_SIZE),
to_sfixed(0.9854,1,L_SIZE),
to_sfixed(0.9855,1,L_SIZE),
to_sfixed(0.9857,1,L_SIZE),
to_sfixed(0.9859,1,L_SIZE),
to_sfixed(0.9860,1,L_SIZE),
to_sfixed(0.9862,1,L_SIZE),
to_sfixed(0.9864,1,L_SIZE),
to_sfixed(0.9865,1,L_SIZE),
to_sfixed(0.9867,1,L_SIZE),
to_sfixed(0.9868,1,L_SIZE),
to_sfixed(0.9870,1,L_SIZE),
to_sfixed(0.9871,1,L_SIZE),
to_sfixed(0.9873,1,L_SIZE),
to_sfixed(0.9874,1,L_SIZE),
to_sfixed(0.9876,1,L_SIZE),
to_sfixed(0.9877,1,L_SIZE),
to_sfixed(0.9879,1,L_SIZE),
to_sfixed(0.9880,1,L_SIZE),
to_sfixed(0.9881,1,L_SIZE),
to_sfixed(0.9883,1,L_SIZE),
to_sfixed(0.9884,1,L_SIZE),
to_sfixed(0.9885,1,L_SIZE),
to_sfixed(0.9887,1,L_SIZE),
to_sfixed(0.9888,1,L_SIZE),
to_sfixed(0.9889,1,L_SIZE),
to_sfixed(0.9891,1,L_SIZE),
to_sfixed(0.9892,1,L_SIZE),
to_sfixed(0.9893,1,L_SIZE),
to_sfixed(0.9894,1,L_SIZE),
to_sfixed(0.9896,1,L_SIZE),
to_sfixed(0.9897,1,L_SIZE),
to_sfixed(0.9898,1,L_SIZE),
to_sfixed(0.9899,1,L_SIZE),
to_sfixed(0.9900,1,L_SIZE),
to_sfixed(0.9902,1,L_SIZE),
to_sfixed(0.9903,1,L_SIZE),
to_sfixed(0.9904,1,L_SIZE),
to_sfixed(0.9905,1,L_SIZE),
to_sfixed(0.9906,1,L_SIZE),
to_sfixed(0.9907,1,L_SIZE),
to_sfixed(0.9908,1,L_SIZE),
to_sfixed(0.9909,1,L_SIZE),
to_sfixed(0.9910,1,L_SIZE),
to_sfixed(0.9911,1,L_SIZE),
to_sfixed(0.9912,1,L_SIZE),
to_sfixed(0.9913,1,L_SIZE),
to_sfixed(0.9914,1,L_SIZE),
to_sfixed(0.9915,1,L_SIZE),
to_sfixed(0.9916,1,L_SIZE),
to_sfixed(0.9917,1,L_SIZE),
to_sfixed(0.9918,1,L_SIZE),
to_sfixed(0.9919,1,L_SIZE),
to_sfixed(0.9920,1,L_SIZE),
to_sfixed(0.9921,1,L_SIZE),
to_sfixed(0.9922,1,L_SIZE),
to_sfixed(0.9923,1,L_SIZE),
to_sfixed(0.9924,1,L_SIZE),
to_sfixed(0.9925,1,L_SIZE),
to_sfixed(0.9926,1,L_SIZE),
to_sfixed(0.9926,1,L_SIZE),
to_sfixed(0.9927,1,L_SIZE),
to_sfixed(0.9928,1,L_SIZE),
to_sfixed(0.9929,1,L_SIZE),
to_sfixed(0.9930,1,L_SIZE),
to_sfixed(0.9931,1,L_SIZE),
to_sfixed(0.9931,1,L_SIZE),
to_sfixed(0.9932,1,L_SIZE),
to_sfixed(0.9933,1,L_SIZE),
to_sfixed(0.9934,1,L_SIZE),
to_sfixed(0.9935,1,L_SIZE),
to_sfixed(0.9935,1,L_SIZE),
to_sfixed(0.9936,1,L_SIZE),
to_sfixed(0.9937,1,L_SIZE),
to_sfixed(0.9938,1,L_SIZE),
to_sfixed(0.9938,1,L_SIZE),
to_sfixed(0.9939,1,L_SIZE),
to_sfixed(0.9940,1,L_SIZE),
to_sfixed(0.9940,1,L_SIZE),
to_sfixed(0.9941,1,L_SIZE),
to_sfixed(0.9942,1,L_SIZE),
to_sfixed(0.9942,1,L_SIZE),
to_sfixed(0.9943,1,L_SIZE),
to_sfixed(0.9944,1,L_SIZE),
to_sfixed(0.9944,1,L_SIZE),
to_sfixed(0.9945,1,L_SIZE),
to_sfixed(0.9946,1,L_SIZE),
to_sfixed(0.9946,1,L_SIZE),
to_sfixed(0.9947,1,L_SIZE),
to_sfixed(0.9948,1,L_SIZE),
to_sfixed(0.9948,1,L_SIZE),
to_sfixed(0.9949,1,L_SIZE),
to_sfixed(0.9949,1,L_SIZE),
to_sfixed(0.9950,1,L_SIZE)
);
-- Signals
signal IN_UNSIGNED : unsigned((NUMBER_OF_BITS-1) downto 0);
signal LOOKUP_TABLE_K : unsigned((NUMBER_OF_BITS-1) downto 0);
signal LOOKUP_TABLE_OUT : INPUT_SFIXED;
signal LOOKUP_TABLE_OUT_CONSTRAINED : CONSTRAINED_SFIXED;
signal UNIT_DELAY_OUT : CONSTRAINED_SFIXED;
--=============================================================================
-- architecture begin
--=============================================================================
begin
IN_UNSIGNED <= unsigned(X_VALUE);
LOOKUP_TABLE_K <= -- Make sure no index will fall out of boundary
to_unsigned(0, NUMBER_OF_BITS) when IN_UNSIGNED <= 0
else
to_unsigned(VECTOR_SIZE, NUMBER_OF_BITS) when IN_UNSIGNED >= VECTOR_SIZE
else
IN_UNSIGNED;
LOOKUP_TABLE_OUT <= TAN_SIG(to_integer(LOOKUP_TABLE_K));
LOOKUP_TABLE_OUT_CONSTRAINED<=
resize(LOOKUP_TABLE_OUT,U_SIZE,L_SIZE);
UNIT_DELAY_PROCESS : process (clk)
begin
if CLK'event and CLK = '1' then
UNIT_DELAY_OUT <= LOOKUP_TABLE_OUT_CONSTRAINED;
end if;
end process UNIT_DELAY_PROCESS;
Y_VALUE <= UNIT_DELAY_OUT;
end RTL;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
169419094ca2d472ced5ee83c92bda01
| 0.57512 | 2.116737 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/7c28a8a0ff9637ec/fifo_generator_0_sim_netlist.vhdl
| 1 | 308,884 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 13:00:13 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_sim_netlist.vhdl
-- Design : fifo_generator_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
comp1 : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0020"
)
port map (
I0 => comp2,
I1 => \out\,
I2 => wr_en,
I3 => wr_rst_busy,
I4 => comp1,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair8";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => \plusOp__0\(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
begin
\rd_dc_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0),
Q => rd_data_count(0)
);
\rd_dc_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1),
Q => rd_data_count(1)
);
\rd_dc_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2),
Q => rd_data_count(2)
);
\rd_dc_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3),
Q => rd_data_count(3)
);
\rd_dc_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4),
Q => rd_data_count(4)
);
\rd_dc_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5),
Q => rd_data_count(5)
);
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6),
Q => rd_data_count(6)
);
\rd_dc_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7),
Q => rd_data_count(7)
);
\rd_dc_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8),
Q => rd_data_count(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
port (
prog_empty : out STD_LOGIC;
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
signal \gdiff.diff_pntr_pad_reg_n_0_[10]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[2]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[3]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[4]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[5]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[6]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[7]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[8]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[9]\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
begin
prog_empty <= \^prog_empty\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => \gdiff.diff_pntr_pad_reg_n_0_[10]\
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => \gdiff.diff_pntr_pad_reg_n_0_[2]\
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => \gdiff.diff_pntr_pad_reg_n_0_[3]\
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => \gdiff.diff_pntr_pad_reg_n_0_[4]\
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => \gdiff.diff_pntr_pad_reg_n_0_[5]\
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => \gdiff.diff_pntr_pad_reg_n_0_[6]\
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => \gdiff.diff_pntr_pad_reg_n_0_[7]\
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => \gdiff.diff_pntr_pad_reg_n_0_[8]\
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => \gdiff.diff_pntr_pad_reg_n_0_[9]\
);
\gpe1.prog_empty_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \^prog_empty\,
I1 => \out\,
I2 => \gpe1.prog_empty_i_i_2_n_0\,
I3 => \gpe1.prog_empty_i_i_3_n_0\,
O => \gpe1.prog_empty_i_i_1_n_0\
);
\gpe1.prog_empty_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7FFFFFFFFFFF"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[9]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[4]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[6]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[3]\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[2]\,
I5 => \gdiff.diff_pntr_pad_reg_n_0_[5]\,
O => \gpe1.prog_empty_i_i_2_n_0\
);
\gpe1.prog_empty_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FAEA"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[10]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[7]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[9]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[8]\,
O => \gpe1.prog_empty_i_i_3_n_0\
);
\gpe1.prog_empty_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gpe1.prog_empty_i_i_1_n_0\,
PRE => AR(0),
Q => \^prog_empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
\wr_data_count_i_reg[9]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gdiff.diff_pntr_pad_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d1_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair13";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gic0.gc0.count_d1_reg[9]_0\(9 downto 0) <= \^gic0.gc0.count_d1_reg[9]_0\(9 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(4),
O => \plusOp__1\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(4),
I5 => \^gic0.gc0.count_d1_reg[9]_0\(5),
O => \plusOp__1\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => \^gic0.gc0.count_d1_reg[9]_0\(6),
O => \plusOp__1\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B4"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(7),
O => \plusOp__1\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => \^gic0.gc0.count_d1_reg[9]_0\(7),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(8),
O => \plusOp__1\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(8),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(7),
I2 => \gic0.gc0.count[9]_i_2_n_0\,
I3 => \^gic0.gc0.count_d1_reg[9]_0\(6),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(9),
O => \plusOp__1\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^gic0.gc0.count_d1_reg[9]_0\(5),
I1 => \^gic0.gc0.count_d1_reg[9]_0\(3),
I2 => \^gic0.gc0.count_d1_reg[9]_0\(1),
I3 => \^gic0.gc0.count_d1_reg[9]_0\(0),
I4 => \^gic0.gc0.count_d1_reg[9]_0\(2),
I5 => \^gic0.gc0.count_d1_reg[9]_0\(4),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(4),
Q => \^q\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(5),
Q => \^q\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(6),
Q => \^q\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(7),
Q => \^q\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(8),
Q => \^q\(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d1_reg[9]_0\(9),
Q => p_13_out(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^gic0.gc0.count_d1_reg[9]_0\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^gic0.gc0.count_d1_reg[9]_0\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^gic0.gc0.count_d1_reg[9]_0\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^gic0.gc0.count_d1_reg[9]_0\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(4),
Q => \^gic0.gc0.count_d1_reg[9]_0\(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(5),
Q => \^gic0.gc0.count_d1_reg[9]_0\(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(6),
Q => \^gic0.gc0.count_d1_reg[9]_0\(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(7),
Q => \^gic0.gc0.count_d1_reg[9]_0\(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(8),
Q => \^gic0.gc0.count_d1_reg[9]_0\(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(9),
Q => \^gic0.gc0.count_d1_reg[9]_0\(9)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
I2 => RD_PNTR_WR(8),
I3 => \^q\(8),
O => v1_reg(0)
);
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[7]\(3)
);
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[7]\(2)
);
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[7]\(1)
);
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[7]\(0)
);
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I1 => RD_PNTR_WR(9),
O => \wr_data_count_i_reg[9]\(1)
);
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => RD_PNTR_WR(8),
O => \wr_data_count_i_reg[9]\(0)
);
minusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
minusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
minusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
minusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
\plusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
O => \gdiff.diff_pntr_pad_reg[8]\(3)
);
\plusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => RD_PNTR_WR(6),
O => \gdiff.diff_pntr_pad_reg[8]\(2)
);
\plusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
O => \gdiff.diff_pntr_pad_reg[8]\(1)
);
\plusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => RD_PNTR_WR(4),
O => \gdiff.diff_pntr_pad_reg[8]\(0)
);
\plusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
O => \gdiff.diff_pntr_pad_reg[10]\(1)
);
\plusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => RD_PNTR_WR(8),
O => \gdiff.diff_pntr_pad_reg[10]\(0)
);
plusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
O => \gdiff.diff_pntr_pad_reg[4]\(3)
);
plusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => RD_PNTR_WR(2),
O => \gdiff.diff_pntr_pad_reg[4]\(2)
);
plusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
O => \gdiff.diff_pntr_pad_reg[4]\(1)
);
plusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => RD_PNTR_WR(0),
O => \gdiff.diff_pntr_pad_reg[4]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
signal \minusOp_carry__0_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_1\ : STD_LOGIC;
signal \minusOp_carry__0_n_2\ : STD_LOGIC;
signal \minusOp_carry__0_n_3\ : STD_LOGIC;
signal \minusOp_carry__0_n_4\ : STD_LOGIC;
signal \minusOp_carry__0_n_5\ : STD_LOGIC;
signal \minusOp_carry__0_n_6\ : STD_LOGIC;
signal \minusOp_carry__0_n_7\ : STD_LOGIC;
signal \minusOp_carry__1_n_3\ : STD_LOGIC;
signal \minusOp_carry__1_n_6\ : STD_LOGIC;
signal \minusOp_carry__1_n_7\ : STD_LOGIC;
signal minusOp_carry_n_0 : STD_LOGIC;
signal minusOp_carry_n_1 : STD_LOGIC;
signal minusOp_carry_n_2 : STD_LOGIC;
signal minusOp_carry_n_3 : STD_LOGIC;
signal minusOp_carry_n_4 : STD_LOGIC;
signal minusOp_carry_n_5 : STD_LOGIC;
signal minusOp_carry_n_6 : STD_LOGIC;
signal minusOp_carry_n_7 : STD_LOGIC;
signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_minusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
minusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => minusOp_carry_n_0,
CO(2) => minusOp_carry_n_1,
CO(1) => minusOp_carry_n_2,
CO(0) => minusOp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[8]\(3 downto 0),
O(3) => minusOp_carry_n_4,
O(2) => minusOp_carry_n_5,
O(1) => minusOp_carry_n_6,
O(0) => minusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\minusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => minusOp_carry_n_0,
CO(3) => \minusOp_carry__0_n_0\,
CO(2) => \minusOp_carry__0_n_1\,
CO(1) => \minusOp_carry__0_n_2\,
CO(0) => \minusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[8]\(7 downto 4),
O(3) => \minusOp_carry__0_n_4\,
O(2) => \minusOp_carry__0_n_5\,
O(1) => \minusOp_carry__0_n_6\,
O(0) => \minusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(3 downto 0)
);
\minusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \minusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \minusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \gic0.gc0.count_d2_reg[8]\(8),
O(3 downto 2) => \NLW_minusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \minusOp_carry__1_n_6\,
O(0) => \minusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d2_reg[9]\(1 downto 0)
);
\wr_data_count_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_7,
Q => wr_data_count(0)
);
\wr_data_count_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_6,
Q => wr_data_count(1)
);
\wr_data_count_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_5,
Q => wr_data_count(2)
);
\wr_data_count_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_4,
Q => wr_data_count(3)
);
\wr_data_count_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_7\,
Q => wr_data_count(4)
);
\wr_data_count_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_6\,
Q => wr_data_count(5)
);
\wr_data_count_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_5\,
Q => wr_data_count(6)
);
\wr_data_count_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_4\,
Q => wr_data_count(7)
);
\wr_data_count_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_7\,
Q => wr_data_count(8)
);
\wr_data_count_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_6\,
Q => wr_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
port (
prog_full : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_2_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_3_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_1\ : STD_LOGIC;
signal \plusOp_carry__0_n_2\ : STD_LOGIC;
signal \plusOp_carry__0_n_3\ : STD_LOGIC;
signal \plusOp_carry__0_n_4\ : STD_LOGIC;
signal \plusOp_carry__0_n_5\ : STD_LOGIC;
signal \plusOp_carry__0_n_6\ : STD_LOGIC;
signal \plusOp_carry__0_n_7\ : STD_LOGIC;
signal \plusOp_carry__1_n_3\ : STD_LOGIC;
signal \plusOp_carry__1_n_6\ : STD_LOGIC;
signal \plusOp_carry__1_n_7\ : STD_LOGIC;
signal plusOp_carry_n_0 : STD_LOGIC;
signal plusOp_carry_n_1 : STD_LOGIC;
signal plusOp_carry_n_2 : STD_LOGIC;
signal plusOp_carry_n_3 : STD_LOGIC;
signal plusOp_carry_n_4 : STD_LOGIC;
signal plusOp_carry_n_5 : STD_LOGIC;
signal plusOp_carry_n_6 : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal NLW_plusOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_plusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_6\,
Q => diff_pntr(9)
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_6,
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_5,
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_4,
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_7\,
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_6\,
Q => diff_pntr(5)
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_5\,
Q => diff_pntr(6)
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_4\,
Q => diff_pntr(7)
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_7\,
Q => diff_pntr(8)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F070007"
)
port map (
I0 => \gpf1.prog_full_i_i_2_n_0\,
I1 => \gpf1.prog_full_i_i_3_n_0\,
I2 => wr_rst_busy,
I3 => ram_full_fb_i_reg,
I4 => \^prog_full\,
O => \gpf1.prog_full_i_i_1_n_0\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFF"
)
port map (
I0 => diff_pntr(4),
I1 => diff_pntr(5),
I2 => diff_pntr(3),
I3 => diff_pntr(2),
I4 => diff_pntr(1),
I5 => diff_pntr(6),
O => \gpf1.prog_full_i_i_2_n_0\
);
\gpf1.prog_full_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => diff_pntr(9),
I1 => diff_pntr(8),
I2 => diff_pntr(7),
O => \gpf1.prog_full_i_i_3_n_0\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gpf1.prog_full_i_i_1_n_0\,
PRE => \out\,
Q => \^prog_full\
);
plusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => plusOp_carry_n_0,
CO(2) => plusOp_carry_n_1,
CO(1) => plusOp_carry_n_2,
CO(0) => plusOp_carry_n_3,
CYINIT => E(0),
DI(3 downto 0) => Q(3 downto 0),
O(3) => plusOp_carry_n_4,
O(2) => plusOp_carry_n_5,
O(1) => plusOp_carry_n_6,
O(0) => NLW_plusOp_carry_O_UNCONNECTED(0),
S(3 downto 0) => S(3 downto 0)
);
\plusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => plusOp_carry_n_0,
CO(3) => \plusOp_carry__0_n_0\,
CO(2) => \plusOp_carry__0_n_1\,
CO(1) => \plusOp_carry__0_n_2\,
CO(0) => \plusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \plusOp_carry__0_n_4\,
O(2) => \plusOp_carry__0_n_5\,
O(1) => \plusOp_carry__0_n_6\,
O(0) => \plusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d1_reg[7]\(3 downto 0)
);
\plusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_plusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_carry__1_n_6\,
O(0) => \plusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d1_reg[9]\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
E(0) => E(0),
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
\rd_dc_i_reg[9]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : in STD_LOGIC;
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gdiff.diff_pntr_pad[10]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[10]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_6_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out_0 : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \rd_dc_i[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[9]_i_1_n_3\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gdiff.diff_pntr_pad_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rd_dc_i_reg[3]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
RD_PNTR_WR(9 downto 0) <= \^rd_pntr_wr\(9 downto 0);
\gdiff.diff_pntr_pad[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \gdiff.diff_pntr_pad[10]_i_2_n_0\
);
\gdiff.diff_pntr_pad[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \gdiff.diff_pntr_pad[4]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \gdiff.diff_pntr_pad[4]_i_4_n_0\
);
\gdiff.diff_pntr_pad[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \gdiff.diff_pntr_pad[4]_i_5_n_0\
);
\gdiff.diff_pntr_pad[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \gdiff.diff_pntr_pad[8]_i_2_n_0\
);
\gdiff.diff_pntr_pad[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \gdiff.diff_pntr_pad[8]_i_3_n_0\
);
\gdiff.diff_pntr_pad[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \gdiff.diff_pntr_pad[8]_i_4_n_0\
);
\gdiff.diff_pntr_pad[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gdiff.diff_pntr_pad_reg[10]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => D(8 downto 7),
S(3 downto 2) => B"00",
S(1) => \gdiff.diff_pntr_pad[10]_i_2_n_0\,
S(0) => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\,
CYINIT => p_0_out,
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 1) => D(2 downto 0),
O(0) => \NLW_gdiff.diff_pntr_pad_reg[4]_i_1_O_UNCONNECTED\(0),
S(3) => \gdiff.diff_pntr_pad[4]_i_3_n_0\,
S(2) => \gdiff.diff_pntr_pad[4]_i_4_n_0\,
S(1) => \gdiff.diff_pntr_pad[4]_i_5_n_0\,
S(0) => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(3) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => D(6 downto 3),
S(3) => \gdiff.diff_pntr_pad[8]_i_2_n_0\,
S(2) => \gdiff.diff_pntr_pad[8]_i_3_n_0\,
S(1) => \gdiff.diff_pntr_pad[8]_i_4_n_0\,
S(0) => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
I2 => p_22_out(1),
I3 => Q(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc0.count_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_d1_reg[7]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_d1_reg[7]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_reg[9]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_reg[9]\(1),
O => v1_reg_2(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
I2 => p_22_out(3),
I3 => Q(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(2),
I1 => \gic0.gc0.count_d1_reg[7]\(2),
I2 => \^rd_pntr_wr\(3),
I3 => \gic0.gc0.count_d1_reg[7]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(2),
I1 => \gic0.gc0.count_reg[9]\(2),
I2 => \^rd_pntr_wr\(3),
I3 => \gic0.gc0.count_reg[9]\(3),
O => v1_reg_2(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
I2 => p_22_out(5),
I3 => Q(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc0.count_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(4),
I1 => \gic0.gc0.count_d1_reg[7]\(4),
I2 => \^rd_pntr_wr\(5),
I3 => \gic0.gc0.count_d1_reg[7]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(4),
I1 => \gic0.gc0.count_reg[9]\(4),
I2 => \^rd_pntr_wr\(5),
I3 => \gic0.gc0.count_reg[9]\(5),
O => v1_reg_2(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
I2 => p_22_out(7),
I3 => Q(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc0.count_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(6),
I1 => \gic0.gc0.count_d1_reg[7]\(6),
I2 => \^rd_pntr_wr\(7),
I3 => \gic0.gc0.count_d1_reg[7]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(6),
I1 => \gic0.gc0.count_reg[9]\(6),
I2 => \^rd_pntr_wr\(7),
I3 => \gic0.gc0.count_reg[9]\(7),
O => v1_reg_2(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
I2 => p_22_out(9),
I3 => Q(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc0.count_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rd_pntr_wr\(8),
I1 => \gic0.gc0.count_reg[9]\(8),
I2 => \^rd_pntr_wr\(9),
I3 => \gic0.gc0.count_reg[9]\(9),
O => v1_reg_2(4)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out_0,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[8]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(9),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => \^rd_pntr_wr\(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => \^rd_pntr_wr\(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => \^rd_pntr_wr\(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => \^rd_pntr_wr\(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => \^rd_pntr_wr\(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => \^rd_pntr_wr\(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => \^rd_pntr_wr\(8)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(9),
Q => \^rd_pntr_wr\(9)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out_0,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => p_22_out(9)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
\rd_dc_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \rd_dc_i[3]_i_2_n_0\
);
\rd_dc_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \rd_dc_i[3]_i_3_n_0\
);
\rd_dc_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \rd_dc_i[3]_i_4_n_0\
);
\rd_dc_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \rd_dc_i[7]_i_2_n_0\
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \rd_dc_i[7]_i_3_n_0\
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \rd_dc_i[7]_i_4_n_0\
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \rd_dc_i[9]_i_2_n_0\
);
\rd_dc_i[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \rd_dc_i[9]_i_3_n_0\
);
\rd_dc_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[3]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[3]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[3]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 1) => \rd_dc_i_reg[9]\(2 downto 0),
O(0) => \NLW_rd_dc_i_reg[3]_i_1_O_UNCONNECTED\(0),
S(3) => \rd_dc_i[3]_i_2_n_0\,
S(2) => \rd_dc_i[3]_i_3_n_0\,
S(1) => \rd_dc_i[3]_i_4_n_0\,
S(0) => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[3]_i_1_n_0\,
CO(3) => \rd_dc_i_reg[7]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => \rd_dc_i_reg[9]\(6 downto 3),
S(3) => \rd_dc_i[7]_i_2_n_0\,
S(2) => \rd_dc_i[7]_i_3_n_0\,
S(1) => \rd_dc_i[7]_i_4_n_0\,
S(0) => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i_reg[9]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \rd_dc_i_reg[9]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \rd_dc_i_reg[9]\(8 downto 7),
S(3 downto 2) => B"00",
S(1) => \rd_dc_i[9]_i_2_n_0\,
S(0) => \rd_dc_i[9]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\out\ => ram_empty_fb_i,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => p_0_out
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
port (
full : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
signal c2_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0),
v1_reg_0(0) => v1_reg_0(0)
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_fb_i_reg => c2_n_0,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
E(0) => E(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
E(0) => E(0),
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
prog_empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \gras.rsts_n_2\ : STD_LOGIC;
signal \^out\ : STD_LOGIC;
begin
\out\ <= \^out\;
\gras.gpe.rdpe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
port map (
AR(0) => AR(0),
D(8 downto 0) => D(8 downto 0),
\out\ => \^out\,
prog_empty => prog_empty,
rd_clk => rd_clk
);
\gras.grdc1.rdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
port map (
AR(0) => AR(0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8 downto 0),
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0)
);
\gras.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_2\,
empty => empty,
\out\ => \^out\,
p_0_out => p_0_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \gras.rsts_n_2\,
Q(9 downto 0) => Q(9 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
\gic0.gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_12 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_23 : STD_LOGIC;
signal wpntr_n_24 : STD_LOGIC;
signal wpntr_n_25 : STD_LOGIC;
signal wpntr_n_26 : STD_LOGIC;
signal wpntr_n_27 : STD_LOGIC;
signal wpntr_n_28 : STD_LOGIC;
signal wpntr_n_29 : STD_LOGIC;
signal wpntr_n_30 : STD_LOGIC;
signal wpntr_n_31 : STD_LOGIC;
signal wpntr_n_32 : STD_LOGIC;
signal wpntr_n_33 : STD_LOGIC;
signal wpntr_n_34 : STD_LOGIC;
signal wpntr_n_35 : STD_LOGIC;
signal wpntr_n_36 : STD_LOGIC;
signal wpntr_n_37 : STD_LOGIC;
signal wpntr_n_38 : STD_LOGIC;
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
E(0) <= \^e\(0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gwas.gpf.wrpf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(8) => p_13_out(8),
Q(7 downto 0) => \^q\(7 downto 0),
S(3) => wpntr_n_35,
S(2) => wpntr_n_36,
S(1) => wpntr_n_37,
S(0) => wpntr_n_38,
\gic0.gc0.count_d1_reg[7]\(3) => wpntr_n_27,
\gic0.gc0.count_d1_reg[7]\(2) => wpntr_n_28,
\gic0.gc0.count_d1_reg[7]\(1) => wpntr_n_29,
\gic0.gc0.count_d1_reg[7]\(0) => wpntr_n_30,
\gic0.gc0.count_d1_reg[9]\(1) => wpntr_n_12,
\gic0.gc0.count_d1_reg[9]\(0) => wpntr_n_13,
\out\ => \out\,
prog_full => prog_full,
ram_full_fb_i_reg => \gwas.wsts_n_1\,
wr_clk => wr_clk,
wr_rst_busy => wr_rst_busy
);
\gwas.gwdc0.wdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
port map (
AR(0) => AR(0),
S(3) => wpntr_n_31,
S(2) => wpntr_n_32,
S(1) => wpntr_n_33,
S(0) => wpntr_n_34,
\gic0.gc0.count_d2_reg[7]\(3) => wpntr_n_23,
\gic0.gc0.count_d2_reg[7]\(2) => wpntr_n_24,
\gic0.gc0.count_d2_reg[7]\(1) => wpntr_n_25,
\gic0.gc0.count_d2_reg[7]\(0) => wpntr_n_26,
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8 downto 0),
\gic0.gc0.count_d2_reg[9]\(1) => wpntr_n_0,
\gic0.gc0.count_d2_reg[9]\(0) => wpntr_n_1,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0)
);
\gwas.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0),
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\out\ => \gwas.wsts_n_1\,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(0) => \c1/v1_reg\(4),
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0),
E(0) => \^e\(0),
Q(8) => p_13_out(8),
Q(7 downto 0) => \^q\(7 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
S(3) => wpntr_n_31,
S(2) => wpntr_n_32,
S(1) => wpntr_n_33,
S(0) => wpntr_n_34,
\gdiff.diff_pntr_pad_reg[10]\(1) => wpntr_n_12,
\gdiff.diff_pntr_pad_reg[10]\(0) => wpntr_n_13,
\gdiff.diff_pntr_pad_reg[4]\(3) => wpntr_n_35,
\gdiff.diff_pntr_pad_reg[4]\(2) => wpntr_n_36,
\gdiff.diff_pntr_pad_reg[4]\(1) => wpntr_n_37,
\gdiff.diff_pntr_pad_reg[4]\(0) => wpntr_n_38,
\gdiff.diff_pntr_pad_reg[8]\(3) => wpntr_n_27,
\gdiff.diff_pntr_pad_reg[8]\(2) => wpntr_n_28,
\gdiff.diff_pntr_pad_reg[8]\(1) => wpntr_n_29,
\gdiff.diff_pntr_pad_reg[8]\(0) => wpntr_n_30,
\gic0.gc0.count_d1_reg[9]_0\(9 downto 0) => \gic0.gc0.count_d1_reg[9]\(9 downto 0),
v1_reg(0) => \c1/v1_reg\(4),
wr_clk => wr_clk,
\wr_data_count_i_reg[7]\(3) => wpntr_n_23,
\wr_data_count_i_reg[7]\(2) => wpntr_n_24,
\wr_data_count_i_reg[7]\(1) => wpntr_n_25,
\wr_data_count_i_reg[7]\(0) => wpntr_n_26,
\wr_data_count_i_reg[9]\(1) => wpntr_n_0,
\wr_data_count_i_reg[9]\(0) => wpntr_n_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
E(0) => E(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => \gic0.gc0.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwas.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 2 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(8 downto 0) => plusOp(10 downto 2),
Q(9 downto 0) => p_0_out_0(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_13_out(7 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\gic0.gc0.count_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
p_0_out => p_0_out,
rd_clk => rd_clk,
\rd_dc_i_reg[9]\(8 downto 0) => minusOp(9 downto 1),
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
v1_reg_1(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
v1_reg_2(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(8 downto 0) => plusOp(10 downto 2),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out_0(9 downto 0),
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
empty => empty,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8 downto 0) => minusOp(9 downto 1),
\out\ => p_2_out,
p_0_out => p_0_out,
prog_empty => prog_empty,
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0),
rd_en => rd_en,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_12_out(9 downto 0),
E(0) => p_18_out,
Q(7 downto 0) => p_13_out(7 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
full => full,
\gic0.gc0.count_d1_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[6]\(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
\out\ => rst_full_ff_i,
prog_full => prog_full,
v1_reg(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0),
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
E(0) => p_18_out,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out_0(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 313;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 314;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 66;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 65;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_0,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 313;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 314;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 66;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 65;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => prog_empty,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => prog_full,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
a362ececb9da826a9adb2cf53c823d7c
| 0.61627 | 2.912324 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/xlib.vhd
| 1 | 8,857 |
-- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2007-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: xlib
-- Description: Xilinx specific components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1, 14.5, 14.6; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.0.10 add s6_cmt_sfs
-- 2013-09-28 535 1.0.9 add s7_cmt_sfs
-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
-- 2008-05-23 149 1.0.4 add iob_io(_gen)
-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);
-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)
-- 2007-12-16 101 1.0.1 add INIT generic ports
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package xlib is
component iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end component;
component iob_reg_i_gen is -- registered IOB, input, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slv(DWIDTH-1 downto 0); -- input data
PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_o is -- registered IOB, output
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_reg_o_gen is -- registered IOB, output, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slv(DWIDTH-1 downto 0); -- output data
PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_io is -- registered IOB, in/output
generic (
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_reg_io_gen is -- registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_io is -- un-registered IOB, in/output
generic (
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_oddr2_simple is -- DDR2 output I/O pad
generic (
ALIGN : string := "NONE"; -- ddr_alignment
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO0 : in slbit; -- output data
DO1 : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_io_gen is -- un-registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_keeper is -- keeper for IOB
port (
PAD : inout slbit -- i/o pad
);
end component;
component iob_keeper_gen is -- keeper for IOB, vector
generic (
DWIDTH : positive := 16); -- data port width
port (
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end component;
component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
end package xlib;
|
gpl-2.0
|
48e1fa1df5af783b0fa1dbd0729c148c
| 0.50604 | 3.83254 | false | false | false | false |
superboy0712/MIPS
|
MIPSSystem.vhd
| 1 | 4,684 |
-- Part of TDT4255 Computer Design laboratory exercises
-- Group for Computer Architecture and Design
-- Department of Computer and Information Science
-- Norwegian University of Science and Technology
-- MIPSSystem.vhd
-- The MIPS processor system to be used in Exercise 1 and 2 during FPGA
-- testing. The system consists of a MIPSProcessor, two memories
-- and a HostComm module that can be used for controlling the processor
-- state or reading/writing the memories. The hostcomm utility (delivered
-- as part of the exercise) can be used from a host computer for this purpose.
-- Make sure you have thoroughly tested your solution with testbenches
-- (including tb_MIPSProcessor.vhd) before attempting FPGA test.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity MIPSSystem is
-- do not change these, the memories are pregenerated at the moment
-- and do not support changing the address width/word size
generic (
ADDR_WIDTH : integer := 8;
DATA_WIDTH : integer := 32
);
port (
clk, reset : in STD_LOGIC;
-- interface towards the UART ports
UART_Rx : in STD_LOGIC;
UART_Tx : out STD_LOGIC;
-- LED output
leds : out STD_LOGIC_VECTOR (3 downto 0)
);
end MIPSSystem;
architecture Behavioral of MIPSSystem is
-- signals for processor control
signal processorEnable : std_logic;
signal processorReset : std_logic;
-- signals for instruction memory, processor port (read only!)
signal procIMemReadData : std_logic_vector(DATA_WIDTH-1 downto 0);
signal procIMemAddr : std_logic_vector(ADDR_WIDTH-1 downto 0);
-- signals for data memory, processor port
signal procDMemWriteEnable : std_logic;
signal procDMemWriteData : std_logic_vector(DATA_WIDTH-1 downto 0);
signal procDMemReadData : std_logic_vector(DATA_WIDTH-1 downto 0);
signal procDMemAddr : std_logic_vector(ADDR_WIDTH-1 downto 0);
-- signals for instruction memory, hostcomm port
signal hcIMemWriteEnable : std_logic;
signal hcIMemWriteData : std_logic_vector(7 downto 0);
signal hcIMemReadData : std_logic_vector(7 downto 0);
signal hcIMemAddr : std_logic_vector(9 downto 0);
-- signals for data memory, hostcomm port
signal hcDMemWriteEnable : std_logic;
signal hcDMemWriteData : std_logic_vector(7 downto 0);
signal hcDMemReadData : std_logic_vector(7 downto 0);
signal hcDMemAddr : std_logic_vector(9 downto 0);
begin
-- instantiate the processor
MIPSProcInst: entity work.MIPSProcessor(Behavioral)
generic map (ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk, reset => processorReset,
processor_enable => processorEnable,
-- instruction memory connection
imem_data_in => procIMemReadData, -- instruction data from memory
imem_address => procIMemAddr, -- instruction address to memory
-- data memory connection
dmem_data_in => procDMemReadData, -- read data from memory
dmem_address => procDMemAddr, -- address to memory
dmem_data_out => procDMemWriteData, -- write data to memory
dmem_write_enable => procDMemWriteEnable -- write enable to memory
);
-- instantiate the host communication module
HostCommInst: entity work.HostComm port map (
clk => clk, reset => reset,
UART_Rx => UART_Rx, UART_Tx => UART_Tx,
proc_en => processorEnable, proc_rst => processorReset,
-- instruction memory connection
imem_data_in => hcIMemReadData, imem_data_out => hcIMemWriteData,
imem_wr_en => hcIMemWriteEnable, imem_addr => hcIMemAddr,
-- data memory connection
dmem_data_in => hcDMemReadData, dmem_data_out => hcDMemWriteData,
dmem_wr_en => hcDMemWriteEnable, dmem_addr => hcDMemAddr
);
-- instantiate the instruction memory
InstrMem: entity work.DualPortMem port map (
clka => clk, clkb => clk,
-- port A: processor connection, read only
wea(0) => '0',
dina => x"00000000",
addra => procIMemAddr, douta => procIMemReadData,
-- port B: hostcomm connection, read+write
web(0) => hcIMemWriteEnable, addrb => hcIMemAddr,
dinb => hcIMemWriteData, doutb => hcIMemReadData
);
-- instantiate the data memory
DataMem: entity work.DualPortMem port map (
clka => clk, clkb => clk,
-- port A: processor connection, read+write
wea(0) => procDMemWriteEnable, dina => procDMemWriteData,
addra => procDMemAddr, douta =>procDMemReadData,
-- port B: hostcomm connection, read+write
web(0) => hcDMemWriteEnable, addrb => hcDMemAddr,
dinb => hcDMemWriteData, doutb => hcDMemReadData
);
-- drive the LEDs
leds(3 downto 0) <= "1010";
end Behavioral;
|
mit
|
0ad5bf73237b69c427fe2915542235e2
| 0.702605 | 3.639472 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
libraries/float_synth.vhdl
| 2 | 26,864 |
-------------------------------------------------------------------------------
-- Synthesis test for the floating point math package
-- This test is designed to be synthesizable and exercise much of the package.
-- Created for vhdl-200x by David Bishop ([email protected])
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:50:32-04 $
-- Version $Id: float_synth.vhdl,v 1.1 2006-06-08 10:50:32-04 l435385 Exp $
-------------------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
use ieee.math_real.all;
entity float_synth is
port (
in1, in2 : in std_logic_vector (31 downto 0); -- inputs
out1 : out std_logic_vector (31 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end entity float_synth;
architecture rtl of float_synth is
subtype fp16 is float (6 downto -9); -- 16 bit
type cmd_type is array (1 to 15) of std_ulogic_vector (cmd'range); -- cmd
signal cmdarray : cmd_type; -- command pipeline
type cry_type is array (0 to 15) of float32; -- arrays
signal outx : cry_type;
signal in1reg3, in2reg3 : float32; -- register stages
begin -- architecture rtl
-- purpose: "0000" test the "+" operator
cmd0reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(0) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(0) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 + in2reg3;
end if;
end process cmd0reg;
-- purpose: "0001" test the "-" operator
cmd1reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(1) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(1) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 - in2reg3;
end if;
end process cmd1reg;
-- purpose: "0010" test the "*" operator
cmd2reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(2) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(2) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 * in2reg3;
end if;
end process cmd2reg;
-- purpose: "0011" performs test the "/" operator
cmd3reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(3) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(3) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
if (cmdarray(4) = "0011") then
outarray(0) := in1reg3 / in2reg3;
else
outarray(0) := (others => '0');
end if;
end if;
end process cmd3reg;
-- purpose: "0100" test the "resize" function
cmd4reg: process (clk, rst_n) is
variable tmpfp161, tmpfp162 : fp16; -- 16 bit fp number
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(4) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(4) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_zero);
when "001" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "010" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "011" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_inf);
when "100" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_neginf);
when "101" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
check_error => false,
round_style => round_zero);
when "110" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low);
when "111" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low
-- size_res => tmpfp161
);
when others => null;
end case;
outarray(0)(-8 downto -23) := tmpfp161;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(6 downto -7) := (others => '0');
end if;
end process cmd4reg;
-- purpose: "0101" Conversion function test
cmd5reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(5) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(5) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := to_unsigned (in1reg3, uns'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "001" =>
uns := to_unsigned (in1reg3, uns);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "010" =>
s := to_signed (in1reg3, s'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "011" =>
s := to_signed (in1reg3, s);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "100" =>
uf := to_ufixed (in1reg3, uf'high, uf'low);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "101" =>
uf := to_ufixed (in1reg3, uf);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "110" =>
sf := to_sfixed (in1reg3, sf'high, sf'low);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when "111" =>
sf := to_sfixed (in1reg3, sf);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when others => null;
end case;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(5 downto -7) := (others => '0');
end if;
end process cmd5reg;
-- purpose: "0110" to_float()
cmd6reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(6) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(6) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, 8, 23);
when "001" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, in1reg3);
when "010" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, 8, 23);
when "011" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, in1reg3);
when "100" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf'high, uf'low);
outarray(0) := to_float(uf, 8, 23);
when "101" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf);
outarray(0) := to_float(uf, in1reg3);
when "110" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf'high, sf'low);
outarray(0) := to_float(sf, 8, 23);
when "111" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf);
outarray(0) := to_float(sf, in1reg3);
when others => null;
end case;
end if;
end process cmd6reg;
-- purpose: "0111" mod function
cmd7reg: process (clk, rst_n) is
variable tmpuns : unsigned (31 downto 0); -- unsigned number
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(7) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(7) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 mod in2reg3;
end if;
end process cmd7reg;
-- purpose: "1000" rem function
cmd8reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(8) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(8) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 rem in2reg3;
end if;
end process cmd8reg;
-- purpose: "1001" to_float (constants) test
cmd9reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(9) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(9) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := to_float(0, 8, 23);
when "001" =>
outarray(0) := to_float(0.0, 8, 23);
when "010" =>
outarray(0) := to_float(8, in1reg3);
when "011" =>
outarray(0) := to_float(8.0, in1reg3);
when "100" =>
outarray(0) := to_float(-8, 8, 23);
when "101" =>
outarray(0) := to_float(-8.0, 8, 23);
when "110" =>
outarray(0) := to_float(27000, in2reg3);
when "111" =>
-- outarray(0) := "01000000010010010000111111011011";
outarray(0) := to_float(MATH_PI, in2reg3);
when others => null;
end case;
end if;
end process cmd9reg;
-- purpose: "1010" data manipulation (+, -, scalb, etc)
cmd10reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable s : SIGNED (7 downto 0); -- signed number
variable outarray : cry_type; -- array for output
constant posinf : float32 := "01111111100000000000000000000000"; -- +inf
constant neginf : float32 := "11111111100000000000000000000000"; -- +inf
constant onept5 : float32 := "00111111110000000000000000000000"; -- 1.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(10) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(10) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := - in1reg3;
when "001" =>
outarray(0) := abs( in1reg3);
when "010" =>
if (cmdarray(4) = "1010") then
s := resize (SIGNED (to_slv (in2reg3(8 downto 5))), s'length);
outarray(0) := Scalb (in1reg3, s);
else
outarray(0) := (others => '0');
end if;
when "011" =>
if (cmdarray(4) = "1010") then
s := logb (in1reg3);
outarray(0) := (others => '0');
outarray(0)(-16 downto -23) := float(std_logic_vector(s));
else
outarray(0) := (others => '0');
end if;
when "100" =>
outarray(0) := Nextafter ( in1reg3, onept5);
when "101" =>
outarray(0) := Nextafter ( in1reg3, -onept5);
when "110" =>
outarray(0) := Nextafter ( x => in1reg3, y => posinf,
check_error => false,
denormalize => false);
when "111" =>
outarray(0) := Nextafter (x => in1reg3, y => neginf,
check_error => false,
denormalize => false);
when others => null;
end case;
end if;
end process cmd10reg;
-- purpose "1011" copysign
cmd11reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(11) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(11) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := Copysign (in1reg3, in2reg3);
end if;
end process cmd11reg;
-- purpose "1100" compare test
cmd12reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
constant fifteenpt5 : float32 := "01000001011110000000000000000000";-- 15.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(12) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(12) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := (others => '0');
if (in1reg3 = in2reg3) then
outarray(0)(outarray(0)'high) := '1';
else
outarray(0)(outarray(0)'high) := '0';
end if;
if (in1reg3 /= in2reg3) then
outarray(0)(outarray(0)'high-1) := '1';
else
outarray(0)(outarray(0)'high-1) := '0';
end if;
if (in1reg3 > in2reg3) then
outarray(0)(outarray(0)'high-2) := '1';
else
outarray(0)(outarray(0)'high-2) := '0';
end if;
if (in1reg3 < in2reg3) then
outarray(0)(outarray(0)'high-3) := '1';
else
outarray(0)(outarray(0)'high-3) := '0';
end if;
if (in1reg3 >= in2reg3) then
outarray(0)(outarray(0)'high-4) := '1';
else
outarray(0)(outarray(0)'high-4) := '0';
end if;
if (in1reg3 <= in2reg3) then
outarray(0)(outarray(0)'high-5) := '1';
else
outarray(0)(outarray(0)'high-5) := '0';
end if;
outarray(0)(outarray(0)'high-6) := \?=\ (in1reg3, 15);
outarray(0)(outarray(0)'high-7) := \?=\ (in1reg3, 15.5);
if (Unordered (in1reg3, in2reg3)) then
outarray(0)(outarray(0)'high-8) := '1';
else
outarray(0)(outarray(0)'high-8) := '0';
end if;
if (Finite (in1reg3)) then
outarray(0)(outarray(0)'high-9) := '1';
else
outarray(0)(outarray(0)'high-9) := '0';
end if;
if (Isnan (in1reg3)) then
outarray(0)(outarray(0)'high-10) := '1';
else
outarray(0)(outarray(0)'high-10) := '0';
end if;
end if;
end process cmd12reg;
-- purpose "1101" boolean test
cmd13reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(13) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(13) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := not (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3;
when "010" =>
outarray(0) := in1reg3 or in2reg3;
when "011" =>
outarray(0) := in1reg3 nand in2reg3;
when "100" =>
outarray(0) := in1reg3 nor in2reg3;
when "101" =>
outarray(0) := in1reg3 xor in2reg3;
when "110" =>
outarray(0) := in1reg3 xnor in2reg3;
when "111" =>
outarray(0) := in1reg3 xor '1';
when others => null;
end case;
end if;
end process cmd13reg;
-- purpose "1110" reduce and vector test
cmd14reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(14) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(14) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := (others => '0');
outarray(0)(outarray(0)'high) := and_reduce (in1reg3);
outarray(0)(outarray(0)'high-1) := nand_reduce (in1reg3);
outarray(0)(outarray(0)'high-2) := or_reduce (in1reg3);
outarray(0)(outarray(0)'high-3) := nor_reduce (in1reg3);
outarray(0)(outarray(0)'high-4) := xor_reduce (in1reg3);
outarray(0)(outarray(0)'high-5) := xnor_reduce (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3(in2reg3'high);
when "010" =>
outarray(0) := in1reg3 or in2reg3(in2reg3'high);
when "011" =>
outarray(0) := in1reg3 nand in2reg3(in2reg3'high);
when "100" =>
outarray(0) := in1reg3 nor in2reg3(in2reg3'high);
when "101" =>
outarray(0) := in2reg3(in2reg3'high) xor in1reg3;
when "110" =>
outarray(0) := in2reg3(in2reg3'high) xnor in1reg3;
when "111" =>
outarray(0) := in2reg3(in2reg3'high) and in1reg3;
when others => null;
end case;
end if;
end process cmd14reg;
-- purpose "1111" + constant
cmd15reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(15) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(15) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := in1reg3 + 1;
when "001" =>
outarray(0) := 1 + in1reg3;
when "010" =>
outarray(0) := in1reg3 + 1.0;
when "011" =>
outarray(0) := 1.0 + in1reg3;
when "100" =>
outarray(0) := in1reg3 * 1;
when "101" =>
outarray(0) := 1 * in1reg3;
when "110" =>
outarray(0) := in1reg3 * 1.0;
when "111" =>
outarray(0) := 1.0 * in1reg3;
when others => null;
end case;
end if;
end process cmd15reg;
-- purpose: multiply floating point
-- type : sequential
-- inputs : clk, rst_n, in1, in2
-- outputs: out1
cmdreg: process (clk, rst_n) is
variable outreg : float32; -- register stages
variable in1reg, in2reg : float32; -- register stages
variable in1reg2, in2reg2 : float32; -- register stages
begin -- process mulreg
if rst_n = '0' then -- asynchronous reset (active low)
in1reg := ( others => '0');
in2reg := ( others => '0');
in1reg2 := ( others => '0');
in2reg2 := ( others => '0');
in1reg3 <= ( others => '0');
in2reg3 <= ( others => '0');
out1 <= ( others => '0');
outreg := (others => '0');
rcloop: for i in 1 to 15 loop
cmdarray (i) <= (others => '0');
end loop rcloop;
elsif rising_edge(clk) then -- rising clock edge
out1 <= to_slv (outreg);
outregc: case cmdarray (13) is
when "0000" => outreg := outx (0);
when "0001" => outreg := outx (1);
when "0010" => outreg := outx (2);
when "0011" => outreg := outx (3);
when "0100" => outreg := outx (4);
when "0101" => outreg := outx (5);
when "0110" => outreg := outx (6);
when "0111" => outreg := outx (7);
when "1000" => outreg := outx (8);
when "1001" => outreg := outx (9);
when "1010" => outreg := outx (10);
when "1011" => outreg := outx (11);
when "1100" => outreg := outx (12);
when "1101" => outreg := outx (13);
when "1110" => outreg := outx (14);
when "1111" => outreg := outx (15);
when others => null;
end case outregc;
cmdpipe: for i in 15 downto 3 loop
cmdarray (i) <= cmdarray (i-1);
end loop cmdpipe;
cmdarray (2) <= std_ulogic_vector(cmd);
in1reg3 <= in1reg2;
in2reg3 <= in2reg2;
in1reg2 := in1reg;
in2reg2 := in2reg;
in1reg := to_float (in1, in1reg);
in2reg := to_float (in2, in2reg);
end if;
end process cmdreg;
end architecture rtl;
|
gpl-3.0
|
e2e1832d2785ba9a854408e5ba3975b5
| 0.51247 | 3.602038 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/pezhman_mem/simulation/bmg_stim_gen.vhd
| 1 | 13,015 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (32767 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"pezhman_mem.mif",
DEFAULT_DATA,
8,
32768);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>32768 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(14 DOWNTO 0) <= READ_ADDR(14 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ_REG(1);
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 32768 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
gpl-3.0
|
31550882552dd2580134722795ee7975
| 0.52985 | 3.696393 | false | false | false | false |
freecores/w11
|
rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd
| 1 | 3,932 |
-- $Id: nexys2_fusp_dummy.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_fusp_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys2_fusp_dummy;
architecture syn of nexys2_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
gpl-2.0
|
68991b909f52bd99a4cf0f7bf674cc65
| 0.532045 | 3.323753 | false | false | false | false |
quicky2000/top_test_image_controler_640_480_1b
|
testbench/testbench_top_test_image_controler_640_480_1b.vhd
| 1 | 2,983 |
--
-- This file is part of top_test_image_controler_640_480_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbench_top_test_image_controler_640_480_1b IS
END testbench_top_test_image_controler_640_480_1b;
ARCHITECTURE behavior OF testbench_top_test_image_controler_640_480_1b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_test_image_controler_640_480_1b
PORT(
clk : IN std_logic;
w1a : INOUT std_logic_vector(15 downto 0);
w1b : INOUT std_logic_vector(15 downto 0);
w2c : INOUT std_logic_vector(15 downto 0);
rx : IN std_logic;
tx : INOUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--BiDirs
signal w1a : std_logic_vector(15 downto 0);
signal w1b : std_logic_vector(15 downto 0);
signal w2c : std_logic_vector(15 downto 0);
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_test_image_controler_640_480_1b PORT MAP (
clk => clk,
w1a => w1a,
w1b => w1b,
w2c => w2c,
rx => rx,
tx => tx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
f6f2f337989b167b6c3b0c6b823c046d
| 0.638284 | 3.761665 | false | true | false | false |
freecores/w11
|
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
| 1 | 7,813 |
-- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp is
end tb_nexys3_fusp;
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
1069bdbbc2fae790cccfc37f5f4ea22b
| 0.53219 | 3.163158 | false | false | false | false |
freecores/w11
|
rtl/ibus/ibd_iist.vhd
| 2 | 28,981 |
-- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibd_iist - syn
-- Description: ibus dev(loc): IIST
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 112 510 0 291 s 15.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 111 504 0 290 s 15.6
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
-- also for dcf_dcf and exc_rte; add iist_mreq and
-- iist_sreq, boot and lock interfaces
-- 2009-06-05 223 0.6 level interrupt, parity logic, exc.ui logic
-- st logic modified (partially tested)
-- 2009-06-01 221 0.5 Initial version (untested, lock&boot missing)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
SID : slv2 := "00"); -- self id
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit; -- interrupt acknowledge
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
IIST_OUT : out iist_line_type; -- iist output
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
IIST_SRES : in iist_sres_type -- cpu->iist responses
);
end ibd_iist;
architecture syn of ibd_iist is
constant ibaddr_iist : slv16 := slv(to_unsigned(8#177500#,16));
constant tdlysnd : natural := 150; -- send delay timer
constant ibaddr_acr : slv1 := "0"; -- acr address offset
constant ibaddr_adr : slv1 := "1"; -- adr address offset
constant acr_ibf_clr : integer := 15; -- clear flag
subtype acr_ibf_sid is integer range 9 downto 8; -- self id
subtype acr_ibf_ac is integer range 3 downto 0; -- ac code
constant ac_pge : slv4 := "0000"; -- 0 program generated enables
constant ac_pgc : slv4 := "0001"; -- 1 program generated control/status
constant ac_ste : slv4 := "0010"; -- 2 sanity timer enables
constant ac_stc : slv4 := "0011"; -- 3 sanity timer control/status
constant ac_msk : slv4 := "0100"; -- 4 input masks
constant ac_pgf : slv4 := "0101"; -- 5 program generated flags
constant ac_stf : slv4 := "0110"; -- 6 sanity timer flags
constant ac_dcf : slv4 := "0111"; -- 7 disconnect flags
constant ac_exc : slv4 := "1000"; -- 10 exceptions
constant ac_mtc : slv4 := "1101"; -- 15 maintenance control
subtype pge_ibf_pbe is integer range 11 downto 8; -- pg boot ena
subtype pge_ibf_pie is integer range 3 downto 0; -- pg int ena
constant pgc_ibf_err : integer := 15; -- error
constant pgc_ibf_grj : integer := 14; -- go reject
constant pgc_ibf_pgrmr : integer := 13; -- pg req refused
constant pgc_ibf_strmr : integer := 12; -- st req refused
constant pgc_ibf_rdy : integer := 11; -- ready flag
subtype pgc_ibf_sid is integer range 9 downto 8; -- self id
constant pgc_ibf_ip : integer := 3; -- int pending
constant pgc_ibf_ie : integer := 2; -- int enable
constant pgc_ibf_ptp : integer := 1; -- pg parity
constant pgc_ibf_go : integer := 0; -- go flag
subtype ste_ibf_sbe is integer range 11 downto 8; -- st boot enable
subtype ste_ibf_sie is integer range 3 downto 0; -- st int enable
subtype stc_ibf_count is integer range 15 downto 8; -- count
constant stc_ibf_tmo : integer := 3; -- timeout
constant stc_ibf_lke : integer := 2; -- lockup enable
constant stc_ibf_stp : integer := 1; -- st parity
constant stc_ibf_enb : integer := 0; -- enable
subtype msk_ibf_bm is integer range 11 downto 8; -- boot mask
subtype msk_ibf_im is integer range 3 downto 0; -- int mask
subtype pgf_ibf_pbf is integer range 11 downto 8; -- boot flags
subtype pgf_ibf_pif is integer range 3 downto 0; -- int flags
subtype stf_ibf_sbf is integer range 11 downto 8; -- boot flags
subtype stf_ibf_sif is integer range 3 downto 0; -- int flags
subtype dcf_ibf_brk is integer range 11 downto 8; -- break flags
subtype dcf_ibf_dcf is integer range 3 downto 0; -- disconnect flags
subtype exc_ibf_ui is integer range 11 downto 8; -- unexpected int
subtype exc_ibf_rte is integer range 3 downto 0; -- transm. error
constant mtc_ibf_mttp : integer := 11; -- maint. type
constant mtc_ibf_mfrm : integer := 10; -- maint. frame err
subtype mtc_ibf_mid is integer range 9 downto 8; -- maint. id
constant mtc_ibf_dsbt : integer := 3; -- disable boot
constant mtc_ibf_enmxd : integer := 2; -- enable maint mux
constant mtc_ibf_enmlp : integer := 1; -- enable maint loop
constant mtc_ibf_dsdrv : integer := 0; -- disable driver
type state_type is (
s_idle, -- idle state
s_clear, -- handle acr clr
s_stsnd, -- handle st transmit
s_pgsnd -- handle pg transmit
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
acr_ac : slv4; -- acr: ac
pge_pbe : slv4; -- pge: pg boot ena
pge_pie : slv4; -- pge: pg int ena
pgc_grj : slbit; -- pgc: go reject
pgc_pgrmr : slbit; -- pgc: pg req refused
pgc_strmr : slbit; -- pgc: st req refused
pgc_ie : slbit; -- pgc: int enable
pgc_ptp : slbit; -- pgc: pg parity
ste_sbe : slv4; -- ste: st boot enable
ste_sie : slv4; -- ste: st int enable
stc_count : slv8; -- stc: count
stc_tmo : slbit; -- stc: timeout
stc_lke : slbit; -- stc: lockup enable
stc_stp : slbit; -- stc: st parity
stc_enb : slbit; -- stc: enable
msk_bm : slv4; -- msk: boot mask
msk_im : slv4; -- msk: int mask
pgf_pbf : slv4; -- pgf: boot flags
pgf_pif : slv4; -- pgf: int flags
stf_sbf : slv4; -- stf: boot flags
stf_sif : slv4; -- stf: int flags
dcf_brk : slv4; -- dcf: break flags
dcf_dcf : slv4; -- dcf: disconnect flags
exc_ui : slv4; -- exc: unexpected int
exc_rte : slv4; -- exc: transm. error
mtc_mttp : slbit; -- mtc: maint. type
mtc_mfrm : slbit; -- mtc: maint. frame err
mtc_mid : slv2; -- mtc: maint. id
mtc_dsbt : slbit; -- mtc: disable boot
mtc_enmxd : slbit; -- mtc: enable maint mux
mtc_enmlp : slbit; -- mtc: enable maint loop
mtc_dsdrv : slbit; -- mtc: disable driver
state : state_type; -- state
req_clear : slbit; -- request clear
req_stsnd : slbit; -- request sanity timer transmit
req_pgsnd : slbit; -- request prog. gen. transmit
tcnt256 : slv8; -- usec clock divider for st clock
tcntsnd : slv8; -- timer for transmit delay
req_lock : slbit; -- cpu lock request
req_boot : slbit; -- cpu boot request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"0000", -- acr_ac
"0000","0000", -- pge_pbe, pge_pie
'0', -- pgc_grj
'0','0', -- pgc_pgrmr, pgc_strmr
'0','0', -- pgc_ie, pgc_ptp
"0000","0000", -- ste_sbe, ste_sie
(others=>'0'), -- stc_count
'0','0', -- stc_tmo, stc_lke
'0','0', -- stc_stp, stc_enb
"0000","0000", -- msk_bm, msk_im
"0000","0000", -- pgf_pbf, pgf_pif
"0000","0000", -- stf_sbf, stf_sif
"0000","0000", -- dcf_brk, dcf_dcf
"0000","0000", -- exc_ui, exc_rte
'0','0', -- mtc_mttp, mtc_mfrm
"00", -- mtc_mid
'0','0', -- mtc_dsbt, mtc_enmxd
'0','0', -- mtc_enmlp, mtc_dsdrv
s_idle, -- state
'0', -- req_clear
'0','0', -- req_stsnd, req_pgsnd
(others=>'0'), -- tcnt256
(others=>'0'), -- tcntsnd
'0','0' -- req_lock, req_boot
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' or -- BRESET is 1 for system and ibus reset
R_REGS.req_clear='1' then
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.pgf_pbf <= N_REGS.pgf_pbf; -- don't reset pg boot flags
R_REGS.stf_sbf <= N_REGS.stf_sbf; -- don't reset st boot flags
R_REGS.tcnt256 <= N_REGS.tcnt256; -- don't reset st clock divider
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, IB_MREQ, EI_ACK, EI_ACK,
IIST_BUS(0), IIST_BUS(1), IIST_BUS(2), IIST_BUS(3),
IIST_SRES)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable int_or : slbit := '0';
variable tcnt256_end : slbit := '0';
variable tcntsnd_end : slbit := '0';
variable eff_id : slv2 := "00";
variable eff_bus : iist_bus_type := iist_bus_init;
variable par_err : slbit := '0';
variable act_ibit : slbit := '0';
variable act_bbit : slbit := '0';
variable iout : iist_line_type := iist_line_init;
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
int_or := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
for i in r.dcf_dcf'range loop
int_or := int_or or r.dcf_dcf(i) or
r.exc_rte(i) or
r.pgf_pif(i) or
r.stf_sif(i);
end loop; -- i
tcnt256_end := '0';
if CE_USEC='1' and r.stc_enb='1'then -- if st enabled on every usec
n.tcnt256 := slv(unsigned(r.tcnt256) + 1); -- advance 8 bit counter
if unsigned(r.tcnt256) = 255 then -- if wrap
tcnt256_end := '1'; -- signal 256 usec passed
end if;
end if;
tcntsnd_end := '0';
n.tcntsnd := slv(unsigned(r.tcntsnd) + 1); -- advance send timer counter
if unsigned(r.tcntsnd) = tdlysnd-1 then -- if delay time reached
tcntsnd_end := '1'; -- signal end
end if;
eff_id := SID; -- effective self-id, normally SID
if r.mtc_enmxd = '1' then -- if maint. mux enabled
eff_id := r.mtc_mid; -- use maint. id
end if;
eff_bus := IIST_BUS;
par_err := '0';
act_ibit := '0';
act_bbit := '0';
iout := iist_line_init; -- default state of out line
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_iist(12 downto 2) then
n.ibsel := '1';
end if;
-- internal state machine
case r.state is
when s_idle => -- idle state
n.tcntsnd := (others=>'0'); -- keep send delay timer zero
if r.req_stsnd = '1' then -- sanity timer request pending
n.state := s_stsnd;
elsif r.req_pgsnd = '1' then -- prog. gen. request pending
n.state := s_pgsnd;
end if;
when s_clear => -- handle acr clr
ibhold := r.ibsel; -- keep req pending if selected
-- r.req_clear is set when in this state and cause a reset in prog_regs
-- --> n.req_clear := '0';
-- --> n.state := s_idle;
when s_stsnd => -- handle st transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_stsnd := '0'; -- clear st transmit request
iout.req := '1'; -- do transmit
iout.stf := '1'; -- signal type = st
iout.imask := r.ste_sie; -- int enables
iout.bmask := r.ste_sbe; -- boot enables
iout.par := not r.stc_stp; -- send parity (odd incl. stf!)
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when s_pgsnd => -- handle pg transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_pgsnd := '0'; -- clear pg transmit request
iout.req := '1'; -- do transmit
iout.stf := '0'; -- signal type = pg
iout.imask := r.pge_pie; -- int enables
iout.bmask := r.pge_pbe; -- boot enables
iout.par := r.pgc_ptp; -- send parity
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when others => null;
end case;
if r.mtc_enmxd = '1' then -- if maintenance mux enabled
iout.stf := r.mtc_mttp; -- force type from mtc_mttp
iout.frm := r.mtc_mfrm; -- force frame from mtc_mfrm
end if;
-- ibus transactions
if r.ibsel = '1' and ibhold='0' then
if IB_MREQ.addr(1 downto 1) = "0" then -- ACR -- access control reg -----
idout(acr_ibf_sid) := SID;
idout(acr_ibf_ac) := r.acr_ac;
if ibw1 = '1' then
if IB_MREQ.din(acr_ibf_clr) = '1' then
n.req_clear := '1';
n.state := s_clear;
end if;
end if;
if ibw0 = '1' then
n.acr_ac := IB_MREQ.din(acr_ibf_ac);
end if;
else -- ADR -- access data reg --------
case r.acr_ac is
when ac_pge => -- PGE -- program gen enables --------
idout(pge_ibf_pbe) := r.pge_pbe;
idout(pge_ibf_pie) := r.pge_pie;
if IB_MREQ.we = '1' then
if r.req_pgsnd = '0' then -- no pg transmit pending
if ibw1 = '1' then
n.pge_pbe := IB_MREQ.din(pge_ibf_pbe);
end if;
if ibw0 = '1' then
n.pge_pie := IB_MREQ.din(pge_ibf_pie);
end if;
else -- if collision with pg transmit
n.pgc_pgrmr := '1'; -- set pge refused flag
end if;
end if;
when ac_pgc => -- PGC -- program gen control/status -
idout(pgc_ibf_err) := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
idout(pgc_ibf_grj) := r.pgc_grj;
idout(pgc_ibf_pgrmr) := r.pgc_pgrmr;
idout(pgc_ibf_strmr) := r.pgc_strmr;
idout(pgc_ibf_rdy) := not r.req_pgsnd;
idout(pgc_ibf_sid) := eff_id;
idout(pgc_ibf_ip) := int_or;
idout(pgc_ibf_ie) := r.pgc_ie;
idout(pgc_ibf_ptp) := r.pgc_ptp;
if ibw1 = '1' then
if IB_MREQ.din(pgc_ibf_err) = '1' then -- '1' written into ERR
n.pgc_grj := '0'; -- clears GRJ
n.pgc_pgrmr := '0'; -- clears PGRMR
n.pgc_strmr := '0'; -- clears STRMR
end if;
end if;
if ibw0 = '1' then
n.pgc_ie := IB_MREQ.din(pgc_ibf_ie);
n.pgc_ptp := IB_MREQ.din(pgc_ibf_ptp);
if IB_MREQ.din(pgc_ibf_go) = '1' then -- GO bit set
if r.req_pgsnd = '0' then -- if ready (no pgsnd pend)
n.req_pgsnd := '1'; -- request pgsnd
else -- if not ready
n.pgc_grj := '1'; -- set go reject flag
end if;
end if;
end if;
when ac_ste => -- STE -- sanity timer enables -------
idout(ste_ibf_sbe) := r.ste_sbe;
idout(ste_ibf_sie) := r.ste_sie;
if IB_MREQ.we = '1' then
if r.req_stsnd = '0' then -- no st transmit pending
if ibw1 = '1' then
n.ste_sbe := IB_MREQ.din(ste_ibf_sbe);
end if;
if ibw0 = '1' then
n.ste_sie := IB_MREQ.din(ste_ibf_sie);
end if;
else -- if collision with st transmit
n.pgc_strmr := '1'; -- set ste refused flag
end if;
end if;
when ac_stc => -- STC -- sanity timer control/status
idout(stc_ibf_count) := r.stc_count;
idout(stc_ibf_tmo) := r.stc_tmo;
idout(stc_ibf_lke) := r.stc_lke;
idout(stc_ibf_stp) := r.stc_stp;
idout(stc_ibf_enb) := r.stc_enb;
if ibw1 = '1' then
n.stc_count := IB_MREQ.din(stc_ibf_count); -- reset st count
n.tcnt256 := (others=>'0'); -- reset usec count
end if;
if ibw0 = '1' then
if IB_MREQ.din(stc_ibf_tmo) = '1' then -- 1 written into TMO
n.stc_tmo := '0';
end if;
n.stc_lke := IB_MREQ.din(stc_ibf_lke);
n.stc_stp := IB_MREQ.din(stc_ibf_stp);
n.stc_enb := IB_MREQ.din(stc_ibf_enb);
end if;
when ac_msk => -- MSK -- input masks ----------------
idout(msk_ibf_bm) := r.msk_bm;
idout(msk_ibf_im) := r.msk_im;
if ibw1 = '1' then
n.msk_bm := IB_MREQ.din(msk_ibf_bm);
end if;
if ibw0 = '1' then
n.msk_im := IB_MREQ.din(msk_ibf_im);
end if;
when ac_pgf => -- PGF -- program generated flags ----
idout(pgf_ibf_pbf) := r.pgf_pbf;
idout(pgf_ibf_pif) := r.pgf_pif;
if ibw1 = '1' then
n.pgf_pbf := r.pgf_pbf and not IB_MREQ.din(pgf_ibf_pbf);
end if;
if ibw0 = '1' then
n.pgf_pif := r.pgf_pif and not IB_MREQ.din(pgf_ibf_pif);
end if;
when ac_stf => -- STF -- sanity timer flags ---------
idout(stf_ibf_sbf) := r.stf_sbf;
idout(stf_ibf_sif) := r.stf_sif;
if ibw1 = '1' then
n.stf_sbf := r.stf_sbf and not IB_MREQ.din(stf_ibf_sbf);
end if;
if ibw0 = '1' then
n.stf_sif := r.stf_sif and not IB_MREQ.din(stf_ibf_sif);
end if;
when ac_dcf => -- DCE -- disconnect flags -----------
idout(dcf_ibf_brk) := r.dcf_brk;
idout(dcf_ibf_dcf) := r.dcf_dcf;
if ibw0 = '1' then
n.dcf_dcf := r.dcf_dcf and not IB_MREQ.din(dcf_ibf_dcf);
end if;
when ac_exc => -- EXC -- exceptions -----------------
idout(exc_ibf_ui) := r.exc_ui;
idout(exc_ibf_rte) := r.exc_rte;
if ibw1 = '1' then
n.exc_ui := r.exc_ui and not IB_MREQ.din(exc_ibf_ui);
end if;
if ibw0 = '1' then
n.exc_rte := r.exc_rte and not IB_MREQ.din(exc_ibf_rte);
end if;
when ac_mtc => -- MTC -- maintenance control --------
idout(mtc_ibf_mttp) := r.mtc_mttp;
idout(mtc_ibf_mfrm) := r.mtc_mfrm;
idout(mtc_ibf_mid) := r.mtc_mid;
idout(mtc_ibf_dsbt) := r.mtc_dsbt;
idout(mtc_ibf_enmxd) := r.mtc_enmxd;
idout(mtc_ibf_enmlp) := r.mtc_enmlp;
idout(mtc_ibf_dsdrv) := r.mtc_dsdrv;
if ibw1 = '1' then
n.mtc_mttp := IB_MREQ.din(mtc_ibf_mttp);
n.mtc_mfrm := IB_MREQ.din(mtc_ibf_mfrm);
n.mtc_mid := IB_MREQ.din(mtc_ibf_mid);
end if;
if ibw0 = '1' then
n.mtc_dsbt := IB_MREQ.din(mtc_ibf_dsbt);
n.mtc_enmxd := IB_MREQ.din(mtc_ibf_enmxd);
n.mtc_enmlp := IB_MREQ.din(mtc_ibf_enmlp);
n.mtc_dsdrv := IB_MREQ.din(mtc_ibf_dsdrv);
end if;
when others => -- access to undefined AC code -------
null;
end case;
if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10
if IB_MREQ.rmw = '0' then -- if not 1st part of rmw
n.acr_ac := slv(unsigned(r.acr_ac) + 1); -- autoincrement
end if;
end if;
end if;
end if;
-- sanity timer
if tcnt256_end = '1' then -- if 256 usec expired (and enabled)
n.stc_count := slv(unsigned(r.stc_count) - 1);
if unsigned(r.stc_count) = 0 then -- if sanity timer expired
n.stc_tmo := '1'; -- set timeout flag
n.req_stsnd := '1'; -- request st transmit
if r.stc_lke = '1' then -- if lockup enabled
n.req_lock := '1'; -- request lockup
end if;
end if;
end if;
-- process iist bus inputs
if r.mtc_enmlp = '1' then -- if mainentance loop
for i in eff_bus'range loop
eff_bus(i) := iout; -- local signal on all input ports
eff_bus(i).dcf := '0'; -- all ports considered connected
end loop; -- i
end if;
for i in eff_bus'range loop
par_err := eff_bus(i).stf xor
eff_bus(i).imask(0) xor eff_bus(i).imask(1) xor
eff_bus(i).imask(2) xor eff_bus(i).imask(3) xor
eff_bus(i).bmask(0) xor eff_bus(i).bmask(1) xor
eff_bus(i).bmask(2) xor eff_bus(i).bmask(3) xor
not eff_bus(i).par;
act_ibit := eff_bus(i).imask(to_integer(unsigned(eff_id)));
act_bbit := eff_bus(i).bmask(to_integer(unsigned(eff_id)));
n.dcf_brk(i) := eff_bus(i).dcf; -- trace dcf state in brk
if eff_bus(i).dcf = '1' then -- if disconnected
if r.msk_im(i) = '0' then -- if not disabled
n.dcf_dcf(i) := '1'; -- set dcf flag
end if;
else -- if connected
if eff_bus(i).req = '1' then -- request received ?
if eff_bus(i).frm='1' or -- frame error seen ?
par_err='1' then -- parity error seen ?
if r.msk_im(i) = '0' then -- if not disabled
n.exc_rte(i) := '1'; -- set rte flag
end if;
else -- here if valid request seen
if act_ibit = '1' then -- interrupt request
if r.msk_im(i) = '1' then -- if disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if enabled
n.req_lock := '0'; -- release lock
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pif(i) := '1'; -- set pif flag
else -- and st request
n.stf_sif(i) := '1'; -- set sif flag
end if;
end if;
end if; -- act_ibit='1'
if act_bbit = '1' then -- boot request
if r.msk_bm(i) = '1' then -- if msk disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if msk enabled
if r.mtc_dsbt = '0' then -- if mtc enabled
n.req_lock := '0'; -- release lock
n.req_boot := '1'; -- request boot
end if;
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pbf(i) := '1'; -- set pbf flag
else -- and st request
n.stf_sbf(i) := '1'; -- set sbf flag
end if;
end if;
end if; -- act_bbit='1'
end if;
end if;
end if;
end loop;
-- process cpu->iist responses
if IIST_SRES.ack_lock = '1' then
n.req_lock := '0';
end if;
if IIST_SRES.ack_boot = '1' then
n.req_boot := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
EI_REQ <= r.pgc_ie and int_or;
if r.mtc_dsdrv = '1' then -- if driver disconnected
iout.dcf := '1'; -- set dcf flag
iout.req := '0'; -- suppress requests
end if;
IIST_OUT <= iout; -- and finally send it out...
IIST_MREQ.lock <= r.req_lock;
IIST_MREQ.boot <= r.req_boot;
end process proc_next;
end syn;
|
gpl-2.0
|
64236ded9b6efb4d7d3b84535a24a20a
| 0.448777 | 3.754988 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd
| 1 | 1,997 |
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-2.0
|
a8a4b0ef09beec2ea0013551e0d9aac9
| 0.645468 | 3.811069 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd
| 1 | 4,623 |
-- $Id: tb_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n2 - sim
-- Description: Test bench for sys_tst_serloop2_n2
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop2_n2 is
end tb_tst_serloop2_n2;
architecture sim of tb_tst_serloop2_n2 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
DCM_H : dcm_sfs
generic map (
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKH,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n2
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
4bd821aeb7bb246575d29724a06c5aec
| 0.524767 | 3.12154 | false | false | false | false |
dumpram/zedboard-ofdm
|
vhdl/dft_in_fsm.vhd
| 1 | 3,123 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity dft_in_fsm is
port (
reset : in std_logic;
clk : in std_logic;
fifo_data : in std_logic_vector(31 downto 0);
fifo_rd_en : out std_logic;
fifo_rd_count : in std_logic_vector(9 downto 0);
dft_data : out std_logic_vector(31 downto 0);
dft_fd_in : out std_logic;
dft_rffd : in std_logic;
dft_data_valid : in std_logic;
fifo_watchdog_reset : out std_logic
);
end dft_in_fsm;
architecture rtl of dft_in_fsm is
constant data_size : integer := 960;
type fsm is (rst, fifo_dft_wait, dft_sample, dft_out_wait);
signal state : fsm := rst;
signal data_cnt : std_logic_vector(16 downto 0);
signal fifo_cnt_prev : std_logic_vector(9 downto 0);
begin
dft_data <= fifo_data;
process(clk)
begin
if (clk'event and clk = '1') then
case state is
when rst =>
fifo_rd_en <= '1';
dft_fd_in <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
state <= fifo_dft_wait;
-- Cekamo popunjavanje FIFO buffera i spremnost DFT-a za prihvat uzoraka
when fifo_dft_wait =>
fifo_rd_en <= '0';
dft_fd_in <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
if (to_integer(unsigned(fifo_rd_count)) < data_size) then
state <= fifo_dft_wait;
-- FIFO ima dovoljno uzoraka; Provjeravamo spremnost DFT-a
elsif (dft_rffd = '0') then
state <= fifo_dft_wait;
else
dft_fd_in <= '1';
fifo_rd_en <= '1';
state <= dft_sample;
end if;
-- Prosljedjujemo uzorke DFT-u
when dft_sample =>
dft_fd_in <= '0';
fifo_rd_en <= '1';
data_cnt <= data_cnt;
if (data_cnt /= (data_cnt'range => '0')) then
data_cnt <= data_cnt - '1';
state <= dft_sample;
else
fifo_rd_en <= '0';
state <= dft_out_wait;
end if;
-- Cekamo dok DFT ne izbaci sve uzorke spektra
when dft_out_wait =>
dft_fd_in <= '0';
fifo_rd_en <= '0';
if (dft_data_valid = '1') then
state <= dft_out_wait;
else
state <= fifo_dft_wait;
end if;
when others =>
null;
end case;
if ( reset = '1') then
state <= rst;
end if;
-- Watchdog control signal
if (fifo_rd_count /= fifo_cnt_prev) then
fifo_watchdog_reset <= '1';
fifo_cnt_prev <= fifo_rd_count;
else
fifo_watchdog_reset <= '0';
fifo_cnt_prev <= fifo_cnt_prev;
end if;
end if;
end process;
end rtl;
|
mit
|
af4a048bdc537b1560eecc2f01690e23
| 0.479987 | 3.520857 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/bp_rs232_4line_iob.vhd
| 2 | 2,770 |
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_4line_iob - syn
-- Description: iob's for 4 line rs232 (RXD,TXD and RTS,CTS)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_ext)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end bp_rs232_4line_iob;
architecture syn of bp_rs232_4line_iob is
begin
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
IOB_CTS : iob_reg_i
port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N);
IOB_RTS : iob_reg_o
port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N);
end syn;
|
gpl-2.0
|
5f533966b21e05e08f188cb0e8392472
| 0.522383 | 3.510773 | false | false | false | false |
unhold/hdl
|
vhdl/pll.vhd
| 1 | 1,494 |
library ieee;
use ieee.std_logic_1164.all;
entity pll is
generic (
multiplier_g : positive;
divider_g : positive);
port (
run_i : in boolean := true;
clock_i : in std_ulogic;
clock_o : out std_ulogic;
lock_o : out std_ulogic);
end;
architecture bhv of pll is
signal pll_clock : std_ulogic := '0';
signal clock_rising, pll_period : delay_length := 1 sec;
begin
measure : process(clock_i)
begin
if rising_edge(clock_i) then
if clock_rising < now then
pll_period <= (now - clock_rising) * divider_g / multiplier_g;
end if;
clock_rising <= now;
end if;
end process;
oscillate : process(pll_period, pll_clock)
begin
if run_i and now > 0 ns then
pll_clock <= transport not pll_clock after pll_period / 2;
end if;
end process;
clock_o <= pll_clock;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tb_pack.all;
entity pll_tb is
end;
architecture tb of pll_tb is
signal clock_time : delay_length := 10 ns;
signal clock_i, clock_o : std_ulogic;
signal run : boolean := true;
begin
pll : entity work.pll(bhv)
generic map (
multiplier_g => 66,
divider_g => 16)
port map (
run_i => run,
clock_i => clock_i,
clock_o => clock_o);
clk_gen(clock_i, run, clock_time);
test : process
begin
clock_time <= 10 ns;
wait for 1 sec;
wait_clk(clock_i, 200);
clock_time <= 1000 ns / 32;
wait_clk(clock_i, 200);
clock_time <= 10 ns;
wait_clk(clock_i, 200);
run <= false;
wait;
end process;
end;
|
gpl-3.0
|
e95f4ac43623381ca9333ff5a17111c1
| 0.647256 | 2.691892 | false | false | false | false |
freecores/w11
|
rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd
| 1 | 17,934 |
-- $Id: fx2_2fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2013-01-04 469 13.3 O76x xc3s1200e-4 112 172 64 169 s 7.4/7.4
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101? 173 64 159 s 8.3/7.4
-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-04 469 1.2 BUGFIX: redo rx logic, now properly pipelined
-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows
-- 2012-01-09 451 1.0 Initial version
-- 2012-01-01 448 0.5 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_ic;
architecture syn of fx2_2fifoctl_ic is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe wait
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp -- s_txdisp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
rxpipe1 : slbit; -- read pipe 1: iob capture stage
rxpipe2 : slbit; -- read pipe 2: fifo write stage
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
'0', -- pepend
'0','0', -- rxpipe1, rxpipe2
ccnt_init, -- ccnt
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS,
FX2_FLAG_N, TXFIFO_VAL, RXSIZE_FX2,
RXFIFO_BUSY, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable pipeok : slbit := '0';
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
n.rxpipe1 := '0';
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and RXFIFO_BUSY='0' then
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
end if;
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_txprep0; -- otherwise switch to tx flow
end if;
-- if more rx to do and possible
elsif slrxok='1' and unsigned(RXSIZE_FX2)>3 then -- !thres must be >3!
islrd := '1';
cc_cnt := '1';
n.rxpipe1 := '1';
if pipeok='1' then
n.state := s_rxdisp; -- 1 cycle read
--n.state := s_rxprep2; -- 2 cycle read
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_idle; -- to idle
end if;
end if;
when s_rxpipe => -- s_rxpipe: read, pipe wait
isloe := '1';
n.state := s_rxprep2;
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
-- rx pipe handling
idata_cei := r.rxpipe1;
n.rxpipe2 := r.rxpipe1;
irxfifo_ena := r.rxpipe2;
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
end if;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
end process proc_next;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
R_MONI_S <= R_MONI_C;
end if;
end if;
end process proc_moni;
proc_almost: process (RXSIZE_USR, TXSIZE_USR)
begin
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
MONI <= R_MONI_S;
end syn;
|
gpl-2.0
|
8e0f62d2641563a784db6000e6117add
| 0.496097 | 3.372955 | false | false | false | false |
superboy0712/MIPS
|
DualPortMem.vhd
| 1 | 7,404 |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:blk_mem_gen:4.3
-- You must compile the wrapper file DualPortMem.vhd when simulating
-- the core, DualPortMem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY DualPortMem IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(7 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0);
clkb: in std_logic;
web: in std_logic_vector(0 downto 0);
addrb: in std_logic_vector(9 downto 0);
dinb: in std_logic_vector(7 downto 0);
doutb: out std_logic_vector(7 downto 0));
END DualPortMem;
ARCHITECTURE DualPortMem_a OF DualPortMem IS
-- synthesis translate_off
component wrapped_DualPortMem
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(7 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0);
clkb: in std_logic;
web: in std_logic_vector(0 downto 0);
addrb: in std_logic_vector(9 downto 0);
dinb: in std_logic_vector(7 downto 0);
doutb: out std_logic_vector(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_DualPortMem use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 2,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 8,
c_initb_val => "0",
c_family => "spartan6",
c_read_width_a => 32,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan6",
c_write_depth_b => 1024,
c_write_depth_a => 256,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 8,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 10,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 8,
c_write_width_a => 32,
c_read_depth_b => 1024,
c_read_depth_a => 256,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DualPortMem
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb);
-- synthesis translate_on
END DualPortMem_a;
|
mit
|
dfaeaa3c55e63a03ac0ea4af95cc939f
| 0.528093 | 3.852237 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/control/input_rom.vhd
| 1 | 84,983 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- if not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : INPUT_ROM.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : INPUT_ROM
-- ARCHITECTURE : rtl
--=============================================================================
-- AUTORS(s) : Agostini, N;
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 14, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- is the to unsigned really required????
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.NN_TYPES_pkg.all;
use work.INPUT_ROM_pkg.all;
--=============================================================================
-- Entity declaration for INPUT_ROM
--=============================================================================
entity INPUT_ROM is
port (
clk : in std_logic;
SAMPLE_NUMBER : in std_logic_vector (7 downto 0);
SELECTED_INPUT : out ARRAY_OF_SFIXED
);
end INPUT_ROM;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture RTL of INPUT_ROM is
-- Constants
constant INPUTS_TABLE : INPUT_TABLE(0 to SAMPLE_SIZE-1) := (
(to_sfixed(0.9595,1,L_SIZE), to_sfixed(0.2948,1,L_SIZE), to_sfixed(0.7523,1,L_SIZE), to_sfixed(0.5200,1,L_SIZE), to_sfixed(0.7840,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.6024,1,L_SIZE), to_sfixed(0.4242,1,L_SIZE), to_sfixed(0.6397,1,L_SIZE), to_sfixed(0.4338,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.9800,1,L_SIZE), to_sfixed(0.6339,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8901,1,L_SIZE), to_sfixed(0.3069,1,L_SIZE), to_sfixed(0.6625,1,L_SIZE), to_sfixed(0.3733,1,L_SIZE), to_sfixed(0.6173,1,L_SIZE), to_sfixed(0.6830,1,L_SIZE), to_sfixed(0.5433,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.3575,1,L_SIZE), to_sfixed(0.3369,1,L_SIZE), to_sfixed(0.6140,1,L_SIZE), to_sfixed(0.8500,1,L_SIZE), to_sfixed(0.6250,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8874,1,L_SIZE), to_sfixed(0.4069,1,L_SIZE), to_sfixed(0.8266,1,L_SIZE), to_sfixed(0.6200,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.6378,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.7849,1,L_SIZE), to_sfixed(0.4369,1,L_SIZE), to_sfixed(0.6023,1,L_SIZE), to_sfixed(0.7925,1,L_SIZE), to_sfixed(0.7054,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9690,1,L_SIZE), to_sfixed(0.3362,1,L_SIZE), to_sfixed(0.7740,1,L_SIZE), to_sfixed(0.5600,1,L_SIZE), to_sfixed(0.6975,1,L_SIZE), to_sfixed(0.9923,1,L_SIZE), to_sfixed(0.6870,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.6089,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.5029,1,L_SIZE), to_sfixed(0.8625,1,L_SIZE), to_sfixed(0.8810,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8928,1,L_SIZE), to_sfixed(0.4466,1,L_SIZE), to_sfixed(0.8885,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.7284,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.5295,1,L_SIZE), to_sfixed(0.5909,1,L_SIZE), to_sfixed(0.5084,1,L_SIZE), to_sfixed(0.3323,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.7325,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9575,1,L_SIZE), to_sfixed(0.3034,1,L_SIZE), to_sfixed(0.7585,1,L_SIZE), to_sfixed(0.5067,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.8428,1,L_SIZE), to_sfixed(0.6673,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.5503,1,L_SIZE), to_sfixed(0.5192,1,L_SIZE), to_sfixed(0.6140,1,L_SIZE), to_sfixed(0.7125,1,L_SIZE), to_sfixed(0.8631,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9703,1,L_SIZE), to_sfixed(0.3224,1,L_SIZE), to_sfixed(0.7585,1,L_SIZE), to_sfixed(0.4867,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.6443,1,L_SIZE), to_sfixed(0.4961,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.5531,1,L_SIZE), to_sfixed(0.4038,1,L_SIZE), to_sfixed(0.5965,1,L_SIZE), to_sfixed(0.8950,1,L_SIZE), to_sfixed(0.7679,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9481,1,L_SIZE), to_sfixed(0.3707,1,L_SIZE), to_sfixed(0.8080,1,L_SIZE), to_sfixed(0.5867,1,L_SIZE), to_sfixed(0.7469,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.4941,1,L_SIZE), to_sfixed(0.4697,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.3885,1,L_SIZE), to_sfixed(0.6199,1,L_SIZE), to_sfixed(0.8950,1,L_SIZE), to_sfixed(0.7708,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.2828,1,L_SIZE), to_sfixed(0.6718,1,L_SIZE), to_sfixed(0.4667,1,L_SIZE), to_sfixed(0.5988,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.5866,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.5531,1,L_SIZE), to_sfixed(0.4000,1,L_SIZE), to_sfixed(0.6316,1,L_SIZE), to_sfixed(0.7125,1,L_SIZE), to_sfixed(0.6220,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9346,1,L_SIZE), to_sfixed(0.2328,1,L_SIZE), to_sfixed(0.7028,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.7680,1,L_SIZE), to_sfixed(0.6201,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.5168,1,L_SIZE), to_sfixed(0.5554,1,L_SIZE), to_sfixed(0.5906,1,L_SIZE), to_sfixed(0.8875,1,L_SIZE), to_sfixed(0.6220,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9508,1,L_SIZE), to_sfixed(0.3724,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.6481,1,L_SIZE), to_sfixed(0.7603,1,L_SIZE), to_sfixed(0.6535,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.6648,1,L_SIZE), to_sfixed(0.4423,1,L_SIZE), to_sfixed(0.7310,1,L_SIZE), to_sfixed(0.7925,1,L_SIZE), to_sfixed(0.8988,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9521,1,L_SIZE), to_sfixed(0.2552,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.5600,1,L_SIZE), to_sfixed(0.5864,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.4783,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.4385,1,L_SIZE), to_sfixed(0.3846,1,L_SIZE), to_sfixed(0.6842,1,L_SIZE), to_sfixed(0.7050,1,L_SIZE), to_sfixed(0.7619,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9272,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.7461,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.5433,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.5056,1,L_SIZE), to_sfixed(0.4308,1,L_SIZE), to_sfixed(0.6725,1,L_SIZE), to_sfixed(0.7250,1,L_SIZE), to_sfixed(0.7857,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9946,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.7399,1,L_SIZE), to_sfixed(0.3800,1,L_SIZE), to_sfixed(0.5617,1,L_SIZE), to_sfixed(0.7990,1,L_SIZE), to_sfixed(0.7264,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.7849,1,L_SIZE), to_sfixed(0.4154,1,L_SIZE), to_sfixed(0.7310,1,L_SIZE), to_sfixed(0.6825,1,L_SIZE), to_sfixed(0.6845,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9697,1,L_SIZE), to_sfixed(0.3224,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.4000,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.8505,1,L_SIZE), to_sfixed(0.7165,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.8268,1,L_SIZE), to_sfixed(0.5769,1,L_SIZE), to_sfixed(0.7018,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.9208,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9191,1,L_SIZE), to_sfixed(0.3121,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.5733,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.7345,1,L_SIZE), to_sfixed(0.5728,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.5615,1,L_SIZE), to_sfixed(0.7485,1,L_SIZE), to_sfixed(0.7200,1,L_SIZE), to_sfixed(0.7798,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9643,1,L_SIZE), to_sfixed(0.3310,1,L_SIZE), to_sfixed(0.8421,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7407,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.6181,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.5503,1,L_SIZE), to_sfixed(0.4769,1,L_SIZE), to_sfixed(0.6257,1,L_SIZE), to_sfixed(0.6625,1,L_SIZE), to_sfixed(0.7619,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9326,1,L_SIZE), to_sfixed(0.2707,1,L_SIZE), to_sfixed(0.8111,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7099,1,L_SIZE), to_sfixed(0.7603,1,L_SIZE), to_sfixed(0.6693,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.4804,1,L_SIZE), to_sfixed(0.5077,1,L_SIZE), to_sfixed(0.6608,1,L_SIZE), to_sfixed(0.6425,1,L_SIZE), to_sfixed(0.6726,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9568,1,L_SIZE), to_sfixed(0.2741,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.5500,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.8505,1,L_SIZE), to_sfixed(0.7736,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.5196,1,L_SIZE), to_sfixed(0.6692,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.7050,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9198,1,L_SIZE), to_sfixed(0.5345,1,L_SIZE), to_sfixed(0.7926,1,L_SIZE), to_sfixed(0.5067,1,L_SIZE), to_sfixed(0.7160,1,L_SIZE), to_sfixed(0.6959,1,L_SIZE), to_sfixed(0.5965,1,L_SIZE), to_sfixed(0.2576,1,L_SIZE), to_sfixed(0.4637,1,L_SIZE), to_sfixed(0.3923,1,L_SIZE), to_sfixed(0.5614,1,L_SIZE), to_sfixed(0.8400,1,L_SIZE), to_sfixed(0.5030,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9481,1,L_SIZE), to_sfixed(0.2810,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.7778,1,L_SIZE), to_sfixed(0.7732,1,L_SIZE), to_sfixed(0.6240,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.5866,1,L_SIZE), to_sfixed(0.4346,1,L_SIZE), to_sfixed(0.6374,1,L_SIZE), to_sfixed(0.9275,1,L_SIZE), to_sfixed(0.4643,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8719,1,L_SIZE), to_sfixed(0.6552,1,L_SIZE), to_sfixed(0.8204,1,L_SIZE), to_sfixed(0.6200,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.6211,1,L_SIZE), to_sfixed(0.4744,1,L_SIZE), to_sfixed(0.3788,1,L_SIZE), to_sfixed(0.5531,1,L_SIZE), to_sfixed(0.3462,1,L_SIZE), to_sfixed(0.6023,1,L_SIZE), to_sfixed(0.8800,1,L_SIZE), to_sfixed(0.4583,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9245,1,L_SIZE), to_sfixed(0.3207,1,L_SIZE), to_sfixed(0.7307,1,L_SIZE), to_sfixed(0.5533,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.6727,1,L_SIZE), to_sfixed(0.5669,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.4721,1,L_SIZE), to_sfixed(0.2923,1,L_SIZE), to_sfixed(0.6491,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.6161,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8665,1,L_SIZE), to_sfixed(0.2759,1,L_SIZE), to_sfixed(0.7802,1,L_SIZE), to_sfixed(0.5933,1,L_SIZE), to_sfixed(0.5864,1,L_SIZE), to_sfixed(0.6392,1,L_SIZE), to_sfixed(0.4665,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.3023,1,L_SIZE), to_sfixed(0.6374,1,L_SIZE), to_sfixed(0.9075,1,L_SIZE), to_sfixed(0.6042,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9103,1,L_SIZE), to_sfixed(0.3121,1,L_SIZE), to_sfixed(0.8080,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.6521,1,L_SIZE), to_sfixed(0.5138,1,L_SIZE), to_sfixed(0.4242,1,L_SIZE), to_sfixed(0.4637,1,L_SIZE), to_sfixed(0.2708,1,L_SIZE), to_sfixed(0.6550,1,L_SIZE), to_sfixed(0.9550,1,L_SIZE), to_sfixed(0.5030,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8800,1,L_SIZE), to_sfixed(0.3534,1,L_SIZE), to_sfixed(0.9969,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.7654,1,L_SIZE), to_sfixed(0.6778,1,L_SIZE), to_sfixed(0.5276,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.5363,1,L_SIZE), to_sfixed(0.2754,1,L_SIZE), to_sfixed(0.6608,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.4940,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9029,1,L_SIZE), to_sfixed(0.3052,1,L_SIZE), to_sfixed(0.8111,1,L_SIZE), to_sfixed(0.5367,1,L_SIZE), to_sfixed(0.5741,1,L_SIZE), to_sfixed(0.7345,1,L_SIZE), to_sfixed(0.5787,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.4050,1,L_SIZE), to_sfixed(0.3692,1,L_SIZE), to_sfixed(0.5380,1,L_SIZE), to_sfixed(0.8050,1,L_SIZE), to_sfixed(0.7113,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8968,1,L_SIZE), to_sfixed(0.2966,1,L_SIZE), to_sfixed(0.6625,1,L_SIZE), to_sfixed(0.5667,1,L_SIZE), to_sfixed(0.5802,1,L_SIZE), to_sfixed(0.6186,1,L_SIZE), to_sfixed(0.4311,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.3038,1,L_SIZE), to_sfixed(0.5965,1,L_SIZE), to_sfixed(0.6925,1,L_SIZE), to_sfixed(0.7649,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9353,1,L_SIZE), to_sfixed(0.3276,1,L_SIZE), to_sfixed(0.8669,1,L_SIZE), to_sfixed(0.6467,1,L_SIZE), to_sfixed(0.6605,1,L_SIZE), to_sfixed(0.7603,1,L_SIZE), to_sfixed(0.5846,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.4916,1,L_SIZE), to_sfixed(0.3462,1,L_SIZE), to_sfixed(0.7310,1,L_SIZE), to_sfixed(0.8500,1,L_SIZE), to_sfixed(0.5446,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9454,1,L_SIZE), to_sfixed(0.2897,1,L_SIZE), to_sfixed(0.6842,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.6830,1,L_SIZE), to_sfixed(0.4587,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.5531,1,L_SIZE), to_sfixed(0.3615,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.8975,1,L_SIZE), to_sfixed(0.6161,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9258,1,L_SIZE), to_sfixed(0.2586,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.7732,1,L_SIZE), to_sfixed(0.6398,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.6648,1,L_SIZE), to_sfixed(0.4385,1,L_SIZE), to_sfixed(0.6959,1,L_SIZE), to_sfixed(0.6775,1,L_SIZE), to_sfixed(0.7649,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9157,1,L_SIZE), to_sfixed(0.2862,1,L_SIZE), to_sfixed(0.7307,1,L_SIZE), to_sfixed(0.6367,1,L_SIZE), to_sfixed(0.6543,1,L_SIZE), to_sfixed(0.7371,1,L_SIZE), to_sfixed(0.6280,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.5447,1,L_SIZE), to_sfixed(0.5308,1,L_SIZE), to_sfixed(0.6374,1,L_SIZE), to_sfixed(0.7200,1,L_SIZE), to_sfixed(0.9018,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9225,1,L_SIZE), to_sfixed(0.3155,1,L_SIZE), to_sfixed(0.7307,1,L_SIZE), to_sfixed(0.5733,1,L_SIZE), to_sfixed(0.6420,1,L_SIZE), to_sfixed(0.6237,1,L_SIZE), to_sfixed(0.5295,1,L_SIZE), to_sfixed(0.6364,1,L_SIZE), to_sfixed(0.5503,1,L_SIZE), to_sfixed(0.2954,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.7175,1,L_SIZE), to_sfixed(0.5893,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9278,1,L_SIZE), to_sfixed(0.2638,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.8148,1,L_SIZE), to_sfixed(0.7603,1,L_SIZE), to_sfixed(0.5394,1,L_SIZE), to_sfixed(0.7576,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.4154,1,L_SIZE), to_sfixed(0.7310,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.7351,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9110,1,L_SIZE), to_sfixed(0.3103,1,L_SIZE), to_sfixed(0.8204,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.6790,1,L_SIZE), to_sfixed(0.6057,1,L_SIZE), to_sfixed(0.4980,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.4302,1,L_SIZE), to_sfixed(0.3231,1,L_SIZE), to_sfixed(0.6433,1,L_SIZE), to_sfixed(0.7175,1,L_SIZE), to_sfixed(0.6518,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9090,1,L_SIZE), to_sfixed(0.3121,1,L_SIZE), to_sfixed(0.7461,1,L_SIZE), to_sfixed(0.6833,1,L_SIZE), to_sfixed(0.6173,1,L_SIZE), to_sfixed(0.6959,1,L_SIZE), to_sfixed(0.5866,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.5196,1,L_SIZE), to_sfixed(0.3923,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.8675,1,L_SIZE), to_sfixed(0.5476,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8955,1,L_SIZE), to_sfixed(0.2828,1,L_SIZE), to_sfixed(0.8793,1,L_SIZE), to_sfixed(0.5167,1,L_SIZE), to_sfixed(0.6790,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.5276,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.3799,1,L_SIZE), to_sfixed(0.3538,1,L_SIZE), to_sfixed(0.6374,1,L_SIZE), to_sfixed(0.6950,1,L_SIZE), to_sfixed(0.5238,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8800,1,L_SIZE), to_sfixed(0.2845,1,L_SIZE), to_sfixed(0.7895,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.6314,1,L_SIZE), to_sfixed(0.4783,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.4022,1,L_SIZE), to_sfixed(0.3269,1,L_SIZE), to_sfixed(0.6550,1,L_SIZE), to_sfixed(0.6275,1,L_SIZE), to_sfixed(0.6577,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8813,1,L_SIZE), to_sfixed(0.2586,1,L_SIZE), to_sfixed(0.6502,1,L_SIZE), to_sfixed(0.5167,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.6186,1,L_SIZE), to_sfixed(0.5197,1,L_SIZE), to_sfixed(0.4242,1,L_SIZE), to_sfixed(0.3827,1,L_SIZE), to_sfixed(0.2846,1,L_SIZE), to_sfixed(0.6901,1,L_SIZE), to_sfixed(0.6725,1,L_SIZE), to_sfixed(0.6071,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9589,1,L_SIZE), to_sfixed(0.6879,1,L_SIZE), to_sfixed(0.7771,1,L_SIZE), to_sfixed(0.4400,1,L_SIZE), to_sfixed(0.7901,1,L_SIZE), to_sfixed(0.7732,1,L_SIZE), to_sfixed(0.5984,1,L_SIZE), to_sfixed(0.3030,1,L_SIZE), to_sfixed(0.5810,1,L_SIZE), to_sfixed(0.3923,1,L_SIZE), to_sfixed(0.5205,1,L_SIZE), to_sfixed(0.8825,1,L_SIZE), to_sfixed(0.4524,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9144,1,L_SIZE), to_sfixed(0.2948,1,L_SIZE), to_sfixed(0.7152,1,L_SIZE), to_sfixed(0.5400,1,L_SIZE), to_sfixed(0.7222,1,L_SIZE), to_sfixed(0.8119,1,L_SIZE), to_sfixed(0.6476,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.6536,1,L_SIZE), to_sfixed(0.4715,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.8450,1,L_SIZE), to_sfixed(0.4732,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9042,1,L_SIZE), to_sfixed(0.6621,1,L_SIZE), to_sfixed(0.6563,1,L_SIZE), to_sfixed(0.6267,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.6314,1,L_SIZE), to_sfixed(0.5276,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.4134,1,L_SIZE), to_sfixed(0.3292,1,L_SIZE), to_sfixed(0.5322,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.6161,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9359,1,L_SIZE), to_sfixed(0.3259,1,L_SIZE), to_sfixed(0.8019,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.8376,1,L_SIZE), to_sfixed(0.7008,1,L_SIZE), to_sfixed(0.2576,1,L_SIZE), to_sfixed(0.4749,1,L_SIZE), to_sfixed(0.4177,1,L_SIZE), to_sfixed(0.5146,1,L_SIZE), to_sfixed(0.8900,1,L_SIZE), to_sfixed(0.6518,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8928,1,L_SIZE), to_sfixed(0.6862,1,L_SIZE), to_sfixed(0.7090,1,L_SIZE), to_sfixed(0.5833,1,L_SIZE), to_sfixed(0.6358,1,L_SIZE), to_sfixed(0.6804,1,L_SIZE), to_sfixed(0.5177,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.4637,1,L_SIZE), to_sfixed(0.3354,1,L_SIZE), to_sfixed(0.4795,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.4048,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8800,1,L_SIZE), to_sfixed(0.3052,1,L_SIZE), to_sfixed(0.6502,1,L_SIZE), to_sfixed(0.5667,1,L_SIZE), to_sfixed(0.6605,1,L_SIZE), to_sfixed(0.7732,1,L_SIZE), to_sfixed(0.5906,1,L_SIZE), to_sfixed(0.4242,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.3877,1,L_SIZE), to_sfixed(0.5146,1,L_SIZE), to_sfixed(0.8375,1,L_SIZE), to_sfixed(0.5268,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9582,1,L_SIZE), to_sfixed(0.6966,1,L_SIZE), to_sfixed(0.7554,1,L_SIZE), to_sfixed(0.6300,1,L_SIZE), to_sfixed(0.6852,1,L_SIZE), to_sfixed(0.7345,1,L_SIZE), to_sfixed(0.5217,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.4031,1,L_SIZE), to_sfixed(0.5088,1,L_SIZE), to_sfixed(0.8325,1,L_SIZE), to_sfixed(0.6429,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9697,1,L_SIZE), to_sfixed(0.6190,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.8376,1,L_SIZE), to_sfixed(0.6240,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.6117,1,L_SIZE), to_sfixed(0.3769,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.8600,1,L_SIZE), to_sfixed(0.6339,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9373,1,L_SIZE), to_sfixed(0.2897,1,L_SIZE), to_sfixed(0.6563,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.7990,1,L_SIZE), to_sfixed(0.6673,1,L_SIZE), to_sfixed(0.3182,1,L_SIZE), to_sfixed(0.5978,1,L_SIZE), to_sfixed(0.4692,1,L_SIZE), to_sfixed(0.5322,1,L_SIZE), to_sfixed(0.8325,1,L_SIZE), to_sfixed(0.5863,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9508,1,L_SIZE), to_sfixed(0.3483,1,L_SIZE), to_sfixed(0.7430,1,L_SIZE), to_sfixed(0.6267,1,L_SIZE), to_sfixed(0.6358,1,L_SIZE), to_sfixed(0.7088,1,L_SIZE), to_sfixed(0.5748,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.6648,1,L_SIZE), to_sfixed(0.4769,1,L_SIZE), to_sfixed(0.6257,1,L_SIZE), to_sfixed(0.6875,1,L_SIZE), to_sfixed(0.6310,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9400,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.7028,1,L_SIZE), to_sfixed(0.5800,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7423,1,L_SIZE), to_sfixed(0.6969,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.5810,1,L_SIZE), to_sfixed(0.6846,1,L_SIZE), to_sfixed(0.6550,1,L_SIZE), to_sfixed(0.7750,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8800,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.6316,1,L_SIZE), to_sfixed(0.4133,1,L_SIZE), to_sfixed(0.5679,1,L_SIZE), to_sfixed(0.7010,1,L_SIZE), to_sfixed(0.6437,1,L_SIZE), to_sfixed(0.2576,1,L_SIZE), to_sfixed(0.8128,1,L_SIZE), to_sfixed(0.5538,1,L_SIZE), to_sfixed(0.6550,1,L_SIZE), to_sfixed(0.7275,1,L_SIZE), to_sfixed(0.6845,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9326,1,L_SIZE), to_sfixed(0.2845,1,L_SIZE), to_sfixed(0.8050,1,L_SIZE), to_sfixed(0.5733,1,L_SIZE), to_sfixed(0.5802,1,L_SIZE), to_sfixed(0.6314,1,L_SIZE), to_sfixed(0.5886,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.6397,1,L_SIZE), to_sfixed(0.4308,1,L_SIZE), to_sfixed(0.7251,1,L_SIZE), to_sfixed(0.8425,1,L_SIZE), to_sfixed(0.7530,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9319,1,L_SIZE), to_sfixed(0.3017,1,L_SIZE), to_sfixed(0.7492,1,L_SIZE), to_sfixed(0.4667,1,L_SIZE), to_sfixed(0.6852,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.7362,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.5223,1,L_SIZE), to_sfixed(0.5423,1,L_SIZE), to_sfixed(0.5906,1,L_SIZE), to_sfixed(0.8150,1,L_SIZE), to_sfixed(0.7083,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9285,1,L_SIZE), to_sfixed(0.3276,1,L_SIZE), to_sfixed(0.8297,1,L_SIZE), to_sfixed(0.5700,1,L_SIZE), to_sfixed(0.7099,1,L_SIZE), to_sfixed(0.7732,1,L_SIZE), to_sfixed(0.5492,1,L_SIZE), to_sfixed(0.5909,1,L_SIZE), to_sfixed(0.4693,1,L_SIZE), to_sfixed(0.4846,1,L_SIZE), to_sfixed(0.6608,1,L_SIZE), to_sfixed(0.7325,1,L_SIZE), to_sfixed(0.8185,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9265,1,L_SIZE), to_sfixed(0.2879,1,L_SIZE), to_sfixed(0.6966,1,L_SIZE), to_sfixed(0.5467,1,L_SIZE), to_sfixed(0.7284,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.5709,1,L_SIZE), to_sfixed(0.3182,1,L_SIZE), to_sfixed(0.4525,1,L_SIZE), to_sfixed(0.4500,1,L_SIZE), to_sfixed(0.5380,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.6310,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9144,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.7616,1,L_SIZE), to_sfixed(0.6833,1,L_SIZE), to_sfixed(0.7160,1,L_SIZE), to_sfixed(0.7629,1,L_SIZE), to_sfixed(0.5472,1,L_SIZE), to_sfixed(0.3030,1,L_SIZE), to_sfixed(0.6844,1,L_SIZE), to_sfixed(0.4808,1,L_SIZE), to_sfixed(0.5731,1,L_SIZE), to_sfixed(0.7575,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9589,1,L_SIZE), to_sfixed(0.2931,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.5433,1,L_SIZE), to_sfixed(0.7284,1,L_SIZE), to_sfixed(0.8247,1,L_SIZE), to_sfixed(0.5906,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.4908,1,L_SIZE), to_sfixed(0.5497,1,L_SIZE), to_sfixed(0.8275,1,L_SIZE), to_sfixed(0.5774,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8962,1,L_SIZE), to_sfixed(0.3397,1,L_SIZE), to_sfixed(0.8297,1,L_SIZE), to_sfixed(0.5600,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.7732,1,L_SIZE), to_sfixed(0.6358,1,L_SIZE), to_sfixed(0.4697,1,L_SIZE), to_sfixed(0.4637,1,L_SIZE), to_sfixed(0.4615,1,L_SIZE), to_sfixed(0.6257,1,L_SIZE), to_sfixed(0.7100,1,L_SIZE), to_sfixed(0.7560,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9252,1,L_SIZE), to_sfixed(0.2466,1,L_SIZE), to_sfixed(0.7740,1,L_SIZE), to_sfixed(0.5567,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.8763,1,L_SIZE), to_sfixed(0.7224,1,L_SIZE), to_sfixed(0.2879,1,L_SIZE), to_sfixed(0.5698,1,L_SIZE), to_sfixed(0.5231,1,L_SIZE), to_sfixed(0.5205,1,L_SIZE), to_sfixed(0.7175,1,L_SIZE), to_sfixed(0.7649,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8341,1,L_SIZE), to_sfixed(0.1621,1,L_SIZE), to_sfixed(0.4211,1,L_SIZE), to_sfixed(0.3533,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.5103,1,L_SIZE), to_sfixed(0.1122,1,L_SIZE), to_sfixed(0.4242,1,L_SIZE), to_sfixed(0.1173,1,L_SIZE), to_sfixed(0.1500,1,L_SIZE), to_sfixed(0.6140,1,L_SIZE), to_sfixed(0.4550,1,L_SIZE), to_sfixed(0.3095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8314,1,L_SIZE), to_sfixed(0.1897,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.5284,1,L_SIZE), to_sfixed(0.2146,1,L_SIZE), to_sfixed(0.9545,1,L_SIZE), to_sfixed(0.1145,1,L_SIZE), to_sfixed(0.2515,1,L_SIZE), to_sfixed(0.7310,1,L_SIZE), to_sfixed(0.4175,1,L_SIZE), to_sfixed(0.4048,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8523,1,L_SIZE), to_sfixed(0.2345,1,L_SIZE), to_sfixed(0.6254,1,L_SIZE), to_sfixed(0.5600,1,L_SIZE), to_sfixed(0.6173,1,L_SIZE), to_sfixed(0.5206,1,L_SIZE), to_sfixed(0.2776,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.1732,1,L_SIZE), to_sfixed(0.4423,1,L_SIZE), to_sfixed(0.5731,1,L_SIZE), to_sfixed(0.3975,1,L_SIZE), to_sfixed(0.2679,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9218,1,L_SIZE), to_sfixed(0.2155,1,L_SIZE), to_sfixed(0.5944,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.5802,1,L_SIZE), to_sfixed(0.5412,1,L_SIZE), to_sfixed(0.3524,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.2039,1,L_SIZE), to_sfixed(0.2923,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.6150,1,L_SIZE), to_sfixed(0.3750,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8341,1,L_SIZE), to_sfixed(0.1948,1,L_SIZE), to_sfixed(0.6687,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.5370,1,L_SIZE), to_sfixed(0.9021,1,L_SIZE), to_sfixed(0.6102,1,L_SIZE), to_sfixed(0.2879,1,L_SIZE), to_sfixed(0.5223,1,L_SIZE), to_sfixed(0.3423,1,L_SIZE), to_sfixed(0.7135,1,L_SIZE), to_sfixed(0.7175,1,L_SIZE), to_sfixed(0.2500,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8206,1,L_SIZE), to_sfixed(0.2500,1,L_SIZE), to_sfixed(0.7833,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.6420,1,L_SIZE), to_sfixed(0.4871,1,L_SIZE), to_sfixed(0.3445,1,L_SIZE), to_sfixed(0.6818,1,L_SIZE), to_sfixed(0.2877,1,L_SIZE), to_sfixed(0.2269,1,L_SIZE), to_sfixed(0.8480,1,L_SIZE), to_sfixed(0.5575,1,L_SIZE), to_sfixed(0.2113,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8341,1,L_SIZE), to_sfixed(0.2086,1,L_SIZE), to_sfixed(0.7926,1,L_SIZE), to_sfixed(0.6033,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.6237,1,L_SIZE), to_sfixed(0.5217,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.5810,1,L_SIZE), to_sfixed(0.3538,1,L_SIZE), to_sfixed(0.6959,1,L_SIZE), to_sfixed(0.5750,1,L_SIZE), to_sfixed(0.4036,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8840,1,L_SIZE), to_sfixed(0.1741,1,L_SIZE), to_sfixed(0.5263,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.4815,1,L_SIZE), to_sfixed(0.7680,1,L_SIZE), to_sfixed(0.6260,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.6369,1,L_SIZE), to_sfixed(0.4077,1,L_SIZE), to_sfixed(0.6550,1,L_SIZE), to_sfixed(0.7950,1,L_SIZE), to_sfixed(0.2988,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8341,1,L_SIZE), to_sfixed(0.2017,1,L_SIZE), to_sfixed(0.5944,1,L_SIZE), to_sfixed(0.6533,1,L_SIZE), to_sfixed(0.4815,1,L_SIZE), to_sfixed(0.5438,1,L_SIZE), to_sfixed(0.3937,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.2905,1,L_SIZE), to_sfixed(0.3600,1,L_SIZE), to_sfixed(0.6550,1,L_SIZE), to_sfixed(0.8700,1,L_SIZE), to_sfixed(0.3036,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8995,1,L_SIZE), to_sfixed(0.1621,1,L_SIZE), to_sfixed(0.7307,1,L_SIZE), to_sfixed(0.5667,1,L_SIZE), to_sfixed(0.6790,1,L_SIZE), to_sfixed(0.6521,1,L_SIZE), to_sfixed(0.2559,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.1173,1,L_SIZE), to_sfixed(0.2438,1,L_SIZE), to_sfixed(0.5965,1,L_SIZE), to_sfixed(0.4825,1,L_SIZE), to_sfixed(0.4464,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8233,1,L_SIZE), to_sfixed(0.2052,1,L_SIZE), to_sfixed(0.5418,1,L_SIZE), to_sfixed(0.5600,1,L_SIZE), to_sfixed(0.9321,1,L_SIZE), to_sfixed(0.4768,1,L_SIZE), to_sfixed(0.2520,1,L_SIZE), to_sfixed(0.2121,1,L_SIZE), to_sfixed(0.6983,1,L_SIZE), to_sfixed(0.2192,1,L_SIZE), to_sfixed(0.7485,1,L_SIZE), to_sfixed(0.7675,1,L_SIZE), to_sfixed(0.4274,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8287,1,L_SIZE), to_sfixed(0.2776,1,L_SIZE), to_sfixed(0.6842,1,L_SIZE), to_sfixed(0.6800,1,L_SIZE), to_sfixed(0.6358,1,L_SIZE), to_sfixed(0.2835,1,L_SIZE), to_sfixed(0.2008,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.2346,1,L_SIZE), to_sfixed(0.5298,1,L_SIZE), to_sfixed(0.4550,1,L_SIZE), to_sfixed(0.5179,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9346,1,L_SIZE), to_sfixed(0.2603,1,L_SIZE), to_sfixed(0.8266,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.7603,1,L_SIZE), to_sfixed(0.5630,1,L_SIZE), to_sfixed(0.3182,1,L_SIZE), to_sfixed(0.5223,1,L_SIZE), to_sfixed(0.2600,1,L_SIZE), to_sfixed(0.7953,1,L_SIZE), to_sfixed(0.7900,1,L_SIZE), to_sfixed(0.2440,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.9096,1,L_SIZE), to_sfixed(0.2862,1,L_SIZE), to_sfixed(0.6935,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.5370,1,L_SIZE), to_sfixed(0.4845,1,L_SIZE), to_sfixed(0.3622,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.2877,1,L_SIZE), to_sfixed(0.2877,1,L_SIZE), to_sfixed(0.5731,1,L_SIZE), to_sfixed(0.6950,1,L_SIZE), to_sfixed(0.2810,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8759,1,L_SIZE), to_sfixed(0.2879,1,L_SIZE), to_sfixed(0.8050,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.8580,1,L_SIZE), to_sfixed(0.8505,1,L_SIZE), to_sfixed(0.5689,1,L_SIZE), to_sfixed(0.3182,1,L_SIZE), to_sfixed(0.5475,1,L_SIZE), to_sfixed(0.2577,1,L_SIZE), to_sfixed(0.7661,1,L_SIZE), to_sfixed(0.8750,1,L_SIZE), to_sfixed(0.5863,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8065,1,L_SIZE), to_sfixed(0.1879,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.8711,1,L_SIZE), to_sfixed(0.4213,1,L_SIZE), to_sfixed(0.1970,1,L_SIZE), to_sfixed(0.4609,1,L_SIZE), to_sfixed(0.2469,1,L_SIZE), to_sfixed(0.5789,1,L_SIZE), to_sfixed(0.7825,1,L_SIZE), to_sfixed(0.5274,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7862,1,L_SIZE), to_sfixed(0.3241,1,L_SIZE), to_sfixed(0.5944,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.5988,1,L_SIZE), to_sfixed(0.4149,1,L_SIZE), to_sfixed(0.3091,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.3212,1,L_SIZE), to_sfixed(0.2923,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.5350,1,L_SIZE), to_sfixed(0.2548,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8786,1,L_SIZE), to_sfixed(0.1552,1,L_SIZE), to_sfixed(0.5294,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.5026,1,L_SIZE), to_sfixed(0.3996,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.3538,1,L_SIZE), to_sfixed(0.6959,1,L_SIZE), to_sfixed(0.6200,1,L_SIZE), to_sfixed(0.2333,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7984,1,L_SIZE), to_sfixed(0.4983,1,L_SIZE), to_sfixed(0.6904,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.4433,1,L_SIZE), to_sfixed(0.2598,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.2654,1,L_SIZE), to_sfixed(0.2038,1,L_SIZE), to_sfixed(0.5614,1,L_SIZE), to_sfixed(0.6300,1,L_SIZE), to_sfixed(0.2976,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8314,1,L_SIZE), to_sfixed(0.1707,1,L_SIZE), to_sfixed(0.6037,1,L_SIZE), to_sfixed(0.4933,1,L_SIZE), to_sfixed(0.8395,1,L_SIZE), to_sfixed(0.4897,1,L_SIZE), to_sfixed(0.3642,1,L_SIZE), to_sfixed(0.5303,1,L_SIZE), to_sfixed(0.7709,1,L_SIZE), to_sfixed(0.2615,1,L_SIZE), to_sfixed(0.6199,1,L_SIZE), to_sfixed(0.5775,1,L_SIZE), to_sfixed(0.4464,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8564,1,L_SIZE), to_sfixed(0.6672,1,L_SIZE), to_sfixed(0.7430,1,L_SIZE), to_sfixed(0.7667,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.7294,1,L_SIZE), to_sfixed(0.5020,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.5447,1,L_SIZE), to_sfixed(0.1977,1,L_SIZE), to_sfixed(0.6959,1,L_SIZE), to_sfixed(0.7825,1,L_SIZE), to_sfixed(0.2756,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8092,1,L_SIZE), to_sfixed(0.1586,1,L_SIZE), to_sfixed(0.6192,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.6237,1,L_SIZE), to_sfixed(0.4449,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.3994,1,L_SIZE), to_sfixed(0.1923,1,L_SIZE), to_sfixed(0.8070,1,L_SIZE), to_sfixed(0.7800,1,L_SIZE), to_sfixed(0.1655,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8577,1,L_SIZE), to_sfixed(0.3121,1,L_SIZE), to_sfixed(0.6811,1,L_SIZE), to_sfixed(0.6267,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.4980,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.4944,1,L_SIZE), to_sfixed(0.3000,1,L_SIZE), to_sfixed(0.6784,1,L_SIZE), to_sfixed(0.7850,1,L_SIZE), to_sfixed(0.4250,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8146,1,L_SIZE), to_sfixed(0.1948,1,L_SIZE), to_sfixed(0.7771,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.4815,1,L_SIZE), to_sfixed(0.5155,1,L_SIZE), to_sfixed(0.3110,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.3911,1,L_SIZE), to_sfixed(0.1692,1,L_SIZE), to_sfixed(0.7661,1,L_SIZE), to_sfixed(0.6800,1,L_SIZE), to_sfixed(0.3750,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8800,1,L_SIZE), to_sfixed(0.6655,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.5247,1,L_SIZE), to_sfixed(0.4253,1,L_SIZE), to_sfixed(0.3130,1,L_SIZE), to_sfixed(0.9242,1,L_SIZE), to_sfixed(0.4525,1,L_SIZE), to_sfixed(0.3692,1,L_SIZE), to_sfixed(0.4912,1,L_SIZE), to_sfixed(0.5025,1,L_SIZE), to_sfixed(0.3065,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7984,1,L_SIZE), to_sfixed(0.1534,1,L_SIZE), to_sfixed(0.7988,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.5802,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.4350,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.6564,1,L_SIZE), to_sfixed(0.2346,1,L_SIZE), to_sfixed(0.4620,1,L_SIZE), to_sfixed(0.7700,1,L_SIZE), to_sfixed(0.3095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8543,1,L_SIZE), to_sfixed(0.1690,1,L_SIZE), to_sfixed(0.6935,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.6111,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.3819,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.2015,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.7900,1,L_SIZE), to_sfixed(0.2679,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8200,1,L_SIZE), to_sfixed(0.2776,1,L_SIZE), to_sfixed(0.7152,1,L_SIZE), to_sfixed(0.7600,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.4588,1,L_SIZE), to_sfixed(0.3327,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.4358,1,L_SIZE), to_sfixed(0.1885,1,L_SIZE), to_sfixed(0.7778,1,L_SIZE), to_sfixed(0.5650,1,L_SIZE), to_sfixed(0.2946,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7856,1,L_SIZE), to_sfixed(0.2879,1,L_SIZE), to_sfixed(0.8111,1,L_SIZE), to_sfixed(0.8667,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.4948,1,L_SIZE), to_sfixed(0.3169,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.3743,1,L_SIZE), to_sfixed(0.2000,1,L_SIZE), to_sfixed(0.7953,1,L_SIZE), to_sfixed(0.8025,1,L_SIZE), to_sfixed(0.3345,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7849,1,L_SIZE), to_sfixed(0.3552,1,L_SIZE), to_sfixed(0.7616,1,L_SIZE), to_sfixed(0.7200,1,L_SIZE), to_sfixed(0.5185,1,L_SIZE), to_sfixed(0.5026,1,L_SIZE), to_sfixed(0.3327,1,L_SIZE), to_sfixed(0.7273,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.2154,1,L_SIZE), to_sfixed(0.5848,1,L_SIZE), to_sfixed(0.6875,1,L_SIZE), to_sfixed(0.4048,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8146,1,L_SIZE), to_sfixed(0.2293,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.7867,1,L_SIZE), to_sfixed(0.4321,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.3130,1,L_SIZE), to_sfixed(0.6364,1,L_SIZE), to_sfixed(0.3855,1,L_SIZE), to_sfixed(0.1338,1,L_SIZE), to_sfixed(0.6257,1,L_SIZE), to_sfixed(0.8025,1,L_SIZE), to_sfixed(0.3720,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8146,1,L_SIZE), to_sfixed(0.3155,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.4124,1,L_SIZE), to_sfixed(0.2953,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.4581,1,L_SIZE), to_sfixed(0.1846,1,L_SIZE), to_sfixed(0.6316,1,L_SIZE), to_sfixed(0.5675,1,L_SIZE), to_sfixed(0.2857,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8092,1,L_SIZE), to_sfixed(0.2603,1,L_SIZE), to_sfixed(0.7492,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.3737,1,L_SIZE), to_sfixed(0.2461,1,L_SIZE), to_sfixed(0.7576,1,L_SIZE), to_sfixed(0.4553,1,L_SIZE), to_sfixed(0.2769,1,L_SIZE), to_sfixed(0.6140,1,L_SIZE), to_sfixed(0.6625,1,L_SIZE), to_sfixed(0.2679,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8557,1,L_SIZE), to_sfixed(0.2638,1,L_SIZE), to_sfixed(0.6997,1,L_SIZE), to_sfixed(0.6900,1,L_SIZE), to_sfixed(0.4938,1,L_SIZE), to_sfixed(0.3557,1,L_SIZE), to_sfixed(0.2874,1,L_SIZE), to_sfixed(0.8788,1,L_SIZE), to_sfixed(0.4525,1,L_SIZE), to_sfixed(0.2346,1,L_SIZE), to_sfixed(0.5614,1,L_SIZE), to_sfixed(0.5150,1,L_SIZE), to_sfixed(0.2946,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8287,1,L_SIZE), to_sfixed(0.4879,1,L_SIZE), to_sfixed(0.6873,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.6314,1,L_SIZE), to_sfixed(0.4429,1,L_SIZE), to_sfixed(0.3788,1,L_SIZE), to_sfixed(0.5559,1,L_SIZE), to_sfixed(0.1654,1,L_SIZE), to_sfixed(0.6725,1,L_SIZE), to_sfixed(0.8250,1,L_SIZE), to_sfixed(0.1726,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7835,1,L_SIZE), to_sfixed(0.3431,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.7784,1,L_SIZE), to_sfixed(0.4449,1,L_SIZE), to_sfixed(0.2576,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.2500,1,L_SIZE), to_sfixed(0.6784,1,L_SIZE), to_sfixed(0.7400,1,L_SIZE), to_sfixed(0.2054,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8409,1,L_SIZE), to_sfixed(0.2621,1,L_SIZE), to_sfixed(0.6811,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.6443,1,L_SIZE), to_sfixed(0.4469,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.9162,1,L_SIZE), to_sfixed(0.2000,1,L_SIZE), to_sfixed(0.6784,1,L_SIZE), to_sfixed(0.6575,1,L_SIZE), to_sfixed(0.5577,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7964,1,L_SIZE), to_sfixed(0.3655,1,L_SIZE), to_sfixed(0.8483,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.8272,1,L_SIZE), to_sfixed(0.4124,1,L_SIZE), to_sfixed(0.1949,1,L_SIZE), to_sfixed(0.2121,1,L_SIZE), to_sfixed(0.4358,1,L_SIZE), to_sfixed(0.1923,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.5650,1,L_SIZE), to_sfixed(0.3720,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8287,1,L_SIZE), to_sfixed(0.2431,1,L_SIZE), to_sfixed(0.6130,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.5247,1,L_SIZE), to_sfixed(0.6572,1,L_SIZE), to_sfixed(0.4921,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.4944,1,L_SIZE), to_sfixed(0.2231,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.6850,1,L_SIZE), to_sfixed(0.2548,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8341,1,L_SIZE), to_sfixed(0.1845,1,L_SIZE), to_sfixed(0.6502,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.9072,1,L_SIZE), to_sfixed(0.7382,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.5447,1,L_SIZE), to_sfixed(0.3462,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.6925,1,L_SIZE), to_sfixed(0.3929,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8287,1,L_SIZE), to_sfixed(0.5466,1,L_SIZE), to_sfixed(0.6842,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.7345,1,L_SIZE), to_sfixed(0.5886,1,L_SIZE), to_sfixed(0.6818,1,L_SIZE), to_sfixed(0.7849,1,L_SIZE), to_sfixed(0.1769,1,L_SIZE), to_sfixed(0.8304,1,L_SIZE), to_sfixed(0.7075,1,L_SIZE), to_sfixed(0.2417,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8146,1,L_SIZE), to_sfixed(0.3586,1,L_SIZE), to_sfixed(0.5263,1,L_SIZE), to_sfixed(0.5833,1,L_SIZE), to_sfixed(0.5988,1,L_SIZE), to_sfixed(0.5747,1,L_SIZE), to_sfixed(0.4272,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.3911,1,L_SIZE), to_sfixed(0.2538,1,L_SIZE), to_sfixed(0.7427,1,L_SIZE), to_sfixed(0.7400,1,L_SIZE), to_sfixed(0.4226,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8496,1,L_SIZE), to_sfixed(0.2310,1,L_SIZE), to_sfixed(0.5882,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.3737,1,L_SIZE), to_sfixed(0.2677,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.1885,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.6925,1,L_SIZE), to_sfixed(0.3345,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8321,1,L_SIZE), to_sfixed(0.4224,1,L_SIZE), to_sfixed(0.7616,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.6598,1,L_SIZE), to_sfixed(0.4154,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.3659,1,L_SIZE), to_sfixed(0.2154,1,L_SIZE), to_sfixed(0.4678,1,L_SIZE), to_sfixed(0.8450,1,L_SIZE), to_sfixed(0.2607,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7970,1,L_SIZE), to_sfixed(0.2966,1,L_SIZE), to_sfixed(0.5820,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.6443,1,L_SIZE), to_sfixed(0.3228,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.3966,1,L_SIZE), to_sfixed(0.1585,1,L_SIZE), to_sfixed(0.5497,1,L_SIZE), to_sfixed(0.6100,1,L_SIZE), to_sfixed(0.2470,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8436,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.6130,1,L_SIZE), to_sfixed(0.6833,1,L_SIZE), to_sfixed(0.5247,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.3780,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.4134,1,L_SIZE), to_sfixed(0.2262,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.8925,1,L_SIZE), to_sfixed(0.4000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8375,1,L_SIZE), to_sfixed(0.4397,1,L_SIZE), to_sfixed(0.7028,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.4330,1,L_SIZE), to_sfixed(0.3622,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.3966,1,L_SIZE), to_sfixed(0.2077,1,L_SIZE), to_sfixed(0.5029,1,L_SIZE), to_sfixed(0.8250,1,L_SIZE), to_sfixed(0.1875,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8260,1,L_SIZE), to_sfixed(0.2983,1,L_SIZE), to_sfixed(0.6563,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.4938,1,L_SIZE), to_sfixed(0.4253,1,L_SIZE), to_sfixed(0.3996,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.4553,1,L_SIZE), to_sfixed(0.2615,1,L_SIZE), to_sfixed(0.5848,1,L_SIZE), to_sfixed(0.7925,1,L_SIZE), to_sfixed(0.3036,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8577,1,L_SIZE), to_sfixed(0.3017,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.5185,1,L_SIZE), to_sfixed(0.3557,1,L_SIZE), to_sfixed(0.3465,1,L_SIZE), to_sfixed(0.7273,1,L_SIZE), to_sfixed(0.4553,1,L_SIZE), to_sfixed(0.2538,1,L_SIZE), to_sfixed(0.5146,1,L_SIZE), to_sfixed(0.6050,1,L_SIZE), to_sfixed(0.2905,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8240,1,L_SIZE), to_sfixed(0.2224,1,L_SIZE), to_sfixed(0.6006,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.5679,1,L_SIZE), to_sfixed(0.6082,1,L_SIZE), to_sfixed(0.4016,1,L_SIZE), to_sfixed(0.5909,1,L_SIZE), to_sfixed(0.5810,1,L_SIZE), to_sfixed(0.2077,1,L_SIZE), to_sfixed(0.5029,1,L_SIZE), to_sfixed(0.7550,1,L_SIZE), to_sfixed(0.1857,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7829,1,L_SIZE), to_sfixed(0.2328,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5802,1,L_SIZE), to_sfixed(0.7062,1,L_SIZE), to_sfixed(0.5748,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.6955,1,L_SIZE), to_sfixed(0.2038,1,L_SIZE), to_sfixed(0.5614,1,L_SIZE), to_sfixed(0.8150,1,L_SIZE), to_sfixed(0.4048,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7728,1,L_SIZE), to_sfixed(0.6448,1,L_SIZE), to_sfixed(0.5635,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.6605,1,L_SIZE), to_sfixed(0.8196,1,L_SIZE), to_sfixed(0.5079,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.2231,1,L_SIZE), to_sfixed(0.4386,1,L_SIZE), to_sfixed(0.7025,1,L_SIZE), to_sfixed(0.3345,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8442,1,L_SIZE), to_sfixed(0.4190,1,L_SIZE), to_sfixed(0.6718,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.6572,1,L_SIZE), to_sfixed(0.4469,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.3408,1,L_SIZE), to_sfixed(0.1538,1,L_SIZE), to_sfixed(0.5263,1,L_SIZE), to_sfixed(0.6950,1,L_SIZE), to_sfixed(0.1935,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7930,1,L_SIZE), to_sfixed(0.4621,1,L_SIZE), to_sfixed(0.9040,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.6358,1,L_SIZE), to_sfixed(0.4510,1,L_SIZE), to_sfixed(0.3996,1,L_SIZE), to_sfixed(0.9091,1,L_SIZE), to_sfixed(0.2933,1,L_SIZE), to_sfixed(0.2923,1,L_SIZE), to_sfixed(0.7193,1,L_SIZE), to_sfixed(0.6250,1,L_SIZE), to_sfixed(0.3613,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7694,1,L_SIZE), to_sfixed(0.1276,1,L_SIZE), to_sfixed(0.7740,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.6392,1,L_SIZE), to_sfixed(0.3957,1,L_SIZE), to_sfixed(0.6364,1,L_SIZE), to_sfixed(0.4022,1,L_SIZE), to_sfixed(0.2369,1,L_SIZE), to_sfixed(0.6433,1,L_SIZE), to_sfixed(0.5775,1,L_SIZE), to_sfixed(0.2583,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8146,1,L_SIZE), to_sfixed(0.2397,1,L_SIZE), to_sfixed(0.7740,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.5185,1,L_SIZE), to_sfixed(0.6598,1,L_SIZE), to_sfixed(0.4508,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.2905,1,L_SIZE), to_sfixed(0.2231,1,L_SIZE), to_sfixed(0.5439,1,L_SIZE), to_sfixed(0.7975,1,L_SIZE), to_sfixed(0.2292,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7438,1,L_SIZE), to_sfixed(0.2603,1,L_SIZE), to_sfixed(0.6811,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.5247,1,L_SIZE), to_sfixed(0.6340,1,L_SIZE), to_sfixed(0.4272,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.5615,1,L_SIZE), to_sfixed(0.1462,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.7175,1,L_SIZE), to_sfixed(0.2423,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7970,1,L_SIZE), to_sfixed(0.2534,1,L_SIZE), to_sfixed(0.6161,1,L_SIZE), to_sfixed(0.6933,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.5103,1,L_SIZE), to_sfixed(0.3150,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.4274,1,L_SIZE), to_sfixed(0.1500,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.8325,1,L_SIZE), to_sfixed(0.2946,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8375,1,L_SIZE), to_sfixed(0.2776,1,L_SIZE), to_sfixed(0.6780,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5155,1,L_SIZE), to_sfixed(0.4114,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.4497,1,L_SIZE), to_sfixed(0.1585,1,L_SIZE), to_sfixed(0.6199,1,L_SIZE), to_sfixed(0.7400,1,L_SIZE), to_sfixed(0.2054,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8611,1,L_SIZE), to_sfixed(0.5914,1,L_SIZE), to_sfixed(0.6130,1,L_SIZE), to_sfixed(0.5333,1,L_SIZE), to_sfixed(0.4938,1,L_SIZE), to_sfixed(0.4201,1,L_SIZE), to_sfixed(0.2461,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.2318,1,L_SIZE), to_sfixed(0.2615,1,L_SIZE), to_sfixed(0.4094,1,L_SIZE), to_sfixed(0.5300,1,L_SIZE), to_sfixed(0.2214,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8092,1,L_SIZE), to_sfixed(0.5914,1,L_SIZE), to_sfixed(0.6192,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.5370,1,L_SIZE), to_sfixed(0.5155,1,L_SIZE), to_sfixed(0.3228,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.5223,1,L_SIZE), to_sfixed(0.0985,1,L_SIZE), to_sfixed(0.5439,1,L_SIZE), to_sfixed(0.7625,1,L_SIZE), to_sfixed(0.3357,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7721,1,L_SIZE), to_sfixed(0.4138,1,L_SIZE), to_sfixed(0.7492,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.7474,1,L_SIZE), to_sfixed(0.5492,1,L_SIZE), to_sfixed(0.4848,1,L_SIZE), to_sfixed(0.5112,1,L_SIZE), to_sfixed(0.2500,1,L_SIZE), to_sfixed(0.4678,1,L_SIZE), to_sfixed(0.8475,1,L_SIZE), to_sfixed(0.3720,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7795,1,L_SIZE), to_sfixed(0.3534,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.9500,1,L_SIZE), to_sfixed(0.7346,1,L_SIZE), to_sfixed(0.8196,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.5223,1,L_SIZE), to_sfixed(0.4615,1,L_SIZE), to_sfixed(0.5439,1,L_SIZE), to_sfixed(0.9225,1,L_SIZE), to_sfixed(0.2768,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8375,1,L_SIZE), to_sfixed(0.7638,1,L_SIZE), to_sfixed(0.8452,1,L_SIZE), to_sfixed(0.8833,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.4193,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.4777,1,L_SIZE), to_sfixed(0.1600,1,L_SIZE), to_sfixed(0.5380,1,L_SIZE), to_sfixed(0.7800,1,L_SIZE), to_sfixed(0.2173,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8800,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.6594,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.6753,1,L_SIZE), to_sfixed(0.5217,1,L_SIZE), to_sfixed(0.4545,1,L_SIZE), to_sfixed(0.5615,1,L_SIZE), to_sfixed(0.2000,1,L_SIZE), to_sfixed(0.4269,1,L_SIZE), to_sfixed(0.7750,1,L_SIZE), to_sfixed(0.2262,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8004,1,L_SIZE), to_sfixed(0.7431,1,L_SIZE), to_sfixed(0.7399,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5062,1,L_SIZE), to_sfixed(0.7371,1,L_SIZE), to_sfixed(0.5965,1,L_SIZE), to_sfixed(0.3182,1,L_SIZE), to_sfixed(0.8128,1,L_SIZE), to_sfixed(0.2154,1,L_SIZE), to_sfixed(0.4386,1,L_SIZE), to_sfixed(0.9100,1,L_SIZE), to_sfixed(0.2262,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8139,1,L_SIZE), to_sfixed(0.3724,1,L_SIZE), to_sfixed(0.6718,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5247,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.5217,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.2123,1,L_SIZE), to_sfixed(0.5029,1,L_SIZE), to_sfixed(0.8200,1,L_SIZE), to_sfixed(0.2250,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8382,1,L_SIZE), to_sfixed(0.2638,1,L_SIZE), to_sfixed(0.7090,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.7062,1,L_SIZE), to_sfixed(0.6201,1,L_SIZE), to_sfixed(0.5909,1,L_SIZE), to_sfixed(0.4944,1,L_SIZE), to_sfixed(0.3031,1,L_SIZE), to_sfixed(0.4035,1,L_SIZE), to_sfixed(0.7100,1,L_SIZE), to_sfixed(0.2095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.7950,1,L_SIZE), to_sfixed(0.3672,1,L_SIZE), to_sfixed(0.8607,1,L_SIZE), to_sfixed(0.9500,1,L_SIZE), to_sfixed(0.5679,1,L_SIZE), to_sfixed(0.5490,1,L_SIZE), to_sfixed(0.4409,1,L_SIZE), to_sfixed(0.8788,1,L_SIZE), to_sfixed(0.4916,1,L_SIZE), to_sfixed(0.2308,1,L_SIZE), to_sfixed(0.5673,1,L_SIZE), to_sfixed(0.6100,1,L_SIZE), to_sfixed(0.2774,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8341,1,L_SIZE), to_sfixed(0.2810,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.8167,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.5722,1,L_SIZE), to_sfixed(0.4823,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.5307,1,L_SIZE), to_sfixed(0.1631,1,L_SIZE), to_sfixed(0.5205,1,L_SIZE), to_sfixed(0.6950,1,L_SIZE), to_sfixed(0.2036,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8119,1,L_SIZE), to_sfixed(0.7414,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.4938,1,L_SIZE), to_sfixed(0.5412,1,L_SIZE), to_sfixed(0.3445,1,L_SIZE), to_sfixed(0.6364,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.2000,1,L_SIZE), to_sfixed(0.4620,1,L_SIZE), to_sfixed(0.6425,1,L_SIZE), to_sfixed(0.3452,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE)),
(to_sfixed(0.8672,1,L_SIZE), to_sfixed(0.2328,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.6000,1,L_SIZE), to_sfixed(0.7531,1,L_SIZE), to_sfixed(0.3892,1,L_SIZE), to_sfixed(0.2461,1,L_SIZE), to_sfixed(0.3182,1,L_SIZE), to_sfixed(0.2626,1,L_SIZE), to_sfixed(0.3154,1,L_SIZE), to_sfixed(0.4444,1,L_SIZE), to_sfixed(0.3225,1,L_SIZE), to_sfixed(0.3750,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8685,1,L_SIZE), to_sfixed(0.5155,1,L_SIZE), to_sfixed(0.7430,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.6420,1,L_SIZE), to_sfixed(0.3351,1,L_SIZE), to_sfixed(0.2402,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.2318,1,L_SIZE), to_sfixed(0.4154,1,L_SIZE), to_sfixed(0.4327,1,L_SIZE), to_sfixed(0.3550,1,L_SIZE), to_sfixed(0.3155,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8638,1,L_SIZE), to_sfixed(0.3983,1,L_SIZE), to_sfixed(0.7430,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.2964,1,L_SIZE), to_sfixed(0.2146,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.2318,1,L_SIZE), to_sfixed(0.4385,1,L_SIZE), to_sfixed(0.3860,1,L_SIZE), to_sfixed(0.3400,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8564,1,L_SIZE), to_sfixed(0.6121,1,L_SIZE), to_sfixed(0.7307,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.6543,1,L_SIZE), to_sfixed(0.4381,1,L_SIZE), to_sfixed(0.2362,1,L_SIZE), to_sfixed(0.2576,1,L_SIZE), to_sfixed(0.2346,1,L_SIZE), to_sfixed(0.3846,1,L_SIZE), to_sfixed(0.4561,1,L_SIZE), to_sfixed(0.3225,1,L_SIZE), to_sfixed(0.3571,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8436,1,L_SIZE), to_sfixed(0.2138,1,L_SIZE), to_sfixed(0.6966,1,L_SIZE), to_sfixed(0.5833,1,L_SIZE), to_sfixed(0.5247,1,L_SIZE), to_sfixed(0.5155,1,L_SIZE), to_sfixed(0.1142,1,L_SIZE), to_sfixed(0.9091,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.4192,1,L_SIZE), to_sfixed(0.4386,1,L_SIZE), to_sfixed(0.3775,1,L_SIZE), to_sfixed(0.3869,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8496,1,L_SIZE), to_sfixed(0.4241,1,L_SIZE), to_sfixed(0.6811,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.5802,1,L_SIZE), to_sfixed(0.4175,1,L_SIZE), to_sfixed(0.1299,1,L_SIZE), to_sfixed(0.9545,1,L_SIZE), to_sfixed(0.2626,1,L_SIZE), to_sfixed(0.5462,1,L_SIZE), to_sfixed(0.4269,1,L_SIZE), to_sfixed(0.3950,1,L_SIZE), to_sfixed(0.4137,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8260,1,L_SIZE), to_sfixed(0.8138,1,L_SIZE), to_sfixed(0.7864,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.3557,1,L_SIZE), to_sfixed(0.0925,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.2235,1,L_SIZE), to_sfixed(0.2962,1,L_SIZE), to_sfixed(0.4386,1,L_SIZE), to_sfixed(0.3175,1,L_SIZE), to_sfixed(0.4286,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8449,1,L_SIZE), to_sfixed(0.9500,1,L_SIZE), to_sfixed(0.8173,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.4613,1,L_SIZE), to_sfixed(0.1181,1,L_SIZE), to_sfixed(0.9545,1,L_SIZE), to_sfixed(0.3073,1,L_SIZE), to_sfixed(0.3846,1,L_SIZE), to_sfixed(0.4795,1,L_SIZE), to_sfixed(0.4225,1,L_SIZE), to_sfixed(0.3065,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9096,1,L_SIZE), to_sfixed(0.6190,1,L_SIZE), to_sfixed(0.6780,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.4175,1,L_SIZE), to_sfixed(0.0945,1,L_SIZE), to_sfixed(0.8788,1,L_SIZE), to_sfixed(0.2458,1,L_SIZE), to_sfixed(0.4385,1,L_SIZE), to_sfixed(0.4737,1,L_SIZE), to_sfixed(0.4550,1,L_SIZE), to_sfixed(0.3452,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8658,1,L_SIZE), to_sfixed(0.5103,1,L_SIZE), to_sfixed(0.8080,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.6235,1,L_SIZE), to_sfixed(0.5979,1,L_SIZE), to_sfixed(0.1181,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.2263,1,L_SIZE), to_sfixed(0.3785,1,L_SIZE), to_sfixed(0.5205,1,L_SIZE), to_sfixed(0.5375,1,L_SIZE), to_sfixed(0.3512,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8719,1,L_SIZE), to_sfixed(0.4845,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.3969,1,L_SIZE), to_sfixed(0.0984,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.2095,1,L_SIZE), to_sfixed(0.3538,1,L_SIZE), to_sfixed(0.4503,1,L_SIZE), to_sfixed(0.5775,1,L_SIZE), to_sfixed(0.3571,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9009,1,L_SIZE), to_sfixed(0.4414,1,L_SIZE), to_sfixed(0.7276,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.3608,1,L_SIZE), to_sfixed(0.0984,1,L_SIZE), to_sfixed(0.5606,1,L_SIZE), to_sfixed(0.1788,1,L_SIZE), to_sfixed(0.4308,1,L_SIZE), to_sfixed(0.4094,1,L_SIZE), to_sfixed(0.6175,1,L_SIZE), to_sfixed(0.4643,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9117,1,L_SIZE), to_sfixed(0.5466,1,L_SIZE), to_sfixed(0.8421,1,L_SIZE), to_sfixed(0.7833,1,L_SIZE), to_sfixed(0.5988,1,L_SIZE), to_sfixed(0.3995,1,L_SIZE), to_sfixed(0.1024,1,L_SIZE), to_sfixed(0.7576,1,L_SIZE), to_sfixed(0.1536,1,L_SIZE), to_sfixed(0.3346,1,L_SIZE), to_sfixed(0.5205,1,L_SIZE), to_sfixed(0.5150,1,L_SIZE), to_sfixed(0.3095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9184,1,L_SIZE), to_sfixed(0.8534,1,L_SIZE), to_sfixed(0.7276,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5679,1,L_SIZE), to_sfixed(0.5155,1,L_SIZE), to_sfixed(0.1575,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.2849,1,L_SIZE), to_sfixed(0.3385,1,L_SIZE), to_sfixed(0.5322,1,L_SIZE), to_sfixed(0.5125,1,L_SIZE), to_sfixed(0.3274,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8260,1,L_SIZE), to_sfixed(0.6690,1,L_SIZE), to_sfixed(0.6811,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.3557,1,L_SIZE), to_sfixed(0.1535,1,L_SIZE), to_sfixed(0.4394,1,L_SIZE), to_sfixed(0.3184,1,L_SIZE), to_sfixed(0.6315,1,L_SIZE), to_sfixed(0.3801,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.5089,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8874,1,L_SIZE), to_sfixed(0.6155,1,L_SIZE), to_sfixed(0.6656,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.3866,1,L_SIZE), to_sfixed(0.1083,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.3631,1,L_SIZE), to_sfixed(0.3077,1,L_SIZE), to_sfixed(0.3509,1,L_SIZE), to_sfixed(0.4200,1,L_SIZE), to_sfixed(0.4940,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9359,1,L_SIZE), to_sfixed(0.8690,1,L_SIZE), to_sfixed(0.6904,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.4938,1,L_SIZE), to_sfixed(0.2526,1,L_SIZE), to_sfixed(0.0669,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.1899,1,L_SIZE), to_sfixed(0.3769,1,L_SIZE), to_sfixed(0.3392,1,L_SIZE), to_sfixed(0.3325,1,L_SIZE), to_sfixed(0.2470,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8678,1,L_SIZE), to_sfixed(0.7948,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.4381,1,L_SIZE), to_sfixed(0.1280,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.2402,1,L_SIZE), to_sfixed(0.5885,1,L_SIZE), to_sfixed(0.3158,1,L_SIZE), to_sfixed(0.4650,1,L_SIZE), to_sfixed(0.3720,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8982,1,L_SIZE), to_sfixed(0.5586,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.5679,1,L_SIZE), to_sfixed(0.4974,1,L_SIZE), to_sfixed(0.1496,1,L_SIZE), to_sfixed(0.6818,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.6477,1,L_SIZE), to_sfixed(0.3216,1,L_SIZE), to_sfixed(0.4050,1,L_SIZE), to_sfixed(0.3869,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8820,1,L_SIZE), to_sfixed(0.6724,1,L_SIZE), to_sfixed(0.7307,1,L_SIZE), to_sfixed(0.7167,1,L_SIZE), to_sfixed(0.6975,1,L_SIZE), to_sfixed(0.3634,1,L_SIZE), to_sfixed(0.2736,1,L_SIZE), to_sfixed(0.5152,1,L_SIZE), to_sfixed(0.3184,1,L_SIZE), to_sfixed(0.7231,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.3325,1,L_SIZE), to_sfixed(0.3274,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9103,1,L_SIZE), to_sfixed(0.5379,1,L_SIZE), to_sfixed(0.8111,1,L_SIZE), to_sfixed(0.8000,1,L_SIZE), to_sfixed(0.7593,1,L_SIZE), to_sfixed(0.3608,1,L_SIZE), to_sfixed(0.3091,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.3492,1,L_SIZE), to_sfixed(0.6615,1,L_SIZE), to_sfixed(0.3450,1,L_SIZE), to_sfixed(0.3250,1,L_SIZE), to_sfixed(0.2976,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8624,1,L_SIZE), to_sfixed(0.4603,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.3814,1,L_SIZE), to_sfixed(0.2677,1,L_SIZE), to_sfixed(0.3636,1,L_SIZE), to_sfixed(0.3520,1,L_SIZE), to_sfixed(0.8308,1,L_SIZE), to_sfixed(0.2807,1,L_SIZE), to_sfixed(0.3675,1,L_SIZE), to_sfixed(0.2857,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8840,1,L_SIZE), to_sfixed(0.3276,1,L_SIZE), to_sfixed(0.8514,1,L_SIZE), to_sfixed(0.8500,1,L_SIZE), to_sfixed(0.7160,1,L_SIZE), to_sfixed(0.5670,1,L_SIZE), to_sfixed(0.2520,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.4358,1,L_SIZE), to_sfixed(0.5462,1,L_SIZE), to_sfixed(0.3567,1,L_SIZE), to_sfixed(0.3325,1,L_SIZE), to_sfixed(0.2530,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8921,1,L_SIZE), to_sfixed(0.5690,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.4639,1,L_SIZE), to_sfixed(0.1634,1,L_SIZE), to_sfixed(0.9242,1,L_SIZE), to_sfixed(0.5223,1,L_SIZE), to_sfixed(0.8092,1,L_SIZE), to_sfixed(0.3275,1,L_SIZE), to_sfixed(0.3775,1,L_SIZE), to_sfixed(0.4018,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8483,1,L_SIZE), to_sfixed(0.2224,1,L_SIZE), to_sfixed(0.6502,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.6358,1,L_SIZE), to_sfixed(0.3814,1,L_SIZE), to_sfixed(0.1142,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.3911,1,L_SIZE), to_sfixed(0.5846,1,L_SIZE), to_sfixed(0.3392,1,L_SIZE), to_sfixed(0.3875,1,L_SIZE), to_sfixed(0.3810,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8881,1,L_SIZE), to_sfixed(0.8948,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.5741,1,L_SIZE), to_sfixed(0.4485,1,L_SIZE), to_sfixed(0.1240,1,L_SIZE), to_sfixed(0.9242,1,L_SIZE), to_sfixed(0.4330,1,L_SIZE), to_sfixed(0.6077,1,L_SIZE), to_sfixed(0.3509,1,L_SIZE), to_sfixed(0.3700,1,L_SIZE), to_sfixed(0.4315,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9332,1,L_SIZE), to_sfixed(0.7103,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.4639,1,L_SIZE), to_sfixed(0.1634,1,L_SIZE), to_sfixed(0.7273,1,L_SIZE), to_sfixed(0.4358,1,L_SIZE), to_sfixed(0.6931,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4100,1,L_SIZE), to_sfixed(0.2857,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8395,1,L_SIZE), to_sfixed(0.5224,1,L_SIZE), to_sfixed(0.8173,1,L_SIZE), to_sfixed(0.9000,1,L_SIZE), to_sfixed(0.5988,1,L_SIZE), to_sfixed(0.4897,1,L_SIZE), to_sfixed(0.1142,1,L_SIZE), to_sfixed(0.9545,1,L_SIZE), to_sfixed(0.3184,1,L_SIZE), to_sfixed(0.5769,1,L_SIZE), to_sfixed(0.3918,1,L_SIZE), to_sfixed(0.4325,1,L_SIZE), to_sfixed(0.5238,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9670,1,L_SIZE), to_sfixed(0.2897,1,L_SIZE), to_sfixed(0.8359,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.6049,1,L_SIZE), to_sfixed(0.7216,1,L_SIZE), to_sfixed(0.2579,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.7542,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4900,1,L_SIZE), to_sfixed(0.3929,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9090,1,L_SIZE), to_sfixed(0.2879,1,L_SIZE), to_sfixed(0.8173,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.5494,1,L_SIZE), to_sfixed(0.6701,1,L_SIZE), to_sfixed(0.2165,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.6397,1,L_SIZE), to_sfixed(0.9038,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4450,1,L_SIZE), to_sfixed(0.3690,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8334,1,L_SIZE), to_sfixed(0.6603,1,L_SIZE), to_sfixed(0.7368,1,L_SIZE), to_sfixed(0.7000,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.5928,1,L_SIZE), to_sfixed(0.1811,1,L_SIZE), to_sfixed(0.7576,1,L_SIZE), to_sfixed(0.2905,1,L_SIZE), to_sfixed(0.5885,1,L_SIZE), to_sfixed(0.3275,1,L_SIZE), to_sfixed(0.3950,1,L_SIZE), to_sfixed(0.3095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9231,1,L_SIZE), to_sfixed(0.5621,1,L_SIZE), to_sfixed(0.7864,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.6605,1,L_SIZE), to_sfixed(0.4716,1,L_SIZE), to_sfixed(0.1102,1,L_SIZE), to_sfixed(0.7576,1,L_SIZE), to_sfixed(0.2235,1,L_SIZE), to_sfixed(0.4523,1,L_SIZE), to_sfixed(0.5614,1,L_SIZE), to_sfixed(0.4550,1,L_SIZE), to_sfixed(0.4048,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8665,1,L_SIZE), to_sfixed(0.5638,1,L_SIZE), to_sfixed(0.7988,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.6543,1,L_SIZE), to_sfixed(0.4253,1,L_SIZE), to_sfixed(0.1181,1,L_SIZE), to_sfixed(0.9091,1,L_SIZE), to_sfixed(0.2682,1,L_SIZE), to_sfixed(0.4292,1,L_SIZE), to_sfixed(0.5088,1,L_SIZE), to_sfixed(0.5275,1,L_SIZE), to_sfixed(0.3393,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8739,1,L_SIZE), to_sfixed(0.5948,1,L_SIZE), to_sfixed(0.7276,1,L_SIZE), to_sfixed(0.6167,1,L_SIZE), to_sfixed(0.6543,1,L_SIZE), to_sfixed(0.3582,1,L_SIZE), to_sfixed(0.1378,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.2626,1,L_SIZE), to_sfixed(0.4062,1,L_SIZE), to_sfixed(0.3977,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(0.4018,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9292,1,L_SIZE), to_sfixed(0.4759,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.7333,1,L_SIZE), to_sfixed(0.5556,1,L_SIZE), to_sfixed(0.3479,1,L_SIZE), to_sfixed(0.1339,1,L_SIZE), to_sfixed(0.6212,1,L_SIZE), to_sfixed(0.2877,1,L_SIZE), to_sfixed(0.7369,1,L_SIZE), to_sfixed(0.4094,1,L_SIZE), to_sfixed(0.4200,1,L_SIZE), to_sfixed(0.3661,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9258,1,L_SIZE), to_sfixed(0.7517,1,L_SIZE), to_sfixed(0.6997,1,L_SIZE), to_sfixed(0.7500,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.3299,1,L_SIZE), to_sfixed(0.0925,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.3212,1,L_SIZE), to_sfixed(0.5092,1,L_SIZE), to_sfixed(0.4561,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(0.3095,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9069,1,L_SIZE), to_sfixed(0.6379,1,L_SIZE), to_sfixed(0.8050,1,L_SIZE), to_sfixed(0.7667,1,L_SIZE), to_sfixed(0.6852,1,L_SIZE), to_sfixed(0.4381,1,L_SIZE), to_sfixed(0.1811,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.8215,1,L_SIZE), to_sfixed(0.4971,1,L_SIZE), to_sfixed(0.3900,1,L_SIZE), to_sfixed(0.4137,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8645,1,L_SIZE), to_sfixed(0.5810,1,L_SIZE), to_sfixed(0.7121,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5432,1,L_SIZE), to_sfixed(0.3814,1,L_SIZE), to_sfixed(0.1299,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.2709,1,L_SIZE), to_sfixed(0.7892,1,L_SIZE), to_sfixed(0.4211,1,L_SIZE), to_sfixed(0.4375,1,L_SIZE), to_sfixed(0.4077,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9157,1,L_SIZE), to_sfixed(0.4448,1,L_SIZE), to_sfixed(0.8328,1,L_SIZE), to_sfixed(0.8167,1,L_SIZE), to_sfixed(0.6481,1,L_SIZE), to_sfixed(0.3995,1,L_SIZE), to_sfixed(0.1654,1,L_SIZE), to_sfixed(0.5909,1,L_SIZE), to_sfixed(0.4302,1,L_SIZE), to_sfixed(0.6662,1,L_SIZE), to_sfixed(0.4327,1,L_SIZE), to_sfixed(0.4500,1,L_SIZE), to_sfixed(0.4464,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9036,1,L_SIZE), to_sfixed(0.7931,1,L_SIZE), to_sfixed(0.8854,1,L_SIZE), to_sfixed(0.8333,1,L_SIZE), to_sfixed(0.6914,1,L_SIZE), to_sfixed(0.5103,1,L_SIZE), to_sfixed(0.1890,1,L_SIZE), to_sfixed(0.4091,1,L_SIZE), to_sfixed(0.3101,1,L_SIZE), to_sfixed(0.6538,1,L_SIZE), to_sfixed(0.3918,1,L_SIZE), to_sfixed(0.4800,1,L_SIZE), to_sfixed(0.3750,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8227,1,L_SIZE), to_sfixed(0.5224,1,L_SIZE), to_sfixed(0.7183,1,L_SIZE), to_sfixed(0.6333,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.3222,1,L_SIZE), to_sfixed(0.0965,1,L_SIZE), to_sfixed(0.6061,1,L_SIZE), to_sfixed(0.2039,1,L_SIZE), to_sfixed(0.4231,1,L_SIZE), to_sfixed(0.3860,1,L_SIZE), to_sfixed(0.4575,1,L_SIZE), to_sfixed(0.3036,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8611,1,L_SIZE), to_sfixed(0.4121,1,L_SIZE), to_sfixed(0.7059,1,L_SIZE), to_sfixed(0.6500,1,L_SIZE), to_sfixed(0.5309,1,L_SIZE), to_sfixed(0.3582,1,L_SIZE), to_sfixed(0.1004,1,L_SIZE), to_sfixed(0.7273,1,L_SIZE), to_sfixed(0.1788,1,L_SIZE), to_sfixed(0.7615,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.4075,1,L_SIZE), to_sfixed(0.2798,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9548,1,L_SIZE), to_sfixed(0.4328,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.5617,1,L_SIZE), to_sfixed(0.4330,1,L_SIZE), to_sfixed(0.1378,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.3464,1,L_SIZE), to_sfixed(0.7462,1,L_SIZE), to_sfixed(0.3626,1,L_SIZE), to_sfixed(0.4275,1,L_SIZE), to_sfixed(0.3929,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9245,1,L_SIZE), to_sfixed(0.9741,1,L_SIZE), to_sfixed(0.7585,1,L_SIZE), to_sfixed(0.6833,1,L_SIZE), to_sfixed(0.5864,1,L_SIZE), to_sfixed(0.4330,1,L_SIZE), to_sfixed(0.1201,1,L_SIZE), to_sfixed(0.7879,1,L_SIZE), to_sfixed(0.2961,1,L_SIZE), to_sfixed(0.5923,1,L_SIZE), to_sfixed(0.3743,1,L_SIZE), to_sfixed(0.4350,1,L_SIZE), to_sfixed(0.4405,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9036,1,L_SIZE), to_sfixed(0.6741,1,L_SIZE), to_sfixed(0.7678,1,L_SIZE), to_sfixed(0.7667,1,L_SIZE), to_sfixed(0.6296,1,L_SIZE), to_sfixed(0.4639,1,L_SIZE), to_sfixed(0.1476,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.3939,1,L_SIZE), to_sfixed(0.5615,1,L_SIZE), to_sfixed(0.4094,1,L_SIZE), to_sfixed(0.3900,1,L_SIZE), to_sfixed(0.4464,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8948,1,L_SIZE), to_sfixed(0.7379,1,L_SIZE), to_sfixed(0.6997,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7407,1,L_SIZE), to_sfixed(0.4098,1,L_SIZE), to_sfixed(0.1358,1,L_SIZE), to_sfixed(0.6515,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.7846,1,L_SIZE), to_sfixed(0.3450,1,L_SIZE), to_sfixed(0.3900,1,L_SIZE), to_sfixed(0.4970,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.8881,1,L_SIZE), to_sfixed(0.4466,1,L_SIZE), to_sfixed(0.7337,1,L_SIZE), to_sfixed(0.6667,1,L_SIZE), to_sfixed(0.7407,1,L_SIZE), to_sfixed(0.4253,1,L_SIZE), to_sfixed(0.1339,1,L_SIZE), to_sfixed(0.8030,1,L_SIZE), to_sfixed(0.4078,1,L_SIZE), to_sfixed(0.7154,1,L_SIZE), to_sfixed(0.3509,1,L_SIZE), to_sfixed(0.4050,1,L_SIZE), to_sfixed(0.5000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE)),
(to_sfixed(0.9528,1,L_SIZE), to_sfixed(0.7069,1,L_SIZE), to_sfixed(0.8483,1,L_SIZE), to_sfixed(0.8167,1,L_SIZE), to_sfixed(0.5926,1,L_SIZE), to_sfixed(0.5284,1,L_SIZE), to_sfixed(0.1496,1,L_SIZE), to_sfixed(0.8485,1,L_SIZE), to_sfixed(0.3771,1,L_SIZE), to_sfixed(0.7077,1,L_SIZE), to_sfixed(0.3567,1,L_SIZE), to_sfixed(0.4000,1,L_SIZE), to_sfixed(0.3333,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(0.0000,1,L_SIZE), to_sfixed(1.0000,1,L_SIZE))
);
-- Signals
signal INPUT : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_INPUT-1));
signal FROM_LOOKUP : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_HIDDEN-1));
signal OUTPUT : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_HIDDEN-1));
-- Signals
signal IN_UNSIGNED : unsigned(7 downto 0);
signal LOOKUP_TABLE_K : unsigned(7 downto 0);
signal LOOKUP_TABLE_OUT : INPUT_LOOKUP_ARRAY;
signal LOOKUP_TABLE_OUT_CONSTRAINED : INPUT_CONSTRAINED_SFIXED_ARRAY;
signal UNIT_DELAY_OUT : INPUT_CONSTRAINED_SFIXED_ARRAY;
--=============================================================================
-- architecture begin
--=============================================================================
begin
IN_UNSIGNED <= unsigned(SAMPLE_NUMBER);
LOOKUP_TABLE_K <= -- Make sure no index will fall out of boundary
to_unsigned(0, 8) when IN_UNSIGNED <= 0
else
to_unsigned(SAMPLE_SIZE, 8) when IN_UNSIGNED >= SAMPLE_SIZE
else
IN_UNSIGNED;
LOOKUP_TABLE_OUT <= INPUTS_TABLE(to_integer(LOOKUP_TABLE_K));
GEN_PROPER_OUTPUT:
for I in 0 to (PERCEPTRONS_INPUT-1+PERCEPTRONS_OUTPUT) generate
LOOKUP_TABLE_OUT_CONSTRAINED(I)<=
resize(LOOKUP_TABLE_OUT(I),U_SIZE,L_SIZE);
end generate GEN_PROPER_OUTPUT;
UNIT_DELAY_PROCESS : process (clk)
begin
if CLK'event and CLK = '1' then
UNIT_DELAY_OUT <= LOOKUP_TABLE_OUT_CONSTRAINED;
end if;
end process UNIT_DELAY_PROCESS;
SELECTED_INPUT <= UNIT_DELAY_OUT;
end RTL;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
82e8cbb0eeb6080c4e4cb66a0838c0a7
| 0.660391 | 2.047093 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_core.vhd
| 2 | 7,943 |
-- $Id: pdp11_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_core - syn
-- Description: pdp11: full processor core
--
-- Dependencies: pdp11_vmbox
-- pdp11_dpath
-- pdp11_decode
-- pdp11_sequencer
-- pdp11_irq
-- pdp11_sys70
-- ibus/ib_sres_or_4
--
-- Test bench: tb/tb_pdp11core
-- tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.3.1 now numeric_std clean
-- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox
-- CP_ADDR now from in port; dpath CP_DIN now from in
-- port; out port CP_DOUT now from _dpath
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.2.4 rename pdp11_ibres_ -> ib_sres_
-- 2008-04-25 138 1.2.3 BRESET: add for _vmbox, use for _irq
-- 2008-04-19 137 1.2.2 add DM_STAT_(DP|VM|CO) port; added pdp11_sys70
-- 2008-03-02 121 1.2.1 remove snoopers
-- 2008-02-17 117 1.2 add em_(mreq|sres) interface for memory
-- 2008-01-20 112 1.1.3 add BRESET port (intbus reset), rename P->BRESET
-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
-- 2008-01-01 109 1.1.1 _vmbox w/ IB_SRES_(CPU|EXT)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
BRESET : out slbit; -- ibus reset
IB_MREQ_M : out ib_mreq_type; -- inbus master request (master)
IB_SRES_M : in ib_sres_type; -- inbus slave response (master)
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end pdp11_core;
architecture syn of pdp11_core is
signal GRESET : slbit := '0';
signal CRESET : slbit := '0';
signal BRESET_L : slbit := '0';
signal SEQ_CRESET : slbit := '0';
signal SEQ_BRESET : slbit := '0';
signal VM_CNTL : vm_cntl_type := vm_cntl_init;
signal VM_STAT : vm_stat_type := vm_stat_init;
signal MMU_MONI : mmu_moni_type := mmu_moni_init;
signal DP_CNTL : dpath_cntl_type := dpath_cntl_init;
signal DP_STAT : dpath_stat_type := dpath_stat_init;
signal DP_PSW : psw_type := psw_init;
signal DP_PC : slv16 := (others=>'0');
signal DP_IREG : slv16 := (others=>'0');
signal VM_DIN : slv16 := (others=>'0');
signal VM_ADDR : slv16 := (others=>'0');
signal VM_DOUT : slv16 := (others=>'0');
signal ID_STAT : decode_stat_type := decode_stat_init;
signal INT_PRI : slv3 := (others=>'0');
signal INT_VECT : slv9_2 := (others=>'0');
signal CP_STAT_L : cp_stat_type := cp_stat_init;
signal INT_ACK : slbit := '0';
signal IB_SRES_DP : ib_sres_type := ib_sres_init;
signal IB_SRES_SEQ : ib_sres_type := ib_sres_init;
signal IB_SRES_IRQ : ib_sres_type := ib_sres_init;
signal IB_SRES_SYS : ib_sres_type := ib_sres_init;
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
begin
GRESET <= RESET;
CRESET <= RESET or SEQ_CRESET;
BRESET_L <= RESET or SEQ_CRESET or SEQ_BRESET;
VMBOX : pdp11_vmbox
port map (
CLK => CLK,
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET_L,
CP_ADDR => CP_ADDR,
VM_CNTL => VM_CNTL,
VM_ADDR => VM_ADDR,
VM_DIN => VM_DIN,
VM_STAT => VM_STAT,
VM_DOUT => VM_DOUT,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
MMU_MONI => MMU_MONI,
IB_MREQ_M => IB_MREQ,
IB_SRES_CPU => IB_SRES,
IB_SRES_EXT => IB_SRES_M,
DM_STAT_VM => DM_STAT_VM
);
DPATH : pdp11_dpath
port map (
CLK => CLK,
CRESET => CRESET,
CNTL => DP_CNTL,
STAT => DP_STAT,
CP_DIN => CP_DIN,
CP_DOUT => CP_DOUT,
PSWOUT => DP_PSW,
PCOUT => DP_PC,
IREG => DP_IREG,
VM_ADDR => VM_ADDR,
VM_DOUT => VM_DOUT,
VM_DIN => VM_DIN,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DP,
DM_STAT_DP => DM_STAT_DP
);
IDEC : pdp11_decode
port map (
IREG => DP_IREG,
STAT => ID_STAT
);
SEQ : pdp11_sequencer
port map (
CLK => CLK,
GRESET => GRESET,
PSW => DP_PSW,
PC => DP_PC,
IREG => DP_IREG,
ID_STAT => ID_STAT,
DP_STAT => DP_STAT,
CP_CNTL => CP_CNTL,
VM_STAT => VM_STAT,
INT_PRI => INT_PRI,
INT_VECT => INT_VECT,
CRESET => SEQ_CRESET,
BRESET => SEQ_BRESET,
MMU_MONI => MMU_MONI,
DP_CNTL => DP_CNTL,
VM_CNTL => VM_CNTL,
CP_STAT => CP_STAT_L,
INT_ACK => INT_ACK,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SEQ
);
IRQ : pdp11_irq
port map (
CLK => CLK,
BRESET => BRESET_L,
INT_ACK => INT_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PRI => INT_PRI,
VECT => INT_VECT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IRQ
);
SYS70 : pdp11_sys70
port map (
CLK => CLK,
CRESET => CRESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SYS
);
IB_SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_DP,
IB_SRES_2 => IB_SRES_SEQ,
IB_SRES_3 => IB_SRES_IRQ,
IB_SRES_4 => IB_SRES_SYS,
IB_SRES_OR => IB_SRES
);
IB_MREQ_M <= IB_MREQ;
CP_STAT <= CP_STAT_L;
BRESET <= BRESET_L;
DM_STAT_CO.cpugo <= CP_STAT_L.cpugo;
DM_STAT_CO.cpuhalt <= CP_STAT_L.cpuhalt;
end syn;
|
gpl-2.0
|
a04f369470f7a98e1e4227cae0532dcb
| 0.537077 | 3.183567 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/control/input_select.vhd
| 1 | 3,302 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : input_select.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : INPUT_SELECT
-- ARCHITECTURE : structure
--=============================================================================
-- AUTORS(s) : Agostini, N;
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 14, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use work.NN_TYPES_pkg.all;
--=============================================================================
-- Entity declaration for INPUT_SELECT
--=============================================================================
entity INPUT_SELECT is
port (
CLK : in std_logic;
SAMPLE_NUMBER : in std_logic_vector (7 downto 0);
NN_INPUT : out ARRAY_OF_SFIXED;
TARGET_VALUE : out ARRAY_OF_SFIXED
);
end INPUT_SELECT;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture STRUCTURE of INPUT_SELECT is
-- Signals
signal SELECTED_INPUT : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_INPUT-1+PERCEPTRONS_OUTPUT));
-- Components
component INPUT_ROM
port (
CLK : in std_logic;
SAMPLE_NUMBER : in std_logic_vector (7 downto 0);
SELECTED_INPUT : out ARRAY_OF_SFIXED
);
end component;
--=============================================================================
-- architecture begin
--=============================================================================
begin
GEN_PROPER_INPUT:
for I in 0 to (PERCEPTRONS_INPUT-1) generate
NN_INPUT(I)<=
SELECTED_INPUT(I);
end generate GEN_PROPER_INPUT;
GEN_PROPER_TARGET:
for I in 0 to (PERCEPTRONS_OUTPUT-1) generate
TARGET_VALUE(I)<=
SELECTED_INPUT(I+PERCEPTRONS_INPUT);
end generate GEN_PROPER_TARGET;
ROM: INPUT_ROM
port map (
CLK => CLK,
SAMPLE_NUMBER => SAMPLE_NUMBER,
SELECTED_INPUT => SELECTED_INPUT
);
end STRUCTURE;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
fb6f283bfe78ed6bfc88b5435a5f73e7
| 0.456996 | 4.598886 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/sn_4x7segctl.vhd
| 2 | 5,432 |
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_4x7segctl - syn
-- Description: Quad 7 segment display controller (for s3board and nexys2/3)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
-- delay and to avoid cross talk between digits
-- 2007-12-16 101 1.0.1 use _N for active low
-- 2007-09-16 83 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end sn_4x7segctl;
architecture syn of sn_4x7segctl is
type regs_type is record
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(0,CDWIDTH)),
(others=>'0')
);
type hex2segtbl_type is array (0 to 15) of slv7;
constant hex2segtbl : hex2segtbl_type :=
("0111111", -- 0: "0000"
"0000110", -- 1: "0001"
"1011011", -- 2: "0010"
"1001111", -- 3: "0011"
"1100110", -- 4: "0100"
"1101101", -- 5: "0101"
"1111101", -- 6: "0110"
"0000111", -- 7: "0111"
"1111111", -- 8: "1000"
"1101111", -- 9: "1001"
"1110111", -- a: "1010"
"1111100", -- b: "1011"
"0111001", -- c: "1100"
"1011110", -- d: "1101"
"1111001", -- e: "1110"
"1110001" -- f: "1111"
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, DIN, DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable cano : slv4 := "0000";
variable chex : slv4 := "0000";
variable cdp : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
n.cdiv := slv(unsigned(r.cdiv) - 1);
if unsigned(r.cdiv) = 0 then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
chex := "0000";
cdp := '0';
case r.dcnt is
when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
when "10" => chex := DIN(11 downto 8); cdp := DP(2);
when "11" => chex := DIN(15 downto 12); cdp := DP(3);
when others => chex := "----"; cdp := '-';
end case;
-- the logic below ensures that the anode PNP driver transistor is switched
-- off in the last quarter of the digit cycle.This prevents 'cross talk'
-- between digits due to transistor turn off delays.
-- For a nexys2 board at 50 MHz observed:
-- no or 4 cycles gap well visible cross talk
-- with 8 cycles still some weak cross talk
-- with 16 cycles none is visible.
-- --> The turn-off delay of the anode driver PNP's this therefore
-- larger 160 ns and below 320 ns.
-- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz.
cano := "1111";
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex))));
end process proc_next;
end syn;
|
gpl-2.0
|
f264427b4353714d1853ffe9157ce4bb
| 0.522275 | 3.672752 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/1e9b998c47ac47df/fifo_generator_rx_inst_sim_netlist.vhdl
| 1 | 197,922 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 09:37:07 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^q\(0),
S => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^q\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^q\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^q\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^q\(4),
R => srst
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^q\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(6),
Q => \^q\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(7),
Q => \^q\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(8),
Q => \^q\(8),
R => srst
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(9),
Q => \^q\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(7),
I3 => p_12_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(7),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(6),
I3 => p_12_out(8),
I4 => p_12_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[9]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(6),
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(7),
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(8),
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(9),
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => ram_empty_i_reg_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => srst,
I1 => ram_empty_fb_i,
I2 => rd_en,
O => tmp_ram_rd_en
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \grss.rsts_n_2\ : STD_LOGIC;
begin
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
E(0) => \grss.rsts_n_2\,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \grss.rsts_n_2\,
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => \^wea\(0),
clk => clk,
full => full,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
srst => srst,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out(9 downto 0),
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_20\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_22\,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
cd1fe3a95f53ff02b7827f5be5b35f30
| 0.657153 | 3.085444 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_mmu.vhd
| 2 | 13,698 |
-- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu - syn
-- Description: pdp11: mmu - memory management unit
--
-- Dependencies: pdp11_mmu_sadr
-- pdp11_mmu_ssr12
-- ibus/ib_sres_or_3
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
-- BUGFIX: set ssr0 trap_mmu even when traps disabled
-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-27 139 1.3.3 allow ssr1/2 tracing even with mmu_ena=0
-- 2008-04-25 138 1.3.2 add BRESET port, clear ssr0/3 with BRESET
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
-- cpacc handling; PADDR generation now on _vmbox
-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ: in ib_mreq_type; -- ibus request
IB_SRES: out ib_sres_type -- ibus response
);
end pdp11_mmu;
architecture syn of pdp11_mmu is
constant ibaddr_ssr0 : slv16 := slv(to_unsigned(8#177572#,16));
constant ibaddr_ssr3 : slv16 := slv(to_unsigned(8#172516#,16));
constant ssr0_ibf_abo_nonres : integer := 15;
constant ssr0_ibf_abo_length : integer := 14;
constant ssr0_ibf_abo_rdonly : integer := 13;
constant ssr0_ibf_trap_mmu : integer := 12;
constant ssr0_ibf_ena_trap : integer := 9;
constant ssr0_ibf_inst_compl : integer := 7;
subtype ssr0_ibf_seg_mode is integer range 6 downto 5;
constant ssr0_ibf_dspace : integer := 4;
subtype ssr0_ibf_seg_num is integer range 3 downto 1;
constant ssr0_ibf_ena_mmu : integer := 0;
constant ssr3_ibf_ena_ubmap : integer := 5;
constant ssr3_ibf_ena_22bit : integer := 4;
constant ssr3_ibf_dspace_km : integer := 2;
constant ssr3_ibf_dspace_sm : integer := 1;
constant ssr3_ibf_dspace_um : integer := 0;
signal IBSEL_SSR0 : slbit := '0'; -- ibus select SSR0
signal IBSEL_SSR3 : slbit := '0'; -- ibus select SSR3
signal R_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
signal N_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
signal R_SSR3 : mmu_ssr3_type := mmu_ssr3_init;
signal ASN : slv4 := "0000"; -- augmented segment number (1+3 bit)
signal AIB_WE : slbit := '0'; -- update AIB
signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
signal TRACE : slbit := '0'; -- enable tracing in ssr1/2
signal DSPACE : slbit := '0'; -- use dspace
signal IB_SRES_SADR : ib_sres_type := ib_sres_init;
signal IB_SRES_SSR12 : ib_sres_type := ib_sres_init;
signal IB_SRES_SSR03 : ib_sres_type := ib_sres_init;
signal SARSDR : sarsdr_type := sarsdr_init;
begin
SADR : pdp11_mmu_sadr port map (
CLK => CLK,
MODE => CNTL.mode,
ASN => ASN,
AIB_WE => AIB_WE,
AIB_SETA => AIB_SETA,
AIB_SETW => AIB_SETW,
SARSDR => SARSDR,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SADR);
SSR12 : pdp11_mmu_ssr12 port map (
CLK => CLK,
CRESET => CRESET,
TRACE => TRACE,
MONI => MONI,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SSR12);
SRES_OR : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_SADR,
IB_SRES_2 => IB_SRES_SSR12,
IB_SRES_3 => IB_SRES_SSR03,
IB_SRES_OR => IB_SRES);
SEL_SSR0 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr0)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR0
);
SEL_SSR3 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr3)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR3
);
proc_ibres : process (IBSEL_SSR0, IBSEL_SSR3, IB_MREQ, R_SSR0, R_SSR3)
variable ssr0out : slv16 := (others=>'0');
variable ssr3out : slv16 := (others=>'0');
begin
ssr0out := (others=>'0');
if IBSEL_SSR0 = '1' then
ssr0out(ssr0_ibf_abo_nonres) := R_SSR0.abo_nonres;
ssr0out(ssr0_ibf_abo_length) := R_SSR0.abo_length;
ssr0out(ssr0_ibf_abo_rdonly) := R_SSR0.abo_rdonly;
ssr0out(ssr0_ibf_trap_mmu) := R_SSR0.trap_mmu;
ssr0out(ssr0_ibf_ena_trap) := R_SSR0.ena_trap;
ssr0out(ssr0_ibf_inst_compl) := R_SSR0.inst_compl;
ssr0out(ssr0_ibf_seg_mode) := R_SSR0.seg_mode;
ssr0out(ssr0_ibf_dspace) := R_SSR0.dspace;
ssr0out(ssr0_ibf_seg_num) := R_SSR0.seg_num;
ssr0out(ssr0_ibf_ena_mmu) := R_SSR0.ena_mmu;
end if;
ssr3out := (others=>'0');
if IBSEL_SSR3 = '1' then
ssr3out(ssr3_ibf_ena_ubmap) := R_SSR3.ena_ubmap;
ssr3out(ssr3_ibf_ena_22bit) := R_SSR3.ena_22bit;
ssr3out(ssr3_ibf_dspace_km) := R_SSR3.dspace_km;
ssr3out(ssr3_ibf_dspace_sm) := R_SSR3.dspace_sm;
ssr3out(ssr3_ibf_dspace_um) := R_SSR3.dspace_um;
end if;
IB_SRES_SSR03.dout <= ssr0out or ssr3out;
IB_SRES_SSR03.ack <= (IBSEL_SSR0 or IBSEL_SSR3) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SSR03.busy <= '0';
end process proc_ibres;
proc_ssr0 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SSR0 <= mmu_ssr0_init;
else
R_SSR0 <= N_SSR0;
end if;
end if;
end process proc_ssr0;
proc_ssr3 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SSR3 <= mmu_ssr3_init;
elsif IBSEL_SSR3='1' and IB_MREQ.we='1' then
if IB_MREQ.be0 = '1' then
R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap);
R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit);
R_SSR3.dspace_km <= IB_MREQ.din(ssr3_ibf_dspace_km);
R_SSR3.dspace_sm <= IB_MREQ.din(ssr3_ibf_dspace_sm);
R_SSR3.dspace_um <= IB_MREQ.din(ssr3_ibf_dspace_um);
end if;
end if;
end if;
end process proc_ssr3;
proc_paddr : process (R_SSR0, R_SSR3, CNTL, SARSDR, VADDR)
variable ipaddrh : slv16 := (others=>'0');
variable dspace_ok : slbit := '0';
variable dspace_en : slbit := '0';
variable asf : slv3 := (others=>'0'); -- va: active segment field
variable bn : slv7 := (others=>'0'); -- va: block number
variable iasn : slv4 := (others=>'0');-- augmented segment number
begin
asf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
dspace_en := '0';
case CNTL.mode is
when "00" => dspace_en := R_SSR3.dspace_km;
when "01" => dspace_en := R_SSR3.dspace_sm;
when "11" => dspace_en := R_SSR3.dspace_um;
when others => null;
end case;
dspace_ok := CNTL.dspace and dspace_en;
iasn(3) := dspace_ok;
iasn(2 downto 0) := asf;
ipaddrh := slv(unsigned("000000000"&bn) + unsigned(SARSDR.saf));
DSPACE <= dspace_ok;
ASN <= iasn;
PADDRH <= ipaddrh;
end process proc_paddr;
proc_nssr0 : process (R_SSR0, R_SSR3, IB_MREQ, IBSEL_SSR0, DSPACE,
CNTL, MONI, SARSDR, VADDR)
variable nssr0 : mmu_ssr0_type := mmu_ssr0_init;
variable asf : slv3 := (others=>'0');
variable bn : slv7 := (others=>'0');
variable abo_nonres : slbit := '0';
variable abo_length : slbit := '0';
variable abo_rdonly : slbit := '0';
variable ssr_freeze : slbit := '0';
variable doabort : slbit := '0';
variable dotrap : slbit := '0';
variable dotrace : slbit := '0';
begin
nssr0 := R_SSR0;
AIB_WE <= '0';
AIB_SETA <= '0';
AIB_SETW <= '0';
ssr_freeze := R_SSR0.abo_nonres or R_SSR0.abo_length or R_SSR0.abo_rdonly;
dotrace := not(CNTL.cacc or ssr_freeze);
asf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
abo_nonres := '0';
abo_length := '0';
abo_rdonly := '0';
doabort := '0';
dotrap := '0';
if SARSDR.ed = '0' then -- ed=0: upward expansion
if unsigned(bn) > unsigned(SARSDR.slf) then
abo_length := '1';
end if;
else -- ed=0: downward expansion
if unsigned(bn) < unsigned(SARSDR.slf) then
abo_length := '1';
end if;
end if;
case SARSDR.acf is -- evaluate accecc control field
when "000" => -- segment non-resident
abo_nonres := '1';
when "001" => -- read-only; trap on read
if CNTL.wacc='1' or CNTL.macc='1' then
abo_rdonly := '1';
end if;
dotrap := '1';
when "010" => -- read-only
if CNTL.wacc='1' or CNTL.macc='1' then
abo_rdonly := '1';
end if;
when "100" => -- read/write; trap on read&write
dotrap := '1';
when "101" => -- read/write; trap on write
dotrap := CNTL.wacc or CNTL.macc;
when "110" => null; -- read/write;
when others => -- unused codes: abort access
abo_nonres := '1';
end case;
if IBSEL_SSR0='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres);
nssr0.abo_length := IB_MREQ.din(ssr0_ibf_abo_length);
nssr0.abo_rdonly := IB_MREQ.din(ssr0_ibf_abo_rdonly);
nssr0.trap_mmu := IB_MREQ.din(ssr0_ibf_trap_mmu);
nssr0.ena_trap := IB_MREQ.din(ssr0_ibf_ena_trap);
end if;
if IB_MREQ.be0 = '1' then
nssr0.ena_mmu := IB_MREQ.din(ssr0_ibf_ena_mmu);
end if;
elsif nssr0.ena_mmu='1' and CNTL.cacc='0' then
if dotrace = '1' then
if MONI.istart = '1' then
nssr0.inst_compl := '0';
elsif MONI.idone = '1' then
nssr0.inst_compl := '0'; -- disable instr.compl logic
end if;
end if;
if CNTL.req = '1' then
AIB_WE <= '1';
if ssr_freeze = '0' then
nssr0.abo_nonres := abo_nonres;
nssr0.abo_length := abo_length;
nssr0.abo_rdonly := abo_rdonly;
end if;
doabort := abo_nonres or abo_length or abo_rdonly;
if doabort = '0' then
AIB_SETA <= '1';
AIB_SETW <= CNTL.wacc or CNTL.macc;
end if;
if ssr_freeze = '0' then
nssr0.dspace := DSPACE;
nssr0.seg_num := asf;
nssr0.seg_mode := CNTL.mode;
end if;
end if;
end if;
if CNTL.req='1' and R_SSR0.ena_mmu='1' and CNTL.cacc='0' and
dotrap='1' then
nssr0.trap_mmu := '1';
end if;
nssr0.trace_prev := dotrace;
if MONI.trace_prev = '0' then
TRACE <= dotrace;
else
TRACE <= R_SSR0.trace_prev;
end if;
N_SSR0 <= nssr0;
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' then
STAT.vaok <= not doabort;
else
STAT.vaok <= '1';
end if;
if R_SSR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
R_SSR0.ena_trap='1' and R_SSR0.trap_mmu='0' and dotrap='1' then
STAT.trap <= '1';
else
STAT.trap <= '0';
end if;
STAT.ena_mmu <= R_SSR0.ena_mmu;
STAT.ena_22bit <= R_SSR3.ena_22bit;
STAT.ena_ubmap <= R_SSR3.ena_ubmap;
end process proc_nssr0;
end syn;
|
gpl-2.0
|
1b3c66ad34219b3afeba4bc9acf4ec3e
| 0.548182 | 3.157676 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rbd_timer.vhd
| 2 | 4,633 |
-- $Id: rbd_timer.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_timer - syn
-- Description: rbus dev: usec precision timer
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-29 351 12.1 M53d xc3s1000-4 19 63 - 34 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbbbb time r/w/- Timer register
-- w: if > 0 timer is running
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
entity rbd_timer is -- rbus dev: usec precision timer
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#00000000#,8)));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DONE : out slbit; -- 1 cycle pulse when expired
BUSY : out slbit -- timer running
);
end entity rbd_timer;
architecture syn of rbd_timer is
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
timer : slv16; -- timer value
timer_act : slbit; -- timer active flag
timer_end : slbit; -- timer done flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- timer
'0','0' -- timer_act,timer_end
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, RB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_dout := (others=>'0');
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr=RB_ADDR then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := RB_MREQ.re or RB_MREQ.we;
if RB_MREQ.we = '1' then
n.timer := RB_MREQ.din;
n.timer_act := '1';
end if;
if RB_MREQ.re = '1' then
irb_dout := r.timer;
end if;
end if;
-- timer logic
-- count down when active and 'on-the-usec'
n.timer_end := '0'; -- ensure end is 1 cycle pulse
if CE_USEC = '1' then -- if at usec
if r.timer_act = '1' then -- if timer active
if unsigned(r.timer) = 0 then -- if timer at end
n.timer_act := '0'; -- mark unactive
n.timer_end := '1'; -- send end marker
else -- else: timer not at end
n.timer := slv(unsigned(r.timer) - 1); -- decrement
end if;
end if;
end if;
N_REGS <= n;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= '0';
RB_SRES.busy <= '0';
DONE <= r.timer_end;
BUSY <= r.timer_act;
end process proc_next;
end syn;
|
gpl-2.0
|
2054ddd33fa0690cb44090b1b14d9d01
| 0.5109 | 3.656669 | false | false | false | false |
freecores/w11
|
rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd
| 2 | 4,798 |
-- $Id: tbd_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_nx_cram_memctl_as - syn
-- Description: Wrapper for nx_cram_memctl_as to avoid records & generics.
-- It has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: nx_cram_memctl_as
-- To test: nx_cram_memctl_as
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 122 0 107 t 11.4
-- 2010-05-30 297 11.4 L68 xc3s1200e-4 91 99 0 95 t 13.1
--
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_memctl
-- 2010-06-03 298 1.0.1 add hack to force IOB'FFs to O_MEM_ADDR
-- 2010-05-30 297 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity tbd_nx_cram_memctl_as is -- CRAM driver (async mode) [tb design]
-- generic: READ0=2;READ1=2;WRITE=3
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tbd_nx_cram_memctl_as;
architecture syn of tbd_nx_cram_memctl_as is
signal ADDR_X : slv22 := (others=>'0');
begin
-- Note: This is a HACk to ensure that the IOB flops are on the O_MEM_ADDR
-- pins. Without par might choose to use IFF's on ADDR, causing varying
-- routing delays to O_MEM_ADDR. Didn't find a better way, setting
-- iob "false" attributes in ADDR didn't help.
-- This logic doesn't hurt, and prevents that IFFs for ADDR compete with
-- OFF's for O_MEM_ADDR.
ADDR_X <= ADDR when RESET='0' else (others=>'0');
MEMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => 2,
READ1DELAY => 2,
WRITEDELAY => 3)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR_X,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
|
gpl-2.0
|
56abe87284cd5e0dd70b22d18d4f1395
| 0.52897 | 3.395612 | false | false | false | false |
dumpram/zedboard-ofdm
|
vhdl/dft_out_fsm.vhd
| 1 | 2,709 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity dft_out_fsm is
port (
reset : in std_logic;
clk : in std_logic;
dft_ce : out std_logic;
dft_dout : in std_logic_vector(31 downto 0);
dft_fd_out : in std_logic;
fifo_data : out std_logic_vector(31 downto 0);
fifo_wr_en : out std_logic;
fifo_wr_count : in std_logic_vector(9 downto 0);
fifo_watchdog_reset : out std_logic
);
end dft_out_fsm;
architecture rtl of dft_out_fsm is
constant data_size : integer := 960;
constant fifo_size : integer := 1024;
type fsm is (rst, idle, fifo_wait, dft_out);
signal state : fsm := rst;
signal data_cnt : std_logic_vector(15 downto 0);
signal fifo_cnt_prev : std_logic_vector(9 downto 0);
begin
fifo_data <= dft_dout;
process(clk)
begin
if (clk'event and clk = '1') then
case state is
when rst =>
dft_ce <= '1';
fifo_wr_en <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
state <= idle;
when idle =>
dft_ce <= '1';
fifo_wr_en <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
if (dft_fd_out = '1') then
if (fifo_wr_count /= (fifo_wr_count'range => '0')) then
dft_ce <= '0';
state <= fifo_wait;
else
dft_ce <= '0';
fifo_wr_en <= '1';
state <= dft_out;
end if;
else
state <= idle;
end if;
when fifo_wait =>
dft_ce <= '0';
fifo_wr_en <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
if (to_integer(unsigned(fifo_wr_count)) > (fifo_size - data_size)) then
state <= fifo_wait;
else
fifo_wr_en <= '1';
dft_ce <= '1';
state <= dft_out;
end if;
when dft_out =>
dft_ce <= '1';
fifo_wr_en <= '1';
data_cnt <= data_cnt;
if (data_cnt /= (data_cnt'range => '0')) then
data_cnt <= data_cnt - '1';
state <= dft_out;
else
fifo_wr_en <= '0';
state <= idle;
end if;
when others =>
null;
end case;
if (reset = '1') then
state <= rst;
end if;
-- Watchdog control signal
if (fifo_wr_count /= fifo_cnt_prev) then
fifo_watchdog_reset <= '1';
fifo_cnt_prev <= fifo_wr_count;
else
fifo_watchdog_reset <= '0';
fifo_cnt_prev <= fifo_cnt_prev;
end if;
end if;
end process;
end rtl;
|
mit
|
be07d0613385dbf31aba39b0ee5e2d30
| 0.507198 | 3.259928 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
| 1 | 20,938 |
-- $Id: sys_w11a_s3.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_s3 - syn
-- Description: w11a test design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp1c
-- vlib/rbus/rb_sres_or_2
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_bram
-- vlib/s3board/s3_sram_dummy
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- bplib/s3board/s3_sram_memctl
-- ibus/ib_sres_or_2
-- ibus/ibdr_minisys
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II
-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II
-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II
-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II
-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II
-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK
-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK
-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK
-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK
-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK
-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK
-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK
-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK
-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16
-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK
-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK
-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL
-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK
-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3
-- 2011-11-19 427 1.4.3 now numeric_std clean
-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.4.1 use now sn_humanio
-- 2010-12-30 351 1.4 ported to rbv3
-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport
-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3
-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl
-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce
-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- add pm1 rs232 (usp) support
-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport
-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy
-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3)
-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes
-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys
-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames
-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust
-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg)
-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys
-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs
-- 2008-02-23 118 1.3.1 add _mem70
-- 2008-02-17 117 1.3 use ext. memory interface of _core;
-- use _cache + memctl or _bram (configurable)
-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)
-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET
-- add _ib_mux2
-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack
-- instanciate all parts directly
-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb
-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO
-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them
-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
--
-- w11a test design for s3board
-- w11a + rlink + serport
--
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_w11a_s3;
architecture syn of sys_w11a_s3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CPU_RESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal CACHE_CHIT : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
signal DISPREG : slv16 := (others=>'0');
constant rbaddr_core0 : slv8 := "00000000";
constant rbaddr_ibus : slv8 := "10000000";
constant rbaddr_hio : slv8 := "11000000";
begin
CLK <= I_CLK50; -- use 50MHz as system clock
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6, -- 64 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_OR => RB_SRES
);
RP2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
CORE : pdp11_core
port map (
CLK => CLK,
RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM_BRAM: if sys_conf_bram > 0 generate
signal HM_VAL_BRAM : slbit := '0';
begin
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => EM_MREQ.req,
HM_VAL => HM_VAL_BRAM,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end generate MEM_BRAM;
MEM_SRAM: if sys_conf_bram = 0 generate
CACHE: pdp11_cache
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
CHIT => CACHE_CHIT,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => HM_ENA,
HM_VAL => CACHE_CHIT,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
SRAM_CTL: s3_sram_memctl
port map (
CLK => CLK,
RESET => CPU_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR(17 downto 0),
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end generate MEM_SRAM;
IB_SRES_OR : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES_IBDR,
IB_SRES_OR => IB_SRES);
IBD_MINI : if false generate
begin
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG);
end generate IBD_MINI;
IBD_MAXI : if true generate
begin
IBDR_SYS : ibdr_maxisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG);
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= CACHE_CHIT;
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
77f7874ee61f1824069b1c3b74cd59ff
| 0.517671 | 2.910076 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.