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|---|---|---|---|---|---|---|---|---|---|---|---|---|
scottlbaker/Nova-SOC
|
src/mytypes.vhd
| 1 | 5,488 |
--========================================================================
-- mytypes.vhd :: Nova global type definitions
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
package my_types IS
--=======================================
-- opcode formats
--=======================================
type OP_FORMAT_TYPE is (
ALU_FORMAT,
MEM_FORMAT,
LDA_FORMAT,
STA_FORMAT,
IOU_FORMAT,
EXT_FORMAT,
UII_FORMAT
);
--=======================================
-- Addressing modes
--=======================================
type ADDR_MODE_TYPE is (
ADM_OK,
ADM_EA
);
--=======================================
-- ALU operations
--=======================================
type ALU_OP_TYPE is (
COM, -- complement
NEG, -- negate
INC, -- increment
DEC, -- decrement
ADC, -- add complement
SUB, -- subtract
ADD, -- add
ANA, -- logical and
TA -- transfer A
);
--=======================================
-- Shifter control
--=======================================
type SHIFT_CTL_TYPE is (
NOP, -- no shift
LEFT, -- shift left
RIGHT, -- shift right
SWAP -- swap hi and lo bytes
);
--=======================================
-- Carry control
--=======================================
type CARRY_CTL_TYPE is (
NOP, -- no change
CLEAR, -- clear carry
SET, -- set carry
INVERT -- invert carry
);
--=======================================
-- Skip control
--=======================================
type SKIP_CTL_TYPE is (
NOP, -- no skip
SKP, -- skip
SKC, -- skip if carry zero
SNC, -- skip if carry non-zero
SZR, -- skip if result zero
SNR, -- skip if result non-zero
SEZ, -- skip if either zero
SBN, -- skip if both non-zero
SKPBN, -- skip if busy is set
SKPBZ, -- skip if busy is zero
SKPDN, -- skip if done is set
SKPDZ, -- skip if done is zero
SKPIE, -- skip if Int enabled
SKPID, -- skip if Int disabled
SKPPF, -- skip if power failed
SKPPO -- skip if power OK
);
--=======================================
-- Program flow-control functions
--=======================================
type FLOW_CTL_TYPE is (
JMP, -- jump to address
JSR, -- jump to subroutine
ISZ, -- incr and skip if zero
DSZ -- decr and skip if zero
);
--=======================================
-- address index control
--=======================================
type IDX_CTL_TYPE is (
ZPG, -- page zero
REL, -- PC relative
IDX2, -- index reg 2
IDX3 -- index reg 3
);
--=======================================
-- address index control
--=======================================
type XFER_CTL_TYPE is (
NOP, -- no I/O transfer
DIA, -- data in from buffer A
DOA, -- data out to buffer A
DIB, -- data in from buffer B
DOB, -- data out to buffer B
DIC, -- data in from buffer C
DOC, -- data out to buffer C
SKP -- skip on condition
);
--=======================================
-- I/O Unit control
--=======================================
type IOU_CTL_TYPE is (
NOP, -- no operation
SBCD, -- set busy; clear done
CBCD, -- clear busy and done
PULSE -- issue a pulse
);
--=======================================
-- Extended opcodes
--=======================================
type EXT_OP_TYPE is (
MUL, -- unsigned multiply
DIV, -- unsigned divide
MULS, -- signed multiply
DIVS, -- signed divide
SAV, -- save registers to stack
RET, -- return from subroutine
PSHA, -- push accumulator
POPA, -- push accumulator
MTSP, -- move to stack pointer
MFSP, -- move from stack pointer
MTFP, -- move to frame pointer
MFFP, -- move from frame pointer
LDB, -- load byte
STB, -- store byte
NOP -- no operation
);
--=======================================
-- Address adder operations
--=======================================
type SX_OP_TYPE is (
REL, -- Relative
INC2, -- Increment by 2
INC1, -- Increment by 1
DEC1 -- Decrement by 1
);
END my_types;
|
gpl-3.0
|
612c30d0bbb74c5241361378b9a04679
| 0.326531 | 5.692946 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/SyncAsyncReset.vhd
| 2 | 2,939 |
-------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
begin
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2,
kResetPolarity => kPolarity) --use double FF synchronizer
port map (
aReset => aRst,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
|
mit
|
3cf28d39158832d0101f95df8edd21be
| 0.654985 | 4.810147 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/AD96xx_92xx_RegisterDecode.vhd
| 1 | 22,047 |
-------------------------------------------------------------------------------
--
-- File: AD96xx_92xx_RegisterDecode.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module implements the register set for the AD96xx and AD92xx
-- simulation models
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.PkgZmodADC.all;
entity AD96xx_92xx_RegisterDecode is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0;
-- Register address width
kAddrWidth : integer range 0 to 32 := 13;
-- Register data width: only 8 data bits currently supported
kRegDataWidth : integer range 0 to 32 := 8
);
Port (
-- 100MHZ clock input
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous reading for register address x01
InsertError : in STD_LOGIC;
-- Signal indicating that the data phase of he register write SPI transaction is completed and aDataDecode is valid
sDataWriteDecodeReady : in STD_LOGIC;
-- Signal indicating that the address phase of the SPI transaction is completed and aAddrDecode is valid
sAddrDecodeReady : in STD_LOGIC;
-- Input register data used to update internal egister values for write register operations
sDataDecode : in STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0);
-- Register address input
sAddrDecode : in STD_LOGIC_VECTOR (kAddrWidth-1 downto 0);
-- Output register data produced by this module upon address decode for register read operations
sRegDataOut : out STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0)
);
end AD96xx_92xx_RegisterDecode;
architecture Behavioral of AD96xx_92xx_RegisterDecode is
signal sAddrDecodeReadyPulse, sAddrDecodeReadyDly : std_logic := '0';
signal sDataWriteDecodeReadyPulse, sDataWriteDecodeReadyDly : std_logic := '0';
signal sReg00 : std_logic_vector(7 downto 0) := x"18";
signal sReg01 : std_logic_vector(7 downto 0) := SelADC_ID(kZmodID);
signal sReg02 : std_logic_vector(7 downto 0) := SelADC_Grade(kZmodID);
signal sReg05 : std_logic_vector(7 downto 0) := x"03";
signal sRegFF : std_logic_vector(7 downto 0) := x"00";
signal sReg08ChA : std_logic_vector(7 downto 0) := x"00";
signal sReg08ChB : std_logic_vector(7 downto 0) := x"00";
signal sReg09 : std_logic_vector(7 downto 0) := x"01";
signal sReg0B : std_logic_vector(7 downto 0) := x"00";
signal sReg0C : std_logic_vector(7 downto 0) := x"00";
signal sReg0DChA : std_logic_vector(7 downto 0) := x"00";
signal sReg0DChB : std_logic_vector(7 downto 0) := x"00";
signal sReg10ChA : std_logic_vector(7 downto 0) := x"00";
signal sReg10ChB : std_logic_vector(7 downto 0) := x"00";
signal sReg14ChA : std_logic_vector(7 downto 0) := x"00";
signal sReg14ChB : std_logic_vector(7 downto 0) := x"00";
signal sReg15 : std_logic_vector(7 downto 0) := x"00";
signal sReg16 : std_logic_vector(7 downto 0) := x"00";
signal sReg17 : std_logic_vector(7 downto 0) := x"00";
signal sReg18 : std_logic_vector(7 downto 0) := x"04";
signal sReg19 : std_logic_vector(7 downto 0) := x"00";
signal sReg1A : std_logic_vector(7 downto 0) := x"00";
signal sReg1B : std_logic_vector(7 downto 0) := x"00";
signal sReg1C : std_logic_vector(7 downto 0) := x"00";
signal sReg2A : std_logic_vector(7 downto 0) := x"01";
signal sReg2EChA : std_logic_vector(7 downto 0) := x"01";
signal sReg2EChB : std_logic_vector(7 downto 0) := x"01";
signal sReg3A : std_logic_vector(7 downto 0) := x"01";
signal sReg100 : std_logic_vector(7 downto 0) := x"00";
signal sReg101 : std_logic_vector(7 downto 0) := x"80";
signal sReg102 : std_logic_vector(7 downto 0) := x"00";
signal sReg00_TimerRst_n : std_logic;
signal sResetReg00 : std_logic;
signal sReg00_Timer : unsigned (24 downto 0);
signal sAddrAux : integer range 0 to 511;
begin
sAddrAux <= to_integer (unsigned (std_logic_vector'((sAddrDecode))));
-- The following section generates a pulse when sAddrDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI read transaction is
-- completed and that sAddrDecode contains valid data.
ProcAddrDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sAddrDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sAddrDecodeReadyDly <= sAddrDecodeReady;
end if;
end process;
sAddrDecodeReadyPulse <= sAddrDecodeReady and (not sAddrDecodeReadyDly);
-- Timer used to reset the soft reset bit of the SPI port config register
-- (Reg00).
ProcReg00Timer: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg00_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sReg00_TimerRst_n = '0') then
sReg00_Timer <= (others => '0');
else
sReg00_Timer <= sReg00_Timer + 1;
end if;
end if;
end process;
-- If the soft reset bit of Reg00 is set over the command interface, it is reset by the
-- AD96xx when the reset operation completes. The maximum amount of time in reality is
-- 290ms, but for the purposes of this simulation model it is only 1us.
ProcResetReg00: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sResetReg00 <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg00_Timer = kCountResetResumeSim) then
sResetReg00 <= '1';
else
sResetReg00 <= '0';
end if;
end if;
end process;
-- Process managing register read operations
ReadRegister: process(SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRegDataOut <= (others => '0');
elsif (rising_edge (SysClk100)) then
if (sAddrDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "0000000000000" =>
sRegDataOut <= sReg00;
when "0000000000001" =>
if (InsertError = '0') then
sRegDataOut <= sReg01;
else
sRegDataOut <= x"00";
end if;
when "0000000000010" =>
sRegDataOut <= sReg02;
when "0000000000101" =>
sRegDataOut <= sReg05;
when "0000011111111" =>
sRegDataOut <= sRegFF;
when "0000000001000" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x08) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg08ChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg08ChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x08) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010001" =>
sRegDataOut <= sReg09;
when "0000000001011" =>
sRegDataOut <= sReg0B;
when "0000000001100" =>
sRegDataOut <= sReg0C;
when "0000000001101" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x0D) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg0DChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg0DChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x0D) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010000" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x10) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg10ChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg10ChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x10) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010100" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg14ChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg14ChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010101" =>
sRegDataOut <= sReg15;
when "0000000010110" =>
sRegDataOut <= sReg16;
when "0000000010111" =>
sRegDataOut <= sReg17;
when "0000000011000" =>
sRegDataOut <= sReg18;
when "0000000011001" =>
sRegDataOut <= sReg19;
when "0000000011010" =>
sRegDataOut <= sReg1A;
when "0000000011011" =>
sRegDataOut <= sReg1B;
when "0000000011100" =>
sRegDataOut <= sReg1C;
when "0000000101010" =>
sRegDataOut <= sReg2A;
when "0000000101110" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg2EChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg2EChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000111010" =>
sRegDataOut <= sReg3A;
when "0000100000000" =>
sRegDataOut <= sReg100;
when "0000100000001" =>
sRegDataOut <= sReg101;
when "0000100000010" =>
sRegDataOut <= sReg102;
when others =>
sRegDataOut <= x"00";
report "Invalid Read Address." & LF & HT & HT
severity ERROR;
end case;
end if;
end if;
end process ReadRegister;
-- The following section generates a pulse when sDataWriteDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI write transaction is
-- completed and that sAddrDecode contains valid data.
ProcDataDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDataWriteDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sDataWriteDecodeReadyDly <= sDataWriteDecodeReady;
end if;
end process;
sDataWriteDecodeReadyPulse <= sDataWriteDecodeReady and (not sDataWriteDecodeReadyDly);
-- Process managing register write operations (Reg00 is treated separately).
WriteRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg01 <= SelADC_ID(kZmodID);
sReg02 <= SelADC_Grade(kZmodID);
sReg05 <= x"03";
sRegFF <= x"00";
sReg08ChA <= x"00";
sReg08ChB <= x"00";
sReg09 <= x"01";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0DChA <= x"00";
sReg0DChB <= x"00";
sReg10ChA <= x"00";
sReg10ChB <= x"00";
sReg14ChA <= x"00";
sReg14ChB <= x"00";
sReg15 <= x"00";
sReg16 <= x"00";
sReg17 <= x"00";
sReg18 <= x"04";
sReg19 <= x"00";
sReg1A <= x"00";
sReg1B <= x"00";
sReg1C <= x"00";
sReg2A <= x"01";
sReg2EChA <= x"01";
sReg2EChB <= x"01";
sReg3A <= x"01";
sReg100 <=x"00";
sReg101 <= x"80";
sReg102 <= x"00";
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "0000000000000" =>
--Reg00 treated separately
when "0000000000001" =>
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when "0000000000010" =>
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when "0000000000101" =>
sReg05 <= sDataDecode;
when "0000011111111" =>
--The transfer register auto clears in an unspecified amount
--of time. For the IP simulation purpose this register can be
--considered constant (x"00").
--sRegFF <= sDataDecode;
when "0000000001000" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x08) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg08ChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg08ChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg08ChA <= sDataDecode;
sReg08ChB <= sDataDecode;
end if;
when "0000000010001" =>
sReg09 <= sDataDecode;
when "0000000001011" =>
sReg0B <= sDataDecode;
when "0000000001100" =>
sReg0C <= sDataDecode;
when "0000000001101" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x0D) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg0DChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg0DChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg0DChA <= sDataDecode;
sReg0DChB <= sDataDecode;
end if;
when "0000000010000" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x10) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg10ChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg10ChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg10ChA <= sDataDecode;
sReg10ChB <= sDataDecode;
end if;
when "0000000010100" =>
sReg14ChA(1 downto 0) <= sDataDecode(1 downto 0);
sReg14ChB(1 downto 0) <= sDataDecode(1 downto 0);
sReg14ChA(3) <= sDataDecode(3);
sReg14ChB(3) <= sDataDecode(3);
sReg14ChA(7 downto 5) <= sDataDecode(7 downto 5);
sReg14ChB(7 downto 5) <= sDataDecode(7 downto 5);
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x10) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg14ChA(2) <= sDataDecode(2);
sReg14ChA(4) <= sDataDecode(4);
elsif (sReg05(1 downto 0) = "10") then
sReg14ChB(2) <= sDataDecode(2);
sReg14ChB(4) <= sDataDecode(4);
elsif (sReg05(1 downto 0) = "11") then
sReg14ChA(2) <= sDataDecode(2);
sReg14ChA(4) <= sDataDecode(4);
sReg14ChB(2) <= sDataDecode(2);
sReg14ChB(4) <= sDataDecode(4);
end if;
when "0000000010101" =>
sReg15 <= sDataDecode;
when "0000000010110" =>
sReg16 <= sDataDecode;
when "0000000010111" =>
sReg17 <= sDataDecode;
when "0000000011000" =>
sReg18 <= sDataDecode;
when "0000000011001" =>
sReg19 <= sDataDecode;
when "0000000011010" =>
sReg1A <= sDataDecode;
when "0000000011011" =>
sReg1B <= sDataDecode;
when "0000000011100" =>
sReg1C <= sDataDecode;
when "0000000101010" =>
sReg2A <= sDataDecode;
when "0000000101110" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x2E) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg2EChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg2EChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg2EChA <= sDataDecode;
sReg2EChB <= sDataDecode;
end if;
when "0000000111010" =>
sReg3A <= sDataDecode;
when "0000100000000" =>
sReg100 <= sDataDecode;
when "0000100000001" =>
sReg101 <= sDataDecode;
when "0000100000010" =>
sReg102 <= sDataDecode;
when others =>
report "Invalid Write Address." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end case;
end if;
end if;
end process WriteRegister;
-- Process managing register write operation for Reg00 individually
WriteRegister00: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg00 <= x"18";
sReg00_TimerRst_n <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReady = '1') then
if (sAddrDecode = "0000000000000") then
sReg00 <= sReg00 or (sDataDecode and aReg00_Mask);
if (sDataDecode(5) = '1' and sDataDecode(2) = '1') then
sReg00_TimerRst_n <= '1';
elsif (sDataDecode(5) = '1' and sDataDecode(2) = '0') then
report "Reg00 bit 5 and 2 must be mirrored." & LF & HT & HT
severity ERROR;
elsif (sDataDecode(5) = '0' and sDataDecode(2) = '1') then
report "Reg00 bit 5 and 2 must be mirrored." & LF & HT & HT
severity ERROR;
end if;
end if;
elsif (sResetReg00 = '1') then
sReg00(5) <= '0';
sReg00(2) <= '0';
sReg00_TimerRst_n <= '0';
end if;
end if;
end process WriteRegister00;
end Behavioral;
|
mit
|
a6ed4f3760369048072999a6047ea4f9
| 0.561618 | 4.279309 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
comparator/com_dataflow_1/com_dataflow_1.vhd
| 1 | 641 |
entity COM is
--generic (D:time);
port (N1, N0, M1, M0: in bit;
GE, LE, E, G, L: out bit);
end COM;
--
-- Optimum two-level product of sums data flow model.
--
architecture POSDF of COM is
signal Z1,Z0: bit;
begin
Z1 <= (not N0 or M1 or M0) and (not N1 or M1) and
(not N1 or not N0 or M0);
Z0 <= (N1 or N0 or not M0) and (N1 or not M1) and
(N0 or not M1 or not M0);
LE <= Z1; --after D;
GE <= Z0; --after D;
E <= Z1 and Z0; --after D;
G <= Z0 and not Z1; --after D;
L <= Z1 and not Z0; --after D;
end POSDF;
--Figure 8.12 VHDL description of data flow model for device COM.
|
mit
|
b5923593b7b6f8f01df560954a390edd
| 0.563183 | 2.553785 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/tb_TestConfigADC.vhd
| 1 | 7,773 |
-------------------------------------------------------------------------------
--
-- File: tb_TestConfigADC.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to illustrate the ConfigADC module behavior.
-- It does not represent an extensive test of the module. The external
-- indirect access SPI interface is not used. The AD96xx_92xxSPI_Model is however
-- requested to deliberately insert an error on the InsertError port to test
-- the response of the configuration state machine error reporting circuitry.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity tb_TestConfigADC is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 1;
kADC_ClkDiv : integer range 1 to 8 := 4
);
end tb_TestConfigADC;
architecture Behavioral of tb_TestConfigADC is
signal SysClk100 : std_logic := '1';
signal asRst_n : std_logic := '0';
signal sSPI_Clk, sSDIO : std_logic := 'X';
signal sCS : std_logic := '1';
signal InsertError : std_logic;
signal sCmdTxAxisTvalid : std_logic;
signal sCmdTxAxisTready : std_logic;
signal sCmdTxAxisTdata : std_logic_vector(31 downto 0);
signal sCmdRxAxisTvalid : STD_LOGIC;
signal sCmdRxAxisTready : std_logic;
signal sCmdRxAxisTdata : std_logic_vector (31 downto 0);
signal sInitDoneADC : std_logic;
signal sConfigError : std_logic;
constant kSysClkPeriod : time := 10ns; -- System Clock Period
begin
ConfigADC_inst: entity work.ConfigADC
Generic Map(
kZmodID => kZmodID,
kADC_ClkDiv => kADC_ClkDiv,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth,
kSimulation => true
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneADC => sInitDoneADC,
sConfigError => sConfigError,
--AD9648 SPI interface signals
sADC_Sclk => sSPI_Clk,
sADC_SDIO => sSDIO,
sADC_CS => sCS,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
TestCmdFIFO: entity work.SPI_IAP_TestModule
Generic Map(
kZmodID => kZmodID
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneADC => sInitDoneADC,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
AD96xx_92xx_inst: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sSPI_Clk => sSPI_Clk,
sSDIO => sSDIO,
sCS => sCS
);
Clock: process
begin
for i in 0 to (kCount5ms*3) loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
Main: process
begin
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
asRst_n <= '0';
InsertError <= '0';
wait for 10 * kSysClkPeriod;
-- Signals are assigned at test bench level on the falling edge of SysClk100.
wait until falling_edge(SysClk100);
-- Release reset and perform the ADC initialization with no error inserted.
asRst_n <= '1';
-- Check if the sInitDoneADC signal is asserted and sConfigError is de-asserted
-- after the configuration timeout period (determined empirically)
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '1')
report "sInitDoneADC signal not asserted when expected" & LF & HT & HT
severity ERROR;
assert (sConfigError = '0')
report "sConfigError signal not de-asserted when expected" & LF & HT & HT
severity ERROR;
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
asRst_n <= '0';
wait for 10*kSysClkPeriod;
wait until falling_edge(SysClk100);
-- Request the ADI_2WireSPI_Model to deliberately insert a register read error.
InsertError <= '1';
asRst_n <= '1';
-- Check if the sInitDoneADC signal is de-asserted and sConfigError is asserted
-- after the configuration timeout period (determined empirically) in the case
-- of an erroneous response of the ADC
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '0')
report "sInitDoneADC signal is erroneously asserted" & LF & HT & HT
severity ERROR;
assert (sConfigError = '1')
report "sConfigError signal not asserted when expected" & LF & HT & HT
severity ERROR;
wait;
end process;
end Behavioral;
|
mit
|
3860a3732ea941106437dc5f11ad8960
| 0.645053 | 4.765788 | false | true | false | false |
SLongofono/digital-design-final-project
|
resetter.vhd
| 1 | 1,254 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity resetter is
port(
clk, rst : in std_logic;
address : out integer;
write : out std_logic
);
end resetter;
architecture Behavioral of resetter is
constant MAX_INDEX : integer := 307199;
type state is (idle, writing);
signal curr_state, next_state : state;
signal index : integer := 0;
begin
process(clk, rst)
begin
if('1' = rst) then
curr_state <= idle;
index <= 0;
elsif(rising_edge(clk)) then
curr_state <= next_state;
end if;
end process;
process(curr_state)
begin
next_state <= curr_state;
write <= '0';
case curr_state is
when idle =>
index <= 0;
-- Do nothing
when writing =>
-- increement the address to be written
index <= index + 1;
-- check if we need to keep going...
if(index > MAX_INDEX) then
next_state <= idle;
-- signal that we are still writing
write <= '1';
else
next_state <= writing;
end if;
end case;
end process;
address <= index;
end Behavioral;
|
mit
|
dcb48e93fc21e918788782970046d3ff
| 0.514354 | 4.111475 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/HS_Deserializer.vhd
| 1 | 18,889 |
-------------------------------------------------------------------------------
--
-- File: HS_Deserializer.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- HS_Deserializer instantiates 7-series-specific primitives for deserialization
-- of a high-speed data burst on a D-PHY data lane. Once enabled it looks
-- for the sync sequence (SoT) and performs necessary alignment to the byte
-- boundary. It outputs either valid de-serialized data, or reports a synchronization
-- error. It is expected to be clocked according to the clocking requirements
-- of the ISERDESE2 primitives.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.DPHY_types.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity HS_Deserializer is
Generic (
kIs8b9b : boolean := false;
kIDLY_TapWidth : natural := 5;
kAddDelay_ps : integer := 0;
kNoLP : boolean := false
);
Port (
dLP0_in : in std_logic_vector(7 downto 0);
dLP1_in : in std_logic_vector(7 downto 0);
dLP0_out : out std_logic_vector(7 downto 0);
dLP1_out : out std_logic_vector(7 downto 0);
SerClk : in STD_LOGIC; -- DDR serial clock
DivClk : in STD_LOGIC; -- SDR parallel clock; 1:8 factor => par clock = ser clock/4
aHSIn : in std_logic;
aLPIn : in std_logic_vector(1 downto 0);
aLPOut : out std_logic_vector(1 downto 0);
dDataOut8 : out std_logic_vector(7 downto 0); --if !kIs8b9b
dDataOut9 : out std_logic_vector(8 downto 0); --if kIs8b9b
dValid : out std_logic;
dSyncHard : out std_logic;
dSyncSoft : out std_logic;
dSyncErr : out std_logic;
--Control for phase alignment
CtlClk : in std_logic;
cIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
cIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
cIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
cIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in std_logic; -- should be de-asserted only when SerClk and DivClk are stable
aSettled : in std_logic --should be asserted when T_HS_SETTLE expired
);
end HS_Deserializer;
architecture Behavioral of HS_Deserializer is
constant kRefClkFreqInMHz : real := 200.0;
constant kAddDelayTaps : natural := natural(ceil(real(kAddDelay_ps) * (kRefClkFreqInMHz*2.0*32.0) / 1_000_000.0));
constant kDelayTaps : natural := 12 + kAddDelayTaps; -- 12*(1/(32*2*F_REF)) = 937.5 ps
function isSoftMatch(mask : std_logic_vector(7 downto 0); word : std_logic_vector(7 downto 0)) return boolean is
variable diff : std_logic_vector(7 downto 0);
variable sum : unsigned(3 downto 0) := "0000";
begin
diff := mask xor word;
SumDiff: for i in diff'high downto diff'low loop
sum := sum + unsigned(diff(i downto i));
end loop;
if (sum = 1) then
return true;
else
return false;
end if;
end isSoftMatch;
procedure findMatch (
constant mask : in std_logic_vector(7 downto 0); --sequence to find
signal word : in std_logic_vector(15 downto 0); --two words most significant first
variable hard : inout std_logic;
variable soft : inout std_logic;
variable alignment : inout natural range 0 to 7
) is
begin
hard := '0';
soft := '0';
--The sync word is constructed in such a way that either there is a match
--or a soft match with 1 bit error, but not both
FindHardLoop: for i in 0 to 7 loop
if (mask = word(i+7 downto i)) then
alignment := i;
hard := '1';
soft := '0';
end if;
end loop FindHardLoop;
if (hard = '0') then
FindSoftLoop: for i in 0 to 7 loop
if (isSoftMatch(mask, word(i+7 downto i))) then
alignment := i;
soft := '1';
end if;
end loop FindSoftLoop;
end if;
end procedure findMatch;
-- Synq sequence as written in the spec (most significant last)
constant kSyncSeq : std_logic_vector(7 downto 0) := "00011101";
signal DataInDly, SerClkInv : std_logic;
signal dDataIn_int : std_logic_vector(7 downto 0);
signal dDataIn_reg : vector8(0 to 3); --data byte pipeline for sync detection and alignment
signal dValid_reg : vector1(0 to 3); --sync flag pipeline
signal dSyncHard_int, dSyncSoft_int, dSyncErr_int : std_logic;
signal dSettled, dSerdesRst, dLogicRst: std_logic;
signal dAlignment_int : natural range 0 to 7 := 0;
signal wordToAlign : std_logic_vector(15 downto 0);
-- LP sampled at high-speed as a nibble
type dLP_t is array (0 to 1) of std_logic_vector(7 downto 0);
signal dLP : dLP_t;
signal dLPBridge, dLPStop : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of dLP: signal is "TRUE";
begin
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => kDelayTaps,
REFCLK_FREQUENCY => kRefClkFreqInMHz,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => DataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => CtlClk, -- Clock for control signals (CE,INC...)
CE => cIDLY_CE,
INC => cIDLY_INC,
IDATAIN => aHSIn, -- Driven by IOB
LD => cIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => cIDLY_CNT, -- current tap value
CINVCTRL => '0');
assert (not kIs8b9b) report "8b9b encoding not supported yet" severity failure;
--Invert locally for ISERDESE2
SerClkInv <= not SerClk;
-- De-serializer, 1:8 DDR, non-cascaded,
-- Least-significant first: bit sent first should be bit(0) in PPI byte
Deserializer: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 1,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER",
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
Q1 => dDataIn_int(0),
Q2 => dDataIn_int(1),
Q3 => dDataIn_int(2),
Q4 => dDataIn_int(3),
Q5 => dDataIn_int(4),
Q6 => dDataIn_int(5),
Q7 => dDataIn_int(6),
Q8 => dDataIn_int(7), -- bit sent first
SHIFTOUT1 => open, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => open, -- Cascade connection to Slave ISERDES
BITSLIP => '0', -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerClkInv, -- Locally inverted clock
CLKDIV => DivClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => DataInDly, -- 1-bit Input signal from IODELAYE1.
RST => dSerdesRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-- We need a reset bridge to use the asynchronous aRst signal to reset our
-- ISERDESE2
SerdesReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => DivClk,
oRst => dSerdesRst);
-- We do not have a lot of time to bring aSettled into the DivClk domain
-- T_HS_SETTLE_max = 145ns + 10*UI
-- T_HS_SETTLE_min = 85ns + 6*UI
-- aSettled measures 85ns, and we synchronize it with only one flip-flop
-- dSettled should be used downstream in simple combinational logic only
SyncAsyncSettled: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 1) --see above
port map (
aReset => not aSettled,
aIn => '1',
OutClk => DivClk,
oOut => dSettled);
-- LP de-serializer, 1:8 DDR, non-cascaded,
-- Although LP signals are low-speed and not synchronous with the HS clock, we need to detect LP
-- state changes as soon as possible due to tight timing between LP states and HS start.
UseOwnLP: if not kNoLP generate
LPxx: for i in 0 to 1 generate
LP_DeserializerX: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 1,
OFB_USED => "FALSE",
IOBDELAY => "NONE", -- combinatorial output = D, registered output = D
SERDES_MODE => "MASTER",
INIT_Q1 => '1',
INIT_Q2 => '1',
INIT_Q3 => '1',
INIT_Q4 => '1',
SRVAL_Q1 => '1',
SRVAL_Q2 => '1',
SRVAL_Q3 => '1',
SRVAL_Q4 => '1')
port map (
Q1 => dLP(i)(0),
Q2 => dLP(i)(1),
Q3 => dLP(i)(2),
Q4 => dLP(i)(3),
Q5 => dLP(i)(4),
Q6 => dLP(i)(5),
Q7 => dLP(i)(6),
Q8 => dLP(i)(7), -- bit sent first
SHIFTOUT1 => open, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => open, -- Cascade connection to Slave ISERDES
BITSLIP => '0', -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerClkInv, -- Locally inverted clock
CLKDIV => DivClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => aLPIn(i),
DDLY => '0', -- 1-bit Input signal from IODELAYE1.
RST => dSerdesRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => aLPOut(i)); -- unregistered output of ISERDESE1
end generate LPxx;
dLP0_out <= dLP(0);
dLP1_out <= dLP(1);
end generate UseOwnLP;
ShareLPFromOtherLane: if kNoLP generate
dLP(0) <= dLP0_in;
dLP(1) <= dLP1_in;
aLPOut <= aLPIn;
end generate ShareLPFromOtherLane;
-- We are in Bridge (or HS) state when we sampled 0 at least 2 times on both LP1 on and LP0
-- TODO: glitch filtering? problematic, because serial clock frequency changes dynamically
dLPBridge <= '1' when dLP(0)(1 downto 0) = "00" and dLP(1)(1 downto 0) = "00" else
'0';
-- We are in Stop state when we sampled 1 at least 2 times on both LP1 on and LP0
-- TODO: glitch filtering? problematic, because serial clock frequency changes dynamically
dLPStop <= '1' when dLP(0)(1 downto 0) = "11" and dLP(1)(1 downto 0) = "11" else
'0';
-- Logic should be held in reset for one more period, because ISERDES output
-- is only valid starting from the second DivClk period
process(DivClk, dSerdesRst)
variable dSerdesRst_q : std_logic;
begin
if (dSerdesRst = '1') then
dLogicRst <= '1';
dSerdesRst_q := '1';
elsif Rising_Edge(DivClk) then
if (dSerdesRst_q = '0' and dSettled = '1') then
dLogicRst <= '0';
elsif (dValid_reg(3) = '0') then
dLogicRst <= '1';
end if;
dSerdesRst_q := dSerdesRst;
end if;
end process;
-------------------------------------------------------------
-- Buffer data to detect sync sequence early enough
-------------------------------------------------------------
DataPipeline: process(DivClk)
begin
if Rising_Edge(DivClk) then
if dLogicRst = '1' then
dDataIn_reg <= (others => (others => '0'));
else
for i in dDataIn_reg'low to dDataIn_reg'high-1 loop
dDataIn_reg(i+1) <= dDataIn_reg(i);
end loop;
dDataIn_reg(0) <= dDataIn_int;
end if;
end if;
end process;
AlignFlagPipeline: process(DivClk)
begin
if Rising_Edge(DivClk) then
if dLogicRst = '1' then
dValid_reg <= (others => '0');
else
for i in 2 to dValid_reg'high-1 loop
dValid_reg(i+1) <= dValid_reg(i);
end loop;
dValid_reg(2) <= (dSyncHard_int or dSyncSoft_int) and not dLPStop;
end if;
end if;
end process;
wordToAlign <= dDataIn_reg(1) & dDataIn_reg(0);
process(DivClk)
variable nextMust : boolean;
variable hard, soft : std_logic;
variable alignment : natural range 0 to 7;
begin
if Rising_Edge(DivClk) then
if (dLogicRst = '1') then
dSyncHard_int <= '0';
dSyncSoft_int <= '0';
dAlignment_int <= 0;
dSyncErr_int <= '0';
nextMust := false;
elsif (dSyncHard_int = '0' and dSyncSoft_int = '0' and dSyncErr_int = '0') then
--If we are seeing ones in the early part of the word, or we saw ones in the latter part of the
--word in the previous period, we must find a sequence or error out
if (dDataIn_reg(0)(7 downto 4) /= "0000" or nextMust) then
findMatch(kSyncSeq, wordToAlign, hard, soft, alignment);
if (hard = '0' and soft = '0') then
dSyncErr_int <= '1';
end if;
dSyncHard_int <= hard;
dSyncSoft_int <= soft;
dAlignment_int <= alignment;
end if;
--If we are seeing ones, we must find the sequence in the next period
if (dDataIn_reg(0)(3 downto 0) /= "0000") then
nextMust := true;
end if;
end if;
end if;
end process;
dSyncErr <= dSyncErr_int;
dSyncHard <= dSyncHard_int;
dSyncSoft <= dSyncSoft_int;
-------------------------------------------------------------
-- Since the sync sequence is short and it is immediately followed by data, using
-- bitslip is out of question because it is slow and would lead to the loss of the first
-- words in the transmission
-------------------------------------------------------------
WordAlignment: process(DivClk)
constant kPos : natural := 3;
variable delay : natural range 0 to kPos := kPos;
begin
if Rising_Edge(DivClk) then
if (dValid_reg(kPos) = '0' or dLogicRst = '1') then
dDataOut8 <= (others => '0');
dValid <= '0';
else
case (dAlignment_int) is
-- 76543210|76543210|76543210
-- 00000000|00011101|abcdefgh
when 0 =>
dDataOut8 <= dDataIn_reg(kPos-1);
-- 00000000|0011101a|bcdefgha
when 1 =>
dDataOut8 <= dDataIn_reg(kPos)(0 downto 0) & dDataIn_reg(kPos-1)(7 downto 1);
-- 00000000|011101ab|cdefghab
when 2 =>
dDataOut8 <= dDataIn_reg(kPos)(1 downto 0) & dDataIn_reg(kPos-1)(7 downto 2);
-- 00000000|11101abc|defghabc
when 3 =>
dDataOut8 <= dDataIn_reg(kPos)(2 downto 0) & dDataIn_reg(kPos-1)(7 downto 3);
-- 00000001|1101abcd|efghabcd
when 4 =>
dDataOut8 <= dDataIn_reg(kPos)(3 downto 0) & dDataIn_reg(kPos-1)(7 downto 4);
-- 00000011|101abcde|fghabcde
when 5 =>
dDataOut8 <= dDataIn_reg(kPos)(4 downto 0) & dDataIn_reg(kPos-1)(7 downto 5);
-- 00000111|01abcdef|ghabcdef
when 6 =>
dDataOut8 <= dDataIn_reg(kPos)(5 downto 0) & dDataIn_reg(kPos-1)(7 downto 6);
-- 00001110|1abcdefg|habcdefg
when 7 =>
dDataOut8 <= dDataIn_reg(kPos)(6 downto 0) & dDataIn_reg(kPos-1)(7 downto 7);
end case;
dValid <= dValid_reg(kPos);
end if;
end if;
end process;
end Behavioral;
|
mit
|
e830091d82552d58fda11e08afd7474b
| 0.546403 | 4.024931 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/SyncBase.vhd
| 2 | 5,104 |
-------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous resets (aiReset, aoReset) are always
-- active-high, and they should not be asserted independently.
-- Changelog:
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with 2 RSD reset (asynchronous assertion, synchronous de-assertion)
-- signals (aiReset, aoReset).
-- 2022-Oct-05: Added Constraints section to header. Added keep_hierarchy
-- attribute to entity.
--
-- Constraints:
-- # Replace <InstSyncBase> with path to SyncAsync instance, keep rest unchanged
-- # Begin scope to SyncBase instance
-- current_instance [get_cells <InstSyncBase>]
-- # Input to synchronizer ignored for timing analysis
-- set_false_path -through [get_pins SyncAsyncx/aIn]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells SyncAsyncx/oSyncStages_reg[*]] -to [get_cells SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to SyncBase instance
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aiReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
aoReset : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of SyncBase : entity is "yes";
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aiReset, InClk)
begin
if (aiReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aoReset => aoReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
mit
|
e974dc473e02026cf129b2ca4529ca79
| 0.682994 | 4.473269 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/SyncAsync.vhd
| 2 | 4,870 |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aoReset) is always active-high.
-- Changelog:
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with an RSD reset (asynchronous assertion, synchronous de-assertion)
-- signal (aoReset).
-- 2022-Oct-05: Added Constraints section to header. Added keep_hierarchy
-- attribute to entity.
--
-- Constraints:
-- # Replace <InstSyncAsync> with path to SyncAsync instance, keep rest unchanged
-- # Begin scope to SyncAsync instance
-- current_instance [get_cells <InstSyncAsync>]
-- # Input to synchronizer ignored for timing analysis
-- set_false_path -through [get_ports -scoped_to_current_instance aIn]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells oSyncStages_reg[*]] -to [get_cells oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to SyncAsync instance
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aoReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of SyncAsync : entity is "yes";
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aoReset)
begin
if (aoReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
mit
|
86d16ccd3bcf2a2b7406bead148a92f8
| 0.692402 | 4.54291 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/tb/DataPathModel.vhd
| 1 | 3,981 |
-------------------------------------------------------------------------------
--
-- File: DataPathModel.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 20 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module emulates the latency of the data path associated with the
-- ZmodAWG1411_Controller (one register stage followed by an ODDR primitive).
-- The latency associated with the calibration block is modeled separately
-- by the CalibDataReference module.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DataPathModel is
Generic (
-- Number of register stages. Set to 2 to emulate the targeted
-- IP latency on the data path. Must be greater or equal to 2.
kLatency : integer range 2 to 2:= 2;
-- Channel data width
kDataWidth : integer := 14
);
Port (
DAC_Clk : in STD_LOGIC;
cCh1DataIn : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
cCh2DataIn : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
cDataOut : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0)
);
end DataPathModel;
architecture Behavioral of DataPathModel is
type cDlyArray_t is array (kLatency-1 downto 0) of std_logic_vector(kDataWidth-1 downto 0);
signal cCh1DataInDly, cCh2DataInDly : cDlyArray_t := (others => (others => '0'));
begin
-- Add kLatency register stages to the data path
ProcDelaySamplingClk : process (DAC_Clk)
begin
if (rising_edge(DAC_Clk)) then
cCh1DataInDly(0) <= cCh1DataIn;
cCh2DataInDly(0) <= cCh2DataIn;
for Index in 1 to kLatency-1 loop
cCh1DataInDly (Index) <= cCh1DataInDly (Index - 1);
cCh2DataInDly (Index) <= cCh2DataInDly (Index - 1);
end loop;
end if;
end process;
-- Emulate the ODDR primitive on the output of the ZmodAWG1411_Controller
ProcOutputData : process (DAC_Clk)
begin
if (rising_edge(DAC_Clk)) then
cDataOut <= cCh1DataInDly (kLatency-2);
elsif (falling_edge(DAC_Clk)) then
cDataOut <= cCh2DataInDly (kLatency-1);
end if;
end process;
end Behavioral;
|
mit
|
114afc0c61bcc893a2c1f5b2af3a765e
| 0.677217 | 4.433185 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
alu/alu.vhd
| 1 | 1,418 |
package PRIMS is
procedure ADD(A,B: in BIT_VECTOR; CIN: in BIT;
SUM: out BIT_VECTOR; COUT: out BIT);
end PRIMS;
package body PRIMS is
procedure ADD(A,B: in BIT_VECTOR; CIN: in BIT;
SUM: out BIT_VECTOR; COUT: out BIT) is
variable SUMV,AV,BV: BIT_VECTOR(A'LENGTH-1 downto 0);
variable CARRY: BIT;
begin
AV := A;
BV := B;
CARRY := CIN;
for I in 0 to SUMV'HIGH loop
SUMV(I) := AV(I) xor BV(I) xor CARRY;
CARRY := (AV(I) and BV(I)) or (AV(I) and CARRY)
or (BV(i) and CARRY);
end loop;
COUT := CARRY;
SUM := SUMV;
end ADD;
end PRIMS;
-- Figure 4.26 (continued)Data operations package
use work.PRIMS.all;
entity ALU is
-- generic(DEL: TIME);
port(A,B: in BIT_VECTOR(3 downto 0); CI: in BIT;
FSEL: in BIT_VECTOR(1 downto 0);
F: out BIT_VECTOR(3 downto 0); COUT: out BIT);
end ALU;
architecture ALG of ALU is
begin
process(A,B,CI,FSEL)
variable FV: BIT_VECTOR(3 downto 0);
variable COUTV: BIT;
begin
case FSEL is
when "00" => F <= A;-- after DEL;
when "01" => F <= not(A);-- after DEL;
when "10" => ADD(A,B,CI,FV,COUTV);
F <= FV;-- after DEL;
COUT <= COUTV;-- after DEL;
when "11" => F <= A and B;-- after DEL;
end case;
end process;
end ALG;
--Figure 4.27 ALU primitive.
|
mit
|
8ee1953733f2391fbe9ab2b6afcee7de
| 0.543724 | 3.102845 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/Divisor.vhd
| 1 | 1,096 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Divisor is
Port (
activacion: in STD_LOGIC;
entrada : in std_logic_vector (31 downto 0);
salida: out std_logic_vector (31 downto 0);
reset_cont: out std_logic);
end Divisor;
architecture Behavioral of Divisor is
signal sal: std_logic_vector (31 downto 0);
signal res: std_logic;
begin
process(activacion)
begin
if activacion='1' then
res<='1';
sal<=entrada;
else
res<='0';
end if;
end process;
salida<=sal;
reset_cont<=res;
end Behavioral;
|
gpl-2.0
|
9cca1b9bcc218231749f0c75e245539c
| 0.586679 | 4.04428 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/start_for_Mat2AXIvdy.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Mat2AXIvdy_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Mat2AXIvdy_shiftReg;
architecture rtl of start_for_Mat2AXIvdy_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Mat2AXIvdy is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Mat2AXIvdy is
component start_for_Mat2AXIvdy_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Mat2AXIvdy_shiftReg : start_for_Mat2AXIvdy_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
c57e351dee177fa2f4cde72c9a71d4c4
| 0.532962 | 3.549407 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/motor_puerta.vhd
| 1 | 718 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity motor_puerta is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
nivel : in STD_LOGIC;
celula : in STD_LOGIC;
accionar_puerta : in STD_LOGIC;
actuador_puerta : out STD_LOGIC);
end motor_puerta;
architecture Behavioral of motor_puerta is
begin
motor_puerta:process(RST,CLK)
begin
if (RST='1') then
actuador_puerta <= '0';
elsif rising_edge(CLK) then
if (accionar_puerta='1') then
actuador_puerta <= '1';
elsif (accionar_puerta='0' AND celula='1' AND nivel='1') then
actuador_puerta <= '1';
else actuador_puerta <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
e3bea60f45f84a28baff010c6cc6e384
| 0.640669 | 3.068376 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/tb/tb_TestTop.vhd
| 1 | 25,788 |
-------------------------------------------------------------------------------
--
-- File: tb_TestTop.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Top level test bench. This test bench does not extensively test all modules
-- of the ZmodAWG1411_Controller.
-- A simulation model is provided for the AD9717 DAC SPI interface to test
-- configuration registers read/write commands.
-- A command queue is loaded into an external FIFO to exercise the IP's SPI
-- indirect access port.
-- A ramp signal is used as stimulus for the data bus. The calibrated samples
-- output by the IP are compared against the expected values in order to test
-- the calibration functionality.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDAC.all;
entity tb_TestTop is
Generic (
-- Simulation system clock period
kSysClkPeriod : time := 10ns;
-- Simulation sampling clock period
kDacClkPeriod : time := 10ns;
-- DAC number of bits
kDAC_Width : integer := 14;
-- DAC dynamic/static calibration
kExtCalibEn : boolean := true;
-- Enable/Disable SPI Indirect Access Port
kExtCmdInterfaceEn : boolean := true;
kExtScaleConfigEn : boolean := true;
-- Channel1 low gain multiplicative (gain) compensation coefficient parameter
kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 low gain additive (offset) compensation coefficient parameter
kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 high gain additive (offset) compensation coefficient parameter
kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel2 low gain multiplicative (gain) compensation coefficient parameter
kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel2 low gain additive (offset) compensation coefficient parameter
kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter
kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel2 high gain additive (offset) compensation coefficient parameter
kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel1 Scale select satic control: 0 -> Low Gain; 1 -> High Gain;
kCh1ScaleStatic : std_logic := '0';
-- Channel2 Scale select satic control: 0 -> Low Gain; 1 -> High Gain;
kCh2ScaleStatic : std_logic := '0'
);
end tb_TestTop;
architecture Behavioral of tb_TestTop is
constant kNumClockCycles : integer := 5000000;
signal DAC_Clk, DAC_InIO_Clk : std_logic := '0';
signal SysClk100 : std_logic := '0';
signal aRst_n: std_logic;
signal sInitDoneDAC: std_logic;
signal sConfigError: std_logic;
signal cDataAxisTvalid: STD_LOGIC;
signal cDataAxisTready: STD_LOGIC;
signal cDataAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal cExtCh1LgMultCoef: std_logic_vector (17 downto 0);
signal cExtCh1LgAddCoef: std_logic_vector (17 downto 0);
signal cExtCh1HgMultCoef: std_logic_vector (17 downto 0);
signal cExtCh1HgAddCoef: std_logic_vector (17 downto 0);
signal cExtCh2LgMultCoef: std_logic_vector (17 downto 0);
signal cExtCh2LgAddCoef: std_logic_vector (17 downto 0);
signal cExtCh2HgAddCoef: std_logic_vector (17 downto 0);
signal cExtCh2HgMultCoef: std_logic_vector (17 downto 0);
signal sTestMode: std_logic;
signal sCmdTxAxisTvalid: STD_LOGIC;
signal sCmdTxAxisTready: STD_LOGIC;
signal sCmdTxAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sCmdRxAxisTvalid: STD_LOGIC;
signal sCmdRxAxisTready: STD_LOGIC;
signal sCmdRxAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sDAC_EnIn: std_logic;
signal sExtCh1Scale, sExtCh2Scale: std_logic;
signal sCh1Scale, sCh2Scale: std_logic;
signal sZmodDAC_CS: std_logic;
signal sZmodDAC_SCLK: std_logic;
signal sZmodDAC_SDIO: std_logic;
signal sZmodDAC_Reset: std_logic;
signal ZmodDAC_ClkIO: std_logic;
signal ZmodDAC_Clkin: std_logic;
signal dZmodDAC_Data: std_logic_vector(kDAC_Width-1 downto 0);
signal sZmodDAC_SetFS1: std_logic;
signal sZmodDAC_SetFS2: std_logic;
signal sZmodDAC_EnOut: std_logic;
signal cDAC_DataCh1 : std_logic_vector(kDAC_Width-1 downto 0);
signal cDAC_DataCh2 : std_logic_vector(kDAC_Width-1 downto 0);
signal cCh1_DataTest : std_logic_vector(kDAC_Width-1 downto 0);
signal cCh2_DataTest : std_logic_vector(kDAC_Width-1 downto 0);
signal cZmodDataTest : std_logic_vector(kDAC_Width-1 downto 0);
signal sCh1DataCheckValid : std_logic := '0';
signal sCh2DataCheckValid : std_logic := '0';
signal cZmodDAC_DataInt : integer;
signal cZmodDataTestInt : integer;
signal cDataDiff : integer;
signal cZmodDAC_DataCnt1 : unsigned(kDAC_Width-1 downto 0) := (others => '0');
signal cZmodDAC_DataCnt2 : unsigned(kDAC_Width-1 downto 0) := "10000000000000";
signal cDataGenCntEn1, cDataGenRst1_n : std_logic;
signal cDataGenCntEn2, cDataGenRst2_n : std_logic;
signal cZmodDataSel : std_logic_vector (2 downto 0);
constant kVal1 : std_logic_vector (15 downto 0) := x"AAAA";
constant kVal2 : std_logic_vector (15 downto 0) := x"5555";
constant kValMin : std_logic_vector (15 downto 0) := x"8000";
constant kValMax : std_logic_vector (15 downto 0) := x"7FFF";
constant tStart : time := 0ns;
constant kDAC_EnLatency : integer := 2;
-- Calibration coefficients use to test the external calibration interface.
-- Must be different values than those assigned as static parameters.
constant kExtCh1LgMultCoef: std_logic_vector (17 downto 0) := "001110111010010100";
constant kExtCh1LgAddCoef: std_logic_vector (17 downto 0) := "111111111010001100";
constant kExtCh1HgMultCoef: std_logic_vector (17 downto 0) := "001111000001101001";
constant kExtCh1HgAddCoef: std_logic_vector (17 downto 0) := "111111111101100111";
constant kExtCh2LgMultCoef: std_logic_vector (17 downto 0) := "001110111110011001";
constant kExtCh2LgAddCoef: std_logic_vector (17 downto 0) := "111111111100101000";
constant kExtCh2HgMultCoef: std_logic_vector (17 downto 0) := "001111001011010110";
constant kExtCh2HgAddCoef: std_logic_vector (17 downto 0) := "111111111110101101";
--
-- 2 stages SyncBase module latency for crossings from SysClk100 domain to
-- domain DAC_InIO_Clk
constant kSyncBaseLatency: time := kSysClkPeriod + 2*kDacClkPeriod;
begin
------------------------------------------------------------------------------------------
--Top level component instantiation
------------------------------------------------------------------------------------------
sCh1Scale <= sExtCh1Scale when kExtScaleConfigEn = true else kCh1ScaleStatic; --Channel1 AC/DC setting (output port or IP parameter)
sCh2Scale <= sExtCh2Scale when kExtScaleConfigEn = true else kCh2ScaleStatic; --Channel2 AC/DC setting (output port or IP parameter)
InstZmodDAC_Cotroller: entity work.ZmodAWG_1411_Controller
Generic Map(
kDAC_Width => kDAC_Width,
kExtCalibEn => kExtCalibEn,
kExtScaleConfigEn => kExtScaleConfigEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCh1ScaleStatic => kCh1ScaleStatic,
kCh2ScaleStatic => kCh2ScaleStatic
)
Port Map(
SysClk100 => SysClk100,
DAC_InIO_Clk => DAC_InIO_Clk,
DAC_Clk => DAC_Clk,
aRst_n => aRst_n,
sTestMode => sTestMode,
sInitDoneDAC => sInitDoneDAC,
sConfigError => sConfigError,
cDataAxisTvalid => cDataAxisTvalid,
cDataAxisTready => cDataAxisTready,
cDataAxisTdata => cDataAxisTdata,
sDAC_EnIn => sDAC_EnIn,
sExtCh1Scale => sExtCh1Scale,
sExtCh2Scale => sExtCh2Scale,
cExtCh1LgMultCoef => cExtCh1LgMultCoef,
cExtCh1LgAddCoef => cExtCh1LgAddCoef,
cExtCh1HgMultCoef => cExtCh1HgMultCoef,
cExtCh1HgAddCoef => cExtCh1HgAddCoef,
cExtCh2LgMultCoef => cExtCh2LgMultCoef,
cExtCh2LgAddCoef => cExtCh2LgAddCoef,
cExtCh2HgMultCoef => cExtCh2HgMultCoef,
cExtCh2HgAddCoef => cExtCh2HgAddCoef,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata,
sZmodDAC_CS => sZmodDAC_CS,
sZmodDAC_SCLK => sZmodDAC_SCLK,
sZmodDAC_SDIO => sZmodDAC_SDIO,
sZmodDAC_Reset => sZmodDAC_Reset,
ZmodDAC_ClkIO => ZmodDAC_ClkIO,
ZmodDAC_Clkin => ZmodDAC_Clkin,
dZmodDAC_Data => dZmodDAC_Data,
sZmodDAC_SetFS1 => sZmodDAC_SetFS1,
sZmodDAC_SetFS2 => sZmodDAC_SetFS2,
sZmodDAC_EnOut => sZmodDAC_EnOut
);
------------------------------------------------------------------------------------------
-- SPI test related modules instantiation
------------------------------------------------------------------------------------------
InstAD9717: entity work.AD9717_2WireSPI_Model
Generic Map(
kZmodID => 7,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => aRst_n,
InsertError => '0',
sSPI_Clk => sZmodDAC_Sclk,
sSDIO => sZmodDAC_SDIO,
sCS => sZmodDAC_CS
);
TestCmdFIFO: entity work.SPI_IAP_AD9717_TestModule
Generic Map(
kZmodID => 7
)
Port Map(
SysClk100 => SysClk100,
asRst_n => aRst_n,
sInitDoneDAC => sInitDoneDAC,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
------------------------------------------------------------------------------------------
-- Calibration test related modules instantiation
------------------------------------------------------------------------------------------
cDAC_DataCh1 <= cDataAxisTdata(31 downto 32-kDAC_Width);
cDAC_DataCh2 <= cDataAxisTdata(15 downto 16-kDAC_Width);
InstCalibDataReferenceCh1 : entity work.CalibDataReference
Generic Map (
kWidth => kDAC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => kCh1LgMultCoefStatic,
kLgAddCoefStatic => kCh1LgAddCoefStatic,
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic,
kInvert => false,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DAC_InIO_Clk,
cTestMode => sTestMode, -- sTestMode is constant in the current test bench
cChIn => cDAC_DataCh1,
cChOut => cCh1_DataTest,
cExtLgMultCoef => cExtCh1LgMultCoef,
cExtLgAddCoef => cExtCh1LgAddCoef,
cExtHgMultCoef => cExtCh1HgMultCoef,
cExtHgAddCoef => cExtCh1HgAddCoef,
cGainState => sCh1Scale);
InstCalibDataReferenceCh2 : entity work.CalibDataReference
Generic Map (
kWidth => kDAC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => kCh2LgMultCoefStatic,
kLgAddCoefStatic => kCh2LgAddCoefStatic,
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic,
kInvert => false,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DAC_InIO_Clk,
cTestMode => sTestMode, -- sTestMode is constant in the current test bench
cChIn => cDAC_DataCh2,
cChOut => cCh2_DataTest,
cExtLgMultCoef => cExtCh2LgMultCoef,
cExtLgAddCoef => cExtCh2LgAddCoef,
cExtHgMultCoef => cExtCh2HgMultCoef,
cExtHgAddCoef => cExtCh2HgAddCoef,
cGainState => sCh2Scale);
InstDataPathModel : entity work.DataPathModel
Generic Map(
kLatency => 2,
kDataWidth => 14
)
Port Map(
DAC_Clk => DAC_InIO_Clk,
cCh1DataIn => cCh1_DataTest,
cCh2DataIn => cCh2_DataTest,
cDataOut => cZmodDataTest
);
cZmodDAC_DataInt <= to_integer(signed(dZmodDAC_Data));
cZmodDataTestInt <= to_integer(signed(cZmodDataTest));
cDataDiff <= cZmodDataTestInt - cZmodDAC_DataInt;
------------------------------------------------------------------------------------------
-- Clock generation
------------------------------------------------------------------------------------------
ProcSystmClock: process
begin
for i in 0 to kNumClockCycles loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
ProcSamplingClk: process
begin
DAC_InIO_Clk <= '0';
for i in 0 to kNumClockCycles loop
wait for kDacClkPeriod/2;
DAC_InIO_Clk <= not DAC_InIO_Clk;
wait for kDacClkPeriod/2;
DAC_InIO_Clk <= not DAC_InIO_Clk;
end loop;
wait;
end process;
ProcDacClk: process
begin
DAC_Clk <= '1';
wait for kDacClkPeriod/4;
DAC_Clk <= '0';
for i in 0 to kNumClockCycles loop
wait for kDacClkPeriod/2;
DAC_Clk <= not DAC_Clk;
wait for kDacClkPeriod/2;
DAC_Clk <= not DAC_Clk;
end loop;
wait;
end process;
------------------------------------------------------------------------------------------
-- Stimuli generation
------------------------------------------------------------------------------------------
-- A ramp signal is used as stimulus for the DAC data bus
ProcDataGen1: process (DAC_InIO_Clk, aRst_n, cDataGenRst1_n)
begin
if ((aRst_n = '0') or (cDataGenRst1_n = '0')) then
cZmodDAC_DataCnt1 <= (others => '0');
elsif (falling_edge(DAC_InIO_Clk)) then
if (cDataGenCntEn1 = '1') then
cZmodDAC_DataCnt1 <= cZmodDAC_DataCnt1 + 1;
end if;
end if;
end process;
ProcDataGen2: process (DAC_InIO_Clk, aRst_n, cDataGenRst2_n)
begin
if ((aRst_n = '0') or (cDataGenRst2_n = '0')) then
cZmodDAC_DataCnt2 <= "10000000000000";
elsif (falling_edge(DAC_InIO_Clk)) then
if (cDataGenCntEn2 = '1') then
cZmodDAC_DataCnt2 <= cZmodDAC_DataCnt2 + 1;
end if;
end if;
end process;
-- Mux that allows selecting (simulating )different patters
-- on the DAC data interface.
ProcZmodDataMux: process (cZmodDAC_DataCnt1,cZmodDAC_DataCnt2, cZmodDataSel)
begin
case (cZmodDataSel) is
when ("000") =>
cDataAxisTdata <= kVal1 & kVal2;
when ("001") =>
cDataAxisTdata <= kVal2 & kVal1;
when ("010") =>
cDataAxisTdata <= std_logic_vector(cZmodDAC_DataCnt1) & "00" & std_logic_vector(cZmodDAC_DataCnt2) & "00";
when ("011") =>
cDataAxisTdata <= kValMin & kValMin;
when ("100") =>
cDataAxisTdata <= kValMax & kValMax;
when others =>
cDataAxisTdata <= std_logic_vector(cZmodDAC_DataCnt1) & "00" & std_logic_vector(cZmodDAC_DataCnt2) & "00";
end case;
end process;
ProcSysClkStimuli: process
begin
sDAC_EnIn <= '0';
sExtCh1Scale <= kCh1ScaleStatic;
sExtCh2Scale <= kCh2ScaleStatic;
aRst_n <= '0';
sTestMode <= '0';
-- Apply a reset condition.
wait for kSysClkPeriod;
wait until falling_edge(SysClk100);
aRst_n <= '1';
sDAC_EnIn <= '1';
wait until sInitDoneDAC = '1';
-- test sZmodDAC_EnOut response to sDAC_EnIn
wait for kDAC_EnLatency*kSysClkPeriod;
wait until falling_edge(SysClk100);
sDAC_EnIn <= '0';
wait for kDAC_EnLatency*kSysClkPeriod;
assert (sZmodDAC_EnOut = '0')
report "sZmodDAC_EnOut not responding to sDAC_EnIn command" & LF & HT & HT
severity ERROR;
sDAC_EnIn <= '1';
wait for kDAC_EnLatency*kSysClkPeriod;
assert (sZmodDAC_EnOut = '1')
report "sZmodDAC_EnOut not responding to sDAC_EnIn command" & LF & HT & HT
severity ERROR;
-- test sZmodDAC_SetFS1/2 initialization
assert (sZmodDAC_SetFS1 = kCh1ScaleStatic)
report "sZmodDAC_SetFS1 initialization error" & LF & HT & HT
severity ERROR;
assert (sZmodDAC_SetFS2 = kCh2ScaleStatic)
report "sZmodDAC_SetFS2 initialization error" & LF & HT & HT
severity ERROR;
-- test sZmodDAC_SetFS1/2 response to sExtCh1Scale
if (kExtScaleConfigEn = true) then
sExtCh1Scale <= '1';
sExtCh2Scale <= '1';
wait for kSysClkPeriod;
assert (sZmodDAC_SetFS1 = '1' and sZmodDAC_SetFS2 = '1')
report "sZmodDAC_SetFS1/2 not responding to sExtCh1/2Scale command" & LF & HT & HT
severity ERROR;
-- Test all possible sample values on the data path for this scale option (useful for the
-- calibration module test).
wait for (2**kDAC_Width)*kSysClkPeriod;
sExtCh1Scale <= '0';
sExtCh2Scale <= '0';
wait for kSysClkPeriod;
assert (sZmodDAC_SetFS1 = '0' and sZmodDAC_SetFS2 = '0')
report "sZmodDAC_SetFS1/2 not responding to sExtCh1/2Scale command" & LF & HT & HT
severity ERROR;
-- Test all possible sample values on the data path for this scale option.
wait for (2**kDAC_Width)*kSysClkPeriod;
sExtCh1Scale <= '1';
sExtCh2Scale <= '0';
wait for kSysClkPeriod;
assert (sZmodDAC_SetFS1 = '1' and sZmodDAC_SetFS2 = '0')
report "sZmodDAC_SetFS1/2 not responding to sExtCh1/2Scale command" & LF & HT & HT
severity ERROR;
-- Test all possible sample values on the data path for this scale option.
wait for (2**kDAC_Width)*kSysClkPeriod;
sExtCh1Scale <= '0';
sExtCh2Scale <= '1';
wait for kSysClkPeriod;
assert (sZmodDAC_SetFS1 = '0' and sZmodDAC_SetFS2 = '1')
report "sZmodDAC_SetFS1/2 not responding to sExtCh1/2Scale command" & LF & HT & HT
severity ERROR;
-- Test all possible sample values on the data path for this scale option.
wait for (2**kDAC_Width)*kSysClkPeriod;
end if;
wait;
end process;
ProcDacClkStimuli: process
begin
-- The coefficients assigned to the external calibration interface
-- use different values than those assigned as static parameters.
cExtCh1LgMultCoef <= kExtCh1LgMultCoef;
cExtCh1LgAddCoef <= kExtCh1LgAddCoef;
cExtCh1HgMultCoef <= kExtCh1HgMultCoef;
cExtCh1HgAddCoef <= kExtCh1HgAddCoef;
cExtCh2LgMultCoef <= kExtCh2LgMultCoef;
cExtCh2LgAddCoef <= kExtCh2LgAddCoef;
cExtCh2HgMultCoef <= kExtCh2HgMultCoef;
cExtCh2HgAddCoef <= kExtCh2HgAddCoef;
cDataGenCntEn1 <= '1';
cDataGenRst1_n <= '1';
cDataGenCntEn2 <= '1';
cDataGenRst2_n <= '1';
cDataAxisTvalid <= '1';
wait until sInitDoneDAC = '1';
-- A counter will be used to generate the input test data for the data path.
-- However, since a 1LSB error is tolerated so that the CalibDataReference can work
-- with real (floating point) values, synchronization problems may not be detected.
-- For this reason, at the beginning of the test 2 values that differ by more than
-- 1 LSB will be generated. By this means, the test assures that the data path and
-- GainOffsetCalib outputs are correctly synchronized with the CalibDataReference.
wait until falling_edge(DAC_InIO_Clk);
cZmodDataSel <= "000";
wait until falling_edge(DAC_InIO_Clk);
cZmodDataSel <= "001";
wait until falling_edge(DAC_InIO_Clk);
-- Test IP response for minimum negative and maximum positive input
cZmodDataSel <= "011";
wait until falling_edge(DAC_InIO_Clk);
cZmodDataSel <= "100";
-- Apply the ramp pattern on the IP's input.
wait until falling_edge(DAC_InIO_Clk);
cZmodDataSel <= "010";
wait;
end process;
-- Check if sZmodDAC_EnOut is disabled while sInitDoneDAC is de-asserted
ProcCheckEnOut: process
begin
assert (sInitDoneDAC = '0' or sZmodDAC_EnOut = '0')
report "sInitDoneDAC and sZmodDAC_EnOut incorrectly asserted after POR" & LF & HT & HT
severity ERROR;
wait until sInitDoneDAC = '1';
assert ((sZmodDAC_EnOut'delayed'last_event) > tStart)
report "sZmodDAC_EnOut asserted sooner than expected" & LF & HT & HT &
"Expected: " & time'image(now) & LF & HT & HT &
"Actual: " & time'image(sZmodDAC_EnOut'delayed'last_event)
severity ERROR;
wait for kDAC_EnLatency*kSysClkPeriod;
wait until falling_edge(SysClk100);
if (sDAC_EnIn = '1') then
assert (sZmodDAC_EnOut = '1')
report "sZmodDAC_EnOut not asserted when expected" & LF & HT & HT
severity ERROR;
end if;
wait;
end process;
-- Process that determines the conditions in which the output data of the
-- Zmod AWG 1411 Controller is invalid due to requested scale changes.
-- sCh1ScaleState, sCh2ScaleState need to be passed to the GainOffseCalib module
-- so that correct calibration coefficients can be applied to the input data
-- (in the ZmodAWG1411_Controller top module). Thus, sExtCh1Scale and sExtCh2Scale
-- need to cross clock domains from the SysClk100 domain to the DAC_InIO_Clk domain
-- where the GainOffseCalib module operates.
-- When the external scale configuration is enabled and an event occurs on
-- sExtCh1Scale/sExtCh2Scale it will propagate to the DAC_InIO_Clk clock domain
-- with a latency equal to kSyncBaseLatency.
-- Because the GainOffseCalib module consists of a 2 stage pipe, when the
-- sCh1ScaleState/sCh2ScaleState finally propagate to the DAC_InIO_Clk domain, it
-- will take another 2 extra DAC_InIO_Clk clock cycles for the calibration module
-- to produce correct data on its output. Due to the ODDR primitive, valid data can
-- be expected on the output in another 2 DAC_InIO_Clk cycles.
-- As a result, it is considered that the output data has unexpected values for
-- kSyncBaseLatency + 4*kDacClkPeriod. This process will not work if consecutive
-- changes on sCh1Scale/sCh2Scale occur at intervals less than
-- kSyncBaseLatency + 4*kDacClkPeriod!
ProcCh1DataCheckValid: process
begin
sCh1DataCheckValid <= '1';
wait until sCh1Scale'event;
sCh1DataCheckValid <= '0';
wait for kSyncBaseLatency + 4*kDacClkPeriod;
end process;
ProcCh2DataCheckValid: process
begin
sCh2DataCheckValid <= '1';
wait until sCh2Scale'event;
sCh2DataCheckValid <= '0';
wait for kSyncBaseLatency + 4*kDacClkPeriod;
end process;
-- Compare the calibrated data samples against the expected values.
ProcCheckCalibData: process (ZmodDAC_ClkIO)
begin
if (rising_edge(ZmodDAC_ClkIO) or falling_edge(ZmodDAC_ClkIO)) then
if ((sInitDoneDAC = '1') and (sCh1DataCheckValid = '1') and (sCh2DataCheckValid = '1')) then
assert (abs(cDataDiff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(cZmodDataTestInt) & LF & HT & HT &
"Actual: " & integer'image(cZmodDAC_DataInt) & LF & HT & HT &
"Difference: " & integer'image(cDataDiff)
severity ERROR;
end if;
end if;
end process;
end Behavioral;
|
mit
|
39d94db49134f7146f887991c4817655
| 0.661664 | 4.399181 | false | true | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/DataPath.vhd
| 1 | 19,827 |
-------------------------------------------------------------------------------
--
-- File: DataPath.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Date: 2021
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
--This module synchronizes the data output by the ADC on the DCO input clock (DcoClkIn)
--to the sampling clock generated by an MMCM in the DcoClkOut domain.
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.PkgZmodDigitizer.all;
entity DataPath is
Generic (
-- Sampling clock frequency (in ns).
kSamplingPeriod : real range 2.5 to 100.0:= 10.0;
-- ADC number of bits.
kADC_Width : integer range 10 to 16 := 14
);
Port (
-- Reference clock.
RefClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in the RefClk domain).
arRst : in std_logic;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in the DcoClkOut domain).
adoRst : in std_logic;
-- AD96xx DCO output clock.
DcoClkIn : in std_logic;
-- AD96xx DCO output clock forwarded to the IP's upper levels.
DcoClkOut : out std_logic;
-- MMCM Locked output signal synchronized on RefClk
rDcoMMCM_LockState : out std_logic;
-- When logic '1', this signal enables data acquisition from the ADC. This signal
-- should be kept in logic '0' until the downstream IP (e.g. DMA controller) is
-- ready to receive the ADC data.
doEnableAcquisition : in std_logic;
-- ADC parallel interleaved output data signals.
diADC_Data : in std_logic_vector(kADC_Width-1 downto 0);
-- AD96xx demutiplexed Channel A data output (synchronized in
-- the DcoClkOut domain).
doChannelA : out STD_LOGIC_VECTOR (kADC_Width-1 downto 0);
-- AD96xx demutiplexed Channel B data output (synchronized in
-- the DcoClkOut domain).
doChannelB : out STD_LOGIC_VECTOR (kADC_Width-1 downto 0);
-- Channel A & B data valid indicator.
doDataOutValid : out STD_LOGIC
);
end DataPath;
architecture Behavioral of DataPath is
-- Function used to compute the CLKOUT1_DIVIDE and CLKFBOUT_MULT_F parameters
-- of the MMCM so that the VCO frequency is in the specified range.
-- The MMCM is used for de-skew purposes, so the MMCM's input and output
-- clock frequency should be the same. The CLKOUT1_DIVIDE and CLKFBOUT_MULT_F
-- need to be adjusted to cover input clock frequencies between 10MHz and
-- 400MHz.
function MMCM_M_Coef(SamplingPeriod:real)
return real is
begin
--400MHz to 200MHz -> VCO frequency = [1200;600]
if ((SamplingPeriod > 2.5) and (SamplingPeriod <= 5.0)) then
return 3.0;
--200MHz to 100MHz
elsif ((SamplingPeriod > 5.0) and (SamplingPeriod <= 10.0)) then
return 6.0;
--100MHz to 50MHz
elsif ((SamplingPeriod > 10.0) and (SamplingPeriod <= 20.0)) then
return 12.0;
--50MHz to 25MHz
elsif ((SamplingPeriod > 20.0) and (SamplingPeriod <= 40.0)) then
return 24.0;
--25MHz to 12.5MHz
elsif ((SamplingPeriod > 40.0) and (SamplingPeriod <= 80.0)) then
return 48.0;
--12.5MHz to 10MHz
elsif (SamplingPeriod > 80.0) then
return 64.0;
--Out of specifications;
else
return 1.0;
end if;
end function;
signal DcoBufgClk, FboutDcoClk, FbinDcoClk, DcoBUFR_Clk, DcoBufioClk, DcoMMCM_Clk1, DcoMMCM_Clk2 : std_logic;
signal dbChannelA_IDDR, dbChannelB_IDDR : std_logic_vector(kADC_Width-1 downto 0);
signal aMMCM_Locked: std_logic;
signal rMMCM_LockedLoc: std_logic;
signal rMMCM_LckdFallingFlag: std_logic;
signal rMMCM_Locked_q: std_logic_vector(3 downto 0);
signal rMMCM_Reset_q: std_logic_vector(3 downto 0);
signal aMMCM_ClkStop, cMMCM_ClkStop: std_logic;
signal rMMCM_ClkStop_q: std_logic_vector(3 downto 0);
signal rMMCM_ClkStopFallingFlag: std_logic;
signal doMMCM_LockedLoc : std_logic;
signal doMMCM_Locked_q : std_logic_vector(3 downto 0);
signal doHandShakeDataOutValid : std_logic;
signal doDataOutValidLoc : std_logic;
signal rHandShakeRdy : std_logic;
constant kClkfboutMultF : real := MMCM_M_Coef(kSamplingPeriod);
constant kClk1Divide : integer := integer(MMCM_M_Coef(kSamplingPeriod));
constant kDummy : std_logic_vector (15 downto 0) := x"0000";
begin
DcoClkOut <= DcoBufgClk;
BUFIO_inst : BUFIO
port map (
O => DcoBufioClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => DcoMMCM_Clk2 -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
------------------------------------------------------------------------------------------
-- Input data interface decode
------------------------------------------------------------------------------------------
--Clock domain crossing between DcoClkIn and DcoBufioClk should be safe,
--the latter clock is generated from the former using an MMCM, and we rely on proper timing analysis
--to ensure timing conditions are met
-- Demultiplex the input data bus
GenerateIDDR : for i in 0 to (kADC_Width-1) generate
InstIDDR : IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE"
-- or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => dbChannelA_IDDR(i), -- 1-bit output for positive edge of clock
Q2 => dbChannelB_IDDR(i), -- 1-bit output for negative edge of clock
C => DcoBufioClk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => diADC_Data(i), -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
end generate GenerateIDDR;
------------------------------------------------------------------------------------------
-- Input data interface de-skew
------------------------------------------------------------------------------------------
--Clock buffer for write FIFO clock.
InstDcoBufg : BUFG
port map (
O => DcoBufgClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => DcoMMCM_Clk1 -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
--FIFO write clock de-skew.
InstBufrFeedbackPLL : BUFR
generic map (
BUFR_DIVIDE => "1", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => FbinDcoClk, -- 1-bit output: Clock output (connect to I/O clock loads).
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => '0', -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => FboutDcoClk --CLK_DCO_Delay -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
Digitizer_MMCM : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => kClkfboutMultF, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => kSamplingPeriod, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => kClk1Divide,
CLKOUT2_DIVIDE => kClk1Divide,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => kClkfboutMultF, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => IDDR_ClockPhase(kSamplingPeriod),
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (FALSE, TRUE)
-- Spread Spectrum: Spread Spectrum Attributes
SS_EN => "FALSE", -- Enables spread spectrum (FALSE, TRUE)
SS_MODE => "CENTER_HIGH", -- CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns) (VALUES)
-- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_USE_FINE_PS => FALSE,
CLKOUT6_USE_FINE_PS => FALSE
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => open, -- 1-bit output: CLKOUT0
CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => DcoMMCM_Clk1, -- 1-bit output: CLKOUT1
CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => DcoMMCM_Clk2, -- 1-bit output: CLKOUT2
CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
CLKOUT6 => open, -- 1-bit output: CLKOUT6
-- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
DO => open, -- 16-bit output: DRP data
DRDY => open, -- 1-bit output: DRP ready
-- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
PSDONE => open, -- 1-bit output: Phase shift done
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => FboutDcoClk, -- 1-bit output: Feedback clock
CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
CLKFBSTOPPED => open, -- 1-bit output: Feedback clock stopped
CLKINSTOPPED => aMMCM_ClkStop, -- 1-bit output: Input clock stopped
LOCKED => aMMCM_Locked, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => DcoClkIn, -- 1-bit input: Primary clock
CLKIN2 => '0', -- 1-bit input: Secondary clock
-- Control Ports: 1-bit (each) input: MMCM control ports
CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
PWRDWN => '0', -- 1-bit input: Power-down
RST => rMMCM_Reset_q(0), -- 1-bit input: Reset
-- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
DADDR => (others => '0'), -- 7-bit input: DRP address
DCLK => '0', -- 1-bit input: DRP clock
DEN => '0', -- 1-bit input: DRP enable
DI => (others => '0'), -- 16-bit input: DRP data
DWE => '0', -- 1-bit input: DRP write enable
-- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
PSCLK => '0', -- 1-bit input: Phase shift clock
PSEN => '0', -- 1-bit input: Phase shift enable
PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => FbinDcoClk -- 1-bit input: Feedback clock
);
------------------------------------------------------------------------------------------
--DcoClock presence detection
------------------------------------------------------------------------------------------
-- Not sure if LOCKED or CLKINSTOPPED should be used to reset the MMCM. For now,
-- logic relying on CLKINSTOPPED is commented out
InstMMCM_LockRefClkSync: entity work.SyncAsync
port map (
aoReset => '0',
aIn => aMMCM_Locked,
OutClk => RefClk,
oOut => rMMCM_LockedLoc);
--the process has no reset signal, however the synchronous logic input
--has no reset either. I don't think this is an issue
ProcMMCM_LockedDetect: process(RefClk)
begin
if Rising_Edge(RefClk) then
rMMCM_Locked_q <= rMMCM_LockedLoc & rMMCM_Locked_q(3 downto 1);
rMMCM_LckdFallingFlag <= rMMCM_Locked_q(3) and not rMMCM_LockedLoc;
end if;
end process;
rDcoMMCM_LockState <= rMMCM_LockedLoc;
------------------------------------------------------------------------------------------
--MMCM Reset
------------------------------------------------------------------------------------------
-- This process will keep the generated reset (rMMCM_Reset_q(0)) asserted for
-- 4 RefClk cycles. The MMCM_RSTMINPULSE Minimum Reset Pulse Width is 5.00ns
-- This condition is guaranteed for Sampling frequencies up to 800MHz.
ProcMMCM_Reset: process(arRst, RefClk)
begin
if (arRst = '1') then
rMMCM_Reset_q <= (others => '1');
elsif Rising_Edge(RefClk) then
--if (cMMCM_ClkStopFallingFlag = '1') then -- Not clear which condition should be used from Xilinx documentation
if (rMMCM_LckdFallingFlag = '1') then
rMMCM_Reset_q <= (others => '1');
else
rMMCM_Reset_q <= '0' & rMMCM_Reset_q(rMMCM_Reset_q'high downto 1);
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Data Output Valid Logic
------------------------------------------------------------------------------------------
-- The output valid flag is forced to '0' when the DCO strobe is lost and is
-- only allowed to be reasserted on the rising edge of doMMCM_Locked.
-- A disadvantage of adding this process is that it adds an extra clock latency
InstMMCM_LockDcoBufgClkSync: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2)
port map (
aiReset => arRst,
InClk => RefClk,
iIn => rMMCM_LockedLoc,
aoReset => adoRst,
OutClk => DcoBufgClk,
oOut => doMMCM_LockedLoc);
InstDigitizerHandshake: entity work.HandshakeData
Generic Map (
kDataWidth => 4)
Port Map (
InClk => RefClk,
OutClk => DcoBufgClk,
iData => rMMCM_Locked_q,
oData => doMMCM_Locked_q,
iPush => rHandShakeRdy,
iRdy => rHandShakeRdy,
oAck => '1',
oValid => doHandShakeDataOutValid,
aiReset => arRst,
aoReset => adoRst
);
--DcoBufgClk and DcoBufioClk are related, since they are generated by the same MMCM,
--and we rely on timing analysis to ensure timing is correctly analized and respected.
ProcOutDataValid: process(DcoBufgClk, adoRst, doEnableAcquisition)
begin
if (adoRst = '1') then
doDataOutValidLoc <= '0';
doChannelA <= (others => '0');
doChannelB <= (others => '0');
elsif Rising_Edge(DcoBufgClk) then
if (doEnableAcquisition = '1') then
if ((doMMCM_LockedLoc = '0') or (doMMCM_Locked_q /= "1111" and doHandShakeDataOutValid = '1')) then
doDataOutValidLoc <= '0';
else
doDataOutValidLoc <= '1';
end if;
if (doDataOutValidLoc = '1') then
doChannelA <= dbChannelA_IDDR;
doChannelB <= dbChannelB_IDDR;
end if;
end if;
end if;
end process;
doDataOutValid <= doDataOutValidLoc;
end Behavioral;
|
mit
|
d3ea3514ac40ab1a24be130a8dc14e78
| 0.549453 | 4.473601 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/ConfigADC.vhd
| 1 | 21,037 |
-------------------------------------------------------------------------------
--
-- File: ConfigADC.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module writes an intial configuration into the ADC registers and then
-- manages the optional SPI Indirect Access Port.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodADC.all;
entity ConfigADC is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0;
-- ADC Clock divider ratio (Register 0x0B of AD96xx and AD92xx).
kADC_ClkDiv : integer range 1 to 8 := 4;
--The number of data bits for the data phase of the SPI transaction:
--only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
--The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 16 to 16 := 16;
kSimulation : boolean := false
);
Port (
-- 100MHZ clock input.
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain).
asRst_n : in STD_LOGIC;
-- ADC initialization complete signaling.
sInitDoneADC : out STD_LOGIC := '0';
-- ADC initialization error signaling.
sConfigError : out STD_LOGIC;
--AD9648 SPI interface signals
sADC_Sclk : out STD_LOGIC;
sADC_SDIO : inout STD_LOGIC;
sADC_CS : out STD_LOGIC := '1';
-- SPI Indirect access port; it provides the means to indirectly access
-- the ADC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
sCmdTxAxisTvalid: IN STD_LOGIC;
sCmdTxAxisTready: OUT STD_LOGIC;
sCmdTxAxisTdata: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
sCmdRxAxisTvalid: OUT STD_LOGIC;
sCmdRxAxisTready: IN STD_LOGIC;
sCmdRxAxisTdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end ConfigADC;
architecture Behavioral of ConfigADC is
signal sCurrentState : FsmStatesADC_t := StStart;
signal sNextState : FsmStatesADC_t;
-- signals used for debug purposes
-- signal fsmcfg_state, fsmcfg_state_r : std_logic_vector(5 downto 0);
--External Command FIFO Interface
signal sLdCmdTxData: std_logic;
signal sCmdTxDataReg: std_logic_vector(23 downto 0);
signal sCmdTxAxisTreadyLoc: std_logic;
signal sCmdRxAxisTvalidLoc: std_logic;
signal sCmdRxAxisTdataLoc : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sCmdCnt : unsigned(4 downto 0);
signal sCmdCntInt : integer range 0 to 31;
signal sIncCmdCnt, sRstCmdCnt : std_logic;
--Initialization complete and configuration error flags
signal sInitDoneADC_Fsm : std_logic := '0';
signal sConfigErrorFsm : std_logic;
--Timers
signal sCfgTimer : unsigned (24 downto 0);
signal sCfgTimerRst_n : std_logic;
--SPI Interface
signal sADC_SPI_RdData : std_logic_vector(kDataWidth-1 downto 0);
signal sADC_SPI_Done : std_logic;
signal sADC_SPI_WrData, sADC_SPI_WrDataR : std_logic_vector(kDataWidth-1 downto 0);
signal sADC_SPI_Addr, sADC_SPI_AddrR : std_logic_vector(kCommandWidth - 4 downto 0);
signal sADC_SPI_Width, sADC_SPI_WidthR : std_logic_vector(1 downto 0);
signal sADC_SPI_RdWr, sADC_SPI_RdWrR : std_logic;
signal sADC_SPI_Busy : std_logic;
signal sADC_ApStart, sADC_ApStartR : std_logic;
signal sCountResetResumeVal : unsigned(kCountResetResume'range);
constant kCmdTotal : integer := SelCmdWrListLength(kZmodID);
constant kADC_SPI_CmdDef : ADC_SPI_Commands_t := SelCmdList(kZmodID);
constant kADC_SPI_RdbckDef : ADC_SPI_Readback_t := SelRdbkList(kZmodID);
constant kADC_SPI_Cmd : ADC_SPI_Commands_t := OverwriteClkDiv(kADC_SPI_CmdDef, kADC_ClkDiv);
constant kADC_SPI_Rdbck : ADC_SPI_Readback_t := OverWriteID_ClkDiv(kZmodID, kADC_SPI_RdbckDef, kADC_ClkDiv);
begin
sCountResetResumeVal <= kCountResetResumeSim when kSimulation else
kCountResetResume;
-- Instantiate the SPI controller.
ADC_SPI_inst: entity work.ADI_SPI
Generic Map(
kSysClkDiv => kSPI_SysClkDiv,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sSPI_Clk => sADC_Sclk,
sSDIO => sADC_SDIO,
sCS => sADC_CS,
sApStart => sADC_ApStartR,
sRdData => sADC_SPI_RdData,
sWrData => sADC_SPI_WrDataR,
sAddr => sADC_SPI_AddrR,
sWidth => sADC_SPI_WidthR, --tested only for width = "00"
sRdWr => sADC_SPI_RdWrR,
sDone => sADC_SPI_Done,
sBusy => sADC_SPI_Busy
);
-- Register the SPI controller inputs.
ProcSPI_ControllerRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sADC_SPI_RdWrR <= '0';
sADC_SPI_WrDataR <= (others => '0');
sADC_SPI_AddrR <= (others => '0');
sADC_SPI_WidthR <= (others => '0');
sADC_ApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sADC_SPI_RdWrR <= sADC_SPI_RdWr;
sADC_SPI_WrDataR <= sADC_SPI_WrData;
sADC_SPI_AddrR <= sADC_SPI_Addr;
sADC_SPI_WidthR <= sADC_SPI_Width;
sADC_ApStartR <= sADC_ApStart;
end if;
end process;
sCmdCntInt <= to_integer(sCmdCnt);
-- Register the SPI Indirect Access Port receive interface outputs.
ProcRxExtFIFO_Reg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdRxAxisTvalid <= '0';
sCmdRxAxisTdata <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCmdRxAxisTvalid <= sCmdRxAxisTvalidLoc;
sCmdRxAxisTdata <= x"000000" & sCmdRxAxisTdataLoc;
end if;
end process;
-- Register the SPI Indirect Access Port transmit interface outputs.
ProcCmdAxisTreadyReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxAxisTready <= '0';
elsif (rising_edge(SysClk100)) then
sCmdTxAxisTready <= sCmdTxAxisTreadyLoc;
end if;
end process;
-- Register the next SPI Indirect Access Port command on the transmit
-- interface when the configuration state machine is capable of processing it.
ProcLdCmdTxData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxDataReg <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sLdCmdTxData = '1') then
sCmdTxDataReg <= sCmdTxAxisTdata(23 downto 0);
end if;
end if;
end process;
-- Timer used to determine timeout conditions for SPI transfers.
-- When a command is sent to the ADC a certain amount of time is allowed for the state
-- machine to read back the expected value in order to make sure the register was correctly
-- configured. Some commands do not take effect immediately, so this mechanism is necessary
-- (SPI Port Config register (address 0x00) soft reset write for example).
ProcCfgTimer: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCfgTimer <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sCfgTimerRst_n = '0') then
sCfgTimer <= (others =>'0');
else
sCfgTimer <= sCfgTimer + 1;
end if;
end if;
end process;
-- Counter used to track the number of successfully sent commands.
ProcCmdCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdCnt <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sRstCmdCnt = '0') then
sCmdCnt <= (others => '0');
elsif (sIncCmdCnt = '1') then
sCmdCnt <= sCmdCnt + 1;
end if;
end if;
end process;
-- Register FSM output flags.
ProcInitDoneReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sInitDoneADC <= '0';
sConfigError <= '0';
elsif (rising_edge(SysClk100)) then
sInitDoneADC <= sInitDoneADC_Fsm;
sConfigError <= sConfigErrorFsm;
end if;
end process;
------------------------------------------------------------------------------------------
-- ADC Configuration state machine
------------------------------------------------------------------------------------------
-- State machine synchronous process.
ProcSyncFsm: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCurrentState <= StStart;
--fsmcfg_state_r <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCurrentState <= sNextState;
--fsmcfg_state_r <= fsmcfg_state;
end if;
end process;
-- Next state and output decode.
ProcNextStateAndOutputDecode: process (sCurrentState, sADC_SPI_RdData, sADC_SPI_Done, sADC_SPI_Busy,
sCmdTxAxisTvalid, sCmdTxAxisTdata, sCmdTxDataReg, sCmdRxAxisTready, sCmdCntInt, sCfgTimer,
sCountResetResumeVal)
begin
sNextState <= sCurrentState;
--fsmcfg_state <= "000000";
sADC_ApStart <= '0';
sADC_SPI_WrData <= (others => '0');
sADC_SPI_Addr <= (others => '0');
sADC_SPI_Width <= (others => '0');
sADC_SPI_RdWr <= '0';
sRstCmdCnt <= '0';
sIncCmdCnt <= '0';
sLdCmdTxData <= '0';
sCfgTimerRst_n <= '0';
sInitDoneADC_Fsm <= '0';
sConfigErrorFsm <= '0';
sCmdTxAxisTreadyLoc <= '0';
sCmdRxAxisTvalidLoc <= '0';
sCmdRxAxisTdataLoc <= (others => '0');
case (sCurrentState) is
when StStart =>
--fsmcfg_state <= "000000";
sNextState <= StWriteControlReg;
-- Perform a register write operation for the sCmdCntInt'th command in the queue.
-- For some sCmdCntInt only register reads are required.
when StWriteControlReg =>
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
--fsmcfg_state <= "000001";
if (kADC_SPI_Cmd(sCmdCntInt)(20 downto 8) = kChipID) then --Read ID skips register write
sNextState <= StReadControlReg;
elsif (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_WrData <= kADC_SPI_Cmd(sCmdCntInt)(7 downto 0);
sADC_SPI_Addr <= kADC_SPI_Cmd(sCmdCntInt)(20 downto 8);
sADC_SPI_Width <= kADC_SPI_Cmd(sCmdCntInt)(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneWriteReg;
end if;
-- Wait for register write command to be completed
when StWaitDoneWriteReg =>
--fsmcfg_state <= "000010";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- AD92xx devices require a Transfer register write operation
-- for the previous register write to take effect.
if ((kZmodID = kZmodScope1010_40) or (kZmodID = kZmodScope1210_40) or (kZmodID = kZmodScope1410_40)) then
sNextState <= StReadTrsfReg;
else
sNextState <= StReadControlReg;
end if;
end if;
-- Read Transfer register and check if it is cleared.
when StReadTrsfReg =>
--fsmcfg_state <= "101110";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_Addr <= kSetTrsfReg(20 downto 8);
sADC_SPI_Width <= kSetTrsfReg(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneTrsfRegRd;
end if;
-- Wait for Transfer register read command to complete.
when StWaitDoneTrsfRegRd =>
--fsmcfg_state <= "101111";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- Check if the expected value has been read; A timeout limit
-- is imposed.
if (sADC_SPI_RdData = x"00") then
sNextState <= StSetTrsfReg;
elsif (sCfgTimer >= kCfgTimeout) then
sNextState <= StError;
else
sNextState <= StReadTrsfReg;
end if;
end if;
-- Set the Transfer field of the Transfer register.
when StSetTrsfReg =>
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
--fsmcfg_state <= "101010";
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_WrData <= kSetTrsfReg(7 downto 0);
sADC_SPI_Addr <= kSetTrsfReg(20 downto 8);
sADC_SPI_Width <= kSetTrsfReg(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneTrsfReg;
end if;
-- Wait for SPI command to be completed.
when StWaitDoneTrsfReg =>
--fsmcfg_state <= "101011";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
sNextState <= StReadControlReg;
end if;
-- Read back the register value configured in the StWriteControlReg state.
when StReadControlReg =>
--fsmcfg_state <= "000110";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_Addr <= kADC_SPI_Cmd(sCmdCntInt)(20 downto 8);
sADC_SPI_Width <= kADC_SPI_Cmd(sCmdCntInt)(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneReadReg;
end if;
-- Wait for SPI command to be completed and compare the read data against
-- the expected value (the kADC_SPI_Rdbck readback sequence)
when StWaitDoneReadReg =>
--fsmcfg_state <= "000111";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- Wait for bits that are set/reset by the ADC to change value
-- (Reg00 soft reset for example). Amount of time not specified by data sheet,
-- the timeout value chosen empirically.
if (sADC_SPI_RdData = kADC_SPI_Rdbck(sCmdCntInt)) then
sNextState <= StCheckCmdCnt;
elsif (sCfgTimer >= kCfgTimeout) then
sNextState <= StError;
else
sNextState <= StReadControlReg;
end if;
end if;
-- Check if the command sequence has completed.
when StCheckCmdCnt =>
--fsmcfg_state <= "000011";
sRstCmdCnt <= '1';
if (sCmdCntInt = kCmdTotal) then
sRstCmdCnt <= '0';
sNextState <= StResetTimer;
else
sIncCmdCnt <= '1';
sNextState <= StWriteControlReg;
end if;
-- Reset timeout timer.
when StResetTimer =>
--fsmcfg_state <= "001001";
sNextState <= StWaitRecover;
-- Wait to recover form power down mode.
when StWaitRecover =>
--fsmcfg_state <= "001010";
sCfgTimerRst_n <= '1';
if (sCfgTimer = sCountResetResumeVal) then
sNextState <= StInitDone;
end if;
-- Indicate that the initialization sequence has completed.
when StInitDone =>
--fsmcfg_state <= "001011";
sInitDoneADC_Fsm <= '1';
sNextState <= StIdle;
-- IDLE state; wait for changes on the SPI Indirect Access Port.
when StIdle =>
--fsmcfg_state <= "001100";
sInitDoneADC_Fsm <= '1';
if ((sCmdTxAxisTvalid = '1') and (sADC_SPI_Busy = '0')) then
sLdCmdTxData <= '1';
if (sCmdTxAxisTdata(23) = '0') then
sNextState <= StExtSPI_WrCmd;
else
sNextState <= StExtSPI_RdCmd;
end if;
end if;
-- Execute the register write command requested on the SPI Indirect Access Port.
when StExtSPI_WrCmd =>
--fsmcfg_state <= "001101";
sInitDoneADC_Fsm <= '1';
sADC_ApStart <= '1';
sADC_SPI_WrData <= sCmdTxDataReg(7 downto 0);
sADC_SPI_Addr <= sCmdTxDataReg(20 downto 8);
sADC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneExtWrReg;
-- Wait for the register write command to complete
when StWaitDoneExtWrReg =>
--fsmcfg_state <= "001110";
sInitDoneADC_Fsm <= '1';
if (sADC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StIdle;
end if;
-- Execute the register read command requested on the SPI Indirect Access Port.
when StExtSPI_RdCmd =>
--fsmcfg_state <= "001111";
sInitDoneADC_Fsm <= '1';
sADC_ApStart <= '1';
sADC_SPI_Addr <= sCmdTxDataReg(20 downto 8);
sADC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneExtRdReg;
-- Wait for the register read command to complete.
when StWaitDoneExtRdReg =>
--fsmcfg_state <= "010000";
sInitDoneADC_Fsm <= '1';
if (sADC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StRegExtRxData;
end if;
-- State used to register the incoming SPI data.
when StRegExtRxData =>
--fsmcfg_state <= "010001";
sInitDoneADC_Fsm <= '1';
sCmdRxAxisTvalidLoc <= '1';
sCmdRxAxisTdataLoc <= sADC_SPI_RdData;
if (sCmdRxAxisTready = '1') then
sNextState <= StIdle;
end if;
-- When an error condition is detected the state machine stalls in this state.
-- An external reset condition is necessary to exit this state.
when StError =>
--fsmcfg_state <= "111111";
sConfigErrorFsm <= '1';
report "ADC Configuration readback error." & LF & HT & HT
severity ERROR;
when others =>
sNextState <= StStart;
end case;
end process;
end Behavioral;
|
mit
|
bcafc58759b85552508a6c12a734a10f
| 0.575082 | 4.644955 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/crc16.vhd
| 2 | 4,017 |
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-------------------------------------------------------------------------------
-- CRC module for data(7:0)
-- lfsr(15:0)=1+x^2+x^15+x^16;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity crc16 is
port ( data_in : in std_logic_vector (7 downto 0);
crc_en , rst, clk : in std_logic;
crc_out_res : out std_logic_vector (15 downto 0);
crc_out : out std_logic_vector (15 downto 0));
end crc16;
architecture imp_crc16 of crc16 is
signal lfsr_q: std_logic_vector (15 downto 0);
signal lfsr_c: std_logic_vector (15 downto 0);
signal data_in1 : std_logic_vector (7 downto 0);
signal crc_out1 : std_logic_vector (15 downto 0);
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of data_in : signal is "true";
--attribute keep of data_in : signal is "true";
begin
crc_out_res <= crc_out1;
crc_out(0) <=not crc_out1(7);
crc_out(1) <=not crc_out1(6);
crc_out(2) <=not crc_out1(5);
crc_out(3) <=not crc_out1(4);
crc_out(4) <=not crc_out1(3);
crc_out(5) <=not crc_out1(2);
crc_out(6) <=not crc_out1(1);
crc_out(7) <=not crc_out1(0);
crc_out(8) <=not crc_out1(15);
crc_out(9) <=not crc_out1(14);
crc_out(10) <=not crc_out1(13);
crc_out(11) <=not crc_out1(12);
crc_out(12) <=not crc_out1(11);
crc_out(13) <=not crc_out1(10);
crc_out(14) <=not crc_out1(9);
crc_out(15) <=not crc_out1(8);
--data_in1(7) <= data_in(0);
--data_in1(6) <= data_in(1);
--data_in1(5) <= data_in(2);
--data_in1(4) <= data_in(3);
--data_in1(3) <= data_in(4);
--data_in1(2) <= data_in(5);
--data_in1(1) <= data_in(6);
--data_in1(0) <= data_in(7);
data_in1 <= data_in;
crc_out1 <= lfsr_q;
lfsr_c(0) <= lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(0) xor data_in1(1) xor data_in1(2) xor data_in1(3) xor data_in1(4) xor data_in1(5) xor data_in1(6) xor data_in1(7);
lfsr_c(1) <= lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(1) xor data_in1(2) xor data_in1(3) xor data_in1(4) xor data_in1(5) xor data_in1(6) xor data_in1(7);
lfsr_c(2) <= lfsr_q(8) xor lfsr_q(9) xor data_in1(0) xor data_in1(1);
lfsr_c(3) <= lfsr_q(9) xor lfsr_q(10) xor data_in1(1) xor data_in1(2);
lfsr_c(4) <= lfsr_q(10) xor lfsr_q(11) xor data_in1(2) xor data_in1(3);
lfsr_c(5) <= lfsr_q(11) xor lfsr_q(12) xor data_in1(3) xor data_in1(4);
lfsr_c(6) <= lfsr_q(12) xor lfsr_q(13) xor data_in1(4) xor data_in1(5);
lfsr_c(7) <= lfsr_q(13) xor lfsr_q(14) xor data_in1(5) xor data_in1(6);
lfsr_c(8) <= lfsr_q(0) xor lfsr_q(14) xor lfsr_q(15) xor data_in1(6) xor data_in1(7);
lfsr_c(9) <= lfsr_q(1) xor lfsr_q(15) xor data_in1(7);
lfsr_c(10) <= lfsr_q(2);
lfsr_c(11) <= lfsr_q(3);
lfsr_c(12) <= lfsr_q(4);
lfsr_c(13) <= lfsr_q(5);
lfsr_c(14) <= lfsr_q(6);
lfsr_c(15) <= lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(15) xor data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
process (clk,rst) begin
if (clk'EVENT and clk = '1') then
if (rst = '0') then
lfsr_q <= b"1111111111111111";
else
if (crc_en = '1') then
lfsr_q <= lfsr_c;
end if;
end if;
end if;
end process;
end architecture imp_crc16;
|
mit
|
ea1464d5dba4f1e870cfe829aeb5a80c
| 0.596465 | 2.520075 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Block_Mat_exit570_pr.vhd
| 1 | 17,379 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_Mat_exit570_pr is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
height : IN STD_LOGIC_VECTOR (15 downto 0);
width : IN STD_LOGIC_VECTOR (15 downto 0);
gamma : IN STD_LOGIC_VECTOR (7 downto 0);
img3_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_rows_V_out_full_n : IN STD_LOGIC;
img3_rows_V_out_write : OUT STD_LOGIC;
img3_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_cols_V_out_full_n : IN STD_LOGIC;
img3_cols_V_out_write : OUT STD_LOGIC;
p_cols_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_out_out_full_n : IN STD_LOGIC;
p_cols_assign_cast_out_out_write : OUT STD_LOGIC;
p_rows_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_out_out_full_n : IN STD_LOGIC;
p_rows_assign_cast_out_out_write : OUT STD_LOGIC;
gamma_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
gamma_out_full_n : IN STD_LOGIC;
gamma_out_write : OUT STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of Block_Mat_exit570_pr is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal img3_rows_V_out_blk_n : STD_LOGIC;
signal img3_cols_V_out_blk_n : STD_LOGIC;
signal p_cols_assign_cast_out_out_blk_n : STD_LOGIC;
signal p_rows_assign_cast_out_out_blk_n : STD_LOGIC;
signal gamma_out_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal ap_return_0_preg : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv16_0;
else
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_return_0_preg <= height;
end if;
end if;
end if;
end process;
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv16_0;
else
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_return_1_preg <= width;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_block_state1_assign_proc : process(real_start, ap_done_reg, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
ap_block_state1 <= ((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
ap_return_0_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n, ap_return_0_preg)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_return_0 <= height;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
ap_return_1_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n, ap_return_1_preg)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_return_1 <= width;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
gamma_out_blk_n_assign_proc : process(ap_CS_fsm_state1, gamma_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
gamma_out_blk_n <= gamma_out_full_n;
else
gamma_out_blk_n <= ap_const_logic_1;
end if;
end process;
gamma_out_din <= gamma;
gamma_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
gamma_out_write <= ap_const_logic_1;
else
gamma_out_write <= ap_const_logic_0;
end if;
end process;
img3_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_cols_V_out_blk_n <= img3_cols_V_out_full_n;
else
img3_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_cols_V_out_din <= width;
img3_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_cols_V_out_write <= ap_const_logic_1;
else
img3_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img3_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_rows_V_out_blk_n <= img3_rows_V_out_full_n;
else
img3_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_rows_V_out_din <= height;
img3_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_rows_V_out_write <= ap_const_logic_1;
else
img3_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
p_cols_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_cols_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_cols_assign_cast_out_out_blk_n <= p_cols_assign_cast_out_out_full_n;
else
p_cols_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_out_out_din <= width(12 - 1 downto 0);
p_cols_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_out_out_write <= ap_const_logic_1;
else
p_cols_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_rows_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_rows_assign_cast_out_out_blk_n <= p_rows_assign_cast_out_out_full_n;
else
p_rows_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_out_out_din <= height(12 - 1 downto 0);
p_rows_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, gamma_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (gamma_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_out_out_write <= ap_const_logic_1;
else
p_rows_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
9970c47040af6b2653a775bd5df9203a
| 0.606364 | 2.71081 | false | false | false | false |
grafi-tt/Maizul
|
src/Top.vhd
| 1 | 5,527 |
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use unisim.vcomponents.all;
use work.types.all;
entity Top is
port (
-- Clock
MCLK1 : in std_logic;
XRST : in std_logic;
-- RS-232C
RS_RX : in std_logic;
RS_TX : out std_logic;
-- SRAM
ZCLKMA : out std_logic_vector(1 downto 0);
ZD : inout std_logic_vector(31 downto 0);
ZA : out std_logic_vector(19 downto 0);
XWA : out std_logic;
XE1 : out std_logic;
E2A : out std_logic;
XE3 : out std_logic;
XGA : out std_logic;
XZCKE : out std_logic;
ADVA : out std_logic;
XLBO : out std_logic;
ZZA : out std_logic;
XFT : out std_logic;
XZBE : out std_logic_vector(3 downto 0));
end Top;
architecture structural of Top is
component DCM1
port(
CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end component;
component U232CRecv is
generic (
-- 9600bps
-- wTime : std_logic_vector(15 downto 0) := x"1B17"
-- 115200bps, 66MHz (perfectly works)
-- wTime : std_logic_vector(15 downto 0) := x"0255"
-- 115200bps, 72MHz
-- wTime : std_logic_vector(15 downto 0) := x"028b"
-- 115200bps, 84MHz
-- wTime : std_logic_vector(15 downto 0) := x"02f7"
-- 115200bps, 99MHz
-- wTime : std_logic_vector(15 downto 0) := x"037f"
-- 115200bps, 99MHz
wTime : std_logic_vector(15 downto 0) := x"03e3"
);
port (
clk : in std_logic;
ok : in std_logic;
rx_pin : in std_logic;
data : out std_logic_vector (7 downto 0);
recf : out std_logic);
end component;
component U232CSend is
generic (
-- 9600bps
-- wTime : std_logic_vector(15 downto 0) := x"1ADB"
-- 115200bps, 66MHz (perfectly works)
-- wTime : std_logic_vector(15 downto 0) := x"0240"
-- 115200bps, 72MHz
-- wTime : std_logic_vector(15 downto 0) := x"0274"
-- 115200bps, 84MHz
-- wTime : std_logic_vector(15 downto 0) := x"02dd"
-- 115200bps, 99MHz
-- wTime : std_logic_vector(15 downto 0) := x"0360"
-- 115200bps, 110MHz
wTime : std_logic_vector(15 downto 0) := x"03c0"
);
port (
clk : in std_logic;
go : in std_logic;
data : in std_logic_vector (7 downto 0);
tx_pin : out std_logic;
sent : out std_logic);
end component;
component SRAM is
port (
clk : in std_logic;
load : in boolean;
addr : in std_logic_vector(19 downto 0);
data : inout std_logic_vector(31 downto 0);
clkPin1 : out std_logic;
clkPin2 : out std_logic;
xStorePin : out std_logic;
xMaskPin : out std_logic_vector(3 downto 0);
addrPin : out std_logic_vector(19 downto 0);
dataPin : inout std_logic_vector(31 downto 0);
xEnablePin1 : out std_logic;
enablePin2 : out std_logic;
xEnablePin3 : out std_logic;
xOutEnablePin : out std_logic;
xClkEnablePin : out std_logic;
advancePin : out std_logic;
xLinearOrderPin : out std_logic;
sleepPin : out std_logic;
xFlowThruPin : out std_logic);
end component;
component DataPath is
port (
clk : in std_logic;
u232c_in : out u232c_in_t;
u232c_out : in u232c_out_t;
sramLoad : out boolean;
sramAddr : out sram_addr;
sramData : inout value_t);
end component;
signal clkfx, clk0, iclk : std_logic;
signal u232c_in : u232c_in_t;
signal u232c_out : u232c_out_t;
signal load : boolean;
signal addr : sram_addr := (others => '0');
signal dataLine : value_t;
begin
dcm_map : DCM1 port map (
CLKIN_IN => MCLK1,
RST_IN => not XRST,
CLKFX_OUT => clkfx,
CLKIN_IBUFG_OUT => iclk,
CLK0_OUT => clk0);
u232c_recv_map : U232CRecv port map (
clk => clkfx,
ok => u232c_in.ok,
data => u232c_out.recv_data,
rx_pin => RS_RX,
recf => u232c_out.recf);
u232c_send_map : U232CSend port map (
clk => clkfx,
go => u232c_in.go,
data => u232c_in.send_data,
tx_pin => RS_TX,
sent => u232c_out.sent);
sram_map : SRAM port map (
clk => clkfx,
load => load,
addr => std_logic_vector(addr),
data => dataLine,
clkPin1 => ZCLKMA(0),
clkPin2 => ZCLKMA(1),
xStorePin => XWA,
xMaskPin => XZBE,
addrPin => ZA,
dataPin => ZD,
xEnablePin1 => XE1,
enablePin2 => E2A,
xEnablePin3 => XE3,
xOutEnablePin => XGA,
xClkEnablePin => XZCKE,
advancePin => ADVA,
xLinearOrderPin => XLBO,
sleepPin => ZZA,
xFlowThruPin => XFT);
data_path_map : DataPath port map (
clk => clkfx,
u232c_in => u232c_in,
u232c_out => u232c_out,
sramLoad => load,
sramAddr => addr,
sramData => dataLine);
end structural;
|
bsd-2-clause
|
42636d94e5086dde28d55e071446e814
| 0.512756 | 3.556628 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/LM.vhd
| 1 | 11,770 |
-------------------------------------------------------------------------------
--
-- File: LM.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.SimpleFIFO;
use work.DebugLib;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LM is
Generic(
kMaxLaneCount : natural := 4;
--PPI
kLaneCount : natural range 1 to 4 := 2 --[1,2,4]
);
Port (
RxByteClkHS : in STD_LOGIC;
RxDataHS : in STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
RxSyncHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxValidHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxActiveHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
--Master AXI-Stream
rbMAxisTdata : out std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
rbMAxisTkeep : out std_logic_vector(kMaxLaneCount - 1 downto 0);
rbMAxisTvalid : out std_logic;
rbMAxisTready : in std_logic;
rbMAxisTlast : out std_logic;
rbErrSkew : out std_logic;
rbErrOvf : out std_logic;
rbEn : in std_logic;
rbRst : in std_logic;
dbgLMLane : out DebugLib.DebugLMLanes_t;
dbgLM : out DebugLib.DebugLM_t
);
end LM;
architecture Behavioral of LM is
type state_t is (stReset, stIdle, stWaitForReady, stWaitForValid, stReceive, stEndReceive, stError);
signal rbState, rbNstate : state_t;
signal rbByteCnt : natural range 0 to kMaxLaneCount - 1 := 0;
signal rbTvalidInt, rbMAxisTvalidInt, rbTlastInt, rbPartial : std_logic;
signal rbTdataInt : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal rbTkeepInt : std_logic_vector(kMaxLaneCount - 1 downto 0);
constant kAllOnes : std_logic_vector(kMaxLaneCount - 1 downto 0) := (others => '1');
alias rbDataHSInt is RxDataHS;
alias rbSyncHSInt is RxSyncHS;
alias rbValidHSInt is RxValidHS;
alias rbActiveHSInt is RxActiveHS;
signal rbRdEn, rbWrEn, rbFull : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbEnInt : std_logic;
-- De-skewed PPI data lanes
signal rbDataHS : STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
signal rbSyncHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbValidHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbActiveHS, rbActiveHS_q : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
-- VHDL-2008 back-port
function orv(vec : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in vec'range loop
result := result or vec(i);
end loop;
return result;
end orv;
-- VHDL-2008 back-port
function andv(vec : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in vec'range loop
result := result and vec(i);
end loop;
return result;
end andv;
begin
dbgLM.state <= std_logic_vector(to_unsigned(state_t'pos(rbState), 3));
dbgLM.rbByteCnt <= std_logic_vector(to_unsigned(rbByteCnt, 2));
-- Shallow, synchronous FIFOs for each data lane are used to delay data
-- on those that transmit earlier than the rest. Thus, data lanes
-- are de-skewed and their RxActiveHS edges aligned. This approach relies
-- on the timing of RxValidHS relative to the corresponding RxActiveHS to be
-- the same for all lanes.
DeskewFIFOs: for i in 0 to kLaneCount - 1 generate
dbgLMLane(i).rbSkwRdEn <= rbRdEn(i);
dbgLMLane(i).rbSkwWrEn <= rbEn;
dbgLMLane(i).rbSkwFull <= rbFull(i);
dbgLMLane(i).rbActiveHS <= rbActiveHS(i);
dbgLMLane(i).rbSyncHS <= rbSyncHS(i);
dbgLMLane(i).rbValidHS <= rbValidHS(i);
dbgLMLane(i).rbDataHS <= rbDataHS((i+1)*8-1 downto i*8);
DeskewFIFOx: entity work.SimpleFIFO
Generic map (kDataWidth => 11)
Port map (
InClk => RxByteClkHS,
iRst => rbRst,
iDataIn => rbActiveHSInt(i) & rbSyncHSInt(i) & rbValidHSInt(i) & rbDataHSInt((i+1)*8-1 downto i*8),
iWrEn => rbWrEn(i),
iRdEn => rbRdEn(i),
iFull => rbFull(i),
iEmpty => open,
iDataOut(10) => rbActiveHS(i),
iDataOut(9) => rbSyncHS(i),
iDataOut(8) => rbValidHS(i),
iDataOut(7 downto 0) => rbDataHS((i+1)*8-1 downto i*8)
);
rbWrEn(i) <= rbEnInt;
rbRdEn(i) <= '0' when (rbState = stReset) else
'0' when (rbActiveHS(i) = '1' and andv(rbActiveHS) = '0' and andv(rbActiveHS_q) = '0') else -- lane is active while others not, pause it
'0' when (andv(rbActiveHS) = '1' and rbState = stWaitForReady) else -- all lanes active, but we are held up by rbMAxisTready
'1';
process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRdEn(i) = '1') then
rbActiveHS_q(i) <= rbActiveHS(i);
end if;
end if;
end process;
end generate DeskewFIFOs;
InternalEnable: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbState = stReset) then
rbEnInt <= '0';
else
rbEnInt <= rbEn;
end if;
end if;
end process;
-- The deskew error flag is set when one of the lanes was halted for so long awaiting valid data on the
-- other lanes that the FIFOs filled up. Possible causes:
-- not all lanes in the specified kLaneCount are receiving data, or
-- lane skew larger than 8 RxByteClkHS periods.
DeskewFullFlag: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbErrSkew <= '0';
elsif (rbEnInt = '1' and orv(rbFull) = '1') then
rbErrSkew <= '1';
end if;
end if;
end process;
-- The overflow error flag set whenever we provide valid data on the AXI-Stream
-- and the slave is not ready to receive. Buffering should be done downstream.
OverflowFlag: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbErrOvf <= '0';
elsif (rbMAxisTvalidInt = '1' and rbMAxisTready = '0') then
rbErrOvf <= '1';
end if;
end if;
end process;
SYNC_PROC: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbState <= stReset;
else
rbState <= rbNstate;
end if;
end if;
end process;
ByteRegisters: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbTdataInt <= (others => '0');
rbTkeepInt <= (others => '0');
else
if (rbState = stReceive or rbState = stWaitForValid) then
--Walk the valid signals, register valid bytes and set keep bits
--Order is important: last bytes are filled from low-order lanes to high-order ones
if (rbTvalidInt = '1') then
rbTkeepInt <= (others => '0');
end if;
for i in 0 to kLaneCount - 1 loop
if (rbValidHS(i) = '0') then
exit;
end if;
rbTdataInt((i+rbByteCnt+1)*8-1 downto (i+rbByteCnt)*8) <= rbDataHS((i+1)*8-1 downto i*8);
rbTkeepInt(i+rbByteCnt) <= '1';
end loop;
end if;
end if;
end if;
end process;
BufferCounter: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbState = stIdle) then
rbByteCnt <= 0;
else
if (rbState = stWaitForValid and orv(rbValidHS) = '1') or (rbState = stReceive) then
if (rbByteCnt = kMaxLaneCount - kLaneCount) then
rbByteCnt <= 0;
else
rbByteCnt <= rbByteCnt + kLaneCount;
end if;
end if;
end if;
end if;
end process;
rbTValidInt <= '1' when ((rbState = stReceive and (rbByteCnt = 0 or orv(rbValidHS) = '0')) -- buffer full, or no more bytes
or (rbState = stEndReceive)) -- flush partial packet
else '0';
rbTlastInt <= '1' when (rbState = stReceive and orv(rbValidHS) = '0') -- no more bytes
or (rbState = stEndReceive) -- partial packet is last
else '0';
OutputRegister: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbMAxisTdata <= rbTdataInt;
rbMAxisTkeep <= rbTkeepInt;
rbMAxisTvalidInt <= rbTvalidInt;
rbMAxisTlast <= rbTlastInt;
else
rbMAxisTvalidInt <= rbTvalidInt;
if (rbTvalidInt = '1') then
rbMAxisTdata <= rbTdataInt;
rbMAxisTkeep <= rbTkeepInt;
rbMAxisTlast <= rbTlastInt;
end if;
end if;
end if;
end process;
rbMAxisTvalid <= rbMAxisTvalidInt;
NEXT_STATE_DECODE: process (rbState, rbActiveHS, rbValidHS, rbFull, rbMAxisTready)
begin
rbNstate <= rbState; --default is to stay in current rbState
case (rbState) is
when stReset =>
if (orv(rbFull) = '0') then
rbNstate <= stWaitForReady;
end if;
when stWaitForReady =>
if (orv(rbFull) = '1') then
rbNstate <= stError;
elsif (rbMAxisTready = '1') then
rbNstate <= stIdle;
end if;
when stIdle =>
if (orv(rbFull) = '1') then --deskew overflow
rbNstate <= stError;
elsif (andv(rbActiveHS) = '1') then --when all channels present active
rbNstate <= stWaitForValid;
end if;
when stWaitForValid => -- in High-Speed reception but no data yet
if (andv(rbValidHS) = '1') then -- first full data
rbNstate <= stReceive;
elsif (orv(rbValidHS) = '1') then -- partial data; first is also the last
rbNstate <= stEndReceive;
end if;
when stReceive => -- we are receiving High-Speed data
if (orv(rbValidHS) = '0') then
rbNstate <= stIdle; --no more data
elsif (andv(rbValidHS) = '0') then -- partial data; last packet
rbNstate <= stEndReceive;
end if;
when stEndReceive =>
rbNstate <= stIdle; -- last packet seen
when stError =>
if (orv(rbActiveHS) = '0') then
rbNstate <= stIdle;
end if;
when others =>
rbNstate <= stIdle;
end case;
end process;
end Behavioral;
|
mit
|
976fc79de593dde6dd496f6bf55ae415
| 0.616653 | 4.006127 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/preesc_tb.vhd
| 2 | 1,659 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY preesc_tb IS
END preesc_tb;
ARCHITECTURE behavior OF preesc_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(31 downto 0);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0):="0000000000000000";
signal salida_uds : std_logic_vector(1 downto 0):="00";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Stimulus process
stim_proc: process
begin
entrada_frec<="00000000000000000100000100010000";
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
ba251f0dcd482b192f2d48e089c1f866
| 0.571429 | 4.673239 | false | false | false | false |
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/PhSeROM.vhd
| 1 | 6,164 |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: PhSeROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 177 11/07/2012 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PhSeROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END PhSeROM;
ARCHITECTURE SYN OF phserom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "PhaseSelectErr.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "PhaseSelectErr.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "PhaseSelectErr.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
57d3ca2b2aa472b856a7763f91de5ca1
| 0.670019 | 3.589983 | false | false | false | false |
olajep/oh
|
src/adi/hdl/library/common/pl330_dma_fifo.vhd
| 1 | 5,182 |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
mit
|
c2754f2f19725bf1558cdc3b007908bc
| 0.601312 | 3.296438 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/FSqr.vhd
| 1 | 2,499 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FSqr is
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FSqr;
architecture twoproc_pipeline of FSqr is
component FSqrTable is
port (
clk : in std_logic;
k : in std_logic_vector(9 downto 0);
v : out std_logic_vector(35 downto 0) := (others => '0'));
end component;
signal k : std_logic_vector(9 downto 0) := (others => '0');
signal v : std_logic_vector(35 downto 0);
signal rest : unsigned(13 downto 0) := (others => '0');
signal sgn_in, sgn_in_p : std_logic := '0';
signal exp_in, exp_in_p : unsigned(7 downto 0) := (others => '0');
signal a0, a0_p : unsigned(22 downto 0) := (others => '0');
signal t1, t1_p : unsigned(22 downto 0) := (others => '0');
begin
conbinatorial1 : process(flt_in)
begin
k <= flt_in(23 downto 14);
end process;
table_map : FSqrTable port map (clk => clk, k => k, v => v);
sequential2 : process(clk)
begin
if rising_edge(clk) then
sgn_in <= flt_in(31);
exp_in <= unsigned(flt_in(30 downto 23));
rest <= unsigned(flt_in(13 downto 0));
end if;
end process;
conbinatorial2 : process(v, rest)
variable a1 : unsigned(12 downto 0);
variable tmp : unsigned(26 downto 0);
begin
a0 <= unsigned(v(35 downto 13));
a1 := unsigned(v(12 downto 0));
tmp := a1 * rest;
t1 <= "000000000" & tmp(26 downto 13);
end process;
sequential3 : process(clk)
begin
if rising_edge(clk) then
sgn_in_p <= sgn_in;
exp_in_p <= exp_in;
a0_p <= a0;
t1_p <= t1;
end if;
end process;
conbinatorial3 : process(sgn_in_p, exp_in_p, a0_p, t1_p)
variable exp_out : unsigned(7 downto 0);
variable frc_out : unsigned(22 downto 0);
begin
if exp_in_p = x"00" then
exp_out := x"00";
frc_out := (others => '0');
elsif sgn_in_p = '1' then
exp_out := x"FF";
frc_out := x"00000" & "00" & '1';
else
exp_out := x"3F" + ("0" & exp_in_p(7 downto 1)) + unsigned'(0 => exp_in_p(0));
frc_out := a0_p + t1_p;
end if;
flt_out <= std_logic_vector(sgn_in_p & exp_out & frc_out);
end process;
end twoproc_pipeline;
|
bsd-2-clause
|
7209b4f82d0c49877b0ec00add084032
| 0.529412 | 3.191571 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/hls_gamma_correction.vhd
| 1 | 43,380 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_gamma_correction is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC );
end;
architecture behav of hls_gamma_correction is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"hls_gamma_correction,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.670000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=5.658125,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=16,HLS_SYN_DSP=0,HLS_SYN_FF=1097,HLS_SYN_LUT=2358}";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant C_S_AXI_WSTRB_WIDTH : INTEGER range 63 downto 0 := 4;
constant C_S_AXI_ADDR_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv24_0 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal gamma : STD_LOGIC_VECTOR (7 downto 0);
signal height : STD_LOGIC_VECTOR (15 downto 0);
signal width : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit570_pr_U0_ap_start : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_start_full_n : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_ap_done : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_ap_continue : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_ap_idle : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_ap_ready : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_start_out : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_start_write : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_img3_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit570_pr_U0_img3_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_img3_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit570_pr_U0_img3_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_p_cols_assign_cast_out_out_din : STD_LOGIC_VECTOR (11 downto 0);
signal Block_Mat_exit570_pr_U0_p_cols_assign_cast_out_out_write : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_p_rows_assign_cast_out_out_din : STD_LOGIC_VECTOR (11 downto 0);
signal Block_Mat_exit570_pr_U0_p_rows_assign_cast_out_out_write : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_gamma_out_din : STD_LOGIC_VECTOR (7 downto 0);
signal Block_Mat_exit570_pr_U0_gamma_out_write : STD_LOGIC;
signal Block_Mat_exit570_pr_U0_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit570_pr_U0_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_channel_done_img0_cols_V_channel : STD_LOGIC;
signal img0_cols_V_channel_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_img0_cols_V_channel : STD_LOGIC := '0';
signal ap_sync_channel_write_img0_cols_V_channel : STD_LOGIC;
signal ap_channel_done_img0_rows_V_channel : STD_LOGIC;
signal img0_rows_V_channel_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_img0_rows_V_channel : STD_LOGIC := '0';
signal ap_sync_channel_write_img0_rows_V_channel : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal AXIvideo2Mat_U0_stream_in_TREADY : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_start : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_done : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_continue : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_idle : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_ready : STD_LOGIC;
signal Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img3_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img3_data_stream_0_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img3_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img3_data_stream_1_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img3_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img3_data_stream_2_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_gamma_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img0_data_stream_0_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img0_data_stream_1_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img0_data_stream_2_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TDATA : STD_LOGIC_VECTOR (23 downto 0);
signal Mat2AXIvideo_U0_stream_out_TVALID : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TKEEP : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TSTRB : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TID : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal img3_rows_V_c_full_n : STD_LOGIC;
signal img3_rows_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img3_rows_V_c_empty_n : STD_LOGIC;
signal img3_cols_V_c_full_n : STD_LOGIC;
signal img3_cols_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img3_cols_V_c_empty_n : STD_LOGIC;
signal p_cols_assign_cast_lo_full_n : STD_LOGIC;
signal p_cols_assign_cast_lo_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_cols_assign_cast_lo_empty_n : STD_LOGIC;
signal p_rows_assign_cast_lo_full_n : STD_LOGIC;
signal p_rows_assign_cast_lo_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_rows_assign_cast_lo_empty_n : STD_LOGIC;
signal gamma_c_full_n : STD_LOGIC;
signal gamma_c_dout : STD_LOGIC_VECTOR (7 downto 0);
signal gamma_c_empty_n : STD_LOGIC;
signal img0_rows_V_channel_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_rows_V_channel_empty_n : STD_LOGIC;
signal img0_cols_V_channel_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_cols_V_channel_empty_n : STD_LOGIC;
signal img0_data_stream_0_s_full_n : STD_LOGIC;
signal img0_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_0_s_empty_n : STD_LOGIC;
signal img0_data_stream_1_s_full_n : STD_LOGIC;
signal img0_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_1_s_empty_n : STD_LOGIC;
signal img0_data_stream_2_s_full_n : STD_LOGIC;
signal img0_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_2_s_empty_n : STD_LOGIC;
signal img3_data_stream_0_s_full_n : STD_LOGIC;
signal img3_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_0_s_empty_n : STD_LOGIC;
signal img3_data_stream_1_s_full_n : STD_LOGIC;
signal img3_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_1_s_empty_n : STD_LOGIC;
signal img3_data_stream_2_s_full_n : STD_LOGIC;
signal img3_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_2_s_empty_n : STD_LOGIC;
signal start_for_Loop_loop_height_pro_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Loop_loop_height_pro_U0_full_n : STD_LOGIC;
signal start_for_Loop_loop_height_pro_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Loop_loop_height_pro_U0_empty_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_full_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_empty_n : STD_LOGIC;
signal AXIvideo2Mat_U0_start_full_n : STD_LOGIC;
signal AXIvideo2Mat_U0_start_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_start_full_n : STD_LOGIC;
signal Loop_loop_height_pro_U0_start_write : STD_LOGIC;
signal Mat2AXIvideo_U0_start_full_n : STD_LOGIC;
signal Mat2AXIvideo_U0_start_write : STD_LOGIC;
component Block_Mat_exit570_pr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
height : IN STD_LOGIC_VECTOR (15 downto 0);
width : IN STD_LOGIC_VECTOR (15 downto 0);
gamma : IN STD_LOGIC_VECTOR (7 downto 0);
img3_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_rows_V_out_full_n : IN STD_LOGIC;
img3_rows_V_out_write : OUT STD_LOGIC;
img3_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_cols_V_out_full_n : IN STD_LOGIC;
img3_cols_V_out_write : OUT STD_LOGIC;
p_cols_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_out_out_full_n : IN STD_LOGIC;
p_cols_assign_cast_out_out_write : OUT STD_LOGIC;
p_rows_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_out_out_full_n : IN STD_LOGIC;
p_rows_assign_cast_out_out_write : OUT STD_LOGIC;
gamma_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
gamma_out_full_n : IN STD_LOGIC;
gamma_out_write : OUT STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (15 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component Loop_loop_height_pro IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img3_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_0_V_full_n : IN STD_LOGIC;
img3_data_stream_0_V_write : OUT STD_LOGIC;
img3_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_1_V_full_n : IN STD_LOGIC;
img3_data_stream_1_V_write : OUT STD_LOGIC;
img3_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_2_V_full_n : IN STD_LOGIC;
img3_data_stream_2_V_write : OUT STD_LOGIC;
gamma_dout : IN STD_LOGIC_VECTOR (7 downto 0);
gamma_empty_n : IN STD_LOGIC;
gamma_read : OUT STD_LOGIC;
img0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_0_V_empty_n : IN STD_LOGIC;
img0_data_stream_0_V_read : OUT STD_LOGIC;
img0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_1_V_empty_n : IN STD_LOGIC;
img0_data_stream_1_V_read : OUT STD_LOGIC;
img0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_2_V_empty_n : IN STD_LOGIC;
img0_data_stream_2_V_read : OUT STD_LOGIC );
end component;
component Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC;
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component fifo_w16_d3_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w12_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w8_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w16_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w8_d1_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Loop_lojbC IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Mat2AXIkbM IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component hls_gamma_correction_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
gamma : OUT STD_LOGIC_VECTOR (7 downto 0);
height : OUT STD_LOGIC_VECTOR (15 downto 0);
width : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
hls_gamma_correction_AXILiteS_s_axi_U : component hls_gamma_correction_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
gamma => gamma,
height => height,
width => width);
Block_Mat_exit570_pr_U0 : component Block_Mat_exit570_pr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Block_Mat_exit570_pr_U0_ap_start,
start_full_n => Block_Mat_exit570_pr_U0_start_full_n,
ap_done => Block_Mat_exit570_pr_U0_ap_done,
ap_continue => Block_Mat_exit570_pr_U0_ap_continue,
ap_idle => Block_Mat_exit570_pr_U0_ap_idle,
ap_ready => Block_Mat_exit570_pr_U0_ap_ready,
start_out => Block_Mat_exit570_pr_U0_start_out,
start_write => Block_Mat_exit570_pr_U0_start_write,
height => height,
width => width,
gamma => gamma,
img3_rows_V_out_din => Block_Mat_exit570_pr_U0_img3_rows_V_out_din,
img3_rows_V_out_full_n => img3_rows_V_c_full_n,
img3_rows_V_out_write => Block_Mat_exit570_pr_U0_img3_rows_V_out_write,
img3_cols_V_out_din => Block_Mat_exit570_pr_U0_img3_cols_V_out_din,
img3_cols_V_out_full_n => img3_cols_V_c_full_n,
img3_cols_V_out_write => Block_Mat_exit570_pr_U0_img3_cols_V_out_write,
p_cols_assign_cast_out_out_din => Block_Mat_exit570_pr_U0_p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n => p_cols_assign_cast_lo_full_n,
p_cols_assign_cast_out_out_write => Block_Mat_exit570_pr_U0_p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din => Block_Mat_exit570_pr_U0_p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n => p_rows_assign_cast_lo_full_n,
p_rows_assign_cast_out_out_write => Block_Mat_exit570_pr_U0_p_rows_assign_cast_out_out_write,
gamma_out_din => Block_Mat_exit570_pr_U0_gamma_out_din,
gamma_out_full_n => gamma_c_full_n,
gamma_out_write => Block_Mat_exit570_pr_U0_gamma_out_write,
ap_return_0 => Block_Mat_exit570_pr_U0_ap_return_0,
ap_return_1 => Block_Mat_exit570_pr_U0_ap_return_1);
AXIvideo2Mat_U0 : component AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => AXIvideo2Mat_U0_ap_start,
ap_done => AXIvideo2Mat_U0_ap_done,
ap_continue => AXIvideo2Mat_U0_ap_continue,
ap_idle => AXIvideo2Mat_U0_ap_idle,
ap_ready => AXIvideo2Mat_U0_ap_ready,
stream_in_TDATA => stream_in_TDATA,
stream_in_TVALID => stream_in_TVALID,
stream_in_TREADY => AXIvideo2Mat_U0_stream_in_TREADY,
stream_in_TKEEP => stream_in_TKEEP,
stream_in_TSTRB => stream_in_TSTRB,
stream_in_TUSER => stream_in_TUSER,
stream_in_TLAST => stream_in_TLAST,
stream_in_TID => stream_in_TID,
stream_in_TDEST => stream_in_TDEST,
img_rows_V_read => img0_rows_V_channel_dout,
img_cols_V_read => img0_cols_V_channel_dout,
img_data_stream_0_V_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => img0_data_stream_0_s_full_n,
img_data_stream_0_V_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => img0_data_stream_1_s_full_n,
img_data_stream_1_V_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => img0_data_stream_2_s_full_n,
img_data_stream_2_V_write => AXIvideo2Mat_U0_img_data_stream_2_V_write);
Loop_loop_height_pro_U0 : component Loop_loop_height_pro
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Loop_loop_height_pro_U0_ap_start,
ap_done => Loop_loop_height_pro_U0_ap_done,
ap_continue => Loop_loop_height_pro_U0_ap_continue,
ap_idle => Loop_loop_height_pro_U0_ap_idle,
ap_ready => Loop_loop_height_pro_U0_ap_ready,
p_rows_assign_cast_loc_dout => p_rows_assign_cast_lo_dout,
p_rows_assign_cast_loc_empty_n => p_rows_assign_cast_lo_empty_n,
p_rows_assign_cast_loc_read => Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read,
p_cols_assign_cast_loc_dout => p_cols_assign_cast_lo_dout,
p_cols_assign_cast_loc_empty_n => p_cols_assign_cast_lo_empty_n,
p_cols_assign_cast_loc_read => Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read,
img3_data_stream_0_V_din => Loop_loop_height_pro_U0_img3_data_stream_0_V_din,
img3_data_stream_0_V_full_n => img3_data_stream_0_s_full_n,
img3_data_stream_0_V_write => Loop_loop_height_pro_U0_img3_data_stream_0_V_write,
img3_data_stream_1_V_din => Loop_loop_height_pro_U0_img3_data_stream_1_V_din,
img3_data_stream_1_V_full_n => img3_data_stream_1_s_full_n,
img3_data_stream_1_V_write => Loop_loop_height_pro_U0_img3_data_stream_1_V_write,
img3_data_stream_2_V_din => Loop_loop_height_pro_U0_img3_data_stream_2_V_din,
img3_data_stream_2_V_full_n => img3_data_stream_2_s_full_n,
img3_data_stream_2_V_write => Loop_loop_height_pro_U0_img3_data_stream_2_V_write,
gamma_dout => gamma_c_dout,
gamma_empty_n => gamma_c_empty_n,
gamma_read => Loop_loop_height_pro_U0_gamma_read,
img0_data_stream_0_V_dout => img0_data_stream_0_s_dout,
img0_data_stream_0_V_empty_n => img0_data_stream_0_s_empty_n,
img0_data_stream_0_V_read => Loop_loop_height_pro_U0_img0_data_stream_0_V_read,
img0_data_stream_1_V_dout => img0_data_stream_1_s_dout,
img0_data_stream_1_V_empty_n => img0_data_stream_1_s_empty_n,
img0_data_stream_1_V_read => Loop_loop_height_pro_U0_img0_data_stream_1_V_read,
img0_data_stream_2_V_dout => img0_data_stream_2_s_dout,
img0_data_stream_2_V_empty_n => img0_data_stream_2_s_empty_n,
img0_data_stream_2_V_read => Loop_loop_height_pro_U0_img0_data_stream_2_V_read);
Mat2AXIvideo_U0 : component Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Mat2AXIvideo_U0_ap_start,
ap_done => Mat2AXIvideo_U0_ap_done,
ap_continue => Mat2AXIvideo_U0_ap_continue,
ap_idle => Mat2AXIvideo_U0_ap_idle,
ap_ready => Mat2AXIvideo_U0_ap_ready,
img_rows_V_dout => img3_rows_V_c_dout,
img_rows_V_empty_n => img3_rows_V_c_empty_n,
img_rows_V_read => Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_dout => img3_cols_V_c_dout,
img_cols_V_empty_n => img3_cols_V_c_empty_n,
img_cols_V_read => Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => img3_data_stream_0_s_dout,
img_data_stream_0_V_empty_n => img3_data_stream_0_s_empty_n,
img_data_stream_0_V_read => Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => img3_data_stream_1_s_dout,
img_data_stream_1_V_empty_n => img3_data_stream_1_s_empty_n,
img_data_stream_1_V_read => Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => img3_data_stream_2_s_dout,
img_data_stream_2_V_empty_n => img3_data_stream_2_s_empty_n,
img_data_stream_2_V_read => Mat2AXIvideo_U0_img_data_stream_2_V_read,
stream_out_TDATA => Mat2AXIvideo_U0_stream_out_TDATA,
stream_out_TVALID => Mat2AXIvideo_U0_stream_out_TVALID,
stream_out_TREADY => stream_out_TREADY,
stream_out_TKEEP => Mat2AXIvideo_U0_stream_out_TKEEP,
stream_out_TSTRB => Mat2AXIvideo_U0_stream_out_TSTRB,
stream_out_TUSER => Mat2AXIvideo_U0_stream_out_TUSER,
stream_out_TLAST => Mat2AXIvideo_U0_stream_out_TLAST,
stream_out_TID => Mat2AXIvideo_U0_stream_out_TID,
stream_out_TDEST => Mat2AXIvideo_U0_stream_out_TDEST);
img3_rows_V_c_U : component fifo_w16_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit570_pr_U0_img3_rows_V_out_din,
if_full_n => img3_rows_V_c_full_n,
if_write => Block_Mat_exit570_pr_U0_img3_rows_V_out_write,
if_dout => img3_rows_V_c_dout,
if_empty_n => img3_rows_V_c_empty_n,
if_read => Mat2AXIvideo_U0_img_rows_V_read);
img3_cols_V_c_U : component fifo_w16_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit570_pr_U0_img3_cols_V_out_din,
if_full_n => img3_cols_V_c_full_n,
if_write => Block_Mat_exit570_pr_U0_img3_cols_V_out_write,
if_dout => img3_cols_V_c_dout,
if_empty_n => img3_cols_V_c_empty_n,
if_read => Mat2AXIvideo_U0_img_cols_V_read);
p_cols_assign_cast_lo_U : component fifo_w12_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit570_pr_U0_p_cols_assign_cast_out_out_din,
if_full_n => p_cols_assign_cast_lo_full_n,
if_write => Block_Mat_exit570_pr_U0_p_cols_assign_cast_out_out_write,
if_dout => p_cols_assign_cast_lo_dout,
if_empty_n => p_cols_assign_cast_lo_empty_n,
if_read => Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read);
p_rows_assign_cast_lo_U : component fifo_w12_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit570_pr_U0_p_rows_assign_cast_out_out_din,
if_full_n => p_rows_assign_cast_lo_full_n,
if_write => Block_Mat_exit570_pr_U0_p_rows_assign_cast_out_out_write,
if_dout => p_rows_assign_cast_lo_dout,
if_empty_n => p_rows_assign_cast_lo_empty_n,
if_read => Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read);
gamma_c_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit570_pr_U0_gamma_out_din,
if_full_n => gamma_c_full_n,
if_write => Block_Mat_exit570_pr_U0_gamma_out_write,
if_dout => gamma_c_dout,
if_empty_n => gamma_c_empty_n,
if_read => Loop_loop_height_pro_U0_gamma_read);
img0_rows_V_channel_U : component fifo_w16_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit570_pr_U0_ap_return_0,
if_full_n => img0_rows_V_channel_full_n,
if_write => ap_channel_done_img0_rows_V_channel,
if_dout => img0_rows_V_channel_dout,
if_empty_n => img0_rows_V_channel_empty_n,
if_read => AXIvideo2Mat_U0_ap_ready);
img0_cols_V_channel_U : component fifo_w16_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit570_pr_U0_ap_return_1,
if_full_n => img0_cols_V_channel_full_n,
if_write => ap_channel_done_img0_cols_V_channel,
if_dout => img0_cols_V_channel_dout,
if_empty_n => img0_cols_V_channel_empty_n,
if_read => AXIvideo2Mat_U0_ap_ready);
img0_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
if_full_n => img0_data_stream_0_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
if_dout => img0_data_stream_0_s_dout,
if_empty_n => img0_data_stream_0_s_empty_n,
if_read => Loop_loop_height_pro_U0_img0_data_stream_0_V_read);
img0_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
if_full_n => img0_data_stream_1_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
if_dout => img0_data_stream_1_s_dout,
if_empty_n => img0_data_stream_1_s_empty_n,
if_read => Loop_loop_height_pro_U0_img0_data_stream_1_V_read);
img0_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
if_full_n => img0_data_stream_2_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
if_dout => img0_data_stream_2_s_dout,
if_empty_n => img0_data_stream_2_s_empty_n,
if_read => Loop_loop_height_pro_U0_img0_data_stream_2_V_read);
img3_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img3_data_stream_0_V_din,
if_full_n => img3_data_stream_0_s_full_n,
if_write => Loop_loop_height_pro_U0_img3_data_stream_0_V_write,
if_dout => img3_data_stream_0_s_dout,
if_empty_n => img3_data_stream_0_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_0_V_read);
img3_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img3_data_stream_1_V_din,
if_full_n => img3_data_stream_1_s_full_n,
if_write => Loop_loop_height_pro_U0_img3_data_stream_1_V_write,
if_dout => img3_data_stream_1_s_dout,
if_empty_n => img3_data_stream_1_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_1_V_read);
img3_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img3_data_stream_2_V_din,
if_full_n => img3_data_stream_2_s_full_n,
if_write => Loop_loop_height_pro_U0_img3_data_stream_2_V_write,
if_dout => img3_data_stream_2_s_dout,
if_empty_n => img3_data_stream_2_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_2_V_read);
start_for_Loop_lojbC_U : component start_for_Loop_lojbC
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Loop_loop_height_pro_U0_din,
if_full_n => start_for_Loop_loop_height_pro_U0_full_n,
if_write => Block_Mat_exit570_pr_U0_start_write,
if_dout => start_for_Loop_loop_height_pro_U0_dout,
if_empty_n => start_for_Loop_loop_height_pro_U0_empty_n,
if_read => Loop_loop_height_pro_U0_ap_ready);
start_for_Mat2AXIkbM_U : component start_for_Mat2AXIkbM
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Mat2AXIvideo_U0_din,
if_full_n => start_for_Mat2AXIvideo_U0_full_n,
if_write => Block_Mat_exit570_pr_U0_start_write,
if_dout => start_for_Mat2AXIvideo_U0_dout,
if_empty_n => start_for_Mat2AXIvideo_U0_empty_n,
if_read => Mat2AXIvideo_U0_ap_ready);
ap_sync_reg_channel_write_img0_cols_V_channel_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_sync_reg_channel_write_img0_cols_V_channel <= ap_const_logic_0;
else
if (((Block_Mat_exit570_pr_U0_ap_done and Block_Mat_exit570_pr_U0_ap_continue) = ap_const_logic_1)) then
ap_sync_reg_channel_write_img0_cols_V_channel <= ap_const_logic_0;
else
ap_sync_reg_channel_write_img0_cols_V_channel <= ap_sync_channel_write_img0_cols_V_channel;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_img0_rows_V_channel_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_sync_reg_channel_write_img0_rows_V_channel <= ap_const_logic_0;
else
if (((Block_Mat_exit570_pr_U0_ap_done and Block_Mat_exit570_pr_U0_ap_continue) = ap_const_logic_1)) then
ap_sync_reg_channel_write_img0_rows_V_channel <= ap_const_logic_0;
else
ap_sync_reg_channel_write_img0_rows_V_channel <= ap_sync_channel_write_img0_rows_V_channel;
end if;
end if;
end if;
end process;
AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
AXIvideo2Mat_U0_ap_start <= (img0_rows_V_channel_empty_n and img0_cols_V_channel_empty_n);
AXIvideo2Mat_U0_start_full_n <= ap_const_logic_1;
AXIvideo2Mat_U0_start_write <= ap_const_logic_0;
Block_Mat_exit570_pr_U0_ap_continue <= (ap_sync_channel_write_img0_rows_V_channel and ap_sync_channel_write_img0_cols_V_channel);
Block_Mat_exit570_pr_U0_ap_start <= ap_const_logic_1;
Block_Mat_exit570_pr_U0_start_full_n <= (start_for_Mat2AXIvideo_U0_full_n and start_for_Loop_loop_height_pro_U0_full_n);
Loop_loop_height_pro_U0_ap_continue <= ap_const_logic_1;
Loop_loop_height_pro_U0_ap_start <= start_for_Loop_loop_height_pro_U0_empty_n;
Loop_loop_height_pro_U0_start_full_n <= ap_const_logic_1;
Loop_loop_height_pro_U0_start_write <= ap_const_logic_0;
Mat2AXIvideo_U0_ap_continue <= ap_const_logic_1;
Mat2AXIvideo_U0_ap_start <= start_for_Mat2AXIvideo_U0_empty_n;
Mat2AXIvideo_U0_start_full_n <= ap_const_logic_1;
Mat2AXIvideo_U0_start_write <= ap_const_logic_0;
ap_channel_done_img0_cols_V_channel <= ((ap_sync_reg_channel_write_img0_cols_V_channel xor ap_const_logic_1) and Block_Mat_exit570_pr_U0_ap_done);
ap_channel_done_img0_rows_V_channel <= ((ap_sync_reg_channel_write_img0_rows_V_channel xor ap_const_logic_1) and Block_Mat_exit570_pr_U0_ap_done);
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sync_channel_write_img0_cols_V_channel <= ((img0_cols_V_channel_full_n and ap_channel_done_img0_cols_V_channel) or ap_sync_reg_channel_write_img0_cols_V_channel);
ap_sync_channel_write_img0_rows_V_channel <= ((img0_rows_V_channel_full_n and ap_channel_done_img0_rows_V_channel) or ap_sync_reg_channel_write_img0_rows_V_channel);
ap_sync_continue <= ap_const_logic_0;
start_for_Loop_loop_height_pro_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_Mat2AXIvideo_U0_din <= (0=>ap_const_logic_1, others=>'-');
stream_in_TREADY <= AXIvideo2Mat_U0_stream_in_TREADY;
stream_out_TDATA <= Mat2AXIvideo_U0_stream_out_TDATA;
stream_out_TDEST <= Mat2AXIvideo_U0_stream_out_TDEST;
stream_out_TID <= Mat2AXIvideo_U0_stream_out_TID;
stream_out_TKEEP <= Mat2AXIvideo_U0_stream_out_TKEEP;
stream_out_TLAST <= Mat2AXIvideo_U0_stream_out_TLAST;
stream_out_TSTRB <= Mat2AXIvideo_U0_stream_out_TSTRB;
stream_out_TUSER <= Mat2AXIvideo_U0_stream_out_TUSER;
stream_out_TVALID <= Mat2AXIvideo_U0_stream_out_TVALID;
end behav;
|
mit
|
70f78f7b8ee4799fa64feaee7d718500
| 0.623951 | 2.803593 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enrcU.vhd
| 1 | 1,686 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_enrcU_DSP48_2 is
port (
a: in std_logic_vector(19 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(27 - 1 downto 0));
end entity;
architecture behav of hls_saturation_enrcU_DSP48_2 is
signal a_cvt: unsigned(19 - 1 downto 0);
signal b_cvt: unsigned(8 - 1 downto 0);
signal p_cvt: unsigned(27 - 1 downto 0);
attribute keep : string;
attribute keep of a_cvt : signal is "true";
attribute keep of b_cvt : signal is "true";
attribute keep of p_cvt : signal is "true";
begin
a_cvt <= unsigned(a);
b_cvt <= unsigned(b);
p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 27));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_enrcU is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_enrcU is
component hls_saturation_enrcU_DSP48_2 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_enrcU_DSP48_2_U : component hls_saturation_enrcU_DSP48_2
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
671e8e5032a47cc35e31254a559d7e21
| 0.616845 | 3.305882 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_bkb.vhd
| 1 | 12,674 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_bkb_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_bkb_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00010101", 2 => "00011100", 3 => "00100010",
4 => "00100111", 5 => "00101011", 6 => "00101110", 7 => "00110010",
8 => "00110101", 9 => "00111000", 10 => "00111011", 11 => "00111101",
12 => "01000000", 13 => "01000010", 14 => "01000100", 15 => "01000110",
16 => "01001000", 17 => "01001010", 18 => "01001100", 19 => "01001110",
20 => "01010000", 21 => "01010010", 22 => "01010100", 23 => "01010101",
24 => "01010111", 25 => "01011001", 26 => "01011010", 27 => "01011100",
28 => "01011101", 29 => "01011111", 30 => "01100000", 31 => "01100010",
32 => "01100011", 33 => "01100101", 34 => "01100110", 35 => "01100111",
36 => "01101001", 37 => "01101010", 38 => "01101011", 39 => "01101101",
40 => "01101110", 41 => "01101111", 42 => "01110000", 43 => "01110010",
44 => "01110011", 45 => "01110100", 46 => "01110101", 47 => "01110110",
48 => "01110111", 49 => "01111000", 50 => "01111010", 51 => "01111011",
52 => "01111100", 53 => "01111101", 54 => "01111110", 55 => "01111111",
56 => "10000000", 57 => "10000001", 58 => "10000010", 59 => "10000011",
60 => "10000100", 61 => "10000101", 62 => "10000110", 63 => "10000111",
64 => "10001000", 65 => "10001001", 66 => "10001010", 67 => "10001011",
68 => "10001100", 69 => "10001101", 70 => "10001110", 71 => "10001111",
72 to 73=> "10010000", 74 => "10010001", 75 => "10010010", 76 => "10010011",
77 => "10010100", 78 => "10010101", 79 => "10010110", 80 to 81=> "10010111",
82 => "10011000", 83 => "10011001", 84 => "10011010", 85 => "10011011",
86 to 87=> "10011100", 88 => "10011101", 89 => "10011110", 90 => "10011111",
91 to 92=> "10100000", 93 => "10100001", 94 => "10100010", 95 => "10100011",
96 to 97=> "10100100", 98 => "10100101", 99 => "10100110", 100 to 101=> "10100111",
102 => "10101000", 103 => "10101001", 104 to 105=> "10101010", 106 => "10101011",
107 => "10101100", 108 to 109=> "10101101", 110 => "10101110", 111 to 112=> "10101111",
113 => "10110000", 114 => "10110001", 115 to 116=> "10110010", 117 => "10110011",
118 to 119=> "10110100", 120 => "10110101", 121 to 122=> "10110110", 123 => "10110111",
124 to 125=> "10111000", 126 => "10111001", 127 to 128=> "10111010", 129 => "10111011",
130 to 131=> "10111100", 132 => "10111101", 133 to 134=> "10111110", 135 => "10111111",
136 to 137=> "11000000", 138 => "11000001", 139 to 140=> "11000010", 141 to 142=> "11000011",
143 => "11000100", 144 to 145=> "11000101", 146 => "11000110", 147 to 148=> "11000111",
149 to 150=> "11001000", 151 => "11001001", 152 to 153=> "11001010", 154 to 155=> "11001011",
156 => "11001100", 157 to 158=> "11001101", 159 to 160=> "11001110", 161 to 162=> "11001111",
163 => "11010000", 164 to 165=> "11010001", 166 to 167=> "11010010", 168 => "11010011",
169 to 170=> "11010100", 171 to 172=> "11010101", 173 to 174=> "11010110", 175 to 176=> "11010111",
177 => "11011000", 178 to 179=> "11011001", 180 to 181=> "11011010", 182 to 183=> "11011011",
184 to 185=> "11011100", 186 to 187=> "11011101", 188 => "11011110", 189 to 190=> "11011111",
191 to 192=> "11100000", 193 to 194=> "11100001", 195 to 196=> "11100010", 197 to 198=> "11100011",
199 to 200=> "11100100", 201 to 202=> "11100101", 203 to 204=> "11100110", 205 to 206=> "11100111",
207 to 208=> "11101000", 209 to 210=> "11101001", 211 to 212=> "11101010", 213 to 214=> "11101011",
215 to 216=> "11101100", 217 to 218=> "11101101", 219 to 220=> "11101110", 221 to 222=> "11101111",
223 to 224=> "11110000", 225 to 226=> "11110001", 227 to 228=> "11110010", 229 to 230=> "11110011",
231 to 232=> "11110100", 233 to 234=> "11110101", 235 to 236=> "11110110", 237 to 238=> "11110111",
239 to 240=> "11111000", 241 to 243=> "11111001", 244 to 245=> "11111010", 246 to 247=> "11111011",
248 to 249=> "11111100", 250 to 251=> "11111101", 252 to 253=> "11111110", 254 to 255=> "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00010101", 2 => "00011100", 3 => "00100010",
4 => "00100111", 5 => "00101011", 6 => "00101110", 7 => "00110010",
8 => "00110101", 9 => "00111000", 10 => "00111011", 11 => "00111101",
12 => "01000000", 13 => "01000010", 14 => "01000100", 15 => "01000110",
16 => "01001000", 17 => "01001010", 18 => "01001100", 19 => "01001110",
20 => "01010000", 21 => "01010010", 22 => "01010100", 23 => "01010101",
24 => "01010111", 25 => "01011001", 26 => "01011010", 27 => "01011100",
28 => "01011101", 29 => "01011111", 30 => "01100000", 31 => "01100010",
32 => "01100011", 33 => "01100101", 34 => "01100110", 35 => "01100111",
36 => "01101001", 37 => "01101010", 38 => "01101011", 39 => "01101101",
40 => "01101110", 41 => "01101111", 42 => "01110000", 43 => "01110010",
44 => "01110011", 45 => "01110100", 46 => "01110101", 47 => "01110110",
48 => "01110111", 49 => "01111000", 50 => "01111010", 51 => "01111011",
52 => "01111100", 53 => "01111101", 54 => "01111110", 55 => "01111111",
56 => "10000000", 57 => "10000001", 58 => "10000010", 59 => "10000011",
60 => "10000100", 61 => "10000101", 62 => "10000110", 63 => "10000111",
64 => "10001000", 65 => "10001001", 66 => "10001010", 67 => "10001011",
68 => "10001100", 69 => "10001101", 70 => "10001110", 71 => "10001111",
72 to 73=> "10010000", 74 => "10010001", 75 => "10010010", 76 => "10010011",
77 => "10010100", 78 => "10010101", 79 => "10010110", 80 to 81=> "10010111",
82 => "10011000", 83 => "10011001", 84 => "10011010", 85 => "10011011",
86 to 87=> "10011100", 88 => "10011101", 89 => "10011110", 90 => "10011111",
91 to 92=> "10100000", 93 => "10100001", 94 => "10100010", 95 => "10100011",
96 to 97=> "10100100", 98 => "10100101", 99 => "10100110", 100 to 101=> "10100111",
102 => "10101000", 103 => "10101001", 104 to 105=> "10101010", 106 => "10101011",
107 => "10101100", 108 to 109=> "10101101", 110 => "10101110", 111 to 112=> "10101111",
113 => "10110000", 114 => "10110001", 115 to 116=> "10110010", 117 => "10110011",
118 to 119=> "10110100", 120 => "10110101", 121 to 122=> "10110110", 123 => "10110111",
124 to 125=> "10111000", 126 => "10111001", 127 to 128=> "10111010", 129 => "10111011",
130 to 131=> "10111100", 132 => "10111101", 133 to 134=> "10111110", 135 => "10111111",
136 to 137=> "11000000", 138 => "11000001", 139 to 140=> "11000010", 141 to 142=> "11000011",
143 => "11000100", 144 to 145=> "11000101", 146 => "11000110", 147 to 148=> "11000111",
149 to 150=> "11001000", 151 => "11001001", 152 to 153=> "11001010", 154 to 155=> "11001011",
156 => "11001100", 157 to 158=> "11001101", 159 to 160=> "11001110", 161 to 162=> "11001111",
163 => "11010000", 164 to 165=> "11010001", 166 to 167=> "11010010", 168 => "11010011",
169 to 170=> "11010100", 171 to 172=> "11010101", 173 to 174=> "11010110", 175 to 176=> "11010111",
177 => "11011000", 178 to 179=> "11011001", 180 to 181=> "11011010", 182 to 183=> "11011011",
184 to 185=> "11011100", 186 to 187=> "11011101", 188 => "11011110", 189 to 190=> "11011111",
191 to 192=> "11100000", 193 to 194=> "11100001", 195 to 196=> "11100010", 197 to 198=> "11100011",
199 to 200=> "11100100", 201 to 202=> "11100101", 203 to 204=> "11100110", 205 to 206=> "11100111",
207 to 208=> "11101000", 209 to 210=> "11101001", 211 to 212=> "11101010", 213 to 214=> "11101011",
215 to 216=> "11101100", 217 to 218=> "11101101", 219 to 220=> "11101110", 221 to 222=> "11101111",
223 to 224=> "11110000", 225 to 226=> "11110001", 227 to 228=> "11110010", 229 to 230=> "11110011",
231 to 232=> "11110100", 233 to 234=> "11110101", 235 to 236=> "11110110", 237 to 238=> "11110111",
239 to 240=> "11111000", 241 to 243=> "11111001", 244 to 245=> "11111010", 246 to 247=> "11111011",
248 to 249=> "11111100", 250 to 251=> "11111101", 252 to 253=> "11111110", 254 to 255=> "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_bkb is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_bkb is
component Loop_loop_height_bkb_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_bkb_rom_U : component Loop_loop_height_bkb_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
cf35bcb31b6da4b16443e601ac21132d
| 0.557835 | 3.569135 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/ttop_TB.vhd
| 2 | 2,650 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:03:48 07/08/2015
-- Design Name:
-- Module Name: D:/Descargas/Frecuencimentro - Presentacion/ttop_TB.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ttop_TB IS
END ttop_TB;
ARCHITECTURE behavior OF ttop_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
10f1180f3f35b9e4e2d0a2def0389b23
| 0.568302 | 4.015152 | false | true | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enpcA.vhd
| 1 | 2,675 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_enpcA_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(29 - 1 downto 0);
b: in std_logic_vector(28 - 1 downto 0);
p: out std_logic_vector(47 - 1 downto 0));
end entity;
architecture behav of hls_saturation_enpcA_MulnS_0 is
signal tmp_product : std_logic_vector(47 - 1 downto 0);
signal a_i : std_logic_vector(29 - 1 downto 0);
signal b_i : std_logic_vector(28 - 1 downto 0);
signal p_tmp : std_logic_vector(47 - 1 downto 0);
signal a_reg0 : std_logic_vector(29 - 1 downto 0);
signal b_reg0 : std_logic_vector(28 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(47 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed('0' & b_reg0))), 47));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_enpcA is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_enpcA is
component hls_saturation_enpcA_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_enpcA_MulnS_0_U : component hls_saturation_enpcA_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
c08ca3f86fb7050c4dab71687563211d
| 0.551776 | 3.442728 | false | false | false | false |
Digilent/vivado-library
|
ip/dvi2rgb/src/dvi2rgb.vhd
| 1 | 14,254 |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "dgl_720p_cea.data"; -- Select EDID file to use
kDebug : boolean := true;
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- DEPRECATED advanced use only; PixelClk and SerialClk stable
pLocked : out std_logic; -- PixelClk and SerialClk stable, async de-assert, assert sync to PixelClk
-- Optional DDC port
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_T : out std_logic;
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
COMPONENT ila_refclk
PORT (
clk : IN STD_LOGIC;
trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_pixclk
PORT (
clk : IN STD_LOGIC;
trig_in : IN STD_LOGIC;
trig_in_ack : OUT STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT ;
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
-- DEBUG
signal dbg_rDlyRst : std_logic;
signal dbg_rRdyRst : std_logic;
signal dbg_rMMCM_Reset : std_logic;
signal dbg_rBUFR_Rst : std_logic;
signal dbg_rMMCM_Locked : std_logic;
signal dbg_Clocking_aLocked : std_logic;
signal dbg_pAlignErr, dbg_pBitslip : std_logic_vector(2 downto 0);
signal dbg_pEyeSize : eyeSize_t;
signal pTrigOut, pTrigOutAck, rTrigOutAck, rTrigOut : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int, -- fast serial clock
dbg_rDlyRst => dbg_rDlyRst,
dbg_rRdyRst => dbg_rRdyRst,
dbg_rMMCM_Reset => dbg_rMMCM_Reset,
dbg_rBUFR_Rst => dbg_rBUFR_Rst,
dbg_rMMCM_Locked => dbg_rMMCM_Locked
);
dbg_Clocking_aLocked <= aLocked;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Sync our locked signal back to the PixelClk domain, because the reset controller block
-- expects it that way.
-- TODO: might need to sync to PixelClk, if BUFG is inserted below
LockedSync: entity work.ResetBridge
generic map (
kPolarity => '0')
port map (
aRst => aLocked,
OutClk => PixelClk_int,
oRst => pLocked);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
dbg_pEyeSize => dbg_pEyeSize(iCh),
dbg_pAlignErr => dbg_pAlignErr(iCh),
dbg_pBitslip => dbg_pBitslip(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(1); -- green is channel 1
pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 8, -- 256 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => SDA_I,
aSDA_O => SDA_O,
aSDA_T => SDA_T,
aSCL_I => SCL_I,
aSCL_O => SCL_O,
aSCL_T => SCL_T);
end generate GenerateDDC;
----------------------------------------------------------------------------------
-- Debug module
----------------------------------------------------------------------------------
GenerateDebug: if kDebug generate
ILA_RefClkx : ila_refclk
PORT MAP (
clk => RefClk,
trig_out => rTrigOut,
trig_out_ack => rTrigOutAck,
probe0(0) => dbg_rDlyRst,
probe1(0) => dbg_rRdyRst,
probe2(0) => dbg_rMMCM_Reset,
probe3(0) => dbg_rBUFR_Rst,
probe4(0) => dbg_rMMCM_Locked,
probe5(0) => dbg_Clocking_aLocked
);
SyncAsyncTrigAck: entity work.SyncAsync
port map (
aReset => '0',
aIn => pTrigOutAck,
OutClk => RefClk,
oOut => rTrigOutAck);
SyncAsyncTrigOut: entity work.SyncAsync
port map (
aReset => '0',
aIn => rTrigOut,
OutClk => PixelClk_int,
oOut => pTrigOut);
ILA_PixClkx : ila_pixclk
PORT MAP (
clk => PixelClk_int,
trig_in => pTrigOut,
trig_in_ack => pTrigOutAck,
probe0(0) => pLockLostRst,
probe1 => dbg_pEyeSize(0),
probe2 => dbg_pEyeSize(1),
probe3 => dbg_pEyeSize(2),
probe4 => dbg_pAlignErr,
probe5 => dbg_pBitslip,
probe6 => pVld,
probe7 => pRdy
);
end generate;
end Behavioral;
|
mit
|
ecf8c86477d50798119b5ed83f4366aa
| 0.610285 | 4.20472 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/MIPI_CSI_2_RX_v1_0_S_AXI_LITE.vhd
| 1 | 15,076 |
-------------------------------------------------------------------------------
--
-- File: MIPI_CSI_2_RX_v1_0_S_AXI_LITE.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MIPI_CSI_2_RX_S_AXI_LITE is
generic (
-- Users to add parameters here
kVersionMajor : natural := 0;
kVersionMinor : natural := 0;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
xEnable : out std_logic;
xRst : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end MIPI_CSI_2_RX_S_AXI_LITE;
architecture arch_imp of MIPI_CSI_2_RX_S_AXI_LITE is
constant kCTRL_EN : natural := 1;
constant kCTRL_RST : natural := 0;
constant kVersion : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(kVersionMajor,16)) & std_logic_vector(to_unsigned(kVersionMinor,16));
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 1
signal control_reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
control_reg <= (kCTRL_RST => '0', kCTRL_EN => '1', others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
control_reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
control_reg <= control_reg;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (control_reg, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= control_reg;
when b"11" =>
reg_data_out <= kVersion;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
xEnable <= control_reg(kCTRL_EN);
xRst <= control_reg(kCTRL_RST);
-- User logic ends
end arch_imp;
|
mit
|
87dd15a616417f3261d3e50d49ec6f9a
| 0.636243 | 3.564909 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/TOP.vhd
| 1 | 4,925 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TOP is
PORT(
boton_seleccionado: IN std_logic_vector(2 DOWNTO 0); --ENTRADAS TOP
piso_actual: IN std_logic_vector(2 DOWNTO 0);
nivel, celula, abierto, cerrado: IN std_logic;
puerta, motor_subir, motor_bajar: OUT std_logic; --SALIDAS TOP
piso0_sel, piso1_sel, piso2_sel: OUT std_logic;
segmentos: OUT std_logic_vector(7 DOWNTO 0);
seg_ctrl: OUT std_logic_vector(3 DOWNTO 0);
clk: in std_logic; --clk:antes de entrar al divisorfrec
reset: in std_logic
);
end TOP;
architecture Behavioral of TOP is
COMPONENT convertidor_piso_actual
PORT(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
piso_actual: IN std_logic_vector(2 DOWNTO 0);
boton_seleccionado: IN std_logic_vector(2 DOWNTO 0);
piso_actual_convertido: OUT std_logic_vector(1 DOWNTO 0);
boton_seleccionado_convertido: OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT divisorfrec
PORT (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
salida:out STD_LOGIC
);
END COMPONENT;
COMPONENT FSM
PORT(
clock,reset,nivel,abierto, cerrado: IN std_logic;
piso,boton :IN STD_LOGIC_VECTOR (1 DOWNTO 0);
boton_memoria: out STD_LOGIC_VECTOR (1 DOWNTO 0);
accionador_puerta: out STD_LOGIC;
accionador_subir, accionador_bajar: out STD_LOGIC
);
END COMPONENT;
COMPONENT gestor_display
PORT (
CLK : in STD_LOGIC;
piso_now : in STD_LOGIC_VECTOR (1 downto 0);
piso_obj : in STD_LOGIC_VECTOR (1 downto 0);
piso_seleccionado : out STD_LOGIC_VECTOR (1 downto 0);
piso_actual : out STD_LOGIC_VECTOR (1 downto 0);
accion : out STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
COMPONENT decoder
PORT (
CLK : IN std_logic;
RST : IN std_logic;
code : IN std_logic_vector(1 DOWNTO 0);
action : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
led : OUT std_logic_vector(6 DOWNTO 0);
dig_ctrl : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT dec_piso_seleccion
PORT (
piso_code : in STD_LOGIC_VECTOR (1 downto 0);
piso0 : out STD_LOGIC;
piso1 : out STD_LOGIC;
piso2 : out STD_LOGIC
);
END COMPONENT;
COMPONENT motor_puerta
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
nivel : in STD_LOGIC;
celula : in STD_LOGIC;
accionar_puerta : in STD_LOGIC;
actuador_puerta : out STD_LOGIC
);
END COMPONENT;
COMPONENT motor_ascensor
PORT(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
accionar_bajar: in STD_LOGIC;
accionar_subir: in STD_LOGIC;
motor_subir: out STD_LOGIC;
motor_bajar : out STD_LOGIC
);
END COMPONENT;
signal sig_puerta:std_logic; --Senal para motor_puerta
signal sig_subir:std_logic; --Senal para motor_subir
signal sig_bajar:std_logic; --Senal para motor_bajar
signal inoutreloj:std_logic; --Senal del divisor de frecuencia
signal inoutpiso_actual:std_logic_vector (1 DOWNTO 0);
signal inoutpiso_deseado:std_logic_vector (1 DOWNTO 0);
signal sig_boton_pulsado:std_logic_vector (1 DOWNTO 0);
signal code_piso_actual:std_logic_vector (1 DOWNTO 0);
signal code_piso_objetivo:std_logic_vector (1 DOWNTO 0);
signal sig_action:std_logic_vector (1 DOWNTO 0);
begin
inst_convertidor_piso_actual:convertidor_piso_actual port map(
clk => clk,
rst => reset,
piso_actual => piso_actual,
boton_seleccionado => boton_seleccionado,
piso_actual_convertido => inoutpiso_actual,
boton_seleccionado_convertido => inoutpiso_deseado
);
inst_divisorfrec:divisorfrec port map(
clk => clk,
reset => reset,
salida => inoutreloj
);
inst_FSM:FSM port map(
abierto => abierto,
cerrado => cerrado,
clock => inoutreloj,
reset => reset,
nivel => nivel,
piso => inoutpiso_actual,
boton => inoutpiso_deseado,
boton_memoria => sig_boton_pulsado,
accionador_puerta => sig_puerta,
accionador_subir => sig_subir,
accionador_bajar => sig_bajar
);
inst_gestor_display:gestor_display port map(
CLK => inoutreloj,
piso_now => inoutpiso_actual,
piso_obj => sig_boton_pulsado,
piso_seleccionado => code_piso_objetivo,
piso_actual => code_piso_actual,
accion => sig_action
);
inst_decoder: decoder port map(
CLK => inoutreloj,
RST => reset,
code => code_piso_actual,
action => sig_action,
led => segmentos (7 downto 1),
dig_ctrl => seg_ctrl
);
segmentos(0) <= '1'; --punto decimal
inst_dec_piso_seleccion:dec_piso_seleccion port map(
piso_code => code_piso_objetivo,
piso0 => piso0_sel,
piso1 => piso1_sel,
piso2 => piso2_sel
);
inst_motor_puerta:motor_puerta port map(
CLK => clk,
RST => reset,
nivel => nivel,
celula => celula,
accionar_puerta => sig_puerta,
actuador_puerta => puerta
);
inst_motor_ascensor:motor_ascensor port map(
CLK => clk,
RST => reset,
accionar_bajar => sig_bajar,
accionar_subir => sig_subir,
motor_subir => motor_subir,
motor_bajar => motor_bajar
);
end Behavioral;
|
gpl-3.0
|
35e90ca6642cf582d7fe38d941ae7706
| 0.676345 | 3.008552 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_endEe.vhd
| 1 | 2,150 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_endEe_DSP48_0 is
port (
in0: in std_logic_vector(20 - 1 downto 0);
in1: in std_logic_vector(16 - 1 downto 0);
in2: in std_logic_vector(27 - 1 downto 0);
dout: out std_logic_vector(36 - 1 downto 0));
end entity;
architecture behav of hls_saturation_endEe_DSP48_0 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(unsigned(in0), 25));
b <= signed(resize(signed(in1), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 36));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_endEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_endEe is
component hls_saturation_endEe_DSP48_0 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_endEe_DSP48_0_U : component hls_saturation_endEe_DSP48_0
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
cd232d6727c216434ab9eb60bf557132
| 0.570233 | 3.359375 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/IO.vhd
| 1 | 5,771 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity IO is
port (
clk : in std_logic;
enable : in boolean;
code : in std_logic_vector(2 downto 0);
getTag : in tag_t;
putVal : in value_t;
blocking : out boolean := false; -- workaround for compatibability
emitTag : out tag_t := "00000";
emitVal : out value_t := (others => '0');
u232c_in : out u232c_in_t := ((others => '0'), '0', '0');
u232c_out : in u232c_out_t;
emit_instw : out blkram_write_t := (false, (others => '0'), (others => '0')));
end IO;
architecture behavioral of IO is
subtype cnt_t is unsigned(1 downto 0);
type buf_t is array(3 downto 0) of std_logic_vector(7 downto 0);
signal recv_cnt, send_cnt : cnt_t := "00";
signal recv_buf, send_buf : buf_t := (others => (others => '0'));
signal inst_ptr_lat : blkram_addr := (others => '0');
signal code_i : std_logic_vector(2 downto 0) := "000";
signal enable_i : boolean := false;
signal getTag_i : tag_t := "00000";
signal putVal_i : value_t := (others => '0');
signal ok, go : std_logic := '0';
signal blocking_i : boolean := false;
begin
u232c_in.ok <= ok;
u232c_in.go <= go;
blocking <= blocking_i;
sequential : process(clk)
variable code_v : std_logic_vector(2 downto 0);
variable enable_v : boolean;
variable getTag_v : tag_t;
variable putVal_v : value_t;
variable recv_cnt_v, send_cnt_v : cnt_t;
variable blocking_v : boolean;
begin
if rising_edge(clk) then
emit_instw.enable <= enable and code = "101";
emit_instw.addr <= inst_ptr_lat;
emit_instw.inst <= instruction_t(putVal);
if enable then
case code is
when "100" =>
inst_ptr_lat <= blkram_addr(putVal(15 downto 0));
when "101" =>
inst_ptr_lat <= inst_ptr_lat + 1;
when others => null;
end case;
end if;
if blocking_i then
code_v := code_i;
enable_v := enable_i;
getTag_v := getTag_i;
putVal_v := putVal_i;
else
code_v := code;
enable_v := enable;
getTag_v := getTag;
putVal_v := putVal;
end if;
code_i <= code_v;
enable_i <= enable_v;
getTag_i <= getTag_v;
putVal_i <= putVal_v;
if u232c_out.recf = '1' and ok = '0' and recv_cnt /= 3 then
ok <= '1';
recv_buf(3 downto 1) <= recv_buf(2 downto 0);
recv_buf(0) <= u232c_out.recv_data;
end if;
if u232c_out.recf = '0' and ok = '1' then
ok <= '0';
end if;
if u232c_out.sent = '1' and go = '0' and send_cnt /= 0 then
go <= '1';
send_cnt_v := send_cnt - 1;
else
send_cnt_v := send_cnt;
end if;
u232c_in.send_data <= send_buf(to_integer(send_cnt - 1));
if u232c_out.sent = '0' and go = '1' then
go <= '0';
end if;
blocking_v := false;
recv_cnt_v := recv_cnt;
if enable_v then
case code_v is
when "000" => assert(false);
when "001" => assert(false);
when others => null;
end case;
case code_v is
when "110" | "111" =>
emitTag <= getTag_v;
when "010" =>
if recv_cnt /= 0 then
emitTag <= getTag_v;
else
emitTag <= "00000";
end if;
when others =>
emitTag <= "00000";
end case;
case code_v is
when "010" =>
if recv_cnt = 0 then
blocking_v := true;
else
recv_cnt_v := recv_cnt - 1;
end if;
when "011" =>
if send_cnt_v = 3 then
blocking_v := true;
else
send_buf(0) <= putVal_v(7 downto 0);
send_buf(3 downto 1) <= send_buf(2 downto 0);
send_cnt_v := send_cnt_v + 1;
end if;
when others => null;
end case;
case code_v is
when "110" =>
emitVal <= x"0000000" & "00" & std_logic_vector(recv_cnt);
when "111" =>
emitVal <= x"0000000" & "00" & std_logic_vector(send_cnt);
when others =>
emitVal <= x"000000" & recv_buf(to_integer(recv_cnt - 1));
end case;
else
emitTag <= "00000";
emitVal <= recv_buf(3) & recv_buf(2) & recv_buf(1) & recv_buf(0);
end if;
if u232c_out.recf = '1' and ok = '0' and recv_cnt /= 3 then
recv_cnt_v := recv_cnt_v + 1;
else
recv_cnt_v := recv_cnt_v;
end if;
recv_cnt <= recv_cnt_v;
send_cnt <= send_cnt_v;
blocking_i <= blocking_v;
end if;
end process;
end behavioral;
|
bsd-2-clause
|
4a441db4123b5553ae4a381bc502381c
| 0.417432 | 3.988252 | false | false | false | false |
mtaygur/vhdl-alu-averagefilter-prng
|
rng.vhd
| 1 | 1,021 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity rng is
port ( output: out std_logic_vector(31 downto 0);
clk: in std_logic;
seed_btn: in std_logic);
end rng;
architecture Behavioral of rng is
signal r1,r2,r3,r4,r_out: std_logic_vector(31 downto 0) := x"00000000";
signal clk_cnt:integer range 0 to 65536 :=0;
signal rnd_begin: std_logic :='0';
begin
process(clk)
begin
if rising_edge(clk) then
if clk_cnt=65535 then
clk_cnt<=0;
end if;
clk_cnt<=clk_cnt+1;
end if;
if rnd_begin='1' then
r_out<=r4;
r4<=r3;
r3<=r2;
r2<=r1;
r1<= ((r2(11 downto 0) & x"00000") xor (x"0000" & r3(31 downto 16))) xor ((r4(21 downto 0) & "0000000000") xor ("000000" & r_out(31 downto 6))) ;
output<=r_out;
elsif rnd_begin='0' then
r4<= std_logic_vector(to_unsigned(clk_cnt,16)) & std_logic_vector(to_unsigned(clk_cnt,16));
r3<= x"D3C4B5A6";
r2<= x"19202122";
r1<= x"184674A2";
end if;
end process;
process(seed_btn)
begin
if rising_edge(seed_btn) then
rnd_begin<='1';
end if;
end process;
end Behavioral;
|
gpl-2.0
|
4279325ed0ae5a8e4b9022eb49f963ca
| 0.681685 | 2.391101 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
lcd_decoder/lcd_decoder.vhd
| 1 | 1,007 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd_decoder is
Port ( d : in std_logic_vector(3 downto 0);
s : out std_logic_vector(6 downto 0));
end lcd_decoder;
architecture Behavioral of lcd_decoder is
begin
S <= "1000000" when D="0000" else
"1111001" when D="0001" else
"0100100" when D="0010" else
"0110000" when D="0011" else
"0011001" when D="0100" else
"0010010" when D="0101" else
"0000010" when D="0110" else
"1111000" when D="0111" else
"0000000" when D="1000" else
"0010000" when D="1001" else
"0001000" when D="1010" else
"0000011" when D="1011" else
"1000110" when D="1100" else
"0100001" when D="1101" else
"0000110" when D="1110" else
"0001110";
end Behavioral;
|
mit
|
f0abdd8b064bce6637574ae87255f8ca
| 0.663357 | 3.166667 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_my_part/Interpolation.vhd
| 1 | 14,024 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity INTERPOLATION is
generic
(
width : integer := 8
);
port
(
Clock : in std_logic;
----------------------------------------------------
B31 : in std_logic_vector( width downto 0 );
B33 : in std_logic_vector( width downto 0 );
B35 : in std_logic_vector( width downto 0 );
G32 : in std_logic_vector( width downto 0 );
G34 : in std_logic_vector( width downto 0 );
------------------------------------------------------
B13 : in std_logic_vector( width downto 0 );
B53 : in std_logic_vector( width downto 0 );
G23 : in std_logic_vector( width downto 0 );
G43 : in std_logic_vector( width downto 0 );
----------------------------------------------------
EdgeHorizontal : in std_logic_vector( width downto 0 );
EdgeVertical : in std_logic_vector( width downto 0 );
mytest : out std_logic_vector( width downto 0 );
-------------------------------------------------------------
G : out std_logic_vector( width downto 0 )
);
end INTERPOLATION;
architecture TABLE of INTERPOLATION is
type Column is array( 0 to 6 ) of std_logic_vector( width downto 0 );
type Matrix is array ( 0 to 6 ) of Column;
constant TestMatrix : Matrix :=
(
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" )
);
signal BayerPattern : Matrix;
component CSAFullAdder is
generic
(
width : integer := 8
);
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
x_3 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end component;
component CSAHalfAdder is
generic
(
width : integer := 8
);
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end component;
component absolute
generic
(
width : integer := 8
);
Port
(
x : in std_logic_vector( width downto 0 );
y : out std_logic_vector( width downto 0)
);
end component;
component CalculateG
generic
(
width : integer := 8
);
port
(
-- Difference0 : in std_logic_vector( width + 3 downto 0 );
-- Difference01 : in std_logic_vector( width + 3 downto 0 );
Difference0 : in std_logic_vector( width downto 0 );
Difference01 : in std_logic_vector( width downto 0 );
IHorizontal : in std_logic_vector( width downto 0 );
IVertical : in std_logic_vector( width downto 0 );
Difference7 : in std_logic_vector( width downto 0 );
DifferenceDver : in std_logic_vector( width + 2 downto 0 );
DifferenceDhor : in std_logic_vector( width + 2 downto 0 );
ElementG : out std_logic_vector( width downto 0 )
);
end component;
-----------------------------------------------------------------------------------------------------------------
-- Ehor - Ever
signal Neg0 : std_logic_vector( width downto 0 );
signal Sum0 : std_logic_vector( width downto 0 );
signal Carry0: std_logic_vector( width downto 0 );
signal DifferenceSum0 : std_logic_vector( width + 1 downto 0 );
signal Difference0 : std_logic_vector( width downto 0 );
-- Ever - Ehor
signal Difference01 : std_logic_vector( width downto 0 );
-----------------------------------------------------------------------------------------------
signal NegB33 : std_logic_vector( width downto 0 );
-- | B31 - B33 |
signal Sum1 : std_logic_vector( width downto 0 );
signal Carry1: std_logic_vector( width downto 0 );
signal DifferenceSum1 : std_logic_vector( width + 1 downto 0 );
signal Difference1 : std_logic_vector( width downto 0 );
signal Value1 : std_logic_vector( width downto 0 );
-- | B35 - B33 |
signal Sum2 : std_logic_vector( width downto 0 );
signal Carry2: std_logic_vector( width downto 0 );
signal DifferenceSum2 : std_logic_vector( width + 1 downto 0 );
signal Difference2 : std_logic_vector( width downto 0 );
signal Value2 : std_logic_vector( width downto 0 );
-- | G32 - G34 |
signal Neg3 : std_logic_vector( width downto 0 );
signal Sum3 : std_logic_vector( width downto 0 );
signal Carry3: std_logic_vector( width downto 0 );
signal DifferenceSum3 : std_logic_vector( width + 1 downto 0 );
signal Difference3 : std_logic_vector( width downto 0 );
signal Value3 : std_logic_vector( width downto 0 );
signal SumDhor : std_logic_vector( width downto 0 );
signal CarryDhor : std_logic_vector( width downto 0 );
signal DifferenceSumDhor : std_logic_vector( width + 1 downto 0 );
signal DifferenceDhor : std_logic_vector( width + 2 downto 0 );
---------------------------------------------------------------------------------------------------
-- | B13 - B33 |
signal Sum4 : std_logic_vector( width downto 0 );
signal Carry4: std_logic_vector( width downto 0 );
signal DifferenceSum4 : std_logic_vector( width + 1 downto 0 );
signal Difference4 : std_logic_vector( width downto 0 );
signal Value4 : std_logic_vector( width downto 0 );
-- | B53 - B33 |
signal Sum5 : std_logic_vector( width downto 0 );
signal Carry5: std_logic_vector( width downto 0 );
signal DifferenceSum5 : std_logic_vector( width + 1 downto 0 );
signal Difference5 : std_logic_vector( width downto 0 );
signal Value5 : std_logic_vector( width downto 0 );
-- | G23 - G43 |
signal Neg6 : std_logic_vector( width downto 0 );
signal Sum6 : std_logic_vector( width downto 0 );
signal Carry6: std_logic_vector( width downto 0 );
signal DifferenceSum6 : std_logic_vector( width + 1 downto 0 );
signal Difference6 : std_logic_vector( width downto 0 );
signal Value6 : std_logic_vector( width downto 0 );
signal SumDver : std_logic_vector( width downto 0 );
signal CarryDver : std_logic_vector( width downto 0 );
signal DifferenceSumDver : std_logic_vector( width + 1 downto 0 );
signal DifferenceDver : std_logic_vector( width + 2 downto 0 );
------------------------------------------------------------------------------------------------------
-- calculate IHorizontal
-- ( G32 + G34 ) / 2
signal SumIhor1 : std_logic_vector( width downto 0 );
signal CarryIhor1 : std_logic_vector( width downto 0 );
signal IhorSum1 : std_logic_vector( width + 1 downto 0 );
signal IHorizontal1 : std_logic_vector( width downto 0 );
-- B33 / 4
signal IHorizontal2 : std_logic_vector( width downto 0 );
-- ( B31 + B35 ) / 8
signal SumIhor3 : std_logic_vector( width downto 0 );
signal CarryIhor3 : std_logic_vector( width downto 0 );
signal IhorSum30 : std_logic_vector( width + 1 downto 0 );
signal IhorSum31 : std_logic_vector( width downto 0 );
signal IHorizontal3 : std_logic_vector( width downto 0 );
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
signal SumIhor : std_logic_vector( width downto 0 );
signal CarryIhor : std_logic_vector( width downto 0 );
signal IhorSum : std_logic_vector( width + 1 downto 0 );
signal IHorizontal : std_logic_vector( width downto 0 );
-- calculate IVertical
-- ( G23 + G43 ) / 2
signal SumIver1 : std_logic_vector( width downto 0 );
signal CarryIver1 : std_logic_vector( width downto 0 );
signal IverSum1 : std_logic_vector( width + 1 downto 0 );
signal IVertical1 : std_logic_vector( width downto 0 );
-- B33 / 4
signal IVertical2 : std_logic_vector( width downto 0 );
-- ( B13 + B53 ) / 8
signal SumIver3 : std_logic_vector( width downto 0 );
signal CarryIver3 : std_logic_vector( width downto 0 );
signal IverSum30 : std_logic_vector( width + 1 downto 0 );
signal IverSum31 : std_logic_vector( width downto 0 );
signal IVertical3 : std_logic_vector( width downto 0 );
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
signal SumIver : std_logic_vector( width downto 0 );
signal CarryIver : std_logic_vector( width downto 0 );
signal IverSum : std_logic_vector( width + 1 downto 0 );
signal IVertical : std_logic_vector( width downto 0 );
----------------------------------------------------------------------------------------
-- ( Ihor + Iver ) / 2
signal Sum7 : std_logic_vector( width downto 0 );
signal Carry7: std_logic_vector( width downto 0 );
signal DifferenceSum7 : std_logic_vector( width + 1 downto 0 );
signal Difference7 : std_logic_vector( width downto 0 );
signal ElementG : std_logic_vector( width downto 0 );
begin
BayerPattern( 6 )( 6 ) <= "000000011";
mytest <= BayerPattern( 6 )( 6 );
-- Ehor - Ever
Neg0 <= not EdgeVertical + '1';
Diff0 : CSAHalfAdder port map( EdgeHorizontal, Neg0, Sum0, Carry0 );
DifferenceSum0 <= ( Carry0 & '0' ) + Sum0;
Difference0 <= DifferenceSum0( width downto 0 );
-- Ever - Ehor
Difference01 <= not Difference0 + '1';
---------------------------------------------------------------------------------------------------------------------
NegB33 <= not B33 + '1';
-- | B31 - B33 |
Diff1 : CSAHalfAdder port map( B31, NegB33, Sum1, Carry1 );
DifferenceSum1 <= ( Carry1 & '0' ) + Sum1;
Difference1 <= DifferenceSum1( width downto 0 );
absoulte1 : absolute port map( Difference1, Value1 );
-- | B35 - B33 |
Diff2 : CSAHalfAdder port map( B35, NegB33, Sum2, Carry2 );
DifferenceSum2 <= ( Carry2 & '0' ) + Sum2;
Difference2 <= DifferenceSum2( width downto 0 );
absoulte2 : absolute port map( Difference2, Value2 );
-- | G32 - G34 |
Neg3 <= not G34 + '1';
Diff3 : CSAHalfAdder port map( G32, Neg3, Sum3, Carry3 );
DifferenceSum3 <= ( Carry3 & '0' ) + Sum3;
Difference3 <= DifferenceSum3( width downto 0 );
absoulte3 : absolute port map( Difference3, Value3 );
-- Dver = | B31 - B33 | + | B35 - B33 | + | G32 - G34 |
Dhor : CSAFullAdder port map( Value1, Value2, Value3, SumDhor, CarryDhor );
DifferenceSumDhor <= ( CarryDhor & '0' ) + SumDhor;
DifferenceDhor <= "00" & DifferenceSumDhor( width downto 0 );
---------------------------------------------------------------------------------------------------------------------
-- | B13 - B33 |
Diff4 : CSAHalfAdder port map( B13, NegB33, Sum4, Carry4 );
DifferenceSum4 <= ( Carry4 & '0' ) + Sum4;
Difference4 <= DifferenceSum4( width downto 0 );
absoulte4 : absolute port map( Difference4, Value4 );
-- | B53 - B33 |
Diff5 : CSAHalfAdder port map( B53, NegB33, Sum5, Carry5 );
DifferenceSum5 <= ( Carry5 & '0' ) + Sum5;
Difference5 <= DifferenceSum5( width downto 0 );
absoulte5 : absolute port map( Difference5, Value5 );
-- | G23 - G43 |
Neg6 <= not G43 + '1';
Diff6 : CSAHalfAdder port map( G23, Neg6, Sum6, Carry6 );
DifferenceSum6 <= ( Carry6 & '0' ) + Sum6;
Difference6 <= DifferenceSum6( width downto 0 );
absoulte6 : absolute port map( Difference6, Value6 );
-- Dver = | B13 - B33 | + | B53 - B33 | + | G23 - G43 |
Dver : CSAFullAdder port map( Value4, Value5, Value6, SumDver, CarryDver );
DifferenceSumDver <= ( CarryDver & '0' ) + SumDver;
DifferenceDver <= "00" & DifferenceSumDver( width downto 0 );
-------------------------------------------------------------------------------------------------------------------
-- calculate IHorizontal value
-- ( G32 + G34 ) / 2
Ihor1 : CSAHalfAdder port map( G32, G34, SumIhor1, CarryIhor1 );
IhorSum1 <= ( CarryIhor1 & '0' ) + SumIhor1;
IHorizontal1 <= IhorSum1( width + 1 downto 1 );
-- B33 / 4
IHorizontal2 <= "00" & B33( width downto 2 );
-- ( B31 + B35 ) / 8
Ihor3 : CSAHalfAdder port map( B31, B35, SumIhor3, CarryIhor3 );
IhorSum30 <= ( CarryIhor3 & '0' ) + SumIhor3;
IhorSum31 <= "00" & IhorSum30( width + 1 downto 3 );
IHorizontal3 <= not IhorSum31 + '1';
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
Ihor : CSAFullAdder port map( IHorizontal1, IHorizontal2, IHorizontal3, SumIhor, CarryIhor );
IhorSum <= ( CarryIhor & '0' ) + SumIhor;
IHorizontal <= IhorSum( width downto 0 );
---------------------------------------------------------------------------------------------------------------------
-- calculate IVertical value
-- ( G23 + G43 ) / 2
Iver1 : CSAHalfAdder port map( G23, G43, SumIver1, CarryIver1 );
IverSum1 <= ( CarryIver1 & '0' ) + SumIver1;
IVertical1 <= IverSum1( width + 1 downto 1 );
-- B33 / 4
IVertical2 <= IHorizontal2;
-- ( B13 + B53 ) / 8
Iver3 : CSAHalfAdder port map( B13, B53, SumIver3, CarryIver3 );
IverSum30 <= ( CarryIver3 & '0' ) + SumIver3;
IverSum31 <= "00" & IverSum30( width + 1 downto 3 );
IVertical3 <= not IverSum31 + '1';
-- ( G23 + G43 ) / 2 + B33 / 4 + ( B13 + B53 ) / 8
Iver : CSAFullAdder port map( IVertical1, IVertical2, IVertical3, SumIver, CarryIver );
IverSum <= ( CarryIver & '0' ) + SumIver;
IVertical <= IverSum( width downto 0 );
----------------------------------------------------------------------------------------------------------------
-- ( Ihor + Iver ) / 2
Diff7 : CSAHalfAdder port map( IHorizontal, IVertical, Sum7, Carry7 );
DifferenceSum7 <= ( Carry7 & '0' ) + Sum7;
Difference7 <= DifferenceSum7( width + 1 downto 1 );
PartG : CalculateG port map( Difference0, Difference01, IHorizontal, IVertical, Difference7, DifferenceDver, DifferenceDhor, ElementG );
G <= ElementG;
end TABLE;
|
mit
|
c126232b76e6daaf31152366f95e2cee
| 0.587778 | 3.543204 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/tb/AD9717_2WireSPI_Model.vhd
| 1 | 15,676 |
-------------------------------------------------------------------------------
--
-- File: AD9717_2WireSPI_Model.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Simulation model for the AD9717 DAC. Currently only the configuration SPI
-- interface implemented. The following conditions are tested:
-- 1. sSpiClk pulse high and low times are respected
-- 2. sSpiClk maximum and minimum (optional) frequency
-- 3. sCS to sSPI_Clk setup and hold times are respected
-- 4. sCS has no glitches during the 1 data byte transaction supported
-- 5. decodes command word and input data for write transactions
-- 6. generates output data byte for read transactions
-- 7. sSDIO to sSPI_Clk setup and hold times are respected
-- 8. No transitions occur on sSDIO and sCS during the idle state
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodDAC.all;
entity AD9717_2WireSPI_Model is
Generic (
-- Parameter identifying the Zmod:
-- 7 -> Zmod AWG 1411 - (AD9717)
kZmodID : integer range 7 to 7 := 7;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 8 to 8 := 8
);
Port (
-- 100MHz clock used by the AD9717_RegisterDecode block
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous
-- reading for register address x01
InsertError : in STD_LOGIC;
-- 2 wire SPI interface
sSPI_Clk : in STD_LOGIC;
sSDIO : inout STD_LOGIC := 'Z';
sCS : in STD_LOGIC
);
end AD9717_2WireSPI_Model;
architecture Behavioral of AD9717_2WireSPI_Model is
signal sR_W_Decode : std_logic;
signal sWidthDecode : std_logic_vector(1 downto 0);
signal sAddrDecode : std_logic_vector(kCommandWidth - 4 downto 0);
signal sAddrDecodeReady : std_logic;
signal sDataWriteDecodeReady : std_logic;
signal sTransactionInProgress : boolean := false;
signal sDataDecode : std_logic_vector(kDataWidth-1 downto 0);
signal sSPI_ClkRising : time := 0 ns;
signal sSPI_ClkCounter : integer := 0;
signal sLastSPI_ClkEdge : time := 0ns;
signal sLastSPI_ClkRisingEdge : time := 0ns;
signal sSclkHigh : time := 0ns;
signal sRegDataOut : std_logic_vector(kDataWidth-1 downto 0) := x"00";
begin
AD9717_RegisterDecode_inst: entity work.AD9717_RegisterDecode
Generic Map(
kZmodID => kZmodID,
kAddrWidth => kCommandWidth-3,
kRegDataWidth => kDataWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sDataWriteDecodeReady => sDataWriteDecodeReady,
sAddrDecodeReady => sAddrDecodeReady,
sDataDecode => sDataDecode,
sAddrDecode => sAddrDecode,
sRegDataOut => sRegDataOut
);
-- Main process; checks for:
-- 1. sSpiClk pulse high and low times are respected.
-- 2. sSpiClk maximum and minimum (optional) frequency.
-- 3. sCS to sSPI_Clk setup and hold times are respected.
-- 4. sCS has no glitches during the 1 data byte transaction supported.
-- 5. decodes command word and input data for write transactions.
-- 6. generates output data byte for read transactions.
-- A sSPI_Clk falling edge is expected before sCS is pulled high.
ProcMain: process
begin
sAddrDecodeReady <= '0';
sDataWriteDecodeReady <= '0';
if (sCS /= '0') then
wait until sCS = '0';
end if;
sSPI_ClkCounter <= 0;
sTransactionInProgress <= true;
sSDIO <= 'Z';
-- Wait for first sSPI_Clk rising edge
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
-- First clock rising edge detected
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
sR_W_Decode <= sSDIO;
-- Check sCS to sSPI_Clk setup time
assert ((sCS'delayed'last_event) >= ktS)
report "setup time between sCS and sSPI_Clk is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktS) & LF & HT & HT &
"Actual: " & time'image(sCS'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk pulse width high for MSB
wait until sSPI_Clk = '0';
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "sSPI_Clk pulse width high is smaller than minimum allowed for command MSB." & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Repeat for the following kCommandWidth-1 sSPI_Clk periods
for i in (kCommandWidth - 2) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowedfor command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
if (i = kCommandWidth - 2) then
sWidthDecode(1) <= sSDIO;
elsif (i = kCommandWidth - 3) then
sWidthDecode(0) <= sSDIO;
else
sAddrDecode(i) <= sSDIO;
if (i=0) then
sAddrDecodeReady <= '1';
end if;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for command bit" & integer'image(i)& LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Drive first data byte when bus changes direction
if (i=0) then
if (sR_W_Decode = '1') then
sSDIO <= sRegDataOut(7);
end if;
sAddrDecodeReady <= '0';
end if;
end loop;
for i in (kDataWidth - 1) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
-- Sample sSDIO on rising edge for write operations
if (sR_W_Decode = '0') then
sDataDecode(i) <= sSDIO;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for data bit" & integer'image(i) & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Assign SDIO on falling edge for read operations
if (sR_W_Decode = '1') then
if (i > 0) then
sSDIO <= sRegDataOut(i-1);
else
sSDIO <= 'Z';
end if;
else
if (i=0) then
sDataWriteDecodeReady <= '1';
end if;
end if;
end loop;
sLastSPI_ClkEdge <= now;
sTransactionInProgress <= false;
wait until sCS = '1';
-- Check hold time between SCLK and sCS
assert ((now - sLastSPI_ClkRisingEdge) >= ktH)
report "Hold time (sCS to sSPI_Clk) is smaller than the minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktH) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkRisingEdge)
severity ERROR;
-- Check if no more than 24 bits transferred
assert ((now - sLastSPI_ClkEdge) = sSPI_Clk'last_event)
report "More than 24 bits transfered for current transaction." & LF & HT & HT
severity FAILURE;
-- Check last sSPI_Clk pulse low duration
assert ((now - sLastSPI_ClkEdge) >= kSclkLow)
report "aSCK pulse width low is smaller than minimum allowed data bit 0" & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkEdge)
severity ERROR;
end process ProcMain;
-- Check if sCS low pulse is held low for the entire transaction
CheckCS: process
begin
if (sCS /= '0') then
wait until sCS = '0';
end if;
wait until sCS = '1';
assert (sTransactionInProgress = false)
report "CS pulse high during transaction." & LF & HT & HT
severity FAILURE;
end process CheckCS;
-- Check if sSDIO to sSPI_Clk setup time is respected
CheckSetup: process
begin
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
sSPI_ClkRising <= now;
-- Check Setup Time
assert (sSDIO'last_active >= ktDS)
report "Setup time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDS) & LF & HT & HT &
"Actual: " & time'image(sSDIO'last_active)
severity ERROR;
end process CheckSetup;
-- Check if sSDIO to sSPI_Clk hold time is respected
CheckHold: process
begin
-- Wait for first clock rising edge
wait until sSPI_ClkRising /= 0 ns;
-- Wait for SDIO next bit to be assigned
wait until sSDIO'event;
-- Check Hold Time
assert ((now - sSPI_ClkRising) >= ktDH)
report "Hold time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDH) & LF & HT & HT &
"Actual: " & time'image(now - sSPI_ClkRising)
severity ERROR;
end process CheckHold;
-- Check sSDIO idle condition
CheckSDIO_Idle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSDIO = '0')
report "SDIO idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSDIO signal and check if they occur during the idle state (sCS = '1');
wait until sSDIO'event;
assert (sCS = '0')
report "SDIO idle condition not respected."
severity WARNING;
end process CheckSDIO_Idle;
CheckSPI_ClkIdle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSPI_Clk = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSPI_Clk signal and check if they occur during the idle state (sCS = '1');
wait until sSPI_Clk'event;
assert (sCS = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
end process CheckSPI_ClkIdle;
end Behavioral;
|
mit
|
47ec96bdb4efee474926c7bb76d71da8
| 0.620949 | 4.204936 | false | false | false | false |
Digilent/vivado-library
|
ip/rgb2dvi/src/rgb2dvi.vhd
| 1 | 8,777 |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 source interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure (optional), encoding and serialization logic.
-- On the input side it has 24-bit RGB video data bus, pixel clock and synchronization
-- signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2dvi is
Generic (
kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kD0Swap : boolean := false; -- P/N Swap Options
kD1Swap : boolean := false;
kD2Swap : boolean := false;
kClkSwap : boolean := false);
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
-- Auxiliary signals
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video in
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic; --pixel-clock recovered from the DVI interface
SerialClk : in std_logic); -- 5x PixelClk
end rgb2dvi;
architecture Behavioral of rgb2dvi is
type dataOut_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type dataOutRaw_t is array (2 downto 0) of std_logic_vector(9 downto 0);
signal pDataOut : dataOut_t;
signal pDataOutRaw : dataOutRaw_t;
signal pDataOutRaw_q : dataOutRaw_t;
signal pVde, pC0, pC1 : std_logic_vector(2 downto 0);
signal aRst_int, aPixelClkLckd : std_logic;
signal PixelClkIO, SerialClkIO, aRstLck, pRstLck : std_logic;
signal pClkOut : std_logic_vector(9 downto 0);
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
-- Generate SerialClk internally?
ClockGenInternal: if kGenerateSerialClk generate
ClockGenX: entity work.ClockGen
Generic map (
kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive => kClkPrimitive) -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port map (
PixelClkIn => PixelClk,
PixelClkOut => PixelClkIO,
SerialClk => SerialClkIO,
aRst => aRst_int,
aLocked => aPixelClkLckd);
--TODO revise this
aRstLck <= not aPixelClkLckd;
end generate ClockGenInternal;
ClockGenExternal: if not kGenerateSerialClk generate
PixelClkIO <= PixelClk;
SerialClkIO <= SerialClk;
aRstLck <= aRst_int;
end generate ClockGenExternal;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRstLck,
OutClk => PixelClk,
oRst => pRstLck);
-- Clock needs no encoding, send a pulse
ClockSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Clk_p,
sDataOut_n => TMDS_Clk_n,
--Encoded parallel data (raw)
pDataOut => pClkOut,
aRst => pRstLck);
DataEncoders: for i in 0 to 2 generate
DataEncoder: entity work.TMDS_Encoder
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
pDataOutRaw => pDataOutRaw(i),
aRst => pRstLck,
pDataOut => pDataOut(i),
pC0 => pC0(i),
pC1 => pC1(i),
pVde => pVde(i)
);
DataSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Data_p(i),
sDataOut_n => TMDS_Data_n(i),
--Encoded parallel data (raw)
pDataOut => pDataOutRaw_q(i),
aRst => pRstLck);
end generate DataEncoders;
-- Swap each bit
D0_direct: if kD0Swap = false generate
pDataOutRaw_q(0) <= pDataOutRaw(0);
end generate;
D0_reverse: if kD0Swap = true generate
pDataOutRaw_q(0) <= not pDataOutRaw(0);
end generate;
D1_direct: if kD1Swap = false generate
pDataOutRaw_q(1) <= pDataOutRaw(1);
end generate;
D1_reverse: if kD1Swap = true generate
pDataOutRaw_q(1) <= not pDataOutRaw(1);
end generate;
D2_direct: if kD2Swap = false generate
pDataOutRaw_q(2) <= pDataOutRaw(2);
end generate;
D2_reverse: if kD2Swap = true generate
pDataOutRaw_q(2) <= not pDataOutRaw(2);
end generate;
Clk_direct: if kClkSwap = false generate
pClkOut <= "1111100000";
end generate;
Clk_reverse: if kClkSwap = true generate
pClkOut <= "0000011111";
end generate;
-- DVI Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason vid_data is packed in RBG order
pDataOut(2) <= vid_pData(23 downto 16); -- red is channel 2
pDataOut(1) <= vid_pData(7 downto 0); -- green is channel 1
pDataOut(0) <= vid_pData(15 downto 8); -- blue is channel 0
pC0(2 downto 1) <= (others => '0'); -- default is low for control signals
pC1(2 downto 1) <= (others => '0'); -- default is low for control signals
pC0(0) <= vid_pHSync; -- channel 0 carries control signals too
pC1(0) <= vid_pVSync; -- channel 0 carries control signals too
pVde <= vid_pVDE & vid_pVDE & vid_pVDE; -- all of them are either active or blanking at once
end Behavioral;
|
mit
|
da3ff4c7cf8b30abc30560ebfbbe2bac
| 0.665261 | 4.227842 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/fifo_w16_d2_A.vhd
| 1 | 4,437 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d2_A_shiftReg;
architecture rtl of fifo_w16_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d2_A is
component fifo_w16_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d2_A_shiftReg : fifo_w16_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
572e68ce94272c345063e15b442f3891
| 0.52558 | 3.4637 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
mux14to2.vhd
| 1 | 2,417 |
-------------------------------------------------------------------------------
--
-- Title : mux14to2
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\mux14to2.vhd
-- Generated : Tue Dec 6 21:54:38 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {mux14to2} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux14to2 is
port(
in1,in2,in3,in4,in5,in6,in7,in8,in9,in10,in11,in12,in13,in14: in std_logic_vector(63 downto 0);
mux_select: in std_logic_vector(3 downto 0);
o1: out std_logic_vector(63 downto 0);
writeback: out std_logic
);
end mux14to2;
--}} End of automatically maintained section
architecture behavioral of mux14to2 is
begin
mux: process (in1,in2,in3,in4,in5,in6,in7,in8,in9,in10,in11,in12,in13,in14,mux_select)
begin
if mux_select = "0010" then
o1 <= in1;
writeback <= '1';
elsif mux_select = "0011" then
o1 <= in2;
writeback <= '1';
elsif mux_select = "0100" then
o1 <= in3;
writeback <= '1';
elsif mux_select = "0101" then
o1 <= in4;
writeback <= '1';
elsif mux_select = "0110" then
o1 <= in5;
writeback <= '1';
elsif mux_select = "0111" then
o1 <= in6;
writeback <= '1';
elsif mux_select = "1000" then
o1 <= in7;
writeback <= '1';
elsif mux_select = "1001" then
o1 <= in8;
writeback <= '1';
elsif mux_select = "1010" then
o1 <= in9;
writeback <= '1';
elsif mux_select = "1011" then
o1 <= in10;
writeback <= '1';
elsif mux_select = "1100" then
o1 <= in11;
writeback <= '1';
elsif mux_select = "1101" then
o1 <= in12;
writeback <= '1';
elsif mux_select = "1110" then
o1 <= in13;
writeback <= '1';
elsif mux_select = "1111" then
o1 <= in14;
writeback <= '1';
else
o1 <= (others => '-');
writeback <= '0';
end if;
end process;
end behavioral;
|
apache-2.0
|
7d83b3148e12906b5ef2db925f99626a
| 0.505999 | 3.106684 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/PkgZmodADC.vhd
| 1 | 31,466 |
-------------------------------------------------------------------------------
--
-- File: PkgZmodADC.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This package contains the constants and functions used for the
-- ZmodScpeController IP
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgZmodADC is
-- Zmod Scope variants identifier
constant kZmodScope1410_105 : integer := 0; -- Zmod Scpe 1410 - 105 (AD9648)
constant kZmodScope1010_40 : integer := 1; -- Zmod Scpe 1010 - 40 (AD9204)
constant kZmodScope1010_125 : integer := 2; -- Zmod Scpe 1010 - 125 (AD9608)
constant kZmodScope1210_40 : integer := 3; -- Zmod Scpe 1210 - 40 (AD9231)
constant kZmodScope1210_125 : integer := 4; -- Zmod Scpe 1210 - 125 (AD9628)
constant kZmodScope1410_40 : integer := 5; -- Zmod Scpe 1410 - 40 (AD9251)
constant kZmodScope1410_125 : integer := 6; -- Zmod Scpe 1410 - 125 (AD9648)
--Timing parameters
constant kSysClkPeriod : time := 10ns; -- System Clock Period
constant ktS : time := 2 ns; -- Setup time between CSB and SCLK
constant ktH : time := 2 ns; -- Hold time between CSB and SCLK
constant ktDS : time := 2 ns; -- Setup time between the data and the rising edge of SCLK
constant ktDH : time := 2 ns; -- Hold time between the data and the rising edge of SCLK
constant ktclk : time := 40 ns; -- minimum period of the SCLK
constant kSclkHigh : time := 10 ns; -- SCLK pulse width high (min)
constant kSclkLow : time := 10 ns; -- SCLK pulse width low (min)
--constant kSclkT_Max : time := 10 ns; -- SCLK pulse width low (min)
constant kSclkT_Min : time := 50 ns; -- SCLK pulse width low (min)
constant kTdcoMax : time := 4.4 ns;
-- Relay Set and Reset signals in simulation. In real life, this constant should be equal to 3ms.
constant kRelayConfigTime : time := 3us;
--ADC Model Registers
constant aReg00_Mask : std_logic_vector(7 downto 0) := "01100110";
--Implementation constants
constant kCS_PulseWidthHigh : integer := 31; --CS pulse width high not specified in AD9648
constant kSPI_DataWidth : integer := 8; --ADI_SPI module data width
constant kSPI_CommandWidth : integer := 16; --ADI_SPI module command width
constant kSPI_AddrWidth : integer := kSPI_CommandWidth - 3; --ADI_SPI module command width
constant kSPI_SysClkDiv : integer := 4; --ADI_SPI module system clock divide constant
--No minimum SPI clock frequency specified by AD9648. The maximum frequency is 25MHz.
type ADC_SPI_Commands_t is array (19 downto 0) of std_logic_vector(23 downto 0);
type ADC_SPI_Readback_t is array (19 downto 0) of std_logic_vector(7 downto 0);
constant kAD96xx_SPI_Cmd : ADC_SPI_Commands_t := (x"000500", --19 Device index: none
x"000800", --18 Power modes: Normal operation
x"000502", --17 Device index: B
x"000800", --16 Power modes: Normal operation
x"000501", --15 Device index: A
x"003A02", --14 Sync control : continuous | sync enable | 0
x"001781", --13 Output Delay; DCO delay enabled; 1.12ns
x"001511", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"002A00", --11 Overrange control: output disable
x"000B03", --10 Clck Divide: 4
x"001680", --9 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"000500", --8 Device index: none
x"001421", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"000803", --6 Power modes: digital reset
x"000502", --5 Device index: B
x"001431", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"000803", --3 Power modes: digital reset
x"000501", --2 Device index: A
x"000100", --1 Chip ID: read chip ID
x"00003C" --0 SPI Port Config: soft reset
);
constant kAD96xx_SPI_Rdbck : ADC_SPI_Readback_t:= (x"00", --19 Device index: none
x"00", --18 Power modes: Normal operation
x"02", --17 Device index: B
x"00", --16 Power modes: Normal operation
x"01", --15 Device index: A
x"02", --14 Sync control : continuous | sync enable | 0
x"81", --13 Output Delay; DCO delay enabled; 1.12ns
x"11", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"00", --11 Overrange control: output disable
x"03", --10 Clck Divide: 4
x"80", --9 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"00", --8 Device index: none
x"21", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"03", --6 Power modes: digital reset
x"02", --5 Device index: B
x"31", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"03", --3 Power modes: digital reset
x"01", --2 Device index: A
x"88", --1 Chip ID expected value:88
x"18" --0 SPI Port Config: soft reset
);
constant kAD92xx_SPI_Cmd : ADC_SPI_Commands_t := (x"000500", --19 Device index: none
x"000800", --18 Power modes: Normal operation
x"000502", --17 Device index: B
x"000800", --16 Power modes: Normal operation
x"000501", --15 Device index: A
x"010002", --14 Sync control : continuous | sync enable | 0
x"001781", --13 Output Delay; DCO delay enabled; 1.12ns
x"001511", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"002A00", --11 Overrange control: output disable
x"000B03", --10 Clck Divide: 4
x"000500", --9 Device index: none
x"001680", --8 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"001421", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"000803", --6 Power modes: digital reset
x"000502", --5 Device index: B
x"001431", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"000803", --3 Power modes: digital reset
x"000501", --2 Device index: A
x"000100", --1 Chip ID: read chip ID
x"00003C" --0 SPI Port Config: soft reset
);
constant kAD92xx_SPI_Rdbck : ADC_SPI_Readback_t:= (x"00", --19 Device index: none
x"00", --18 Power modes: Normal operation
x"02", --17 Device index: B
x"00", --16 Power modes: Normal operation
x"01", --15 Device index: A
x"02", --14 Sync control : continuous | sync enable | 0
x"81", --13 Output Delay; DCO delay enabled; 1.12ns
x"11", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"00", --11 Overrange control: output disable
x"03", --10 Clck Divide: 4
x"00", --9 Device index: none
x"80", --8 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"21", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"03", --6 Power modes: digital reset
x"02", --5 Device index: B
x"31", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"03", --3 Power modes: digital reset
x"01", --2 Device index: A
x"88", --1 Chip ID expected value:88
x"18" --0 SPI Port Config: soft reset
);
constant kSetTrsfReg : std_logic_vector(23 downto 0) := x"00FF01";
--ADC Register addresses
constant kDevIndex : std_logic_vector(12 downto 0) := "00000" & x"05";
constant kPwrModes : std_logic_vector(12 downto 0) := "00000" & x"08";
constant kSyncCtrll : std_logic_vector(12 downto 0) := "00000" & x"3A";
constant kOutDly : std_logic_vector(12 downto 0) := "00000" & x"17";
constant kOutAdj : std_logic_vector(12 downto 0) := "00000" & x"15";
constant kOvrrCtrl : std_logic_vector(12 downto 0) := "00000" & x"2A";
constant kClkPhCtrl : std_logic_vector(12 downto 0) := "00000" & x"16";
constant kClkDiv : std_logic_vector(12 downto 0) := "00000" & x"0B";
constant kOutMode : std_logic_vector(12 downto 0) := "00000" & x"14";
constant kChipID : std_logic_vector(12 downto 0) := "00000" & x"01";
constant kSPI_PortCfg : std_logic_vector(12 downto 0) := "00000" & x"01";
--ID Register value for supported Zmods
constant AD9648_ID : std_logic_vector(7 downto 0) := x"88";
constant AD9204_ID : std_logic_vector(7 downto 0) := x"25";
constant AD9608_ID : std_logic_vector(7 downto 0) := x"9C";
constant AD9231_ID : std_logic_vector(7 downto 0) := x"24";
constant AD9628_ID : std_logic_vector(7 downto 0) := x"89";
constant AD9251_ID : std_logic_vector(7 downto 0) := x"23";
constant AD9648_Grade : std_logic_vector(7 downto 0) := x"40";
constant AD9204_Grade : std_logic_vector(7 downto 0) := x"10";
constant AD9608_Grade : std_logic_vector(7 downto 0) := x"50";
constant AD9231_Grade : std_logic_vector(7 downto 0) := x"10";
constant AD9628_Grade : std_logic_vector(7 downto 0) := x"50";
constant AD9251_Grade : std_logic_vector(7 downto 0) := x"10";
-- number of commands to load in the TX command FIFO for the CommandFIFO module
constant kCmdFIFO_NoWrCmds : integer := 3;
-- command list loaded in the TX command FIFO of the CommandFIFO module
type CmdFIFO_WrCmdList_t is array (kCmdFIFO_NoWrCmds downto 0) of std_logic_vector(23 downto 0);
constant kCmdFIFO_WrList : CmdFIFO_WrCmdList_t := (x"800200", -- read chip grade
x"800100", -- read chip ID
x"00003C", -- write SPI Port Config
x"000000" -- dummy
);
-- number of commands expected to be returned and loaded in the RX command FIFO of
-- the CommandFIFO module by the AD9648_SPI_Module in the tb_TestConfigADC test bench.
-- It should be equal to the number of read commands in the kCmdFIFO_WrList.
constant kCmdFIFO_NoRdCmds : integer := 2;
-- data expected in return after sending the kCmdFIFO_WrList commands by the CommandFIFO module
type CmdFIFO_RdCmdList_t is array (kCmdFIFO_NoRdCmds-1 downto 0) of std_logic_vector(7 downto 0);
constant kCmdFIFO_Timeout : unsigned (23 downto 0) := x"000600";
type CalibCoef_t is record
LgMultCoef : std_logic_vector (17 downto 0);
LgAddCoef : std_logic_vector (17 downto 0);
HgMultCoef : std_logic_vector (17 downto 0);
HgAddCoef : std_logic_vector (17 downto 0);
end record;
type RelayConfig_t is record
CouplingConfig : std_logic;
GainConfig : std_logic;
end record;
constant kCmdWrTotal_AD9648 : integer := 19;
constant kCmdWrTotal_AD9204 : integer := 19;
constant kCmdWrTotal_AD9608 : integer := 19;
constant kCmdWrTotal_AD9231 : integer := 19;
constant kCmdWrTotal_AD9628 : integer := 19;
constant kCmdWrTotal_AD9251 : integer := 19;
constant kCmdReadID_Index : integer := 1; --Read ID command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
constant kCmdClkDivIndex : integer := 10; --Clock Divide command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
-- Constant used to measure 290ms (with a clock frequency of 100MHz) to allow the ADC's
-- transition from power down to normal operation (ConfigADC.vhd).
-- 290ms value is computed from:
-- https://www.analog.com/media/en/technical-documentation/data-sheets/ad9648.pdf page 40,
-- "The pseudo code sequence for a digital reset":
-- 2.9e6 sample clock cycles @ 10MHz minimum sampling clock frequency (for ZmodScope) = 290ms
constant kCountResetResume : unsigned := to_unsigned (28999999, 25);
-- Smaller version of the kCountResetResume, used only for simulation purposes.
-- (999 + 1) clock cycles @ 100MHz frequency means 10us.
constant kCountResetResumeSim : unsigned := to_unsigned (999, 25);
-- Constant used to measure 4ms (with a clock frequency of 100MHz) that allows to
-- determine the timin intervals for the relay drive signals (ConfigRelays.vhd)
constant kCount4ms : unsigned := to_unsigned (399999, 24);
-- Smaller version of the kCount4ms, used only for simulation purposes.
-- (399 + 1) clock cycles @ 100MHz frequency means 4us.
constant kCount4msSim : unsigned := to_unsigned (399, 24);
-- Constant used to measure 5ms with a clock frequency of 100MHz
-- Used to determine the ADC calibration timeout condition (tb_TestConfigADC.vhd and tb_TestTop.vhd)
constant kCount5ms : integer := 500000;
-- Constant used to measure 291ms (with a clock frequency of 100MHz) that determines a
-- timeout condition on the ADC's SPI interface (ConfigADC.vhd)
-- This value has to be larger than kCountResetResume, otherwise false timeouts on the ADC
-- SPI interface will occur (i.e. after an ADC soft reset is performed).
constant kCfgTimeout : unsigned := to_unsigned (29099999, 25);
type FsmStatesADC_t is (StStart, StCheckCmdCnt, StWriteSoftReset, StWaitDoneRst, StReadPortConfig,
StCheckResetDone, StReadID, StWaitDoneID, StWriteControlReg, StWaitDoneWriteReg,
StWaitDoneReadReg, StReadControlReg, StResetTimer, StWaitRecover, StInitDone, StIdle,
StError, StExtSPI_RdCmd, StExtSPI_WrCmd, StWaitDoneExtWrReg,
StWaitDoneExtRdReg, StRegExtRxData, StSetTrsfReg, StWaitDoneTrsfReg, StReadTrsfReg, StWaitDoneTrsfRegRd);
type FsmStatesRelays_t is (StStart, StConfigCouplingCh1, StConfigCouplingCh1Rst, StConfigCouplingCh2,
StConfigCouplingCh2Rst, StConfigGainCh1, StConfigGainCh1Rst, StConfigGainCh2,
StConfigGainCh2Rst, StPushInitDone, StWaitRdy, StIdle, StError, StWaitAckCouplingCh1,
StChangeCouplingCh1, StWaitAckCouplingCh2, StChangeCouplingCh2, StWaitAckGainCh1,
StChangeGainCh1, StWaitAckGainCh2, StChangeGainCh2, StRstCfgPulse);
type FsmStatesSPI_t is (StIdle, StWrite, StRead1, StRead2, StRead3, StDone, StAssertCS);
constant kRangeLg : real := 26.25;
constant kRangeHg : real := 1.086;
constant kRangeIdealLg : real := 25.0;
constant kRangeIdealHg : real := 1.0;
-- Function used to determine the Chip ID based on the ZmodIC parameter
-- that identifies the Zmod.
function SelADC_ID(ZmodIC:integer)
return std_logic_vector;
-- Function used to determine the Chip grade based on the ZmodIC parameter
-- that identifies the Zmod.
function SelADC_Grade(ZmodIC:integer)
return std_logic_vector;
-- Function used to determine the Clock devide ratio field of register 0x0B
-- based on the kADC_ClkDiv generic
function DetClkDiv(ADC_ClkDiv:integer)
return std_logic_vector;
-- The initiaization command list is different depending on which Zmod is targeted.
-- The SelCmdList function is used to select the appropriate command list based on
-- the ZmodIC parameter.
function SelCmdList(ZmodIC:integer)
return ADC_SPI_Commands_t;
-- The initiaization command readback list is different depending on which Zmod is
-- targeted. The SelCmdList function is used to select the appropriate command list
-- based on the ZmodIC parameter.
function SelRdbkList(ZmodIC:integer)
return ADC_SPI_Readback_t;
-- The OverwriteClkDiv function is used to overwrite the Clock divide ratio field of commad list
-- (CmdList) sent as parameter based on ADC_ClkDiv. It is important to note that the "write
-- Clock Divide register" (address 0x0B) command shares the same position (kCmdClkDivIndex) in
-- the command list for the currently supported Zmods.
function OverwriteClkDiv(CmdList:ADC_SPI_Commands_t; ADC_ClkDiv:integer)
return ADC_SPI_Commands_t;
-- The OverWriteID_ClkDiv function is used to overwrite the ADC chip ID field of the
-- command readback list (RdbkList) based on the ZmodIC parameter.
function OverWriteID_ClkDiv(ZmodIC:integer; RdbkList:ADC_SPI_Readback_t; ADC_ClkDiv:integer)
return ADC_SPI_Readback_t;
-- The SelCmdWrListLength function is used to detrmine the command list
-- length based on the ZmodIC parameter.
function SelCmdWrListLength(ZmodIC:integer)
return integer;
-- Function used to determine the ADC resolution (kADC_Width) based on the ZmodIC parameter.
-- Used in the top level test bench.
function SelADC_Width(ZmodIC:integer)
return integer;
-- Function used to compute the IDDR sampling clock phase as a function of the sampling
-- period. This is necessary so the clock phase is always an integer multiple of
-- (45 degrees/output clock division factor) of the MMCM which generates it.
function IDDR_ClockPhase(SamplingPeriod:real)
return real;
end PkgZmodADC;
package body PkgZmodADC is
function SelADC_ID(ZmodIC:integer)
return std_logic_vector is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return AD9648_ID;
when kZmodScope1010_40 =>
return AD9204_ID;
when kZmodScope1010_125 =>
return AD9608_ID;
when kZmodScope1210_40 =>
return AD9231_ID;
when kZmodScope1210_125 =>
return AD9628_ID;
when kZmodScope1410_40 =>
return AD9251_ID;
when kZmodScope1410_125 =>
return AD9648_ID;
when others =>
return x"00";
end case;
end function;
function SelADC_Grade(ZmodIC:integer)
return std_logic_vector is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return AD9648_Grade;
when kZmodScope1010_40 =>
return AD9204_Grade;
when kZmodScope1010_125 =>
return AD9608_Grade;
when kZmodScope1210_40 =>
return AD9231_Grade;
when kZmodScope1210_125 =>
return AD9628_Grade;
when kZmodScope1410_40 =>
return AD9251_Grade;
when kZmodScope1410_125 =>
return AD9648_Grade;
when others =>
return x"00";
end case;
end function;
function DetClkDiv(ADC_ClkDiv:integer)
return std_logic_vector is
begin
if (ADC_ClkDiv = 1) then
return x"00";
elsif (ADC_ClkDiv = 2) then
return x"01";
elsif (ADC_ClkDiv = 3) then
return x"02";
elsif (ADC_ClkDiv = 4) then
return x"03";
elsif (ADC_ClkDiv = 5) then
return x"04";
elsif (ADC_ClkDiv = 6) then
return x"05";
elsif (ADC_ClkDiv = 7) then
return x"06";
elsif (ADC_ClkDiv = 8) then
return x"07";
else
return x"00";
end if;
end function;
function SelCmdList(ZmodIC:integer)
return ADC_SPI_Commands_t is
variable CmdListV : ADC_SPI_Commands_t := kAD96xx_SPI_Cmd;
begin
case ZmodIC is
when kZmodScope1410_105 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodScope1010_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodScope1010_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodScope1210_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodScope1210_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodScope1410_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodScope1410_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when others =>
CmdListV := (others => (others => '0'));
return CmdListV;
end case;
end function;
function SelRdbkList(ZmodIC:integer)
return ADC_SPI_Readback_t is
variable RdbkListV : ADC_SPI_Readback_t := kAD96xx_SPI_Rdbck;
begin
case ZmodIC is
when kZmodScope1410_105 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1010_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1010_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1210_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1210_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1410_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1410_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when others =>
RdbkListV := (others => (others => '0'));
return RdbkListV;
end case;
end function;
function OverwriteClkDiv(CmdList:ADC_SPI_Commands_t; ADC_ClkDiv:integer)
return ADC_SPI_Commands_t is
variable CmdListV : ADC_SPI_Commands_t := CmdList;
begin
CmdListV(kCmdClkDivIndex) := CmdList(kCmdClkDivIndex)(23 downto 8) & DetClkDiv(ADC_ClkDiv);
return CmdListV;
end function;
function OverWriteID_ClkDiv(ZmodIC:integer; RdbkList:ADC_SPI_Readback_t; ADC_ClkDiv:integer)
return ADC_SPI_Readback_t is
variable RdbkListV : ADC_SPI_Readback_t := RdbkList;
begin
RdbkListV(kCmdClkDivIndex) := DetClkDiv(ADC_ClkDiv);
case ZmodIC is
when kZmodScope1410_105 =>
RdbkListV(kCmdReadID_Index) := AD9648_ID;
return RdbkListV;
when kZmodScope1010_40 =>
RdbkListV(kCmdReadID_Index) := AD9204_ID;
return RdbkListV;
when kZmodScope1010_125 =>
RdbkListV(kCmdReadID_Index) := AD9608_ID;
return RdbkListV;
when kZmodScope1210_40 =>
RdbkListV(kCmdReadID_Index) := AD9231_ID;
return RdbkListV;
when kZmodScope1210_125 =>
RdbkListV(kCmdReadID_Index) := AD9628_ID;
return RdbkListV;
when kZmodScope1410_40 =>
RdbkListV(kCmdReadID_Index) := AD9251_ID;
return RdbkListV;
when kZmodScope1410_125 =>
RdbkListV(kCmdReadID_Index) := AD9648_ID;
return RdbkListV;
when others =>
RdbkListV(kCmdReadID_Index) := x"00";
return RdbkListV;
end case;
end function;
function SelCmdWrListLength(ZmodIC:integer)
return integer is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return kCmdWrTotal_AD9648;
when kZmodScope1010_40 =>
return kCmdWrTotal_AD9204;
when kZmodScope1010_125 =>
return kCmdWrTotal_AD9608;
when kZmodScope1210_40 =>
return kCmdWrTotal_AD9231;
when kZmodScope1210_125 =>
return kCmdWrTotal_AD9628;
when kZmodScope1410_40 =>
return kCmdWrTotal_AD9251;
when kZmodScope1410_125 =>
return kCmdWrTotal_AD9648;
when others =>
return 0;
end case;
end function;
function SelADC_Width(ZmodIC:integer)
return integer is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return 14;
when kZmodScope1010_40 =>
return 10;
when kZmodScope1010_125 =>
return 10;
when kZmodScope1210_40 =>
return 12;
when kZmodScope1210_125 =>
return 12;
when kZmodScope1410_40 =>
return 14;
when kZmodScope1410_125 =>
return 14;
when others =>
return 14;
end case;
end function;
function IDDR_ClockPhase(SamplingPeriod:real)
return real is
begin
--400MHz to 200MHz
if ((SamplingPeriod > 2.5) and (SamplingPeriod <= 5.0)) then
return 120.0;
--200MHz to 111MHz
elsif ((SamplingPeriod > 5.0) and (SamplingPeriod <= 9.0)) then
return 127.5;
--111MHz to 100MHz
elsif ((SamplingPeriod > 9.0) and (SamplingPeriod <= 10.0)) then
return 120.0;
--100MHz to 50MHz
elsif ((SamplingPeriod > 10.0) and (SamplingPeriod <= 20.0)) then
return 123.75;
--50MHz to 25MHz
elsif ((SamplingPeriod > 20.0) and (SamplingPeriod <= 40.0)) then
return 125.625;
--25MHz to 12.5MHz
elsif ((SamplingPeriod > 40.0) and (SamplingPeriod <= 80.0)) then
return 125.625;
--12.5MHz to 10MHz
elsif (SamplingPeriod > 80.0) then
return 125.859375;
--Out of specifications;
else
return 1.0;
end if;
end function;
end PkgZmodADC;
|
mit
|
49b1d8316b30f0b804bab38aec11c2ac
| 0.54338 | 4.84465 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/AD96xx_92xxSPI_Model.vhd
| 1 | 15,991 |
-------------------------------------------------------------------------------
--
-- File: AD96xx_92xxSPI_Model.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Simulation model for the AD9648 ADC. Currently only the configuration SPI
-- interface implemented. The following conditions are tested:
-- 1. sSpiClk pulse high and low times are respected
-- 2. sSpiClk maximum and minimum (optional) frequency
-- 3. sCS to sSPI_Clk setup and hold times are respected
-- 4. sCS has no glitches during the 1 data byte transaction supported
-- 5. decodes command word and input data for write transactions
-- 6. generates output data byte for read transactions
-- 7. sSDIO to sSPI_Clk setup and hold times are respected
-- 8. No transitions occur on sSDIO and sCS during the idle state
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity AD96xx_92xxSPI_Model is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 0 to 63 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 0 to 63 := 8
);
Port (
-- 100MHz clock used by the AD9648_RegisterDecode block
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous
-- reading for register address x01
InsertError : in STD_LOGIC;
-- 2 wire SPI interface
sSPI_Clk : in STD_LOGIC;
sSDIO : inout STD_LOGIC := 'Z';
sCS : in STD_LOGIC
);
end AD96xx_92xxSPI_Model;
architecture Behavioral of AD96xx_92xxSPI_Model is
signal sR_W_Decode : std_logic;
signal sWidthDecode : std_logic_vector(1 downto 0);
signal sAddrDecode : std_logic_vector(kCommandWidth - 4 downto 0);
signal sAddrDecodeReady : std_logic;
signal sDataWriteDecodeReady : std_logic;
signal sTransactionInProgress : boolean := false;
signal sDataDecode : std_logic_vector(kDataWidth-1 downto 0);
signal sSPI_ClkRising : time := 0 ns;
signal sSPI_ClkCounter : integer := 0;
signal sLastSPI_ClkEdge : time := 0ns;
signal sLastSPI_ClkRisingEdge : time := 0ns;
signal sSclkHigh : time := 0ns;
signal sRegDataOut : std_logic_vector(kDataWidth-1 downto 0) := x"00";
begin
AD9648_RegisterDecode_inst: entity work.AD96xx_92xx_RegisterDecode
Generic Map(
kZmodID => kZmodID,
kAddrWidth => kCommandWidth-3,
kRegDataWidth => kDataWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sDataWriteDecodeReady => sDataWriteDecodeReady,
sAddrDecodeReady => sAddrDecodeReady,
sDataDecode => sDataDecode,
sAddrDecode => sAddrDecode,
sRegDataOut => sRegDataOut
);
-- ADC Main process; checks for:
-- 1. sSpiClk pulse high and low times are respected.
-- 2. sSpiClk maximum and minimum (optional) frequency.
-- 3. sCS to sSPI_Clk setup and hold times are respected.
-- 4. sCS has no glitches during the 1 data byte transaction supported.
-- 5. decodes command word and input data for write transactions.
-- 6. generates output data byte for read transactions.
-- A sSPI_Clk falling edge is expected before sCS is pulled high.
ADC_Main: process
begin
sAddrDecodeReady <= '0';
sDataWriteDecodeReady <= '0';
if (sCS /= '0') then
wait until sCS = '0';
end if;
sSPI_ClkCounter <= 0;
sTransactionInProgress <= true;
sSDIO <= 'Z';
-- Wait for first sSPI_Clk rising edge
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
-- First clock rising edge detected
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
sR_W_Decode <= sSDIO;
-- Check sCS to sSPI_Clk setup time
assert ((sCS'delayed'last_event) >= ktS)
report "setup time between sCS and sSPI_Clk is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktS) & LF & HT & HT &
"Actual: " & time'image(sCS'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk pulse width high for MSB
wait until sSPI_Clk = '0';
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "sSPI_Clk pulse width high is smaller than minimum allowed for command MSB." & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Repeat for the following kCommandWidth-1 sSPI_Clk periods
for i in (kCommandWidth - 2) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
if (i = kCommandWidth - 2) then
sWidthDecode(1) <= sSDIO;
elsif (i = kCommandWidth - 3) then
sWidthDecode(0) <= sSDIO;
else
sAddrDecode(i) <= sSDIO;
if (i=0) then
sAddrDecodeReady <= '1';
end if;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for command bit" & integer'image(i)& LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Drive first data byte when bus changes direction
if (i=0) then
if (sR_W_Decode = '1') then
sSDIO <= sRegDataOut(7);
end if;
sAddrDecodeReady <= '0';
end if;
end loop;
for i in (kDataWidth - 1) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
-- Sample sSDIO on rising edge for write operations
if (sR_W_Decode = '0') then
sDataDecode(i) <= sSDIO;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for data bit" & integer'image(i) & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Assign SDIO on falling edge for read operations
if (sR_W_Decode = '1') then
if (i > 0) then
sSDIO <= sRegDataOut(i-1);
else
sSDIO <= 'Z';
end if;
else
if (i=0) then
sDataWriteDecodeReady <= '1';
end if;
end if;
end loop;
sLastSPI_ClkEdge <= now;
sTransactionInProgress <= false;
wait until sCS = '1';
-- Check hold time between SCLK and sCS
assert ((now - sLastSPI_ClkRisingEdge) >= ktH)
report "Hold time (sCS to sSPI_Clk) is smaller than the minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktH) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkRisingEdge)
severity ERROR;
-- Check if no more than 24 bits transferred
assert ((now - sLastSPI_ClkEdge) = sSPI_Clk'last_event)
report "More than 24 bits transfered for current transaction." & LF & HT & HT
severity FAILURE;
-- Check last sSPI_Clk pulse low duration
assert ((now - sLastSPI_ClkEdge) >= kSclkLow)
report "aSCK pulse width low is smaller than minimum allowed data bit 0" & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkEdge)
severity ERROR;
end process ADC_Main;
-- Check if sCS low pulse is held low for the entire transaction
CheckCS: process
begin
if (sCS /= '0') then
wait until sCS = '0';
end if;
wait until sCS = '1';
assert (sTransactionInProgress = false)
report "CS pulse high during transaction." & LF & HT & HT
severity FAILURE;
end process CheckCS;
-- Check if sSDIO to sSPI_Clk setup time is respected
CheckSetup: process
begin
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
sSPI_ClkRising <= now;
-- Check Setup Time
assert (sSDIO'last_active >= ktDS)
report "Setup time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDS) & LF & HT & HT &
"Actual: " & time'image(sSDIO'last_active)
severity ERROR;
end process CheckSetup;
-- Check if sSDIO to sSPI_Clk hold time is respected
CheckHold: process
begin
-- Wait for first clock rising edge
wait until sSPI_ClkRising /= 0 ns;
-- Wait for SDIO next bit to be assigned
wait until sSDIO'event;
-- Check Hold Time
assert ((now - sSPI_ClkRising) >= ktDH)
report "Hold time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDH) & LF & HT & HT &
"Actual: " & time'image(now - sSPI_ClkRising)
severity ERROR;
end process CheckHold;
-- Check sSDIO idle condition
CheckSDIO_Idle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSDIO = '0')
report "SDIO idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSDIO signal and check if they occur during the idle state (sCS = '1');
wait until sSDIO'event;
assert (sCS = '0')
report "SDIO idle condition not respected."
severity WARNING;
end process CheckSDIO_Idle;
CheckSPI_ClkIdle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSPI_Clk = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSPI_Clk signal and check if they occur during the idle state (sCS = '1');
wait until sSPI_Clk'event;
assert (sCS = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
end process CheckSPI_ClkIdle;
end Behavioral;
|
mit
|
758f899c23a6ad4ce04b69f64f269587
| 0.617535 | 4.193811 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/fifo_w8_d2_A.vhd
| 1 | 4,426 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d2_A_shiftReg;
architecture rtl of fifo_w8_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d2_A is
component fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d2_A_shiftReg : fifo_w8_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
b3169d32e800ecbab9271dd77a82e646
| 0.524401 | 3.455113 | false | false | false | false |
danesgo/i2s-rec-zybo
|
i2s-rec.vhd
| 1 | 3,043 |
----------------------------------------------------------------------------------
-- Engineer: Daniel González
--
-- Create Date: 22:08:55 09/27/2015
-- Design Name:
-- Module Name: i2s_rec - Behavioral
-- Project Name:
-- Target Devices: Zybo Developing Board
-- Tool versions:
-- Description: i2s comunication module for recording audio trough the on board codec SSM2603 in slave mode, using default
-- configurations, Mic input(mono) 24-bit ADC @ 48KHz.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- SSM2603 Codec on the zybo
-- Rec Mono (One Channel) Fs=48Khz, BCLK = 1.152MHz (48000Hz * 24bits = 1.152Mhz)
entity i2s_rec is
generic(
width: integer := 24 -- Single Channel 24 bit ADC.
);
port(
clk: in std_logic; -- main zybo clock 125 MHz
recdat: in std_logic; -- data to be recorded
rst: in std_logic; --reset
--output
mclk: out std_logic; -- 12.2MHz (obtained from the SSM2603 codec datasheet)
bclk: out std_logic; -- 1.152MHz
reclrc: out std_logic; -- always low = '0' because it's always channel 1
mute: out std_logic; -- always high = '1' because it's never muted
done: out std_logic;
d_out: out std_logic_vector(width-1 downto 0)
);
end i2s_rec;
architecture Behavioral of i2s_rec is
--Signals Declarations
signal bclk_s: std_logic; --bit serial clock signal
signal mclk_s: std_logic; --master clock signal
signal CLKcount: integer range 0 to 55 := 0; -- Clock counter and divider 125MHz/1.152MHz = 108.5
signal CLKcnt: integer range 0 to 6 := 0; -- Clock counter an divider 125MHz/12.288MHz = 10.17
signal b_cnt: integer range 0 to width := 0;-- received bit counter
signal b_reg: std_logic_vector (width-1 downto 0); --received data vector
begin
Frec_DividerBCLK: process(clk, rst) begin
if (rst = '1') then
--reset state
bclk_s <= '0';
CLKcount <= 0;
elsif rising_edge(clk) then
if (CLKcount = 53) then --supposed to be 54 but that generates 1.136MHz
bclk_s <= not(bclk_s);
CLKcount <= 0;
else
CLKcount <= CLKcount + 1;
end if;
end if;
end process;
Frec_DividerMCLK: process(clk, rst) begin
if (rst = '1') then
--reset state
mclk_s <= '0';
CLKcnt <= 0;
elsif rising_edge(clk) then
if (CLKcnt = 4) then --supposed to be 5 but that generates 10.416MHz
mclk_s <= not(mclk_s);
CLKcnt <= 0;
else
CLKcnt <= CLKcnt + 1;
end if;
end if;
end process;
Data_ret: process(bclk_s, rst) begin
if (rst = '1') then
--reset state
elsif rising_edge(bclk_s) then
if (b_cnt = width-1) then
b_reg <= b_reg(width - 2 downto 0) & recdat; --Chapus!
b_cnt <= 0;
done <= '1';
else
b_reg <= b_reg(width - 2 downto 0) & recdat;
b_cnt <= b_cnt + 1;
done <= '0';
end if;
end if;
end process;
bclk <= bclk_s;
mclk <= mclk_s;
reclrc <= '0';
mute <= '1';
d_out <= b_reg;
end Behavioral;
|
mit
|
47a1fc39934b04666b4a47fa522fd00f
| 0.607495 | 3.011881 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fadd-grafi/fadd/fadd.vhd
| 1 | 5,190 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FloatAdder is
port (
fltIn1 : in std_logic_vector(31 downto 0);
fltIn2 : in std_logic_vector(31 downto 0);
fltOut : out std_logic_vector(31 downto 0));
end FloatAdder;
architecture FAddImp of FloatAdder is
component FractionLeftPadding
port (
frcIn : in std_logic_vector(23 downto 0);
nlz : out std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0));
end component;
component FractionRightShifter is
port (
frcIn : in std_logic_vector(23 downto 0);
len : in std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0);
fstOverOut : out std_logic;
sndOverOut : out std_logic;
tailAnyOut : out std_logic);
end component;
signal sgn1, sgn2 : std_logic;
signal exp1, exp2 : std_logic_vector( 7 downto 0);
signal frc1, frc2 : std_logic_vector(23 downto 0);
signal isAdd : boolean;
signal lenRawSft : std_logic_vector(8 downto 0);
signal lenSft : std_logic_vector(4 downto 0);
signal validPosSft, validNegSft : boolean;
signal zeroSft, posSft : boolean;
signal sgnSup, sgnInf : std_logic;
signal expUnif : std_logic_vector(7 downto 0);
signal frcInf : std_logic_vector(23 downto 0);
signal frcUnifSup, frcUnifInf : std_logic_vector(23 downto 0);
signal fstOver, sndOver, tailAny : std_logic;
signal roundFurther, roundFurtherDbl, roundFurtherHlf : std_logic;
signal frcOutAdder1, frcOutAdder2 : std_logic_vector(24 downto 0);
signal noFlow, noDown : boolean;
signal frcIreg : std_logic_vector(23 downto 0);
signal nlz : std_logic_vector(4 downto 0);
signal downFrc : std_logic;
signal expOutSubRaw : std_logic_vector(8 downto 0);
signal expOutAdd, expOutSub : std_logic_vector( 7 downto 0);
signal frcOutAdd, frcOutSub : std_logic_vector(23 downto 0);
signal sgnOutSub: std_logic;
begin
sgn1 <= fltIn1(31);
exp1 <= fltIn1(30 downto 23);
frc1 <= '1' & fltIn1(22 downto 0);
sgn2 <= fltIn2(31);
exp2 <= fltIn2(30 downto 23);
frc2 <= '1' & fltIn2(22 downto 0);
lenRawSft <= ('0' & exp1) - ('0' & exp2);
validPosSft <= lenRawSft(8 downto 5) = "0000";
zeroSft <= validPosSft and lenRawSft(4 downto 0) = "00000";
validNegSft <= lenRawSft(8 downto 5) = "1111" and lenRawSft(4 downto 0) /= "00000";
posSft <= lenRawSft(8) = '0';
lenSft <= lenRawSft(4 downto 0) when validPosSft else
"00000"-(lenRawSft(4 downto 0)) when validNegSft else
"11111";
sgnSup <= sgn1 when posSft else sgn2;
sgnInf <= sgn2 when posSft else sgn1;
expUnif <= exp1 when posSft else exp2;
frcUnifSup <= frc1 when posSft else frc2;
frcInf <= frc2 when posSft else frc1;
sftUnifFrc: FractionRightShifter port map (
frcIn => frcInf,
len => lenSft,
frcOut => frcUnifInf,
fstOverOut => fstOver,
sndOverOut => sndOver,
tailAnyOut => tailAny);
roundFurtherHlf <= sndOver and (tailAny or fstOver);
roundFurther <= fstOver and ((sndOver or tailAny) or (frcUnifSup(0) xor frcUnifInf(0)));
roundFurtherDbl <= (frcUnifSup(0) and frcUnifInf(0)) or
( (frcUnifSup(0) or frcUnifInf(0)) and
(((fstOver or sndOver) or tailAny) or (frcUnifSup(1) xor frcUnifInf(1))));
isAdd <= sgn1 = sgn2;
frcOutAdder1 <= ('0' & frcUnifSup) + ('0' & frcUnifInf) + roundFurther when isAdd else
('0' & frcUnifSup) - ('0' & frcUnifInf) - roundFurther;
frcOutAdder2 <= ("00" & (frcUnifSup(23 downto 1))) + ("00" & (frcUnifInf(23 downto 1))) + roundFurtherDbl when isAdd else
('0' & frcUnifInf) - ('0' & frcUnifSup) - roundFurther when zeroSft else
('0' & (frcUnifSup(22 downto 0)) & '0') - ('0' & (frcUnifInf(22 downto 0) & fstOver)) - roundFurtherHlf;
noFlow <= frcOutAdder1(24) = '0';
noDown <= frcOutAdder1(23) = '1';
expOutAdd <= expUnif when noFlow else expUnif+1;
frcOutAdd <= (others => '0') when expOutAdd = "11111111" else
frcOutAdder1(23 downto 0) when noFlow else
frcOutAdder2(23 downto 0);
sgnOutSub <= sgnSup when not zeroSft or noFlow else sgnInf;
frcIreg <= frcOutAdder1(23 downto 0) when zeroSft and noFlow else
frcOutAdder2(23 downto 0) when zeroSft and not noFlow else
frcOutAdder1(23 downto 0) when noDown else
frcOutAdder2(23 downto 0);
padFrcIreg: FractionLeftPadding port map (
frcIn => frcIreg,
nlz => nlz,
frcOut => frcOutSub);
downFrc <= '0' when zeroSft or noDown else '1';
expOutSubRaw <= ('0' & expUnif) - ("0000" & nlz) - downFrc;
expOutSub <= expOutSubRaw(7 downto 0) when expOutSubRaw(8) = '0' else "00000000";
fltOut <= sgnSup & expOutAdd & frcOutAdd(22 downto 0) when isAdd else
sgnOutSub & expOutSub & frcOutSub(22 downto 0);
end FAddImp;
|
bsd-2-clause
|
16c0de18795ebf5f91c61bf1cf7ab1ab
| 0.618497 | 3.665254 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/nova.vhd
| 1 | 57,485 |
--======================================================================
-- nova.vhd :: Nova instruction-set compatible microprocessor
--======================================================================
--
-- The Nova was an elegantly simple 16-bit minicompter designed by
-- Edson Decastro, the founder of Data General, Inc.
-- The orignial Nova-1200 was implemented in MSI TTL on a single
-- 15"x15" circuit board. The Nova 1200 was followed by several more
-- Nova processors including the Nova-3 and Nova-4, all of which shared
-- an upwardly-compatible instruction set (later models had additional
-- instructions. The NOVA had four 16-bit accumulators, as well as a
-- program counter, stack pointer, and stack frame pointer registers
-- (the last two were only on later Nova models).
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use work.my_types.all;
entity IP_NOVA is
port (
ADDR_15 : out std_logic_vector(15 downto 1); -- for debug only
ADDR_OUT : out std_logic_vector(15 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
DEVCODE : out std_logic_vector( 5 downto 0); -- I/O device
R_W : out std_logic; -- Mem 1==read 0==write
IORW : out std_logic; -- I/O 1==read 0==write
BYTE : out std_logic; -- Byte memory operation
IOM : out std_logic; -- 1==I/O 0==memory
SYNC : out std_logic; -- Opcode fetch status
IRQ : in std_logic; -- Interrupt Request (active-low)
PWR_GOOD : in std_logic; -- Power good
RDY : in std_logic; -- Ready input
RESET : in std_logic; -- Reset input (active-low)
FEN : in std_logic; -- clock enable
CLK : in std_logic; -- System Clock
DBUG7 : out std_logic; -- for debug
DBUG6 : out std_logic; -- for debug
DBUG5 : out std_logic; -- for debug
DBUG4 : out std_logic; -- for debug
DBUG3 : out std_logic; -- for debug
DBUG2 : out std_logic; -- for debug
DBUG1 : out std_logic -- for debug
);
end IP_NOVA;
architecture BEHAVIORAL of IP_NOVA is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
--=================================================================
-- Register operations
--=================================================================
type REG_OP_TYPE is (
LDR, -- load from ALU result bus
HOLD -- hold
);
--=================================================================
-- Scratch-register operations
--=================================================================
type SR1_OP_TYPE is (
LDR, -- load from ALU result bus
LD_DB, -- load from data bus
HOLD -- hold
);
--=================================================================
-- Program-Counter operations
--=================================================================
type PC_OP_TYPE is (
LDR, -- load from ALU result bus
LD_SX, -- load from address adder
LD_EA, -- load from EA
HOLD -- hold
);
--=================================================================
-- Stack Pointer operations
--=================================================================
type SP_OP_TYPE is (
LDR, -- load from ALU result bus
LD_FP, -- load from FP
LD_SX, -- load from address adder
HOLD -- hold
);
--=================================================================
-- Frame Pointer operations
--=================================================================
type FP_OP_TYPE is (
LDR, -- load from ALU result bus
LD_SP, -- load from SP
HOLD -- hold
);
--=================================================================
-- Effective address register operations
--=================================================================
type EA_OP_TYPE is (
LD_SX, -- load from address adder
LD_DB, -- load from data bus
LD_SR1, -- load from scratch register
LD_ZP, -- load zero-page address
HOLD -- hold
);
--=================================================================
-- Address Adder B-mux Selects
--=================================================================
type SX_BSEL_TYPE is (
SEL_PC,
SEL_AC2,
SEL_AC3,
SEL_EA,
SEL_SP
);
--=================================================================
-- Microcode States
--=================================================================
type UCODE_STATE_TYPE is (
AUTO_DEC1,
AUTO_INC1,
CHECK_SKIP,
EA_VALID,
FETCH_OPCODE,
GOT_OPCODE,
HALT_1,
JSR_1,
PSHA_1,
STORE_SR1,
STORE_EA,
RET_1,
RET_2,
RET_3,
RET_4,
RET_5,
SAV_1,
SAV_2,
SAV_3,
SAV_4,
SAV_5,
SAV_6,
RST_1,
UII_1
);
signal STATE : UCODE_STATE_TYPE;
signal NEXT_STATE : UCODE_STATE_TYPE;
signal AC0_OPCODE : REG_OP_TYPE; -- Accumulator 0 micro op
signal AC1_OPCODE : REG_OP_TYPE; -- Accumulator 1 micro op
signal AC2_OPCODE : REG_OP_TYPE; -- Accumulator 2 micro op
signal AC3_OPCODE : REG_OP_TYPE; -- Accumulator 3 micro op
signal SR1_OPCODE : SR1_OP_TYPE; -- Scratch Reg 1 micro op
signal PC_OPCODE : PC_OP_TYPE; -- Program-counter micro op
signal EA_OPCODE : EA_OP_TYPE; -- EA register micro op
signal SP_OPCODE : SP_OP_TYPE; -- Stack pointer micro op
signal FP_OPCODE : FP_OP_TYPE; -- Frame pointer micro op
signal ALX_OPCODE : ALU_OP_TYPE; -- ALU micro-op (from decoder)
signal ALY_OPCODE : ALU_OP_TYPE; -- ALU micro-op (auxilary)
signal ALU_OPCODE : ALU_OP_TYPE; -- ALU micro-op
signal USE_ALU : std_logic; -- select ALU micro-op
signal SX_OPCODE : SX_OP_TYPE; -- Address adder micro op
signal SX_BSEL : SX_BSEL_TYPE; -- Address adder operand select
signal FORMAT : OP_FORMAT_TYPE; -- Opcode format
signal ADDR_MODE : ADDR_MODE_TYPE; -- Address mode
signal IDX_CTL : IDX_CTL_TYPE; -- Index control
signal CARRY_CTL : CARRY_CTL_TYPE; -- Carry control
signal SHIFT_CTL : SHIFT_CTL_TYPE; -- Shift control
signal SHIFT_DEC : SHIFT_CTL_TYPE; -- Shift control
signal SKIP_CTL : SKIP_CTL_TYPE; -- Shift control
signal FLOW_CTL : FLOW_CTL_TYPE; -- Flow control
signal XFER_CTL : XFER_CTL_TYPE; -- Transfer control
signal IOU_CTL : IOU_CTL_TYPE; -- I/O control
signal EXT_OP : EXT_OP_TYPE; -- Extended opcode
signal NO_LOAD : std_logic; -- Load control
signal IND_CTL : std_logic; -- Indirect bit from decoder
signal INDIRECT : std_logic; -- Indirect level flop
signal CLR_IND : std_logic; -- clear Indirect flop
signal PC_TO_AC3 : std_logic; -- save PC for JSR
signal ASX_SEL : std_logic_vector( 1 downto 0); -- from decoder
signal ASY_SEL : std_logic_vector( 1 downto 0); -- auxilary select
signal ACS_SEL : std_logic_vector( 1 downto 0); -- source select
signal USE_ACS : std_logic; -- use aux select
signal ACS_FP : std_logic; -- select FP
signal ACS_SP : std_logic; -- select SP
signal ACS_SR1 : std_logic; -- select SR1
signal ACS_DIN : std_logic; -- select data_in
signal LDB_OP : std_logic; -- load byte
signal STB_OP : std_logic; -- store byte
signal BMUX_SEL : std_logic_vector( 1 downto 0); -- from decoder
signal DEST_SEL : std_logic_vector( 1 downto 0); -- dest reg select
signal ADY_SEL : std_logic_vector( 1 downto 0); -- auxilary select
signal USE_ACD : std_logic; -- use aux select
signal AMUX : std_logic_vector(15 downto 0); -- source mux
signal BMUX : std_logic_vector(15 downto 0); -- dest mux
-- Internal busses
signal RBUS : std_logic_vector(15 downto 0); -- result bus
signal SX : std_logic_vector(15 downto 0); -- address bus S
signal BX : std_logic_vector(15 downto 0); -- address bus B
signal ADDR_OX : std_logic_vector(15 downto 0); -- Internal addr bus
-- Architectural registers
signal AC0 : std_logic_vector(15 downto 0); -- accumulator 0
signal AC1 : std_logic_vector(15 downto 0); -- accumulator 1
signal AC2 : std_logic_vector(15 downto 0); -- accumulator 2
signal AC3 : std_logic_vector(15 downto 0); -- accumulator 3
signal SP : std_logic_vector(15 downto 0); -- stack pointer
signal FP : std_logic_vector(15 downto 0); -- frame pointer
signal PC : std_logic_vector(15 downto 0); -- program counter
signal EA : std_logic_vector(15 downto 0); -- effective address
-- Scratch registers
signal SR1 : std_logic_vector(15 downto 0); -- scratch reg 1
signal OPREG : std_logic_vector(15 downto 0); -- opcode reg
-- Status flags
signal IRQ_FF : std_logic; -- IRQ flip-flop
signal INTEN : std_logic; -- Interrupt Enable flip-flop
signal CBIT : std_logic; -- carry flag
signal ZBIT : std_logic; -- zero flag
signal LOAD_STAT : std_logic; -- Load I/O busy/done flags
signal BUSY : std_logic; -- I/O busy flag
signal DONE : std_logic; -- I/O done flag
-- Status flag update
signal UPDATE_C : std_logic; -- update carry flag
signal UPDATE_Z : std_logic; -- update zero flag
signal RESTORE : std_logic; -- Restore flags
signal SET_I : std_logic; -- set Interrupt Enable flag
signal CLR_I : std_logic; -- clear Interrupt Enable flag
signal SET_C : std_logic; -- load CBIT
-- Misc
signal MY_RESET : std_logic; -- active high reset
signal MMWRITE : std_logic; -- Mem Write control
signal IOWRITE : std_logic; -- I/O Write control
signal ACC_LOAD : std_logic; -- accumulator load
signal SKIP_COND : std_logic; -- skip condition
--================================================================
-- Constant definition section
--================================================================
-- Interrupt vector = $0002
constant INT_VEC : std_logic_vector(15 downto 0) := "0000000000000010";
-- Misc
constant END_OF_WAIT : std_logic_vector(8 downto 0) := "100000000";
--================================================================
-- Component definition section
--================================================================
--==========================
-- instruction decoder
--==========================
component DECODE
port (
-- opcode input
DECODE_IN : in std_logic_vector(15 downto 0);
-- opcode classes
FORMAT : out OP_FORMAT_TYPE; -- opcode format
ADDR_MODE : out ADDR_MODE_TYPE; -- address mode
-- ALU opcode fields
SRC_SEL : out std_logic_vector(1 downto 0); -- Source register
DST_SEL : out std_logic_vector(1 downto 0); -- Destination reg
ALU_OP : out ALU_OP_TYPE; -- ALU micro-op
SHIFT_CTL : out SHIFT_CTL_TYPE; -- Shifter control
CARRY_CTL : out CARRY_CTL_TYPE; -- Carry control
NO_LOAD : out std_logic; -- Load control
SKIP_CTL : out SKIP_CTL_TYPE; -- Skip control
-- Memory xfer opcode fields
FLOW_CTL : out FLOW_CTL_TYPE; -- Flow control
IND_CTL : out std_logic; -- Indirect control
IDX_CTL : out IDX_CTL_TYPE; -- Index control
-- I/O opcode fields
XFER_CTL : out XFER_CTL_TYPE; -- Transfer control
IOU_CTL : out IOU_CTL_TYPE; -- I/O device control
EXT_OP : out EXT_OP_TYPE -- extended opcode
);
end component;
--==========================
-- 16-bit ALU
--==========================
component ALU
port (
RBUS : out std_logic_vector(15 downto 0); -- Result bus
CBIT : out std_logic; -- carry status
ZBIT : out std_logic; -- zero status
ABUS : in std_logic_vector(15 downto 0); -- Src reg
BBUS : in std_logic_vector(15 downto 0); -- Dst reg
ALU_OP : in ALU_OP_TYPE; -- ALU op
SHIFT_CTL : in SHIFT_CTL_TYPE; -- Shifter op
CARRY_CTL : in CARRY_CTL_TYPE; -- ALU op
UPDATE_C : in std_logic; -- update carry flag
UPDATE_Z : in std_logic; -- update zero flag
RESTORE : in std_logic; -- restore flags
SET_C : in std_logic; -- load CBIT
RESET : in std_logic; -- reset
FEN : in std_logic; -- clock enable
CLK : in std_logic -- System clock
);
end component;
--==========================
-- 16-bit Address Adder
--==========================
component ADDR
port (
SX : out std_logic_vector(15 downto 0); -- result bus
BX : in std_logic_vector(15 downto 0); -- operand bus
DISP : in std_logic_vector( 7 downto 0); -- displacement
OP : in SX_OP_TYPE -- micro op
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
--================================================================
-- Start of the behavioral description
--================================================================
MY_RESET <= not RESET;
--================================================================
-- Microcode state machine
--================================================================
MICROCODE_STATE_MACHINE:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if ((FEN = '1') and (RDY = '1')) then
STATE <= NEXT_STATE;
-- reset state
if (MY_RESET = '1') then
STATE <= RST_1;
end if;
end if;
end if;
end process;
--================================================================
-- Source register mux
--================================================================
SRC_REGISTER_MUX:
process(ACS_SEL, AC0, AC1, AC2, AC3, USE_ACS, CBIT,
ACS_DIN, DATA_IN, ACS_FP, FP, ACS_SP, SP, ACS_SR1, SR1,
LDB_OP, BMUX)
begin
case ACS_SEL is
when "00" =>
AMUX <= AC0;
when "01" =>
AMUX <= AC1;
when "10" =>
AMUX <= AC2;
when others =>
AMUX <= AC3;
-- special case for SAV opcode
if (USE_ACS = '1') then
AMUX <= CBIT & AC3(14 downto 0);
end if;
end case;
if (ACS_FP = '1') then
AMUX <= '0' & FP(15 downto 1);
end if;
if (ACS_SP = '1') then
AMUX <= '0' & SP(15 downto 1);
end if;
if (ACS_SR1 = '1') then
AMUX <= SR1;
end if;
if (ACS_DIN = '1') then
AMUX <= DATA_IN;
end if;
if (LDB_OP = '1') then
-- check bit 0 of the byte address
if (BMUX(0) = '0') then
AMUX <= "00000000" & DATA_IN( 7 downto 0);
else
AMUX <= "00000000" & DATA_IN(15 downto 8);
end if;
end if;
end process;
--================================================================
-- Destination mux
--================================================================
DST_REGISTER_MUX:
process(BMUX_SEL, AC0, AC1, AC2, AC3)
begin
case BMUX_SEL is
when "00" =>
BMUX <= AC0;
when "01" =>
BMUX <= AC1;
when "10" =>
BMUX <= AC2;
when others =>
BMUX <= AC3;
end case;
end process;
--================================================================
-- Select Accumulator to load
--================================================================
REGISTER_LOAD_SELECT:
process(DEST_SEL, ACC_LOAD)
begin
AC0_OPCODE <= HOLD;
AC1_OPCODE <= HOLD;
AC2_OPCODE <= HOLD;
AC3_OPCODE <= HOLD;
if (ACC_LOAD = '1') then
case DEST_SEL is
when "00" =>
AC0_OPCODE <= LDR;
when "01" =>
AC1_OPCODE <= LDR;
when "10" =>
AC2_OPCODE <= LDR;
when others =>
AC3_OPCODE <= LDR;
end case;
end if;
end process;
--==================================================
-- Address Adder Mux B
--==================================================
ADDRESS_ADDER_MUX_B:
process(SX_BSEL, AC2, AC3, EA, SP, PC)
begin
case SX_BSEL IS
when SEL_AC2 =>
BX <= AC2(14 downto 0) & '0';
when SEL_AC3 =>
BX <= AC3(14 downto 0) & '0';
when SEL_EA =>
BX <= EA;
when SEL_SP =>
BX <= SP;
when others =>
BX <= PC;
end case;
end process;
--================================================================
-- Debug signals
--================================================================
DBUG1 <= '0';
DBUG2 <= '0';
DBUG3 <= '0';
DBUG4 <= '0';
DBUG5 <= '0';
DBUG6 <= '0';
DBUG7 <= '0';
ADDR_OUT <= ADDR_OX;
ADDR_15 <= ADDR_OX(15 downto 1); -- for simulation display
DEVCODE <= OPREG(5 downto 0); -- I/O device code
--================================================================
-- Register IRQ (active-low) inputs
--================================================================
INTERRUPT_STATUS_REGISTERS:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
-- only set the IRQ flip-flop if enabled
IRQ_FF <= not (IRQ or not INTEN);
-- Interrupt Enable flag
if (SET_I = '1') then
INTEN <= '1';
end if;
if (CLR_I = '1') then
INTEN <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
IRQ_FF <= '0';
INTEN <= '0';
end if;
end process;
--================================================================
-- I/O Busy/Done Status
--================================================================
BUSY_DONE_STATUS:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (LOAD_STAT = '1') then
BUSY <= DATA_IN(15);
DONE <= DATA_IN(14);
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
BUSY <= '0';
DONE <= '0';
end if;
end process;
--================================================================
-- Indirect status
--================================================================
INDIRECT_STATUS:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (STATE = GOT_OPCODE) then
INDIRECT <= IND_CTL;
end if;
if (CLR_IND = '1') then
INDIRECT <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
INDIRECT <= '1'; -- jmp @3
end if;
end process;
--================================================================
-- Opcode Register
--================================================================
OPCODE_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (STATE = FETCH_OPCODE) then
OPREG <= DATA_IN;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
OPREG <= x"0403"; -- jmp @3
end if;
end process;
--================================================================
-- Micro-operation and next-state generation
--================================================================
MICRO_OP_AND_NEXT_STATE_GENERATION:
process(ADDR_MODE, STATE, RBUS, PC, EA, SP, SR1, IRQ_FF, OPREG,
EXT_OP, IOU_CTL, XFER_CTL, SKIP_CTL, FLOW_CTL, IDX_CTL,
BMUX, SKIP_COND, FORMAT, INDIRECT, DATA_IN,
NO_LOAD, SHIFT_DEC)
begin
-- default micro-ops
PC_OPCODE <= HOLD;
SX_OPCODE <= INC1;
SX_BSEL <= SEL_PC;
EA_OPCODE <= HOLD;
SP_OPCODE <= HOLD;
FP_OPCODE <= HOLD;
SR1_OPCODE <= HOLD;
MMWRITE <= '0'; -- 0==read 1==write
IOWRITE <= '0'; -- 0==read 1==write
BYTE <= '0'; -- 1==byte 0==word
IOM <= '0'; -- 1==I/O 0==memory
ACC_LOAD <= '0';
ACS_FP <= '0';
ACS_SP <= '0';
ACS_SR1 <= '0';
ACS_DIN <= '0';
DATA_OUT <= RBUS;
NEXT_STATE <= FETCH_OPCODE;
SHIFT_CTL <= SHIFT_DEC;
ADDR_OX <= PC;
USE_ALU <= '0'; -- use aux ALU control
USE_ACS <= '0'; -- use aux source register select
USE_ACD <= '0'; -- use aux dest register select
ALY_OPCODE <= INC; -- default auxillary ALU op
ASY_SEL <= "00"; -- default auxillary source select
ADY_SEL <= "00"; -- default auxillary source select
UPDATE_C <= '0'; -- update carry flag
UPDATE_Z <= '0'; -- update zero flag
RESTORE <= '0'; -- restore ALU flags
SET_I <= '0'; -- set Interrupt Enable flag
CLR_I <= '0'; -- clear Interrupt Enable flag
SET_C <= '0'; -- load CBIT
CLR_IND <= '0'; -- clear indirect flop
LOAD_STAT <= '0'; -- load I/O busy/done status
PC_TO_AC3 <= '0'; -- save PC for JSR
LDB_OP <= '0'; -- load byte operation
STB_OP <= '0'; -- store byte operation
case STATE is
--============================================
-- Reset startup sequence
--============================================
when RST_1 =>
-- Stay here until reset is de-bounced
PC_OPCODE <= HOLD;
NEXT_STATE <= GOT_OPCODE;
--============================================
-- Fetch Opcode State
--============================================
when FETCH_OPCODE =>
-- Check for IRQ
if (IRQ_FF = '1') then
CLR_I <= '1'; -- Disable further interrupts
ADDR_OX <= "0000000000000010";
USE_ALU <= '1';
ALY_OPCODE <= TA;
PC_OPCODE <= LDR; -- load vector
NEXT_STATE <= FETCH_OPCODE;
else
-- Fetch the opcode
NEXT_STATE <= GOT_OPCODE;
end if;
--============================================
-- Opcode Latch contains an opcode
--============================================
when GOT_OPCODE =>
PC_OPCODE <= LD_SX;
case ADDR_MODE is
--=================================
-- Calculate Effective Address
--=================================
when ADM_EA =>
PC_OPCODE <= HOLD;
case IDX_CTL is
when REL => -- PC relative
SX_OPCODE <= REL;
SX_BSEL <= SEL_PC;
EA_OPCODE <= LD_SX;
when IDX2 => -- AC2 indexed
SX_OPCODE <= REL;
SX_BSEL <= SEL_AC2;
EA_OPCODE <= LD_SX;
when IDX3 => -- AC3 indexed
SX_OPCODE <= REL;
SX_BSEL <= SEL_AC3;
EA_OPCODE <= LD_SX;
when others => -- zero page
EA_OPCODE <= LD_ZP;
end case;
NEXT_STATE <= EA_VALID;
--=================================
-- Implied Addressing Mode
--=================================
when others =>
case FORMAT is
when ALU_FORMAT =>
UPDATE_C <= '1';
UPDATE_Z <= '1';
-- load control
ACC_LOAD <= not NO_LOAD;
case SKIP_CTL is
when SKP => -- skip always
SX_OPCODE <= INC2;
SX_BSEL <= SEL_PC;
if (NO_LOAD = '1') then
UPDATE_C <= '0';
UPDATE_Z <= '0';
end if;
NEXT_STATE <= FETCH_OPCODE;
when NOP => -- skip never
NEXT_STATE <= FETCH_OPCODE;
when others => -- evaluate skip cond
NEXT_STATE <= CHECK_SKIP;
end case;
when IOU_FORMAT =>
IOM <= '1';
-- check for device 0x3f special cases
if (OPREG(5 downto 0) = "111111") then
-- Interrupt Enable flag control
case IOU_CTL is
when SBCD => -- set
SET_I <= '1';
when CBCD => -- clear
CLR_I <= '1';
when others =>
end case;
case XFER_CTL is
when DIA => -- read switches
ACC_LOAD <= '1';
when DOA => -- nop
when DIB => -- interrupt acknowledge
ACC_LOAD <= '1';
when DOB => -- mask out
when DIC => -- I/O reset
when DOC => -- Halt
PC_OPCODE <= HOLD;
NEXT_STATE <= HALT_1;
when SKP => -- CPU skip
NEXT_STATE <= CHECK_SKIP;
when others =>
end case;
else
case XFER_CTL is
when NOP => -- special case ops
when DIA => -- data in from buffer A
ACC_LOAD <= '1';
ACS_DIN <= '1';
when DOA => -- data out to buffer A
IOWRITE <= '1';
when DIB => -- data in from buffer B
ACC_LOAD <= '1';
ACS_DIN <= '1';
when DOB => -- data out to buffer B
IOWRITE <= '1';
when DIC => -- data in from buffer C
ACC_LOAD <= '1';
ACS_DIN <= '1';
when DOC => -- data out to buffer C
IOWRITE <= '1';
when SKP => -- skip on I/O condition
LOAD_STAT <= '1';
NEXT_STATE <= CHECK_SKIP;
when others =>
end case;
end if;
when EXT_FORMAT =>
case EXT_OP is
when LDB => -- load byte
LDB_OP <= '1';
ADDR_OX <= BMUX;
ACC_LOAD <= '1';
when STB => -- store byte
STB_OP <= '1';
MMWRITE <= '1';
BYTE <= '1';
ADDR_OX <= BMUX;
if (BMUX(0) = '1') then
SHIFT_CTL <= SWAP;
end if;
when MTFP => -- move to frame pointer
FP_OPCODE <= LDR;
when MFFP => -- move from frame pointer
ACS_FP <= '1';
ACC_LOAD <= '1';
when MTSP => -- move to stack pointer
SP_OPCODE <= LDR;
when MFSP => -- move from stack pointer
ACS_SP <= '1';
ACC_LOAD <= '1';
when PSHA => -- push accumulator
-- pre-inc the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= INC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= PSHA_1;
when POPA => -- pop accumulator
ACS_DIN <= '1';
ACC_LOAD <= '1';
ADDR_OX <= SP;
-- decrement the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= DEC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= FETCH_OPCODE;
when SAV => -- save registers
NEXT_STATE <= SAV_1;
when RET => -- return from subroutine
ACS_FP <= '1';
SP_OPCODE <= LD_FP; -- copy FP to SP
NEXT_STATE <= RET_1;
when others =>
end case;
-- unimplemented
when others =>
NEXT_STATE <= UII_1;
end case; -- end of FORMAT case
end case; -- end of ADDR_MODE case
if (FORMAT = UII_FORMAT) then
NEXT_STATE <= UII_1;
end if;
--=====================================================
-- At this point we have the 16-bit absolute address
-- stored in the EA register.
--=====================================================
when EA_VALID =>
PC_OPCODE <= HOLD;
NEXT_STATE <= FETCH_OPCODE;
-- Check for indirection
ADDR_OX <= EA;
if (INDIRECT = '1') then
NEXT_STATE <= EA_VALID;
EA_OPCODE <= LD_DB; -- load vector
-- check for levels of indirection
if (DATA_IN(15) = '0') then
-- Indirection is complete
CLR_IND <= '1'; -- clear indirect flop
end if;
-- check for Auto-Inc/Auto-Dec
if (EA(15 downto 6) = "0000000000") then
if (EA( 5 downto 4) = "10") then
EA_OPCODE <= HOLD;
SR1_OPCODE <= LD_DB;
NEXT_STATE <= AUTO_INC1;
end if;
if (EA( 5 downto 4) = "11") then
EA_OPCODE <= HOLD;
SR1_OPCODE <= LD_DB;
NEXT_STATE <= AUTO_DEC1;
end if;
end if;
else
PC_OPCODE <= LD_SX;
case FORMAT is
-- load the selected accumulator
when LDA_FORMAT =>
ACS_DIN <= '1';
ACC_LOAD <= '1';
-- store the selected accumulator
when STA_FORMAT =>
MMWRITE <= '1';
-- Program flow control
when MEM_FORMAT =>
case FLOW_CTL is
-- jump to address
when JMP =>
PC_OPCODE <= LD_EA;
-- jump to subroutine
when JSR =>
PC_OPCODE <= LD_SX;
NEXT_STATE <= JSR_1;
-- incr and skip if zero
when ISZ =>
ACS_DIN <= '1';
SR1_OPCODE <= LDR;
UPDATE_Z <= '1';
NEXT_STATE <= STORE_SR1;
-- decr and skip if zero
when DSZ =>
ACS_DIN <= '1';
SR1_OPCODE <= LDR;
UPDATE_Z <= '1';
NEXT_STATE <= STORE_SR1;
-- unimplemented
when others =>
NEXT_STATE <= UII_1;
end case;
-- unimplemented
when others =>
NEXT_STATE <= UII_1;
end case;
end if;
--=====================================================
-- Complete the ISZ/DSZ instructions
--=====================================================
when STORE_SR1 =>
-- store the scratch register
ADDR_OX <= EA;
DATA_OUT <= SR1;
PC_OPCODE <= HOLD;
MMWRITE <= '1';
NEXT_STATE <= CHECK_SKIP;
--=====================================================
-- Complete AutoInc and AutoDec Indirection
--=====================================================
when AUTO_INC1 =>
ACS_SR1 <= '1';
USE_ALU <= '1';
ALY_OPCODE <= INC;
SR1_OPCODE <= LDR;
NEXT_STATE <= STORE_EA;
when AUTO_DEC1 =>
ACS_SR1 <= '1';
USE_ALU <= '1';
ALY_OPCODE <= DEC;
SR1_OPCODE <= LDR;
NEXT_STATE <= STORE_EA;
when STORE_EA =>
-- store the scratch register
ADDR_OX <= EA;
DATA_OUT <= SR1;
EA_OPCODE <= LD_SR1;
MMWRITE <= '1';
NEXT_STATE <= EA_VALID;
--=====================================================
-- Evaluate the skip
--=====================================================
when CHECK_SKIP =>
if (SKIP_COND = '1') then
PC_OPCODE <= LD_SX;
else
PC_OPCODE <= HOLD;
end if;
-- restore flags after no-load op
if (NO_LOAD = '1') then
RESTORE <= '1';
end if;
--=====================================================
-- Complete the JSR instruction
--=====================================================
when JSR_1 =>
-- save the PC in AC3
PC_TO_AC3 <= '1';
-- load the PC from EA
PC_OPCODE <= LD_EA;
NEXT_STATE <= FETCH_OPCODE;
--=====================================================
-- Complete the SAV instruction
--=====================================================
when SAV_1 =>
-- pre-inc the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= INC1;
SP_OPCODE <= LD_SX;
PC_OPCODE <= HOLD;
NEXT_STATE <= SAV_2;
when SAV_2 =>
-- save AC0
USE_ACS <= '1';
ASY_SEL <= "00";
ADDR_OX <= SP;
MMWRITE <= '1';
-- increment the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= INC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= SAV_3;
when SAV_3 =>
-- save AC1
USE_ACS <= '1';
ASY_SEL <= "01";
ADDR_OX <= SP;
MMWRITE <= '1';
-- increment the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= INC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= SAV_4;
when SAV_4 =>
-- save AC2
USE_ACS <= '1';
ASY_SEL <= "10";
ADDR_OX <= SP;
MMWRITE <= '1';
-- increment the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= INC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= SAV_5;
when SAV_5 =>
-- save the frame pointer
ACS_FP <= '1';
ADDR_OX <= SP;
MMWRITE <= '1';
-- increment the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= INC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= SAV_6;
when SAV_6 =>
-- save AC3
USE_ACS <= '1';
ASY_SEL <= "11";
ADDR_OX <= SP;
MMWRITE <= '1';
-- copy the SP to FP
FP_OPCODE <= LD_SP;
NEXT_STATE <= FETCH_OPCODE;
--=====================================================
-- Complete the RET instruction
--=====================================================
when RET_1 =>
-- restore the PC and CBIT
ACS_DIN <= '1';
PC_OPCODE <= LDR;
SET_C <= '1';
ADDR_OX <= SP;
-- decrement the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= DEC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= RET_2;
when RET_2 =>
-- restore AC3 and the frame pointer
ACS_DIN <= '1';
USE_ACD <= '1';
ADY_SEL <= "11";
ACC_LOAD <= '1';
FP_OPCODE <= LDR;
ADDR_OX <= SP;
-- decrement the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= DEC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= RET_3;
when RET_3 =>
-- restore AC2
ACS_DIN <= '1';
USE_ACD <= '1';
ADY_SEL <= "10";
ACC_LOAD <= '1';
ADDR_OX <= SP;
-- decrement the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= DEC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= RET_4;
when RET_4 =>
-- restore AC1
ACS_DIN <= '1';
USE_ACD <= '1';
ADY_SEL <= "01";
ACC_LOAD <= '1';
ADDR_OX <= SP;
-- decrement the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= DEC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= RET_5;
when RET_5 =>
-- restore AC0
ACS_DIN <= '1';
USE_ACD <= '1';
ADY_SEL <= "00";
ACC_LOAD <= '1';
ADDR_OX <= SP;
-- decrement the stack pointer
SX_BSEL <= SEL_SP;
SX_OPCODE <= DEC1;
SP_OPCODE <= LD_SX;
NEXT_STATE <= FETCH_OPCODE;
--=====================================================
-- Complete the PSHA instruction
--=====================================================
when PSHA_1 =>
ADDR_OX <= SP;
MMWRITE <= '1';
NEXT_STATE <= FETCH_OPCODE;
--=====================================================
-- CPU Halt
--=====================================================
when HALT_1 =>
PC_OPCODE <= HOLD;
NEXT_STATE <= HALT_1;
-- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- Halt should jump to the virtual console
-- This is not implemented yet
-- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--=====================================================
-- Unimplemeted trap
--=====================================================
when others =>
PC_OPCODE <= HOLD;
NEXT_STATE <= UII_1;
end case;
end process;
--================================================================
-- Read/Write Status output pin
--================================================================
R_W <= not MMWRITE;
IORW <= not IOWRITE;
--================================================================
-- Skip control
--================================================================
SKIP_CONTROL:
process(SKIP_CTL, CBIT, ZBIT, DONE, BUSY, INTEN, PWR_GOOD)
begin
case SKIP_CTL is
when SKP => -- skip always
SKIP_COND <= '1';
when SKC => -- skip if carry zero
SKIP_COND <= not CBIT;
when SNC => -- skip if carry non-zero
SKIP_COND <= CBIT;
when SZR => -- skip if result zero
SKIP_COND <= ZBIT;
when SNR => -- skip if result non-zero
SKIP_COND <= not ZBIT;
when SEZ => -- skip if either zero
SKIP_COND <= ZBIT or (not CBIT);
when SBN => -- skip if both non-zero
SKIP_COND <= (not ZBIT) and CBIT;
when SKPBZ => -- skip if busy is zero
SKIP_COND <= not DONE;
when SKPDN => -- skip if done is set
SKIP_COND <= DONE;
when SKPDZ => -- skip if done is zero
SKIP_COND <= not BUSY;
when SKPBN => -- skip if busy is set
SKIP_COND <= BUSY;
when SKPIE => -- skip if Int enabled
SKIP_COND <= INTEN;
when SKPID => -- skip if Int disabled
SKIP_COND <= not INTEN;
when SKPPF => -- skip if power failed
SKIP_COND <= not PWR_GOOD;
when SKPPO => -- skip if power OK
SKIP_COND <= PWR_GOOD;
when others => -- no skip
SKIP_COND <= '0';
end case;
end process;
--================================================================
-- ALU opcode Mux
--================================================================
ALU_OPCODE_MUX:
process(USE_ALU, ALX_OPCODE, ALY_OPCODE)
begin
-- Usually ALU control comes from the decoder
-- but occasionally we want to override that control
ALU_OPCODE <= ALX_OPCODE;
if (USE_ALU = '1') then
ALU_OPCODE <= ALY_OPCODE;
end if;
end process;
--================================================================
-- Register source-select Mux
--================================================================
SOURCE_SELECT_MUX:
process(ASX_SEL, USE_ACS, ASY_SEL)
begin
-- Usually source select control comes from the decoder
-- but occasionally we want to override that control
ACS_SEL <= ASX_SEL;
if (USE_ACS = '1') then
ACS_SEL <= ASY_SEL;
end if;
end process;
--================================================================
-- Destination resiter select
--================================================================
DESTINATION_REGISTER_SELECT:
process(BMUX_SEL, USE_ACD, ADY_SEL, LDB_OP, STB_OP, ASX_SEL)
begin
-- Usually destination select control comes from the decoder
-- but occasionally we want to override that control
DEST_SEL <= BMUX_SEL;
if (USE_ACD = '1') then
DEST_SEL <= ADY_SEL;
end if;
-- The src and dst were swapped for the LDB instruction
-- due to logic optimization reasons
if ((LDB_OP = '1') or (STB_OP = '1')) then
DEST_SEL <= ASX_SEL;
end if;
end process;
--=====================================================
-- Sync Status Output flip-flop
--=====================================================
SYNC_STATUS_FLIP_FLOP:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (NEXT_STATE = FETCH_OPCODE) then
SYNC <= '1';
else
SYNC <= '0';
end if;
end if;
end if;
end process;
--================================================================
-- Accumulator AC0
--================================================================
ACCUMULATOR_0:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (AC0_OPCODE = LDR) then
AC0 <= RBUS;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
AC0 <= (others => '0');
end if;
end process;
--================================================================
-- Accumulator AC1
--================================================================
ACCUMULATOR_1:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (AC1_OPCODE = LDR) then
AC1 <= RBUS;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
AC1 <= (others => '0');
end if;
end process;
--================================================================
-- Accumulator AC2
--================================================================
ACCUMULATOR_2:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (AC2_OPCODE = LDR) then
AC2 <= RBUS;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
AC2 <= (others => '0');
end if;
end process;
--================================================================
-- Accumulator AC3
--================================================================
ACCUMULATOR_3:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (AC3_OPCODE = LDR) then
AC3 <= RBUS;
end if;
if (PC_TO_AC3 = '1') then
AC3 <= '0' & PC(15 downto 1);
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
AC3 <= (others => '0');
end if;
end process;
--================================================================
-- Scratch Register SR1
--================================================================
SCRATCH_REGISTER_1:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case SR1_OPCODE is
when LDR =>
SR1 <= RBUS;
when LD_DB =>
SR1 <= DATA_IN;
when others =>
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
SR1 <= (others => '0');
end if;
end process;
--================================================================
-- Stack Pointer (SP)
--================================================================
STACK_POINTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case SP_OPCODE is
when LDR =>
SP <= RBUS(14 downto 0) & '0';
when LD_FP =>
SP <= FP;
when LD_SX =>
SP <= SX;
when others =>
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
SP <= (others => '0');
end if;
end process;
--================================================================
-- Frame Pointer (FP)
--================================================================
FRAME_POINTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case FP_OPCODE is
when LDR =>
FP <= RBUS(14 downto 0) & '0';
when LD_SP =>
FP <= SP;
when others =>
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
FP <= (others => '0');
end if;
end process;
--================================================================
-- Program Counter (PC)
--================================================================
PROGRAM_COUNTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case PC_OPCODE is
when LD_SX =>
PC <= SX;
when LDR =>
PC <= RBUS(14 downto 0) & '0';
when LD_EA =>
PC <= EA;
when others =>
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
PC <= x"0100";
end if;
end process;
--=================================================
-- Effective Address register (EA)
--=================================================
EA_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case EA_OPCODE is
when LD_SX =>
EA <= SX;
when LD_DB =>
EA <= DATA_IN(14 downto 0) & '0';
when LD_SR1 =>
EA <= SR1(14 downto 0) & '0';
when LD_ZP =>
EA <= "0000000" & OPREG(7 downto 0) & '0';
when others =>
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
EA <= (others => '0');
end if;
end process;
--===================================
-- Instantiate the ALU
--===================================
ALU1:
ALU port map (
RBUS => RBUS,
CBIT => CBIT,
ZBIT => ZBIT,
ABUS => AMUX,
BBUS => BMUX,
ALU_OP => ALU_OPCODE,
SHIFT_CTL => SHIFT_CTL,
CARRY_CTL => CARRY_CTL,
UPDATE_C => UPDATE_C,
UPDATE_Z => UPDATE_Z,
RESTORE => RESTORE,
SET_C => SET_C,
RESET => MY_RESET,
FEN => FEN,
CLK => CLK
);
--=============================================
-- Instantiate the 16-bit Address Adder
--=============================================
ADDR1:
ADDR port map (
SX => SX,
BX => BX,
DISP => OPREG(7 downto 0),
OP => SX_OPCODE
);
--=========================================
-- Instantiate the instruction decoder
--=========================================
DECODER:
DECODE port map (
DECODE_IN => OPREG,
FORMAT => FORMAT,
ADDR_MODE => ADDR_MODE,
SRC_SEL => ASX_SEL,
DST_SEL => BMUX_SEL,
ALU_OP => ALX_OPCODE,
SHIFT_CTL => SHIFT_DEC,
CARRY_CTL => CARRY_CTL,
NO_LOAD => NO_LOAD,
SKIP_CTL => SKIP_CTL,
FLOW_CTL => FLOW_CTL,
IND_CTL => IND_CTL,
IDX_CTL => IDX_CTL,
XFER_CTL => XFER_CTL,
IOU_CTL => IOU_CTL,
EXT_OP => EXT_OP
);
end BEHAVIORAL;
|
gpl-3.0
|
be33859f475df5eeea41818f639f0f50
| 0.340993 | 5.088069 | false | false | false | false |
Digilent/vivado-library
|
ip/clock_forwarder/hdl/clock_forwarder.vhd
| 1 | 1,829 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clock_forwarder is
generic (
kArch : string := "artix7"
);
port (
aRst : in std_logic;
InClk : in std_logic;
iCE : in std_logic;
OutClk : out std_logic
);
end clock_forwarder;
architecture arch_imp of clock_forwarder is
begin
zynquplus: if kArch = "zynquplus" or kArch = "kintexuplus" or kArch = "virtexuplus" generate
begin
ODDRE1_inst : ODDRE1
generic map (
IS_C_INVERTED => '0', -- Optional inversion for C
IS_D1_INVERTED => '0', -- Unsupported, do not use
IS_D2_INVERTED => '0', -- Unsupported, do not use
SRVAL => '0' -- Initializes the ODDRE1 Flip-Flops to the specified value ('0', '1')
)
port map (
Q => OutClk, -- 1-bit output: Data output to IOB
C => InClk, -- 1-bit input: High-speed clock input
D1 => '1', -- 1-bit input: Parallel data input 1
D2 => '0', -- 1-bit input: Parallel data input 2
SR => aRst -- 1-bit input: Active High Async Reset
);
end generate zynquplus;
nonzynquplus: if not (kArch = "zynquplus" or kArch = "kintexuplus" or kArch = "virtexuplus") generate
begin
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => OutClk, -- 1-bit DDR output
C => InClk, -- 1-bit clock input
CE => iCE, -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => aRst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate nonzynquplus;
end arch_imp;
|
mit
|
c8edf55fcb83f6fafc1464a2b50b06ec
| 0.586113 | 3.387037 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/tb/tb_LM.vhd
| 1 | 7,680 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/31/2017 07:40:43 PM
-- Design Name:
-- Module Name: tb_LM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use STD.textio.all; -- basic I/O
use ieee.std_logic_textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_LM is
-- Port ( );
end tb_LM;
architecture Behavioral of tb_LM is
component LM is
Generic(
kMaxLaneCount : natural := 4;
--PPI
kLaneCount : natural range 1 to 4 := 2 --[1,2,4]
);
Port (
RxByteClkHS : in STD_LOGIC;
RxDataHS : in STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
RxSyncHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxValidHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxActiveHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
--Master AXI-Stream
rbMAxisTdata : out std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
rbMAxisTkeep : out std_logic_vector(kMaxLaneCount - 1 downto 0);
rbMAxisTvalid : out std_logic;
rbMAxisTready : in std_logic;
rbMAxisTlast : out std_logic;
rbErrSkew : out std_logic;
rbErrOvf : out std_logic;
rbEn : in std_logic;
rbRst : in std_logic
);
end component LM;
constant kLaneCount : natural := 4;
constant kMaxLaneCount : natural := 4;
signal RxByteClkHS : STD_LOGIC := '0';
signal RxDataHS : STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
signal RxSyncHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal RxValidHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal RxActiveHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal m_axis_tdata : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal m_axis_tkeep : std_logic_vector(kMaxLaneCount - 1 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tlast : std_logic;
signal m_axis_tid : std_logic;
signal rbRst, rbEn : std_logic;
constant kClkPeriod : time := 10 ns;
procedure Idle(dur : in time; signal RxValidHS : out std_logic; signal RxSyncHS : out std_logic;
signal RxActiveHS : out std_logic; signal RxDataHS : out std_logic_vector) is
begin
RxValidHS <= '0';
RxSyncHS <= '0';
RxActiveHS <= '0';
RxDataHS <= (others => '-');
wait for dur;
end procedure;
procedure SetFor(cPeriods : in natural; signal Rx: out std_logic; value : in std_logic; signal RxClk: in std_logic) is
begin
Rx <= value;
for i in 1 to cPeriods loop
wait until Rising_Edge(RxClk);
end loop;
end procedure;
type mem is array (natural range <>) of std_logic_vector(7 downto 0);
--LSByte first
constant data_stim : mem := (x"CC", x"78", x"00", x"0F",
x"FF", x"00", x"00", x"02", x"B9", x"DC", x"F3", x"72", x"BB", x"D4", x"B8", x"5A", x"C8", x"75", x"C2", x"7C", x"81", x"F8", x"05", x"DF", x"FF", x"00", x"00", x"01",
x"F0", x"00",
--dummy data
x"fc", x"04", x"29", x"37"
);
begin
--TODO generate for all lane counts
RxByteClkHS <= not RxByteClkHS after kClkPeriod / 2;
Lanes: for iLane in 0 to kLaneCount-1 generate
LaneStimulus: process
begin
Idle(100ns, RxValidHS(iLane), RxSyncHS(iLane), RxActiveHS(iLane), RxDataHS((iLane+1)*8-1 downto iLane*8));
wait until Rising_Edge(RxByteClkHS);
if (iLane = 0) then
--lane skew
wait until Rising_Edge(RxByteClkHS);
wait until Rising_Edge(RxByteClkHS);
end if;
if (iLane = 1) then
--lane skew
wait until Rising_Edge(RxByteClkHS);
end if;
RxActiveHS(iLane) <= '1';
SetFor(1, RxSyncHS(iLane), '1', RxByteClkHS);
RxSyncHS(iLane) <= '0';
SendData: for i in 0 to data_stim'length/kLaneCount loop
if (kLaneCount*i + iLane > data_stim'length-1) then
RxDataHS((iLane+1)*8-1 downto iLane*8) <= (others => '-');
RxValidHS(iLane) <= '0';
RxActiveHS(iLane) <= '0';
else
RxDataHS((iLane+1)*8-1 downto iLane*8) <= data_stim(kLaneCount*i+iLane);
RxValidHS(iLane) <= '1';
end if;
wait until Rising_Edge(RxByteClkHS);
end loop SendData;
RxActiveHS(iLane) <= '0';
RxValidHS(iLane) <= '0';
wait;
end process;
end generate Lanes;
process
begin
rbRst <= '1';
rbEn <= '0';
m_axis_tready <= '0';
wait until Rising_Edge(RxByteClkHS);
wait until Rising_Edge(RxByteClkHS);
wait until Rising_Edge(RxByteClkHS);
rbRst <= '0';
rbEn <= '1';
SetFor(17, m_axis_tready, '0', RxByteClkHS);
m_axis_tready <= '1';
wait;
end process;
Verification: process (RxByteClkHS)
variable cnt_byte : natural := 0;
variable my_line : line; -- type 'line' comes from textio
begin
if Rising_Edge(RxByteClkHS) then
if (m_axis_tvalid = '1') then
if (m_axis_tready = '1') then
for i in 0 to kMaxLaneCount - 1 loop
if (m_axis_tkeep(i) = '1') then
if m_axis_tdata((i+1)*8-1 downto i*8) /= data_stim(cnt_byte) then
write(my_line, string'("Error at byte "));
write(my_line, cnt_byte);
write(my_line, string'(", data: "));
write(my_line, m_axis_tdata((i+1)*8-1 downto i*8));
write(my_line, string'(", stim: "));
write(my_line, data_stim(cnt_byte));
writeline(output, my_line);
end if;
cnt_byte := cnt_byte + 1;
end if;
end loop;
if (m_axis_tlast = '1' and cnt_byte < data_stim'length) or
(m_axis_tlast = '0' and cnt_byte >= data_stim'length) then
write(my_line, string'("Error at last byte; misaligned cnt_byte="));
write(my_line, cnt_byte);
writeline(output, my_line);
end if;
if (m_axis_tlast = '1' and cnt_byte = data_stim'length) then
write(my_line, string'("Success, received last byte"));
writeline(output, my_line);
end if;
else
write(my_line, string'("Error, overflow"));
writeline(output, my_line);
assert (false) report "Error, overflow" severity failure;
end if;
end if;
end if;
end process;
DUT: LM
generic map (
kLaneCount => kLaneCount
)
port map (
RxByteClkHS => RxByteClkHS,
RxDataHS => RxDataHS,
RxSyncHS => RxSyncHS,
RxValidHS => RxValidHS,
RxActiveHS => RxActiveHS,
rbMAxisTdata => m_axis_tdata,
rbMAxisTkeep => m_axis_tkeep,
rbMAxisTvalid => m_axis_tvalid,
rbMAxisTready => m_axis_tready,
rbMAxisTlast => m_axis_tlast,
rbErrSkew => open,
rbErrOvf => open,
rbEn => rbEn,
rbRst => rbRst
);
end Behavioral;
|
mit
|
58cd1461a219275d2fa31cdb5d0c8c3e
| 0.559115 | 3.813307 | false | false | false | false |
SLongofono/digital-design-final-project
|
memory.vhd
| 1 | 911 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
port (
clk : in std_logic;
rst : in std_logic;
write : in std_logic;
address_read : in integer;
address_write : in integer;
write_data : in std_logic_vector(11 downto 0);
read_data : out std_logic_vector(11 downto 0)
);
end memory;
architecture behav of memory is
type ram is array (0 to 307199) of std_logic_vector(11 downto 0);
signal myram : ram := (others => "101010101010");
signal read_address : integer;
begin
process(clk, rst)
begin
-- **Note** Not synthesizable if a reset is added
if rising_edge(clk) then
if ('1' = write ) then
myram(address_write) <= write_data;
end if;
read_address <= address_read;
end if;
end process;
read_data <= myram(read_address);
end behav;
|
mit
|
ccd80fe0517cccb5c226b1a8501cdfea
| 0.603732 | 3.490421 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/ConversorBinToBCD_TB.vhd
| 2 | 1,867 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ConversorBinToBCD_TB IS
END ConversorBinToBCD_TB;
ARCHITECTURE behavior OF ConversorBinToBCD_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd
PORT(
entrada_bin : IN std_logic_vector(15 downto 0);
millares : OUT std_logic_vector(3 downto 0);
centenas : OUT std_logic_vector(3 downto 0);
decenas : OUT std_logic_vector(3 downto 0);
unidades : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_bin : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal millares : std_logic_vector(3 downto 0);
signal centenas : std_logic_vector(3 downto 0);
signal decenas : std_logic_vector(3 downto 0);
signal unidades : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd PORT MAP (
entrada_bin => entrada_bin,
millares => millares,
centenas => centenas,
decenas => decenas,
unidades => unidades
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
entrada_bin<="0001111100101101";
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
463eadef313f7e95fa82504dca0cbc91
| 0.564542 | 4.542579 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_streg8j.vhd
| 1 | 2,149 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_streg8j_DSP48_4 is
port (
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(24 - 1 downto 0);
in2: in std_logic_vector(30 - 1 downto 0);
dout: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of hls_contrast_streg8j_DSP48_4 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(unsigned(in1), 25));
b <= signed(resize(signed(in0), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 32));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_streg8j is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_streg8j is
component hls_contrast_streg8j_DSP48_4 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_streg8j_DSP48_4_U : component hls_contrast_streg8j_DSP48_4
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
66e89c155d9beedcd4170a2cc553a5a3
| 0.570033 | 3.285933 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/HS_Clocking.vhd
| 1 | 11,224 |
-------------------------------------------------------------------------------
--
-- File: HS_Clocking.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary primitives to obtain a fast
-- serial clock and a divided parallel clock from the the D-PHY high-speed
-- clock input. It also instantiates logic for IDELAYE2 primitives to be
-- usable throughout the design.
-- Connect this module to the output of the HS clock lane input buffer. Connect
-- an architecture-dependent 200/300 MHz reference clock for IDELAYCTRL
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity HS_Clocking is
Generic (
kGenerateMMCM : boolean := false;
kCtlClkFreqHz : integer := 100_000_000;
kRefClkFreqHz : integer := 200_000_000;
kAddDelay_ps : integer := 0
);
Port (
HS_Clock : in STD_LOGIC;
HS_SerClk : out STD_LOGIC;
HS_Div4Clk : out STD_LOGIC;
CtlClk : in STD_LOGIC;
cRst : in std_logic; --Must be asserted when CtlClk or HS_Clk are not present/stable; must be de-asserted synchronously with CtlClk
aLocked : out std_logic;
dbg_cBUFR_Rst : out std_logic;
dbg_cMMCM_Rst : out std_logic;
dbg_cMMCM_RstTout : out std_logic;
dbg_cMMCM_Locked : out std_logic
);
end HS_Clocking;
architecture Behavioral of HS_Clocking is
constant kRefClkFreqInMHz : real := real(kRefClkFreqHz) / 1_000_000.0;
constant kDelayTaps : natural := natural(ceil(real(kAddDelay_ps) * (kRefClkFreqInMHz*2.0*32.0) / 1_000_000.0));
constant kMMCM_RSTMINPULSE : real := 5.0; --ns; Artix-7 spec
constant kTMMCM_Rst : natural := natural(ceil(kMMCM_RSTMINPULSE / (10.0**9) * real(kCtlClkFreqHz)));
signal cBUFR_Rst, cExtRst, cMMCM_Rst : std_logic;
signal cDelayCnt : natural range 0 to kTMMCM_Rst := 0;
signal cMMCM_RstTout, cDelayCntEn : std_logic;
signal aMMCM_Locked, cMMCM_Locked, cMMCM_LockedFalling, cMMCM_LockedRising : std_logic;
signal cMMCM_Reset_q : std_logic_vector(1 downto 0);
signal cMMCM_Locked_q : std_logic_vector(1 downto 0);
signal dDiv4ClkActive : std_logic;
signal ClkFbOut, ClkFbIn, HS_Clock_1X, HS_Div4Clk_int, HS_Clock_Buf, HS_ClockDly : std_logic;
signal divclk_dbg : std_logic;
begin
dbg_cBUFR_Rst <= cBUFR_Rst;
dbg_cMMCM_Rst <= cMMCM_Rst;
dbg_cMMCM_RstTout <= cMMCM_RstTout;
dbg_cMMCM_Locked <= cMMCM_Locked;
cExtRst <= cRst;
-- Time delay counter running on CtlClk, because it has a known, fixed frequency
-- We use it to keep track of timing parameters in time units rather than UIs.
DelayCounter: process(CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cDelayCntEn = '0') then
cDelayCnt <= 0;
else
cDelayCnt <= cDelayCnt + 1;
end if;
end if;
end process DelayCounter;
cMMCM_RstTout <= '1' when cDelayCnt = kTMMCM_Rst else '0';
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "FIXED", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => kDelayTaps,
REFCLK_FREQUENCY => kRefClkFreqInMHz,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "CLOCK") -- CLOCK, DATA
port map (
DATAOUT => HS_ClockDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => CtlClk, -- Not used in FIXED mode
CE => '0', -- Not used in FIXED mode
INC => '0', -- Not used in FIXED mode
IDATAIN => HS_Clock, -- Driven by IOB
LD => '0', -- Not used in FIXED mode
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", -- Not used in FIXED mode
CNTVALUEOUT => open, -- Not used in FIXED mode
CINVCTRL => '0' -- Not used in FIXED mode
);
--Complex use case, with MMCM
GenMMCM: if kGenerateMMCM generate
SerClockGen: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 15.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 15.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.666, --60MHz for now
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => ClkFbOut,
CLKFBOUTB => open,
CLKOUT0 => HS_Clock_1X,
CLKOUT0B => open,
CLKOUT1 => open,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => ClkFbIn,
CLKIN1 => HS_ClockDly,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => aMMCM_Locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => cMMCM_Rst);
-- To make sure the MMCM output is phase-aligned to its input, we need to replicate the buffers from clock output
-- in the feedback loop. Since we use a BUFIO/BUFR pair at the MMCM output, we add a BUFR to the feedback loop
FeedbackBuffer: BUFR
generic map (
BUFR_DIVIDE => "1", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => ClkFbIn, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => cMMCM_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => ClkFbOut -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
-- Synchronize MMCM Locked into the CtlClk domain
MMCM_LockSync: entity work.SyncAsync
port map (
aReset => '0',
aIn => aMMCM_Locked,
OutClk => CtlClk,
oOut => cMMCM_Locked);
-- Edge detector for MMCM Locked flag;
MMCM_LockedDetect: process(CtlClk)
begin
if Rising_Edge(CtlClk) then
cMMCM_Locked_q <= cMMCM_Locked & cMMCM_Locked_q(1);
cMMCM_LockedFalling <= cMMCM_Locked_q(1) and not cMMCM_Locked;
cMMCM_LockedRising <= not cMMCM_Locked_q(1) and cMMCM_Locked;
end if;
end process MMCM_LockedDetect;
-- Generate MMCM reset on external reset or lock lost event
MMCM_Reset: process(cExtRst, CtlClk)
begin
if (cExtRst = '1') then
cMMCM_Rst <= '1';
cDelayCntEn <= '1';
elsif Rising_Edge(CtlClk) then
if (cMMCM_LockedFalling = '1') then
cMMCM_Rst <= '1';
cDelayCntEn <= '1';
elsif cMMCM_RstTout = '1' then --count down to minimum reset pulse width
cMMCM_Rst <= '0';
cDelayCntEn <= '0';
end if;
end if;
end process MMCM_Reset;
cBUFR_Rst <= not cMMCM_Locked;
HS_Clock_Buf <= HS_Clock_1X;
end generate GenMMCM;
GenNoMMCM: if not kGenerateMMCM generate
--Simple use case, no PLL, just BUFIO and BUFR
HS_Clock_Buf <= HS_ClockDly;
cBUFR_Rst <= cExtRst when Rising_Edge(CtlClk); --make external reset glitch free
cDelayCntEn <= '0';
cMMCM_Rst <= '0';
cMMCM_Locked <= '1';
end generate GenNoMMCM;
--Fast serial clock
SerialClkBuffer: BUFIO
port map (
O => HS_SerClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => HS_Clock_Buf -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
-- 1x slow parallel clock
DivClkBuffer: BUFR
generic map (
BUFR_DIVIDE => "4", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => HS_Div4Clk_int, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => cBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => HS_Clock_Buf -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
SyncAsyncLocked: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => cBUFR_Rst,
aIn => '1',
OutClk => HS_Div4Clk_int,
oOut => dDiv4ClkActive);
HS_Div4Clk <= HS_Div4Clk_int;
aLocked <= dDiv4ClkActive;
end Behavioral;
|
mit
|
224fdaa8fcdbf17d18c37607bc20fef6
| 0.580185 | 3.992885 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/ControladorSegmentos_tb.vhd
| 2 | 2,010 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ControladorSegmentos_tb IS
END ControladorSegmentos_tb;
ARCHITECTURE behavior OF ControladorSegmentos_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ControladorSegmentos
PORT(
code : IN std_logic_vector(15 downto 0);
clk : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal code : std_logic_vector(15 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal selector : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ms;
constant code_1234_BCD : std_logic_vector (15 downto 0):= "0001001000110100";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ControladorSegmentos PORT MAP (
code => code,
clk => clk,
led => led,
selector => selector
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
code<=code_1234_BCD;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
071c85efde9506a405173cf9c633b60d
| 0.563682 | 4.486607 | false | false | false | false |
SLongofono/digital-design-final-project
|
button.vhd
| 1 | 1,772 |
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 04/20/2017 05:59:28 PM
-- Description: Debouncing Circuit For Buttons
-- Based on starter code by Scott Larson of DigiKey
-- Retrieved 4/25/16
-- https://eewiki.net/pages/viewpage.action?pageId=4980758#DebounceLogicCircuit(withVHDLexample)-ExampleVHDLCode
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity button is
generic(counter_size : INTEGER := 20); -- debounce time control
port(
clk : in std_logic; -- system clock, assumed 100 MHz
rst : in std_logic; -- system reset
hw_in : in std_logic; -- input from physical button
button_assert : out std_logic);--debounced signal
end button;
architecture behav of button is
signal buf1, buf2 : std_logic; -- input buffer digits
signal reset_counter : std_logic; -- toggle reset_counter
signal counter : std_logic_vector(counter_size downto 0);-- := (OTHERS => '0'); --counter output
begin
reset_counter <= buf1 xor buf2; -- on change, reset_counter is high
process(clk)
begin
if('1' = rst) then
counter <= (others => '0');
elsif(rising_edge(clk)) then
buf1 <= hw_in;
buf2 <= buf1;
if(reset_counter = '1') then --input changed, start timer
counter <= (others => '0');
elsif(counter(counter_size) = '1') then -- debounced, output last matched signal
button_assert <= buf2;
else
counter <= counter + 1; -- not debounced yet, keep waiting
end if;
end if;
end process;
end behav;
|
mit
|
15561b64d5ec52c5fe96e0ed9fa9d3fb
| 0.569413 | 3.973094 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_strehbi.vhd
| 1 | 2,147 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_strehbi_DSP48_5 is
port (
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(22 - 1 downto 0);
in2: in std_logic_vector(30 - 1 downto 0);
dout: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of hls_contrast_strehbi_DSP48_5 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(signed(in1), 25));
b <= signed(resize(signed(in0), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 32));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_strehbi is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_strehbi is
component hls_contrast_strehbi_DSP48_5 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_strehbi_DSP48_5_U : component hls_contrast_strehbi_DSP48_5
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
8bdfa68927974da5054dd0e991920ca3
| 0.569632 | 3.354688 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
ID_EXE_Register.vhd
| 1 | 2,247 |
-------------------------------------------------------------------------------
--
-- Title : ID_EXE_Register
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\ID_EXE_Register.vhd
-- Generated : Wed Dec 7 15:21:24 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ID_EXE_Register} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ID_EXE_Register is
port (
rs1_in, rs2_in : in std_logic_vector(63 downto 0);
op_code_in : in std_logic_vector(3 downto 0);
rd_address_in : in std_logic_vector(3 downto 0);
rs1_out, rs2_out : out std_logic_vector(63 downto 0);
op_code_out : out std_logic_vector(3 downto 0);
rd_address_out : out std_logic_vector(3 downto 0);
clk : in std_logic
);
end ID_EXE_Register;
architecture behavioral of ID_EXE_Register is
begin
process (clk)
variable rs1_in_reg, rs2_in_reg : std_logic_vector(63 downto 0);
variable op_code_in_reg : std_logic_vector(3 downto 0) := "0000";
variable rd_address_in_reg : std_logic_vector(3 downto 0);
variable rs1_out_reg, rs2_out_reg : std_logic_vector(63 downto 0);
variable op_code_out_reg : std_logic_vector(3 downto 0) := "0000";
variable rd_address_out_reg : std_logic_vector(3 downto 0);
begin
if rising_edge(clk) then
rs1_out_reg := rs1_in_reg;
rs2_out_reg := rs2_in_reg;
op_code_out_reg := op_code_in_reg;
rd_address_out_reg := rd_address_in_reg;
rs1_in_reg := rs1_in;
rs2_in_reg := rs2_in;
op_code_in_reg := op_code_in;
rd_address_in_reg := rd_address_in;
end if;
rs1_out <= rs1_out_reg;
rs2_out <= rs2_out_reg;
op_code_out <= op_code_out_reg;
rd_address_out <= rd_address_out_reg;
end process;
end behavioral;
|
apache-2.0
|
8da9ba9d448d570d9d28085f76cbd747
| 0.542946 | 3.09931 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/start_for_Resize_U0.vhd
| 1 | 4,642 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Resize_U0_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Resize_U0_shiftReg;
architecture rtl of start_for_Resize_U0_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity start_for_Resize_U0 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Resize_U0 is
component start_for_Resize_U0_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
if (mOutPtr = conv_std_logic_vector(0, 3)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Resize_U0_shiftReg : start_for_Resize_U0_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
797c73b3e61950ebd9614db94cd1bf7d
| 0.537484 | 3.474551 | false | false | false | false |
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/ctrclk.vhd
| 1 | 3,838 |
-- megafunction wizard: %LPM_DECODE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_DECODE
-- ============================================================
-- File Name: ctrclk.vhd
-- Megafunction Name(s):
-- LPM_DECODE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY ctrclk IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
eq0 : OUT STD_LOGIC
);
END ctrclk;
ARCHITECTURE SYN OF ctrclk IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_decode
GENERIC (
lpm_decodes : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
eq : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
eq0 <= sub_wire1;
LPM_DECODE_component : LPM_DECODE
GENERIC MAP (
lpm_decodes => 4,
lpm_type => "LPM_DECODE",
lpm_width => 2
)
PORT MAP (
data => data,
eq => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BaseDec NUMERIC "1"
-- Retrieval info: PRIVATE: EnableInput NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: eq0 NUMERIC "1"
-- Retrieval info: PRIVATE: eq1 NUMERIC "0"
-- Retrieval info: PRIVATE: eq2 NUMERIC "0"
-- Retrieval info: PRIVATE: eq3 NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DECODES NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DECODE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: @eq 0 0 4 0 OUTPUT NODEFVAL "@eq[3..0]"
-- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]"
-- Retrieval info: USED_PORT: eq0 0 0 0 0 OUTPUT NODEFVAL "eq0"
-- Retrieval info: CONNECT: @data 0 0 2 0 data 0 0 2 0
-- Retrieval info: CONNECT: eq0 0 0 0 0 @eq 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ctrclk.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ctrclk.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ctrclk.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ctrclk.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ctrclk_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
9bd5ab49f1ca3ef8356fa78c1a60f5db
| 0.640959 | 3.711799 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/conversor_bin_to_bcd_grande.vhd
| 2 | 2,940 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity bcd_g is
Port (
entrada_int: in std_logic_vector (31 downto 0);
decenas_millones : out std_logic_vector (3 downto 0);
millones : out std_logic_vector (3 downto 0);
centenas_mill : out std_logic_vector (3 downto 0);
decenas_mill : out std_logic_vector (3 downto 0);
millares : out std_logic_vector (3 downto 0);
centenas : out std_logic_vector (3 downto 0);
decenas : out std_logic_vector (3 downto 0);
unidades : out std_logic_vector (3 downto 0)
);
end bcd_g;
architecture Behavioral of bcd_g is
begin
bin_to_bcd : process (entrada_int)
variable shift : STD_LOGIC_VECTOR(71 downto 0);
begin
shift := (others => '0');
shift(34 downto 3) := entrada_int;
for i in 0 to 28 loop
if shift(35 downto 32) > 4 then
shift(35 downto 32) := shift(35 downto 32) + 3;
end if;
if shift(39 downto 36) > 4 then
shift(39 downto 36) := shift(39 downto 36) + 3;
end if;
if shift(43 downto 40) > 4 then
shift(43 downto 40) := shift(43 downto 40) + 3;
end if;
if shift(47 downto 44) > 4 then
shift(47 downto 44) := shift(47 downto 44) + 3;
end if;
if shift(51 downto 48) > 4 then
shift(51 downto 48) := shift(51 downto 48) + 3;
end if;
if shift(55 downto 52) > 4 then
shift(55 downto 52) := shift(55 downto 52) + 3;
end if;
if shift(59 downto 56) > 4 then
shift(59 downto 56) := shift(59 downto 56) + 3;
end if;
if shift(63 downto 60) > 4 then
shift(63 downto 60) := shift(63 downto 60) + 3;
end if;
shift(71 downto 1):=shift(70 downto 0);
end loop;
decenas_millones <= std_logic_vector(shift(63 downto 60));
millones <= std_logic_vector(shift(59 downto 56));
centenas_mill <= std_logic_vector(shift(55 downto 52));
decenas_mill <= std_logic_vector(shift(51 downto 48));
millares <= std_logic_vector(shift(47 downto 44));
centenas <= std_logic_vector(shift(43 downto 40));
decenas <= std_logic_vector(shift(39 downto 36));
unidades <= std_logic_vector(shift(35 downto 32));
end process;
end Behavioral;
|
gpl-2.0
|
a9201ba3e69f2e063bfe70ca294ed1ca
| 0.561565 | 3.833116 | false | false | false | false |
grafi-tt/Maizul
|
src/Hardware/U232CRecv.vhd
| 1 | 2,422 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232CRecv is
generic (
wTime : std_logic_vector(15 downto 0) := x"1B17");
port (
clk : in std_logic;
ok : in std_logic;
rx_pin : in std_logic;
data : out std_logic_vector (7 downto 0);
recf : out std_logic);
end U232CRecv;
architecture statemachine of U232CRecv is
signal countdown : std_logic_vector(15 downto 0);
signal buf : std_logic_vector(8 downto 0) := (others => '0');
signal state : integer range 0 to 11 := 11;
signal recf_i : std_logic;
begin
recf <= recf_i;
recf_i <= '1' when state = 0 else '0';
buf(8) <= rx_pin;
everyClock : process(clk)
begin
if rising_edge(clk) then
case state is
when 11 =>
if buf(8) = '1' then
-- read start bit at half of wTime
countdown <= "0"&wTime(15 downto 1);
state <= 10;
end if;
when 10 =>
if buf(8) = '0' then
if countdown = 0 then
countdown <= wTime;
state <= state-1;
else
countdown <= countdown-1;
end if;
else
countdown <= "0"&wTime(15 downto 1);
end if;
when 1 =>
if countdown = 0 then
if buf(8) = '1' then
state <= 0;
data <= buf(7 downto 0);
else
state <= 11;
end if;
else
countdown <= countdown-1;
end if;
when 0 =>
if ok = '1' then
state <= 11;
end if;
when others =>
if countdown = 0 then
buf(7 downto 0) <= buf(8 downto 1);
countdown <= wTime;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end statemachine;
|
bsd-2-clause
|
67c448ca3d1480c87a342dcab9a21eea
| 0.386045 | 4.844 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/combination.vhd
| 1 | 4,896 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:58:50 07/05/05
-- Design Name:
-- Module Name: combination - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity combination is
port( x1 : in std_logic_vector(8 downto 0);
x2 : in std_logic_vector(8 downto 0);
x3 : in std_logic_vector(8 downto 0);
-- x4_1 : in std_logic_vector(8 downto 0);
-- x5_1 : in std_logic_vector(8 downto 0);
Output : out std_logic_vector(10 downto 0));
end combination;
architecture Behavioral of combination is
component Do_2
port( Data_in : in std_logic_vector(8 downto 0);
Data_out : out std_logic_vector(8 downto 0)
);
end component;
component half_adder
port(x,y : in std_logic;
Hsum,Hcarry : out std_logic );
end component;
component CSA
port(x_1 : in std_logic_vector(8 downto 0);
x_2 : in std_logic_vector(8 downto 0);
x_3 : in std_logic_vector(8 downto 0);
Sum : out std_logic_vector(8 downto 0);
Carry : out std_logic_vector(8 downto 0)
);
end component;
component CPA
port( A , B : in std_logic_vector(7 downto 0);
-- C0 : in std_logic;
S : out std_logic_vector(7 downto 0);
C8 : out std_logic );
end component;
signal S1 : std_logic_vector( 8 downto 0);
signal C1 : std_logic_vector( 8 downto 0);
--signal S2 : std_logic_vector( 8 downto 0);
--signal C2 : std_logic_vector( 8 downto 0);
--signal S3 : std_logic_vector( 7 downto 0);
--signal C3 : std_logic_vector( 7 downto 0);
--signal C1_1 : std_logic_vector( 7 downto 0);
--signal HC_S : std_logic;
--signal HC_C : std_logic;
--signal S4 : std_logic_vector(7 downto 0);
--signal C4 : std_logic_vector(7 downto 0);
--signal S5 : std_logic_vector( 7 downto 0);
--signal C5 : std_logic_vector( 7 downto 0);
signal add : std_logic_vector(7 downto 0);
--signal C4 : std_logic_vector(8 downto 0);
--signal C5 : std_logic_vector(10 downto 0);
signal C8_1 : std_logic;
signal CF_S : std_logic;
signal CF_C : std_logic;
--signal x4_2 : std_logic_vector(8 downto 0);
--signal x5_2 : std_logic_vector(8 downto 0);
--signal x4 : std_logic_vector(8 downto 0);
--signal x5 : std_logic_vector(8 downto 0);
--signal x1 : std_logic_vector(8 downto 0);
--signal x2 : std_logic_vector(8 downto 0);
--signal x3 : std_logic_vector(8 downto 0);
signal ChenS : std_logic_vector(7 downto 0);
signal ChenC : std_logic_vector(7 downto 0);
begin
--x1 <= x1_1(8)& x1_1(8)& x1_1(7) & x1_1(6) & x1_1(5) & x1_1(4) & x1_1(3) & x1_1(2) &x1_1(1); --x1 /2
--x2 <= x2_1(8)& x2_1(8)& x2_1(7) & x2_1(6) & x2_1(5) & x2_1(4) & x2_1(3) & x2_1(2) &x2_1(1); --x2 /2
--x3 <= x3_1(8)& x3_1(8)& x3_1(8) & x3_1(7) & x3_1(6) & x3_1(5) & x3_1(4) & x3_1(3) &x3_1(2) ; --x3 /4
--x4_2 <= x4_1(8)& x4_1(8)& x4_1(8) & x4_1(8) & x4_1(7) & x4_1(6) & x4_1(5) & x4_1(4) &x4_1(3) ; --x4 /8
--x5_2 <= x5_1(8)& x5_1(8)& x5_1(8) & x5_1(8) & x5_1(7) & x5_1(6) & x5_1(5) & x5_1(4) &x5_1(3) ; --x5 /8
--T1 : Do_2 port map(x4_2,x4);
--T2 : Do_2 port map(x5_2,x5);
--x4 <= (x4_1);
--x5 <= (x5_1);
--combination : for i in 0 to 8 generate
D1: CSA port map (x1 , x2 , x3 , S1, C1);
--end generate;
ChenS <= S1(8) & S1(7) & S1(6) & S1(5) & S1(4) & S1(3) & S1(2) & S1(1);
ChenC <= C1(7) & C1(6) & C1(5) & C1(4) & C1(3) & C1(2) & C1(1) & C1(0);
--combination2 : for i in 0 to 8 generate
-- D2: CSA port map (x4 , x5 , S1 , S2 ,C2);
--end generate;
-- S3 <= S2(8) & S2(7) & S2(6) & S2(5) & S2(4) & S2(3) & S2(2) & S2(1) ;
-- C3 <= C2(7) & C2(6) & C2(5) & C2(4) & C2(3) & C2(2) & C2(1) & C2(0) ;
-- C1_1 <= C1(7) & C1(6) & C1(5) & C1(4) & C1(3) & C1(2) & C1(1) & C1(0) ;
--combination3 : for i in 0 to 8 generate
-- D3 : CSA2 port map (S3 , C3 , C1_1 , S4, C4) ;
-- D5 : half_adder port map(C2(8) ,C1(8) ,HC_S,HC_C);
--end generate;
-- S5 <= HC_S & S4(7) & S4(6) & S4(5) & S4(4) & S4(3) & S4(2) & S4(1) ;
-- C5 <= C4(7) & C4(6) & C4(5) & C4(4) & C4(3) & C4(2) & C4(1) & C4(0);
D4: CPA port map (ChenS,ChenC,add,C8_1);
-- add <= signed(S5(8)&S5) + signed(C3);
D6 : half_adder port map(C8_1 , C1(8) , CF_S,CF_C ) ;
-- Output <= add(6)&add(5)&add(4)&add(3)&add(2)&add(1)&add(0) & S4(0) & S2(0); -- CF_C& CF_S &
Output <= CF_C & CF_S & add & S1(0);
end Behavioral;
|
mit
|
cc9f6e24430e8a40107c1ab38fc097ad
| 0.542688 | 2.233577 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/ConversorBinBCD.vhd
| 2 | 1,643 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bcd is
Port (
entrada_int: in integer range 0 to 65536;
millares : out std_logic_vector (3 downto 0);
centenas : out std_logic_vector (3 downto 0);
decenas : out std_logic_vector (3 downto 0);
unidades : out std_logic_vector (3 downto 0)
);
end bcd;
architecture Behavioral of bcd is
signal entrada_bin: std_logic_vector(15 downto 0);
begin
entrada_bin<=std_logic_vector(to_unsigned(entrada_int,entrada_bin'length));
bin_to_bcd : process (entrada_bin)
variable shift : unsigned(31 downto 0);
alias num is shift(15 downto 0);
alias unidad is shift(19 downto 16);
alias decena is shift(23 downto 20);
alias centena is shift(27 downto 24);
alias millar is shift(31 downto 28);
begin
num := unsigned(entrada_bin);
unidad := "0000";
decena := "0000";
centena := "0000";
millar := "0000";
for i in 1 to num'Length loop
if unidad >= 5 then
unidad := unidad + 3;
end if;
if decena >= 5 then
decena := decena + 3;
end if;
if centena >= 5 then
centena := centena + 3;
end if;
if millar >= 5 then
millar := millar + 3;
end if;
shift := shift_left(shift, 1);
end loop;
millares <= std_logic_vector(millar);
centenas <= std_logic_vector(centena);
decenas <= std_logic_vector(decena);
unidades <= std_logic_vector(unidad);
end process;
end Behavioral;
|
gpl-2.0
|
b2eebc5f69309dc664707353cb76053c
| 0.572124 | 3.768349 | false | false | false | false |
pollow/Multi_Cycle_CPU
|
ipcore_dir/Mem_B/example_design/Mem_B_prod.vhd
| 1 | 10,331 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: Mem_B_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : Mem_B.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Mem_B_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END Mem_B_prod;
ARCHITECTURE xilinx OF Mem_B_prod IS
COMPONENT Mem_B_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : Mem_B_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
8fbff28a5f2188dcb98520212ceebbd3
| 0.479237 | 3.810771 | false | false | false | false |
igormacedo/vhdlstudy
|
genericmux.vhd
| 1 | 1,976 |
--autor: igor macedo silva
--description: generic multiplexer for a generic number of inputs and generic bus size.
library ieee;
use ieee.std_logic_1164.all;
--creation of specifc package for array input
package barramento is
--constant insize: integer := 4;
--constant bussize: integer := 4;
--type int_matrix is array (integer range <>) of std_logic_vector(integer range <>);
type logic_matrix is array (natural range <>, natural range <>) of std_logic;
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.barramento.all;
entity muxt is
generic(
insize: integer := 2;
bussize: integer := 4
);
port(
--i0, i1, i2, i3 : in bit;4
--type int_array is array ((insize-1) to 0) of bit_vector((bussize-1) downto 0);
bar : in logic_matrix(0 to (insize-1),0 to (bussize-1));
s : out std_logic_vector(0 to (bussize-1));
c : in integer range 0 to insize-1
);
end entity;
architecture estrutura of muxt is
begin
process(c)
begin
for i in 0 to (bussize-1) loop
s(i) <= bar(c,i);
end loop;
end process;
end architecture;
--=========================================================================
--autor: igor macedo silva
--description: generic multiplexer for a generic number of inputs and generic bus size.
--creation of specifc package for array input
-- package barramento is
-- constant insize: integer := 4;
-- constant bussize: integer := 4;
-- type int_array is array (integer range <>) of bit_vector(integer range <>);
-- end package;
--
-- use work.barramento.all;
--
-- entity muxt is
-- --generic(insize: integer := 4);
-- --generic(bussize: integer := 4);
-- port(
-- --i0, i1, i2, i3 : in bit;
-- --type int_array is array ((insize-1) to 0) of bit_vector((bussize-1) downto 0);
-- bar : in int_array;
-- s : out bit_vector((bussize-1) downto 0);
-- c : in integer range insize-1 downto 0
-- );
-- end entity;
--
-- architecture estrutura of muxt is
-- begin
-- s <= bar(c);
-- end architecture;
|
mit
|
d6a09953d12112b5b7f31cf62dd36214
| 0.6417 | 2.975904 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_kbM.vhd
| 1 | 6,685 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_kbM_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_kbM_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000010", 2 => "00000100", 3 => "00000101",
4 => "00000111", 5 => "00001001", 6 => "00001011", 7 => "00001100",
8 => "00001110", 9 => "00010000", 10 => "00010010", 11 => "00010011",
12 => "00010101", 13 => "00010111", 14 => "00011001", 15 => "00011010",
16 => "00011100", 17 => "00011110", 18 => "00011111", 19 => "00100001",
20 => "00100011", 21 => "00100100", 22 => "00100110", 23 => "00101000",
24 => "00101001", 25 => "00101011", 26 => "00101101", 27 => "00101110",
28 => "00110000", 29 => "00110010", 30 => "00110011", 31 => "00110101",
32 => "00110110", 33 => "00111000", 34 => "00111010", 35 => "00111011",
36 => "00111101", 37 => "00111110", 38 => "01000000", 39 => "01000001",
40 => "01000011", 41 => "01000101", 42 => "01000110", 43 => "01001000",
44 => "01001001", 45 => "01001011", 46 => "01001100", 47 => "01001110",
48 => "01001111", 49 => "01010001", 50 => "01010010", 51 => "01010100",
52 => "01010101", 53 => "01010111", 54 => "01011000", 55 => "01011010",
56 => "01011011", 57 => "01011100", 58 => "01011110", 59 => "01011111",
60 => "01100001", 61 => "01100010", 62 => "01100100", 63 => "01100101",
64 => "01100110", 65 => "01101000", 66 => "01101001", 67 => "01101011",
68 => "01101100", 69 => "01101101", 70 => "01101111", 71 => "01110000",
72 => "01110001", 73 => "01110011", 74 => "01110100", 75 => "01110101",
76 => "01110111", 77 => "01111000", 78 => "01111001", 79 => "01111011",
80 => "01111100", 81 => "01111101", 82 => "01111111", 83 => "10000000",
84 => "10000001", 85 => "10000010", 86 => "10000100", 87 => "10000101",
88 => "10000110", 89 => "10000111", 90 => "10001001", 91 => "10001010",
92 => "10001011", 93 => "10001100", 94 => "10001101", 95 => "10001111",
96 => "10010000", 97 => "10010001", 98 => "10010010", 99 => "10010011",
100 => "10010101", 101 => "10010110", 102 => "10010111", 103 => "10011000",
104 => "10011001", 105 => "10011010", 106 => "10011100", 107 => "10011101",
108 => "10011110", 109 => "10011111", 110 => "10100000", 111 => "10100001",
112 => "10100010", 113 => "10100011", 114 => "10100100", 115 => "10100110",
116 => "10100111", 117 => "10101000", 118 => "10101001", 119 => "10101010",
120 => "10101011", 121 => "10101100", 122 => "10101101", 123 => "10101110",
124 => "10101111", 125 => "10110000", 126 => "10110001", 127 => "10110010",
128 => "10110011", 129 => "10110100", 130 => "10110101", 131 => "10110110",
132 => "10110111", 133 => "10111000", 134 => "10111001", 135 => "10111010",
136 => "10111011", 137 => "10111100", 138 => "10111101", 139 => "10111110",
140 to 141=> "10111111", 142 => "11000000", 143 => "11000001", 144 => "11000010",
145 => "11000011", 146 => "11000100", 147 => "11000101", 148 => "11000110",
149 to 150=> "11000111", 151 => "11001000", 152 => "11001001", 153 => "11001010",
154 => "11001011", 155 to 156=> "11001100", 157 => "11001101", 158 => "11001110",
159 => "11001111", 160 to 161=> "11010000", 162 => "11010001", 163 => "11010010",
164 => "11010011", 165 to 166=> "11010100", 167 => "11010101", 168 => "11010110",
169 to 170=> "11010111", 171 => "11011000", 172 => "11011001", 173 to 174=> "11011010",
175 => "11011011", 176 to 177=> "11011100", 178 => "11011101", 179 to 180=> "11011110",
181 => "11011111", 182 to 183=> "11100000", 184 => "11100001", 185 to 186=> "11100010",
187 => "11100011", 188 to 189=> "11100100", 190 to 191=> "11100101", 192 => "11100110",
193 to 194=> "11100111", 195 to 196=> "11101000", 197 to 198=> "11101001", 199 => "11101010",
200 to 201=> "11101011", 202 to 203=> "11101100", 204 to 205=> "11101101", 206 to 207=> "11101110",
208 to 209=> "11101111", 210 to 211=> "11110000", 212 to 213=> "11110001", 214 to 216=> "11110010",
217 to 218=> "11110011", 219 to 220=> "11110100", 221 to 223=> "11110101", 224 to 225=> "11110110",
226 to 228=> "11110111", 229 to 231=> "11111000", 232 to 234=> "11111001", 235 to 237=> "11111010",
238 to 240=> "11111011", 241 to 244=> "11111100", 245 to 248=> "11111101", 249 to 252=> "11111110",
253 to 255=> "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_kbM is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_kbM is
component Loop_loop_height_kbM_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_kbM_rom_U : component Loop_loop_height_kbM_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
d7736fbecbd3a04eee267e59bafd65ec
| 0.544652 | 3.649017 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
sixteenbit_module.vhd
| 1 | 2,690 |
-------------------------------------------------------------------------------
--
-- Title : sixteenbit_module
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\sixteenbit_module.vhd
-- Generated : Thu Nov 17 12:32:08 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {sixteenbit_module} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sixteenbit_module is
port(
c0: in std_logic;
a: in std_logic_vector (15 downto 0);
b: in std_logic_vector (15 downto 0);
s: out std_logic_vector (15 downto 0);
Carry: out std_logic;
P64bit: out std_logic;
G64bit: out std_logic
);
end sixteenbit_module;
--}} End of automatically maintained section
architecture structural of sixteenbit_module is
signal P, G: std_logic_vector (3 downto 0);
Signal C: std_logic_vector (3 downto 1);
begin
fourcla1: entity fourbit_submodule port map(a(0) => a(0), a(1) => a(1), a(2) => a(2), a(3) => a(3), b(0) => b(0), b(1) => b(1), b(2) => b(2), b(3) => b(3), s(0) =>s(0), s(1) => s(1), s(2) => s(2), s(3) => s(3), Pi =>P(0), Gi => G(0), c0 => c0);
fourcla2: entity fourbit_submodule port map(a(0) => a(4), a(1) => a(5), a(2) => a(6), a(3) => a(7), b(0) => b(4), b(1) => b(5), b(2) => b(6), b(3) => b(7), s(0) =>s(4), s(1) => s(5), s(2) => s(6), s(3) => s(7), Pi =>P(1), Gi => G(1), c0 => C(1));
fourcla3: entity fourbit_submodule port map(a(0) => a(8), a(1) => a(9), a(2) => a(10), a(3) => a(11), b(0) => b(8), b(1) => b(9), b(2) => b(10), b(3) => b(11), s(0) =>s(8), s(1) => s(9), s(2) => s(10), s(3) => s(11), Pi =>P(2), Gi => G(2), c0 => C(2));
fourcla4: entity fourbit_submodule port map(a(0) => a(12), a(1) => a(13), a(2) => a(14), a(3) => a(15), b(0) => b(12), b(1) => b(13), b(2) => b(14), b(3) => b(15), s(0) =>s(12), s(1) => s(13), s(2) => s(14), s(3) => s(15), Pi =>P(3), Gi => G(3), c0 => C(3));
secondlevel: entity second_level_CLA port map(c0 => c0, Pi(0) => P(0), Pi(1) => P(1), Pi(2) => P(2), Pi(3) => P(3), Gi(0) => G(0), Gi(1) => G(1), Gi(2) => G(2), Gi(3) => G(3), Ci(1) => C(1), Ci(2) => C(2), Ci(3) => C(3), Ci(4) => Carry, P64bit => P64bit, G64bit => G64bit);
end structural;
|
apache-2.0
|
e219926655ca9c61afc08cc0a57b6087
| 0.455762 | 2.569245 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/ConfigADC.vhd
| 1 | 21,293 |
-------------------------------------------------------------------------------
--
-- File: ConfigADC.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module writes an intial configuration into the ADC registers and then
-- manages the optional SPI Indirect Access Port.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDigitizer.all;
entity ConfigADC is
Generic (
-- Parameter identifying the Zmod:
-- 6 -> Zmod Digitizer 1430 - 125 (AD9648)
kZmodID : integer range 6 to 6 := 6;
-- ADC Clock divider ratio (Register 0x0B of AD96xx and AD92xx).
kADC_ClkDiv : integer range 1 to 8 := 1;
--The number of data bits for the data phase of the SPI transaction:
--only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
--The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 16 to 16 := 16;
kSimulation : boolean := false
);
Port (
-- 100MHZ clock input.
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain).
asRst_n : in STD_LOGIC;
-- ADC initialization complete signaling
sInitDoneADC : out STD_LOGIC := '0';
-- ADC initialization error signaling
sConfigError : out STD_LOGIC;
-- ADC initialization enable signal
--Configuration of the ADC over SPI should be done after sConfigADCEnable is asserted which only happens after the CDCE clock generator is configured
--and the PLL inside the CDCE is locked, otherwise the ADC should be kept in reset
sConfigADCEnable : in STD_LOGIC;
--AD9648 SPI interface signals
sADC_Sclk : out STD_LOGIC;
sADC_SDIO : inout STD_LOGIC;
sADC_CS : out STD_LOGIC := '1';
-- SPI Indirect access port; it provides the means to indirectly access
-- the ADC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
sCmdTxAxisTvalid: IN STD_LOGIC;
sCmdTxAxisTready: OUT STD_LOGIC;
sCmdTxAxisTdata: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
sCmdRxAxisTvalid: OUT STD_LOGIC;
sCmdRxAxisTready: IN STD_LOGIC;
sCmdRxAxisTdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end ConfigADC;
architecture Behavioral of ConfigADC is
signal sCurrentState : FsmStatesADC_t := StStart;
signal sNextState : FsmStatesADC_t;
-- signals used for debug purposes
-- signal fsmcfg_state, fsmcfg_state_r : std_logic_vector(5 downto 0);
--External Command FIFO Interface
signal sLdCmdTxData: std_logic;
signal sCmdTxDataReg: std_logic_vector(23 downto 0);
signal sCmdTxAxisTreadyLoc: std_logic;
signal sCmdRxAxisTvalidLoc: std_logic;
signal sCmdRxAxisTdataLoc : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sCmdCnt : unsigned(4 downto 0);
signal sCmdCntInt : integer range 0 to 31;
signal sIncCmdCnt, sRstCmdCnt : std_logic;
--Initialization complete and configuration error flags
signal sInitDoneADC_Fsm : std_logic := '0';
signal sConfigErrorFsm : std_logic;
--Timers
signal sCfgTimer : unsigned (kCountResetResume'range);
signal sCfgTimerRst_n : std_logic;
--SPI Interface
signal sADC_SPI_RdData : std_logic_vector(kDataWidth-1 downto 0);
signal sADC_SPI_Done : std_logic;
signal sADC_SPI_WrData, sADC_SPI_WrDataR : std_logic_vector(kDataWidth-1 downto 0);
signal sADC_SPI_Addr, sADC_SPI_AddrR : std_logic_vector(kCommandWidth - 4 downto 0);
signal sADC_SPI_Width, sADC_SPI_WidthR : std_logic_vector(1 downto 0);
signal sADC_SPI_RdWr, sADC_SPI_RdWrR : std_logic;
signal sADC_SPI_Busy : std_logic;
signal sADC_ApStart, sADC_ApStartR : std_logic;
signal sCountResetResumeVal : unsigned(kCountResetResume'range);
constant kCmdTotal : integer := SelCmdWrListLength(kZmodID);
constant kADC_SPI_CmdDef : ADC_SPI_Commands_t := SelCmdList(kZmodID);
constant kADC_SPI_RdbckDef : ADC_SPI_Readback_t := SelRdbkList(kZmodID);
constant kADC_SPI_Cmd : ADC_SPI_Commands_t := OverwriteClkDiv(kADC_SPI_CmdDef, kADC_ClkDiv);
constant kADC_SPI_Rdbck : ADC_SPI_Readback_t := OverWriteID_ClkDiv(kZmodID, kADC_SPI_RdbckDef, kADC_ClkDiv);
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of sCurrentState, sNextState : signal is "TRUE";
begin
sCountResetResumeVal <= kCountResetResumeSim when kSimulation else
kCountResetResume;
-- Instantiate the SPI controller.
ADC_SPI_inst: entity work.ADI_SPI
Generic Map(
kSysClkDiv => kSPI_SysClkDiv,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sSPI_Clk => sADC_Sclk,
sSDIO => sADC_SDIO,
sCS => sADC_CS,
sApStart => sADC_ApStartR,
sRdData => sADC_SPI_RdData,
sWrData => sADC_SPI_WrDataR,
sAddr => sADC_SPI_AddrR,
sWidth => sADC_SPI_WidthR, --tested only for width = "00"
sRdWr => sADC_SPI_RdWrR,
sDone => sADC_SPI_Done,
sBusy => sADC_SPI_Busy
);
-- Register the SPI controller inputs.
ProcSPI_ControllerRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sADC_SPI_RdWrR <= '0';
sADC_SPI_WrDataR <= (others => '0');
sADC_SPI_AddrR <= (others => '0');
sADC_SPI_WidthR <= (others => '0');
sADC_ApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sADC_SPI_RdWrR <= sADC_SPI_RdWr;
sADC_SPI_WrDataR <= sADC_SPI_WrData;
sADC_SPI_AddrR <= sADC_SPI_Addr;
sADC_SPI_WidthR <= sADC_SPI_Width;
sADC_ApStartR <= sADC_ApStart;
end if;
end process;
sCmdCntInt <= to_integer(sCmdCnt);
-- Register the SPI Indirect Access Port receive interface outputs.
ProcRxExtFIFO_Reg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdRxAxisTvalid <= '0';
sCmdRxAxisTdata <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCmdRxAxisTvalid <= sCmdRxAxisTvalidLoc;
sCmdRxAxisTdata <= x"000000" & sCmdRxAxisTdataLoc;
end if;
end process;
-- Register the SPI Indirect Access Port transmit interface outputs.
ProcCmdAxisTreadyReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxAxisTready <= '0';
elsif (rising_edge(SysClk100)) then
sCmdTxAxisTready <= sCmdTxAxisTreadyLoc;
end if;
end process;
-- Register the next SPI Indirect Access Port command on the transmit
-- interface when the configuration state machine is capable of processing it.
ProcLdCmdTxData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxDataReg <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sLdCmdTxData = '1') then
sCmdTxDataReg <= sCmdTxAxisTdata(23 downto 0);
end if;
end if;
end process;
-- Timer used to determine timeout conditions for SPI transfers.
-- When a command is sent to the ADC a certain amount of time is allowed for the state
-- machine to read back the expected value in order to make sure the register was correctly
-- configured. Some commands do not take effect immediately, so this mechanism is necessary
-- (SPI Port Config register (address 0x00) soft reset write for example).
ProcCfgTimer: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCfgTimer <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sCfgTimerRst_n = '0') then
sCfgTimer <= (others =>'0');
else
sCfgTimer <= sCfgTimer + 1;
end if;
end if;
end process;
-- Counter used to track the number of successfully sent commands.
ProcCmdCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdCnt <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sRstCmdCnt = '0') then
sCmdCnt <= (others => '0');
elsif (sIncCmdCnt = '1') then
sCmdCnt <= sCmdCnt + 1;
end if;
end if;
end process;
-- Register FSM output flags.
ProcInitDoneReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sInitDoneADC <= '0';
sConfigError <= '0';
elsif (rising_edge(SysClk100)) then
sInitDoneADC <= sInitDoneADC_Fsm;
sConfigError <= sConfigErrorFsm;
end if;
end process;
------------------------------------------------------------------------------------------
-- ADC Configuration state machine
------------------------------------------------------------------------------------------
-- State machine synchronous process.
ProcSyncFsm: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCurrentState <= StStart;
--fsmcfg_state_r <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCurrentState <= sNextState;
--fsmcfg_state_r <= fsmcfg_state;
end if;
end process;
-- Next state and output decode.
ProcNextStateAndOutputDecode: process (sCurrentState, sADC_SPI_RdData, sADC_SPI_Done, sADC_SPI_Busy,
sCmdTxAxisTvalid, sCmdTxAxisTdata, sCmdTxDataReg, sCmdRxAxisTready, sCmdCntInt, sCfgTimer, sConfigADCEnable,
sCountResetResumeVal)
begin
sNextState <= sCurrentState;
--fsmcfg_state <= "000000";
sADC_ApStart <= '0';
sADC_SPI_WrData <= (others => '0');
sADC_SPI_Addr <= (others => '0');
sADC_SPI_Width <= (others => '0');
sADC_SPI_RdWr <= '0';
sRstCmdCnt <= '0';
sIncCmdCnt <= '0';
sLdCmdTxData <= '0';
sCfgTimerRst_n <= '0';
sInitDoneADC_Fsm <= '0';
sConfigErrorFsm <= '0';
sCmdTxAxisTreadyLoc <= '0';
sCmdRxAxisTvalidLoc <= '0';
sCmdRxAxisTdataLoc <= (others => '0');
case (sCurrentState) is
when StStart =>
--fsmcfg_state <= "000000";
if (sConfigADCEnable = '1') then
sNextState <= StWriteControlReg;
end if;
-- Perform a register write operation for the sCmdCntInt'th command in the queue.
-- For some sCmdCntInt only register reads are required.
when StWriteControlReg =>
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
--fsmcfg_state <= "000001";
if (kADC_SPI_Cmd(sCmdCntInt)(20 downto 8) = kChipID) then --Read ID skips register write
sNextState <= StReadControlReg;
elsif (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_WrData <= kADC_SPI_Cmd(sCmdCntInt)(7 downto 0);
sADC_SPI_Addr <= kADC_SPI_Cmd(sCmdCntInt)(20 downto 8);
sADC_SPI_Width <= kADC_SPI_Cmd(sCmdCntInt)(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneWriteReg;
end if;
-- Wait for register write command to be completed
when StWaitDoneWriteReg =>
--fsmcfg_state <= "000010";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- AD92xx devices require a Transfer register write operation
-- for the previous register write to take effect.
if ((kZmodID = kZmodDigitizer1030_40) or (kZmodID = kZmodDigitizer1230_40) or (kZmodID = kZmodDigitizer1430_40)) then
sNextState <= StReadTrsfReg;
else
sNextState <= StReadControlReg;
end if;
end if;
-- Read Transfer register and check if it is cleared.
when StReadTrsfReg =>
--fsmcfg_state <= "101110";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_Addr <= kSetTrsfReg(20 downto 8);
sADC_SPI_Width <= kSetTrsfReg(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneTrsfRegRd;
end if;
-- Wait for Transfer register read command to complete.
when StWaitDoneTrsfRegRd =>
--fsmcfg_state <= "101111";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- Check if the expected value has been read; A timeout limit
-- is imposed.
if (sADC_SPI_RdData = x"00") then
sNextState <= StSetTrsfReg;
elsif (sCfgTimer >= kCfgTimeout) then
sNextState <= StError;
else
sNextState <= StReadTrsfReg;
end if;
end if;
-- Set the Transfer field of the Transfer register.
when StSetTrsfReg =>
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
--fsmcfg_state <= "101010";
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_WrData <= kSetTrsfReg(7 downto 0);
sADC_SPI_Addr <= kSetTrsfReg(20 downto 8);
sADC_SPI_Width <= kSetTrsfReg(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneTrsfReg;
end if;
-- Wait for SPI command to be completed.
when StWaitDoneTrsfReg =>
--fsmcfg_state <= "101011";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
sNextState <= StReadControlReg;
end if;
-- Read back the register value configured in the StWriteControlReg state.
when StReadControlReg =>
--fsmcfg_state <= "000110";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_Addr <= kADC_SPI_Cmd(sCmdCntInt)(20 downto 8);
sADC_SPI_Width <= kADC_SPI_Cmd(sCmdCntInt)(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneReadReg;
end if;
-- Wait for SPI command to be completed and compare the read data against
-- the expected value (the kADC_SPI_Rdbck readback sequence)
when StWaitDoneReadReg =>
--fsmcfg_state <= "000111";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- Wait for bits that are set/reset by the ADC to change value
-- (Reg00 soft reset for example). Amount of time not specified by data sheet,
-- the timeout value chosen empirically.
if (sADC_SPI_RdData = kADC_SPI_Rdbck(sCmdCntInt)) then
sNextState <= StCheckCmdCnt;
elsif (sCfgTimer >= kCfgTimeout) then
sNextState <= StError;
else
sNextState <= StReadControlReg;
end if;
end if;
-- Check if the command sequence has completed.
when StCheckCmdCnt =>
--fsmcfg_state <= "000011";
sRstCmdCnt <= '1';
if (sCmdCntInt = kCmdTotal) then
sRstCmdCnt <= '0';
sNextState <= StResetTimer;
else
sIncCmdCnt <= '1';
sNextState <= StWriteControlReg;
end if;
-- Reset timeout timer.
when StResetTimer =>
--fsmcfg_state <= "001001";
sNextState <= StWaitRecover;
-- Wait to recover form power down mode.
when StWaitRecover =>
--fsmcfg_state <= "001010";
sCfgTimerRst_n <= '1';
if (sCfgTimer = sCountResetResumeVal) then
sNextState <= StInitDone;
end if;
-- Indicate that the initialization sequence has completed.
when StInitDone =>
--fsmcfg_state <= "001011";
sInitDoneADC_Fsm <= '1';
sNextState <= StIdle;
-- IDLE state; wait for changes on the SPI Indirect Access Port.
when StIdle =>
--fsmcfg_state <= "001100";
sInitDoneADC_Fsm <= '1';
if ((sCmdTxAxisTvalid = '1') and (sADC_SPI_Busy = '0')) then
sLdCmdTxData <= '1';
if (sCmdTxAxisTdata(23) = '0') then
sNextState <= StExtSPI_WrCmd;
else
sNextState <= StExtSPI_RdCmd;
end if;
end if;
-- Execute the register write command requested on the SPI Indirect Access Port.
when StExtSPI_WrCmd =>
--fsmcfg_state <= "001101";
sInitDoneADC_Fsm <= '1';
sADC_ApStart <= '1';
sADC_SPI_WrData <= sCmdTxDataReg(7 downto 0);
sADC_SPI_Addr <= sCmdTxDataReg(20 downto 8);
sADC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneExtWrReg;
-- Wait for the register write command to complete
when StWaitDoneExtWrReg =>
--fsmcfg_state <= "001110";
sInitDoneADC_Fsm <= '1';
if (sADC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StIdle;
end if;
-- Execute the register read command requested on the SPI Indirect Access Port.
when StExtSPI_RdCmd =>
--fsmcfg_state <= "001111";
sInitDoneADC_Fsm <= '1';
sADC_ApStart <= '1';
sADC_SPI_Addr <= sCmdTxDataReg(20 downto 8);
sADC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneExtRdReg;
-- Wait for the register read command to complete.
when StWaitDoneExtRdReg =>
--fsmcfg_state <= "010000";
sInitDoneADC_Fsm <= '1';
if (sADC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StRegExtRxData;
end if;
-- State used to register the incoming SPI data.
when StRegExtRxData =>
--fsmcfg_state <= "010001";
sInitDoneADC_Fsm <= '1';
sCmdRxAxisTvalidLoc <= '1';
sCmdRxAxisTdataLoc <= sADC_SPI_RdData;
if (sCmdRxAxisTready = '1') then
sNextState <= StIdle;
end if;
-- When an error condition is detected the state machine stalls in this state.
-- An external reset condition is necessary to exit this state.
when StError =>
--fsmcfg_state <= "111111";
sConfigErrorFsm <= '1';
report "ADC Configuration readback error." & LF & HT & HT
severity ERROR;
when others =>
sNextState <= StStart;
end case;
end process;
end Behavioral;
|
mit
|
29b76b8770257f2f7aff432191c5393a
| 0.581224 | 4.678752 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/start_for_Loop_lojbC.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Loop_lojbC_shiftReg;
architecture rtl of start_for_Loop_lojbC_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Loop_lojbC is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Loop_lojbC is
component start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Loop_lojbC_shiftReg : start_for_Loop_lojbC_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
8a43f36d88d1ca01977f0292bfb5f3de
| 0.53118 | 3.549407 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/fifo_w16_d1_A.vhd
| 2 | 4,433 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d1_A_shiftReg;
architecture rtl of fifo_w16_d1_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d1_A is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d1_A is
component fifo_w16_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d1_A_shiftReg : fifo_w16_d1_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
331ae535bd05d576a88fae433d022e3d
| 0.525152 | 3.460578 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
sfhs.vhd
| 1 | 2,533 |
-------------------------------------------------------------------------------
--
-- Title : sfhs
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\sfhs.vhd
-- Generated : Tue Dec 6 14:06:41 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {sfhs} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity sfhs is
port(
rs1: in std_logic_vector(63 downto 0);
rs2: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end sfhs;
--}} End of automatically maintained section
architecture behavioral of sfhs is
begin
process(rs1,rs2)
variable sum1: unsigned(16 downto 0);
variable sum2: unsigned(16 downto 0);
variable sum3: unsigned(16 downto 0);
variable sum4: unsigned(16 downto 0);
begin
sum1:=unsigned('0'&rs1(63 downto 48)) - unsigned('0'&rs2(63 downto 48));
if(unsigned('0'&rs1(63 downto 48)) < unsigned('0'&rs2(63 downto 48))) then
sum1 := to_unsigned(0,17);
end if;
sum2:=unsigned('0'&rs1(47 downto 32)) - unsigned('0'&rs2(47 downto 32));
if(unsigned('0'&rs1(47 downto 32)) < unsigned('0'&rs2(47 downto 32))) then
sum2 := to_unsigned(0,17);
end if;
sum3:=unsigned('0'&rs1(31 downto 16)) - unsigned('0'&rs2(31 downto 16));
if(unsigned('0'&rs1(31 downto 16)) < unsigned('0'&rs2(31 downto 16))) then
sum3 := to_unsigned(0,17);
end if;
sum4:=unsigned('0'&rs1(15 downto 0)) - unsigned('0'&rs2(15 downto 0));
if(unsigned('0'&rs1(15 downto 0)) < unsigned('0'&rs2(15 downto 0))) then
sum4 := to_unsigned(0,17);
end if;
rd(63 downto 48)<= std_logic_vector(sum1(15 downto 0));
rd(47 downto 32)<= std_logic_vector(sum2(15 downto 0));
rd(31 downto 16)<= std_logic_vector(sum3(15 downto 0));
rd(15 downto 0) <= std_logic_vector(sum4(15 downto 0));
end process;
end behavioral;
|
apache-2.0
|
409e725ad628396b0fa9df5712b17a9f
| 0.512041 | 3.363878 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fadd-grafi/fadd/block.vhd
| 1 | 3,131 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FractionLeftPadding is
port (
frcIn : in std_logic_vector(23 downto 0);
nlz : out std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0));
end FractionLeftPadding;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FractionRightShifter is
port (
frcIn : in std_logic_vector(23 downto 0);
len : in std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0);
fstOverOut : out std_logic;
sndOverout : out std_logic;
tailAnyout : out std_logic);
end FractionRightShifter;
architecture PaddingL24 of FractionLeftPadding is
type ufrc_step_vector is array (3 downto 0) of unsigned(23 downto 0);
signal uFrc : ufrc_step_vector;
signal uFrcIn : unsigned(23 downto 0);
signal uFrcOut : unsigned(23 downto 0);
begin
uFrcIn <= unsigned(frcIn);
nlz(4) <= '1' when uFrcIn (23 downto 8) = 0 else '0';
uFrc(3) <= uFrcIn sll 16 when uFrcIn (23 downto 8) = 0 else uFrcIn;
nlz(3) <= '1' when uFrc(3)(23 downto 12) = 0 else '0';
uFrc(2) <= uFrc(3) sll 8 when uFrc(3)(23 downto 12) = 0 else uFrc(3);
nlz(2) <= '1' when uFrc(2)(23 downto 20) = 0 else '0';
uFrc(1) <= uFrc(2) sll 4 when uFrc(2)(23 downto 20) = 0 else uFrc(2);
nlz(1) <= '1' when uFrc(1)(23 downto 22) = 0 else '0';
uFrc(0) <= uFrc(1) sll 2 when uFrc(1)(23 downto 22) = 0 else uFrc(1);
nlz(0) <= '1' when uFrc(0)(23 downto 23) = 0 else '0';
uFrcOut <= uFrc(0) sll 1 when uFrc(0)(23 downto 23) = 0 else uFrc(0);
frcOut <= std_logic_vector(uFrcOut);
end PaddingL24;
architecture BarrelShifterR24Mod of FractionRightShifter is
type ufrc_step_vector is array (3 downto 0) of unsigned(25 downto 0);
signal uFrc: ufrc_step_vector;
signal uFrcIn: unsigned(25 downto 0);
signal uFrcOut: unsigned(25 downto 0);
signal tailAny: std_logic_vector (3 downto 0);
begin
uFrcIn <= unsigned(frcIn) & "00";
tailAny(3) <= '1' when len(4) = '1' and uFrcIn(15 downto 0) /= 0 else '0';
uFrc(3) <= uFrcIn srl 16 when len(4) = '1' else uFrcIn;
tailAny(2) <= '1' when len(3) = '1' and uFrc(3)(7 downto 0) /= 0 else tailAny(3);
uFrc(2) <= uFrc(3) srl 8 when len(3) = '1' else uFrc(3);
tailAny(1) <= '1' when len(2) = '1' and uFrc(2)(3 downto 0) /= 0 else tailAny(2);
uFrc(1) <= uFrc(2) srl 4 when len(2) = '1' else uFrc(2);
tailAny(0) <= '1' when len(1) = '1' and uFrc(1)(1 downto 0) /= 0 else tailAny(1);
uFrc(0) <= uFrc(1) srl 2 when len(1) = '1' else uFrc(1);
tailAnyOut <= '1' when len(0) = '1' and uFrc(0)(0 downto 0) /= 0 else tailAny(0);
uFrcOut <= uFrc(0) srl 1 when len(0) = '1' else uFrc(0);
sndOverOut <= uFrcOut(0);
fstOverOut <= uFrcOut(1);
frcOut <= std_logic_vector(uFrcOut(25 downto 2));
end BarrelShifterR24Mod;
|
bsd-2-clause
|
20bfde62f419db121748799ff9faa8f6
| 0.595337 | 3.069608 | false | false | false | false |
olajep/oh
|
src/adi/hdl/library/common/dma_fifo.vhd
| 1 | 3,611 |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of dma_fifo is
constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1;
type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0);
signal data_fifo : MEM;
signal wr_addr : natural range 0 to FIFO_MAX;
signal rd_addr : natural range 0 to FIFO_MAX;
signal not_full, not_empty : Boolean;
begin
in_ack <= '1' when not_full else '0';
out_stb <= '1' when not_empty else '0';
out_data <= data_fifo(rd_addr);
fifo_data: process (clk) is
begin
if rising_edge(clk) then
if not_full then
data_fifo(wr_addr) <= in_data;
end if;
end if;
end process;
fifo_ctrl: process (clk) is
variable free_cnt : integer range 0 to FIFO_MAX + 1;
begin
if rising_edge(clk) then
if (resetn = '0') or (fifo_reset = '1') then
wr_addr <= 0;
rd_addr <= 0;
free_cnt := FIFO_MAX + 1;
not_empty <= False;
not_full <= True;
else
if in_stb = '1' and not_full then
wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt - 1;
end if;
if out_ack = '1' and not_empty then
rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1);
free_cnt := free_cnt + 1;
end if;
not_full <= not (free_cnt = 0);
not_empty <= not (free_cnt = FIFO_MAX + 1);
end if;
end if;
end process;
end;
|
mit
|
a2a65157b8a524e405ba6d775463f2ed
| 0.605096 | 3.343519 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd
| 2 | 13,948 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl330_dma_fifo;
use adi_common_v1_00_a.axi_ctrlif;
entity axi_i2s_adi_v1_2 is
generic (
-- Users to add parameters here
C_SLOT_WIDTH : integer := 24;
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_DMA_TYPE : integer := 0;
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- Serial Data interface
DATA_CLK_I : in std_logic;
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
MUTEN_O : out std_logic;
-- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- AXI Streaming DMA RX interface
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
--PL330 DMA TX interface
DMA_REQ_TX_ACLK : in std_logic;
DMA_REQ_TX_RSTN : in std_logic;
DMA_REQ_TX_DAVALID : in std_logic;
DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_TX_DAREADY : out std_logic;
DMA_REQ_TX_DRVALID : out std_logic;
DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_TX_DRLAST : out std_logic;
DMA_REQ_TX_DRREADY : in std_logic;
-- PL330 DMA RX interface
DMA_REQ_RX_ACLK : in std_logic;
DMA_REQ_RX_RSTN : in std_logic;
DMA_REQ_RX_DAVALID : in std_logic;
DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_RX_DAREADY : out std_logic;
DMA_REQ_RX_DRVALID : out std_logic;
DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_RX_DRLAST : out std_logic;
DMA_REQ_RX_DRREADY : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_i2s_adi_v1_2;
architecture arch_imp of axi_i2s_adi_v1_2 is
-- component declaration
component axi_i2s_adi_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
rd_addr : out integer range 0 to 12 - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
wr_addr : out integer range 0 to 12 - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_stb : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_i2s_adi_S_AXI;
signal i2s_reset : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_enable : Boolean;
signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal tx_ack : std_logic;
signal tx_stb : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_in_ack : std_logic;
signal rx_enable : Boolean;
signal rx_fifo_reset : std_logic;
signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal rx_ack : std_logic;
signal rx_stb : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_out_stb : std_logic;
signal bclk_div_rate : natural range 0 to 255;
signal lrclk_div_rate : natural range 0 to 255;
signal period_len : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
signal rx_sample : std_logic_vector(23 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 11;
signal rd_addr : integer range 0 to 11;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
signal tx_fifo_stb : std_logic;
signal rx_fifo_ack : std_logic;
signal cnt : integer range 0 to 2**16-1;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_i2s_adi_S_AXI_inst : axi_i2s_adi_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
wr_addr => wr_addr,
wr_data => wr_data,
wr_stb => wr_stb,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
process (s00_axi_aclk)
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
cnt <= 0;
else
cnt <= (cnt + 1) mod 2**16;
end if;
end if;
end process;
streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8),
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
out_stb => tx_stb,
out_ack => tx_ack,
out_data => tx_data
);
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
period_len => period_len,
in_stb => rx_stb,
in_ack => rx_ack,
in_data => rx_data,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8),
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate;
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
tx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 0
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
in_data => wr_data(31 downto 8),
in_stb => tx_fifo_stb,
in_ack => tx_in_ack,
out_ack => tx_ack,
out_stb => tx_stb,
out_data => tx_data,
dclk => DMA_REQ_TX_ACLK,
dresetn => DMA_REQ_TX_RSTN,
davalid => DMA_REQ_TX_DAVALID,
daready => DMA_REQ_TX_DAREADY,
datype => DMA_REQ_TX_DATYPE,
drvalid => DMA_REQ_TX_DRVALID,
drready => DMA_REQ_TX_DRREADY,
drtype => DMA_REQ_TX_DRTYPE,
drlast => DMA_REQ_TX_DRLAST
);
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
rx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 1
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => rx_fifo_reset,
enable => rx_enable,
in_ack => rx_ack,
in_stb => rx_stb,
in_data => rx_data,
out_data => rx_sample,
out_ack => rx_fifo_ack,
out_stb => rx_out_stb,
dclk => DMA_REQ_RX_ACLK,
dresetn => DMA_REQ_RX_RSTN,
davalid => DMA_REQ_RX_DAVALID,
daready => DMA_REQ_RX_DAREADY,
datype => DMA_REQ_RX_DATYPE,
drvalid => DMA_REQ_RX_DRVALID,
drready => DMA_REQ_RX_DRREADY,
drtype => DMA_REQ_RX_DRTYPE,
drlast => DMA_REQ_RX_DRLAST
);
end generate;
ctrl : entity i2s_controller
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_BCLK_POL => C_BCLK_POL,
C_LRCLK_POL => C_LRCLK_POL,
C_NUM_CH => C_NUM_CH,
C_HAS_TX => C_HAS_TX,
C_HAS_RX => C_HAS_RX
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
data_clk => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
tx_enable => tx_enable,
tx_ack => tx_ack,
tx_stb => tx_stb,
tx_data => tx_data,
rx_enable => rx_enable,
rx_ack => rx_ack,
rx_stb => rx_stb,
rx_data => rx_data,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate
);
tx_fifo_full <= not(tx_in_ack);
tx_fifo_empty <= not(tx_stb);
rx_fifo_full <= not(rx_ack);
rx_fifo_empty <= not(rx_out_stb);
i2s_reset <= I2S_RESET_REG(0);
tx_fifo_reset <= I2S_RESET_REG(1);
rx_fifo_reset <= I2S_RESET_REG(2);
tx_enable <= I2S_CONTROL_REG(0) = '1';
rx_enable <= I2S_CONTROL_REG(1) = '1';
MUTEN_O <= not(I2S_CONTROL_REG(2));
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
process(rd_addr)
begin
case rd_addr is
when 1 => rd_data <= I2S_CONTROL_REG and x"00000007";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
when 8 => rd_data <= x"0000000" & rx_fifo_full & rx_fifo_empty & tx_fifo_full & tx_fifo_empty;
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
when others => rd_data <= (others => '0');
end case;
end process;
process(s00_axi_aclk) is
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
PERIOD_LEN_REG <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
if wr_stb = '1' then
case wr_addr is
when 0 => I2S_RESET_REG <= wr_data;
when 1 => I2S_CONTROL_REG <= wr_data;
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
when 6 => PERIOD_LEN_REG <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
mit
|
b5fa3af5b0e58d73918725d316e680d5
| 0.630771 | 2.448306 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
ahs.vhd
| 1 | 2,628 |
-------------------------------------------------------------------------------
--
-- Title : ahs
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\ahs.vhd
-- Generated : Tue Dec 6 14:06:21 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ahs} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.ALL;
entity ahs is
port(
rs1: in std_logic_vector(63 downto 0);
rs2: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end ahs;
--}} End of automatically maintained section
architecture behavioral of ahs is
begin
process(rs1,rs2)
variable sum1: unsigned(16 downto 0);
variable sum2: unsigned(16 downto 0);
variable sum3: unsigned(16 downto 0);
variable sum4: unsigned(16 downto 0);
begin
sum1:=unsigned('0'&rs1(63 downto 48)) + unsigned('0'&rs2(63 downto 48));
sum2:=unsigned('0'&rs1(47 downto 32)) + unsigned('0'&rs2(47 downto 32));
sum3:=unsigned('0'&rs1(31 downto 16)) + unsigned('0'&rs2(31 downto 16));
sum4:=unsigned('0'&rs1(15 downto 0)) + unsigned('0'&rs2(15 downto 0));
if(sum1>65536) then
sum1 := to_unsigned(65535,17);
end if;
sum2:=unsigned('0'&rs1(47 downto 32)) + unsigned('0'&rs2(47 downto 32));
if(sum2>65536) then
sum2 := to_unsigned(65535,17);
end if;
sum3:=unsigned('0'&rs1(31 downto 16)) + unsigned('0'&rs2(31 downto 16));
if(sum3>65536) then
sum3 := to_unsigned(65535,17);
end if;
sum4:=unsigned('0'&rs1(15 downto 0)) + unsigned('0'&rs2(15 downto 0));
if(sum4>65536) then
sum4 := to_unsigned(65535,17);
end if;
rd(63 downto 48)<= std_logic_vector(sum1(15 downto 0));
rd(47 downto 32)<= std_logic_vector(sum2(15 downto 0));
rd(31 downto 16)<= std_logic_vector(sum3(15 downto 0));
rd(15 downto 0) <= std_logic_vector(sum4(15 downto 0));
end process;
end behavioral;
|
apache-2.0
|
6a3854e3dc6922bd3109bb6c43cf6f73
| 0.498858 | 3.439791 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/TBFAdd.vhd
| 1 | 2,401 |
library ieee;
use ieee.std_logic_1164.ALL;
entity TBFAdd is
end TBFAdd;
architecture testbench of TBFAdd is
component TBCommon
port (
clk : buffer std_logic;
a : out std_logic_vector(31 downto 0);
b : out std_logic_vector(31 downto 0);
d : in std_logic_vector(31 downto 0));
end component;
component FAdd
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end component;
signal clk : std_logic;
signal a1, b1, d1 : std_logic_vector(31 downto 0);
signal a2, b2, d2 : std_logic_vector(31 downto 0) := (others => '0');
signal a3, b3, d3 : std_logic_vector(31 downto 0) := (others => '0');
signal d_out, d_fadd : std_logic_vector(31 downto 0);
signal x1 : boolean;
signal x2, x3 : boolean := false;
signal a_sgn, b_sgn : std_logic;
signal a_exp, b_exp : std_logic_vector(7 downto 0);
signal a_frc, b_frc : std_logic_vector(22 downto 0);
constant z_exp : std_logic_vector(7 downto 0) := (others => '0');
constant h_exp : std_logic_vector(7 downto 0) := (others => '1');
constant z_frc : std_logic_vector(22 downto 0) := (others => '0');
constant o_frc : std_logic_vector(22 downto 0) := x"00000" & "001";
begin
tbcommon_map : TBCommon port map (
clk => clk,
a => a1,
b => b1,
d => d_out);
fadd_map : FAdd port map (
clk => clk,
flt_in1 => a1,
flt_in2 => b1,
flt_out => d_fadd);
main : process(clk)
begin
if rising_edge(clk) then
a2 <= a1;
b2 <= b1;
d2 <= d1;
x2 <= x1;
a3 <= a2;
b3 <= b2;
d3 <= d2;
x3 <= x2;
end if;
end process;
a_sgn <= a1(31);
b_sgn <= b1(31);
a_exp <= a1(30 downto 23);
b_exp <= b1(30 downto 23);
a_frc <= a1(22 downto 0);
b_frc <= b1(22 downto 0);
d1 <= a_sgn & h_exp & a_frc when b_exp /= h_exp else
b_sgn & h_exp & b_frc when a_exp /= h_exp else
(a_sgn and b_sgn) & h_exp & (a_frc or b_frc or (x"00000" & "00" & (a_sgn xor b_sgn)));
x1 <= a_exp = h_exp or b_exp = h_exp;
d_out <= d3 when x3 else d_fadd;
end testbench;
|
bsd-2-clause
|
8d3772d73d1efa5f25dd4b291c55c6c6
| 0.51895 | 3.005006 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
addersubtractor.vhd
| 1 | 1,539 |
-------------------------------------------------------------------------------
--
-- Title : addersubtractor
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\addersubtractor.vhd
-- Generated : Wed Dec 7 15:49:53 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {addersubtractor} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity addersubtractor is
port(
a: in std_logic_vector (63 downto 0);
b: in std_logic_vector (63 downto 0);
s: out std_logic_vector (63 downto 0);
Carry: out std_logic;
addorsub: in std_logic
);
end addersubtractor;
--}} End of automatically maintained section
architecture behavioral of addersubtractor is
signal b_sig: std_logic_vector(63 downto 0);
signal c_sig: std_logic;
begin
u: entity addorsub port map(addorsub => addorsub, i1 => b, c0 => c_sig, o1 => b_sig);
u0: entity thirtytwobit_module port map( a => a, b =>b_sig, c0 => c_sig, Carry => Carry, s => s);
end behavioral;
|
apache-2.0
|
e6c42f8f002bebd4080ac39f605f4caf
| 0.493177 | 3.92602 | false | false | false | false |
Digilent/vivado-library
|
module/synchronizers/ResetBridge.vhd
| 2 | 5,567 |
-------------------------------------------------------------------------------
--
-- File: ResetBridge.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (aoRst). The signal aoRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
-- The additional output register does not have placement and overly
-- restrictive delay constraints, so that the tools can freely replicate it,
-- if needed.
--
-- Constraints:
-- # Replace <InstResetBridge> with path to ResetBridge instance, keep rest unchanged
-- # Begin scope to ResetBridge instance
-- current_instance [get_cells <InstResetBridge>]
-- # Reset input to the synchronizer must be ignored for timing analysis
-- set_false_path -through [get_ports -scoped_to_current_instance aRst]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] -to [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to ResetBridge instance
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1';
kStages : natural := 2;
kOutputFF : boolean := false); -- additional output FF for replication
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
aoRst : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of ResetBridge : entity is "yes";
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int, aoRst_int : std_logic;
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
OutputFF_Yes: if kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => '0',
OutClk => OutClk,
oOut => aoRst_int);
-- Output FF that can be replicated by the tools, if needed
OutputFF: process (OutClk, aoRst_int)
begin
if (aoRst_int = '1') then
aoRst <= kPolarity;
elsif Rising_Edge(OutClk) then
aoRst <= not kPolarity;
end if;
end process;
end generate OutputFF_Yes;
OutputFF_No: if not kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => aoRst);
end generate OutputFF_No;
end Behavioral;
|
mit
|
ae0093f4294f9db36ee5406c7356a71d
| 0.67954 | 4.600826 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/Predict.vhd
| 1 | 7,380 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
-- prediction counter
-- 10 00 <-fail-|-success-> 01 11
entity Predict is
port (
clk : in std_logic;
d : in predict_in_t;
q : out predict_out_t);
end Predict;
architecture twoproc of Predict is
attribute ram_style : string;
constant gshare_wid : natural := 9;
type gshare_ram_t is array(0 to (2**gshare_wid)-1) of std_logic_vector(1 downto 0);
signal gshare_ram : gshare_ram_t := (others => (others => '0'));
attribute ram_style of gshare_ram : signal is "distributed";
signal gshare_we : boolean;
signal gshare_wkey : std_logic_vector(gshare_wid-1 downto 0) := (others => '0');
signal gshare_wval : std_logic_vector(1 downto 0) := "00";
type cont_t is record
gshared : boolean;
gshared_key : std_logic_vector(gshare_wid-1 downto 0);
gshared_val : std_logic_vector(1 downto 0);
end record;
signal cont : cont_t;
constant hist_len : natural := 4;
signal hist : std_logic_vector(hist_len-1 downto 0) := (others => '0');
signal hist_wval : std_logic;
constant stack_wid : natural := 6;
type stack_ram_t is array(0 to (2**stack_wid)-1) of blkram_addr;
signal stack_ram : stack_ram_t := (others => (others => '0'));
attribute ram_style of stack_ram : signal is "distributed";
signal stack_top, stack_top_next, stack_top_back : unsigned(stack_wid-1 downto 0) := (others => '0');
signal stack_topp, stack_topp_next, stack_topp_back : unsigned(stack_wid-1 downto 0) := (others => '1');
signal stack_push : boolean := false;
constant buf_len : natural := 2;
type buf_t is array(buf_len-1 downto 0) of blkram_addr;
type cont_buf_t is array(buf_len-1 downto 0) of cont_t;
signal buf : buf_t := (others => (others => '0'));
signal cont_buf : cont_buf_t := (others => (false, (others => '0'), "00"));
signal addr : blkram_addr;
signal imm_addr : blkram_addr;
signal stack_addr : blkram_addr;
begin
imm_addr <= blkram_addr(d.inst(15 downto 0));
stack_addr <= stack_ram(to_integer(stack_topp));
q.addr <= addr;
sequential : process(clk)
begin
if rising_edge(clk) then
if d.enable_fetch then
buf <= addr & buf(buf_len-1 downto 1);
cont_buf <= cont & cont_buf(buf_len-1 downto 1);
stack_top <= stack_top_next;
stack_topp <= stack_topp_next;
stack_top_back <= stack_top;
stack_topp_back <= stack_topp;
if gshare_we then
hist <= hist_wval & hist(hist_len-1 downto 1);
gshare_ram(to_integer(unsigned(gshare_wkey))) <= gshare_wval;
end if;
if stack_push then
stack_ram(to_integer(stack_top)) <= d.pc;
end if;
end if;
end if;
end process;
combinatorial : process(d, imm_addr, stack_addr, gshare_ram, stack_top, stack_topp, buf(0), cont_buf(0), stack_top_back, stack_topp_back)
variable upper : std_logic_vector(hist_len-1 downto 0);
variable lower : std_logic_vector(gshare_wid-hist_len-1 downto 0);
variable gshare : boolean;
variable gshare_key : std_logic_vector(gshare_wid-1 downto 0);
variable gshare_val : std_logic_vector(1 downto 0);
variable cont_head : cont_t;
variable succeed : boolean;
variable stack_top_next_v, stack_topp_next_v : unsigned(stack_wid-1 downto 0);
variable stack_push_v : boolean;
begin
succeed := buf(0) = d.target or not d.enable_target;
q.succeed <= succeed;
upper := std_logic_vector(imm_addr(gshare_wid-1 downto gshare_wid-hist_len));
lower := std_logic_vector(imm_addr(gshare_wid-hist_len-1 downto 0));
gshare_key := (upper xor hist) & lower;
gshare_val := gshare_ram(to_integer(unsigned(gshare_key)));
gshare := false;
stack_top_next_v := stack_top;
stack_topp_next_v := stack_topp;
stack_push_v := false;
if succeed then
if d.inst(31) = '1' then
case d.inst(30 downto 29) is
when "00" | "01" => -- gshare (TODO: use 01 for loop prediction?)
gshare := true;
if gshare_val(0) = '0' then
addr <= d.pc;
else
addr <= imm_addr;
end if;
when "10" => -- static no jump
addr <= d.pc;
when "11" => -- static jump
addr <= imm_addr;
when others => null;
end case;
elsif d.inst(30 downto 28) = "101" then
case d.inst(27 downto 26) is
when "00" => -- imm jump
addr <= imm_addr;
when "01" => -- call
addr <= imm_addr;
stack_push_v := true;
stack_top_next_v := stack_top + 1;
stack_topp_next_v := stack_topp + 1;
when "10" => -- ret
addr <= stack_addr;
stack_top_next_v := stack_top - 1;
stack_topp_next_v := stack_topp - 1;
when "11" => -- not jump
addr <= d.pc;
when others => null;
end case;
else
addr <= d.pc;
end if;
else
stack_top_next_v := stack_top_back;
stack_topp_next_v := stack_topp_back;
addr <= d.target;
end if;
stack_top_next <= stack_top_next_v;
stack_topp_next <= stack_topp_next_v;
stack_push <= stack_push_v;
cont <= (gshared => gshare, gshared_key => gshare_key, gshared_val => gshare_val);
cont_head := cont_buf(0);
if succeed then
case cont_head.gshared_val is
when "10" =>
gshare_wval <= "10";
hist_wval <= '0';
when "00" =>
gshare_wval <= "10";
hist_wval <= '0';
when "01" =>
gshare_wval <= "11";
hist_wval <= '1';
when "11" =>
gshare_wval <= "11";
hist_wval <= '1';
when others => assert false;
end case;
else
case cont_head.gshared_val is
when "10" =>
gshare_wval <= "00";
hist_wval <= '1';
when "00" =>
gshare_wval <= "01";
hist_wval <= '1';
when "01" =>
gshare_wval <= "00";
hist_wval <= '0';
when "11" =>
gshare_wval <= "01";
hist_wval <= '0';
when others => assert false;
end case;
end if;
gshare_we <= d.enable_target and cont_head.gshared;
gshare_wkey <= cont_head.gshared_key;
end process;
end twoproc;
|
bsd-2-clause
|
3021af98ebba765c765bdf31d512fbf4
| 0.48794 | 3.874016 | false | false | false | false |
Digilent/vivado-library
|
ip/AXI_DPTI_1.0/src/DPTI_To_AXI_S_Converter.vhd
| 1 | 13,564 |
------------------------------------------------------------------------------
--
-- File: DPTI_to_AXI_S_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module reads data from the DPTI interface and converts it so that it is
-- compatible with the AXI STREAM interface. Along with 32 bit TDATA, it also generates
-- the 4 bit TKEEP, TVALID and TLAST, using TREADY as an input. On the DPTI side,
-- it uses the interface clock PROG_CLK, it reads data from pDataIn and uses pRxf
-- to identify valid data and it generates the output enable pOe signal and pRd which
-- requests more data. All these ports will be connected to the DPTI ports in the top.
-- The pDataIn bus will also pass through an IOBUF controlled by pOe. The converter works
-- by reading a data byte fron the DPTI, it then determines if the data is valid,
-- and if it is, it then uses it to create the TDATA bus and the TKEEP bus. The module
-- will wait until it has 4 valid bytes in order to avoid sending incomplete transfers,
-- except for the last transfer which can be incomplete due to the nature of the length
-- which is requested (if the number is not divisible by 4). When a transfer is prepared,
-- the TVALID signal is generated which acomplishes the actual transfer along with the
-- TLAST signal when the transfer is the last one. During this time, it monitors the
-- TREADY signal as well as pRxf signal coming from the DPTI interface. In order to
-- control the module, two AXI Lite registers are used, one for direction/control and
-- one for the lenght of the transfer, which are synchronized in the top module.
-- The module also uses a reset signal aResetRx which is generated in the top module.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;
entity DPTI_to_AXI_S_converter is
Port (
-- clock, reset and DPTI signals
pResetnRx : in std_logic;
PROG_CLK : in std_logic;
pRxf : in std_logic;
pRd : out std_logic;
pOe : out std_logic;
pDataIn : in std_logic_vector (7 downto 0);
-- AXI Stream signals
pInTready : in std_logic;
pOutTdata : out std_logic_vector (31 downto 0);
pOutTvalid : out std_logic;
pOutTlast : out std_logic;
pOutTkeep : out std_logic_vector (3 downto 0);
-- AXI Lite registers
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pRxLengthEmpty : out std_logic
);
end DPTI_to_AXI_S_converter;
architecture Behavioral of DPTI_to_AXI_S_converter is
--------------------------------------------------------------------------------------------------------------------------
signal Index: integer range 0 to 3;
signal pCountSentBytes : std_logic_vector (1 downto 0);
signal pCountBytesIncrFlag : std_logic := '1';
signal pRxEnDir : std_logic := '0';
signal pLengthRxCnt : std_logic_vector (23 downto 0);
signal pCtlRd : std_logic := '1';
signal pCtlOutTvalid : std_logic := '0';
signal pCtlOutTlast : std_logic := '0';
signal pLengthRxCntDepletedFlag : std_logic := '0';
signal pAuxLengthRxDecrFlag : std_logic := '0';
signal pLastTransferFlag : std_logic := '0';
signal pRxfDelay : std_logic := '1';
--------------------------------------------------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------------------------------------------------
pOutTlast <= pCtlOutTlast;
pOutTvalid <= pCtlOutTvalid;
pOe <= not pRxEnDir ;
pRd <= pCtlRd;
pCtlOutTvalid <= '1' when pCountSentBytes = 0 and pCountBytesIncrFlag = '0' else '0'; -- TVALID signal is generated
-- pCountSentBytes = 0 - allows TVALID to be '1' only after 4 valid data bytes have been processed
-- pCountBytesIncrFlag = '0' - This signal will ensure that the TVALID signal is high for only one Clock period. It checks if the current byte is valid or not. The counter will only increment when the data byte is valid.
pCtlOutTlast <= '1' when pCountSentBytes = 0 and pCountBytesIncrFlag = '0' and pLengthRxCnt < 4 else '0'; -- TLAST signal is generated
-- TLAST is very similar to TVALID however it must only be asserted at the end of the last AXI STREAM transfer. In order to accomplish this, pLengthRxCnt must be less than 4 (no more than 4 bytes left to transfer) so that only one more STREAM transfer is needed.
pCtlRd <= '0' when pLastTransferFlag = '0' and pInTready = '1' and pRxfDelay = '0' else '1'; -- PROG_RDN is generated
-- the signal must be 0 only when TREADY (input) is '1' since that means that the STREAM interface is ready for at least one extra set of data since the date currently being read will be transfered in the next AXI STREAM transfer
-- pLastTransferFlag indicatges that only one more transfer will be required. Once this signal is '1' this indicates that there is no more data required for the dpti to stream transfer
-- pRxfDelay will mirror the PROG_RXEN signal received from the DPTI interface. when the FTDI empties its internal FIFO, it will drive PROG_RXEN high and even if the FPGA can still receive data, PROG_RDN must be driven high, otherwise the FTDI will provide the wrong data when PROG_RXEN becomes '0'
pLastTransferFlag <= '1' when pLengthRxCnt < 4 else '0'; -- This signal will indicate when the module has reached the last AXI Stream transfer. If there are less than 4 bytes left to be transfered
-- this signal is used to determine when there is only one STREAM transfer left
pRxLengthEmpty <= '1' when pLengthRxCnt = 0 else '0'; -- this signal (used by driver) will indicate the status of the module. when high, the module is ready to do another transfer
--------------------------------------------------------------------------------------------------------------------------
generate_pRxfDelay: process(PROG_CLK) -- the signal pRxfDelay will be identical to PROG_RXEN delayed by one clock period which will then become the PROG_RDN signal.
begin
if rising_edge (PROG_CLK) then
if pRxf = '1' then
pRxfDelay <= '1';
else
pRxfDelay <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pCountSentBytes: process (PROG_CLK, pResetnRx) -- this counter will increment when a valid byte was read from the DPTI interface and processed
begin
if pResetnRx = '0' then
pCountSentBytes <= (others => '0');
pCountBytesIncrFlag <= '1';
elsif rising_edge(PROG_CLK) then
if pLengthRxCnt > 0 and ((pRxf = '0' and pRxfDelay = '0') or pLastTransferFlag = '1') and pInTready = '1' then -- check if a transfer is in progress and all the conditions are in place to read and process a byte
pCountSentBytes <= pCountSentBytes + '1'; -- the counter is incremented
pCountBytesIncrFlag <= '0'; -- the flag which indicates a change in the counter's value
elsif pLengthRxCnt = 0 then -- if a transfer was completed
pCountSentBytes <= (others => '0'); -- counter is reset
pCountBytesIncrFlag <= '1'; -- flag is set
else
pCountSentBytes <= pCountSentBytes; -- when a transfer is in progress and conditions for a valid byte to be processed are not met
pCountBytesIncrFlag <= '1'; -- flag is set
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_Index: process (PROG_CLK, pResetnRx) -- the Index integer is used for positioning the individual bytes in the 4 byte TDATA register
begin
if pResetnRx = '0' then
Index <= 0;
elsif rising_edge(PROG_CLK) then
if pLengthRxCnt > 0 and pRxf = '0' and pRxfDelay = '0' and pInTready = '1' then -- in order to increment Index, the data provided must be valid and the receivind FIFO must not be full
if Index < 3 then -- index will have values between 0 and 3
Index <= Index + 1; -- when conditions are met, index is incremented
else
Index <= 0;
end if;
elsif pLengthRxCnt = 0 then -- when a transfer is completed, Index becomes 0
Index <= 0;
else
Index <= Index;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pOutTdata: process (PROG_CLK, pResetnRx, Index, pLengthRxCnt) is -- TDATA is generated from data received from the DPTI interface
begin
if (pResetnRx = '0') then
pOutTdata <= (others => '0');
elsif rising_edge(PROG_CLK) then
if pLengthRxCnt > 3 and pRxEnDir = '1' and pRxf = '0' and pRxfDelay = '0' and pInTready = '1' then -- conditions for data to be considered valid
pOutTdata(( 8 * (Index + 1)) - 1 downto ( 8 * (Index))) <= pDataIn(7 downto 0); -- TDATA bus is being built. the new byte's position is determined by the value of Index
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
gen_pOutTkeep_read_AXI_Lite_registers: process (PROG_CLK, pResetnRx, Index, pLengthRxCnt) is -- reading the AXI Lite registers, controlling the main counters, generating TKEEP
begin
if (pResetnRx = '0') then
pLengthRxCnt <= (others => '0');
elsif rising_edge(PROG_CLK) then
if pOvalidControl = '1' and pLengthRxCnt = 0 then -- the control bit (and the direction) can only be changed when the module is idle
pRxEnDir <= pAXI_L_Control (1); -- Reading control byte from AXI LITE register. Bit (1) sets the transfer's direction.
end if;
if pOvalidLength = '1' and pRxEnDir = '1' then -- checking if the module was enabled and if valid value is present in the LENGTH register
pLengthRxCnt (23 downto 0) <= pAXI_L_Length(23 downto 0) + "11"; -- The counter will be the requested transfer length + 3 so that after all of the valid bytes are received and processed, there will be 3 more clock periods where it will decrement which will allow us to generate the signals required to send the last STREAM transfer, especially TLAST.
end if;
if pLengthRxCnt > 0 and (pLastTransferFlag = '1' or (pRxf = '0' and pRxfDelay = '0' and pInTready = '1')) then -- here the module checks if the byte received is valid or if we are going to send the last STREAM package
pLengthRxCnt <= pLengthRxCnt - '1'; -- the counter is decremented.
end if;
if pLengthRxCnt > 3 and pRxf = '0' and pRxfDelay = '0' and pInTready = '1' then -- check when a valid byte has been read from the DPTI interface
pOutTkeep (Index) <= '1'; -- the TKEEP bit of the byte sent to AXI STREAM in the "generate_pOutTdata" process is set
else
pOutTkeep (Index) <= '0'; -- if the byte is not valid, the bit will be '0'
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
end Behavioral;
|
mit
|
22541b24105d6b2c52042ef075ca9914
| 0.622899 | 4.565466 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_fYi.vhd
| 1 | 13,862 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_fYi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_fYi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00000101", 2 => "00001000", 3 => "00001011",
4 => "00001101", 5 => "00001111", 6 => "00010010", 7 => "00010100",
8 => "00010110", 9 => "00010111", 10 => "00011001", 11 => "00011011",
12 => "00011101", 13 => "00011110", 14 => "00100000", 15 => "00100010",
16 => "00100011", 17 => "00100101", 18 => "00100110", 19 => "00101000",
20 => "00101001", 21 => "00101011", 22 => "00101100", 23 => "00101110",
24 => "00101111", 25 => "00110001", 26 => "00110010", 27 => "00110011",
28 => "00110101", 29 => "00110110", 30 => "00110111", 31 => "00111001",
32 => "00111010", 33 => "00111011", 34 => "00111100", 35 => "00111110",
36 => "00111111", 37 => "01000000", 38 => "01000001", 39 => "01000011",
40 => "01000100", 41 => "01000101", 42 => "01000110", 43 => "01001000",
44 => "01001001", 45 => "01001010", 46 => "01001011", 47 => "01001100",
48 => "01001101", 49 => "01001110", 50 => "01010000", 51 => "01010001",
52 => "01010010", 53 => "01010011", 54 => "01010100", 55 => "01010101",
56 => "01010110", 57 => "01010111", 58 => "01011001", 59 => "01011010",
60 => "01011011", 61 => "01011100", 62 => "01011101", 63 => "01011110",
64 => "01011111", 65 => "01100000", 66 => "01100001", 67 => "01100010",
68 => "01100011", 69 => "01100100", 70 => "01100101", 71 => "01100110",
72 => "01100111", 73 => "01101000", 74 => "01101001", 75 => "01101010",
76 => "01101011", 77 => "01101100", 78 => "01101101", 79 => "01101110",
80 => "01101111", 81 => "01110000", 82 => "01110001", 83 => "01110010",
84 => "01110011", 85 => "01110100", 86 => "01110101", 87 => "01110110",
88 => "01110111", 89 => "01111000", 90 => "01111001", 91 => "01111010",
92 => "01111011", 93 => "01111100", 94 => "01111101", 95 => "01111110",
96 => "01111111", 97 => "10000000", 98 => "10000001", 99 => "10000010",
100 => "10000011", 101 => "10000100", 102 to 103=> "10000101", 104 => "10000110",
105 => "10000111", 106 => "10001000", 107 => "10001001", 108 => "10001010",
109 => "10001011", 110 => "10001100", 111 => "10001101", 112 => "10001110",
113 to 114=> "10001111", 115 => "10010000", 116 => "10010001", 117 => "10010010",
118 => "10010011", 119 => "10010100", 120 => "10010101", 121 => "10010110",
122 to 123=> "10010111", 124 => "10011000", 125 => "10011001", 126 => "10011010",
127 => "10011011", 128 => "10011100", 129 => "10011101", 130 to 131=> "10011110",
132 => "10011111", 133 => "10100000", 134 => "10100001", 135 => "10100010",
136 => "10100011", 137 to 138=> "10100100", 139 => "10100101", 140 => "10100110",
141 => "10100111", 142 => "10101000", 143 => "10101001", 144 to 145=> "10101010",
146 => "10101011", 147 => "10101100", 148 => "10101101", 149 => "10101110",
150 to 151=> "10101111", 152 => "10110000", 153 => "10110001", 154 => "10110010",
155 => "10110011", 156 to 157=> "10110100", 158 => "10110101", 159 => "10110110",
160 => "10110111", 161 to 162=> "10111000", 163 => "10111001", 164 => "10111010",
165 => "10111011", 166 to 167=> "10111100", 168 => "10111101", 169 => "10111110",
170 => "10111111", 171 to 172=> "11000000", 173 => "11000001", 174 => "11000010",
175 => "11000011", 176 to 177=> "11000100", 178 => "11000101", 179 => "11000110",
180 => "11000111", 181 to 182=> "11001000", 183 => "11001001", 184 => "11001010",
185 => "11001011", 186 to 187=> "11001100", 188 => "11001101", 189 => "11001110",
190 to 191=> "11001111", 192 => "11010000", 193 => "11010001", 194 => "11010010",
195 to 196=> "11010011", 197 => "11010100", 198 => "11010101", 199 to 200=> "11010110",
201 => "11010111", 202 => "11011000", 203 to 204=> "11011001", 205 => "11011010",
206 => "11011011", 207 to 208=> "11011100", 209 => "11011101", 210 => "11011110",
211 to 212=> "11011111", 213 => "11100000", 214 => "11100001", 215 to 216=> "11100010",
217 => "11100011", 218 => "11100100", 219 to 220=> "11100101", 221 => "11100110",
222 => "11100111", 223 to 224=> "11101000", 225 => "11101001", 226 => "11101010",
227 to 228=> "11101011", 229 => "11101100", 230 => "11101101", 231 to 232=> "11101110",
233 => "11101111", 234 => "11110000", 235 to 236=> "11110001", 237 => "11110010",
238 to 239=> "11110011", 240 => "11110100", 241 => "11110101", 242 to 243=> "11110110",
244 => "11110111", 245 => "11111000", 246 to 247=> "11111001", 248 => "11111010",
249 to 250=> "11111011", 251 => "11111100", 252 => "11111101", 253 to 254=> "11111110",
255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00000101", 2 => "00001000", 3 => "00001011",
4 => "00001101", 5 => "00001111", 6 => "00010010", 7 => "00010100",
8 => "00010110", 9 => "00010111", 10 => "00011001", 11 => "00011011",
12 => "00011101", 13 => "00011110", 14 => "00100000", 15 => "00100010",
16 => "00100011", 17 => "00100101", 18 => "00100110", 19 => "00101000",
20 => "00101001", 21 => "00101011", 22 => "00101100", 23 => "00101110",
24 => "00101111", 25 => "00110001", 26 => "00110010", 27 => "00110011",
28 => "00110101", 29 => "00110110", 30 => "00110111", 31 => "00111001",
32 => "00111010", 33 => "00111011", 34 => "00111100", 35 => "00111110",
36 => "00111111", 37 => "01000000", 38 => "01000001", 39 => "01000011",
40 => "01000100", 41 => "01000101", 42 => "01000110", 43 => "01001000",
44 => "01001001", 45 => "01001010", 46 => "01001011", 47 => "01001100",
48 => "01001101", 49 => "01001110", 50 => "01010000", 51 => "01010001",
52 => "01010010", 53 => "01010011", 54 => "01010100", 55 => "01010101",
56 => "01010110", 57 => "01010111", 58 => "01011001", 59 => "01011010",
60 => "01011011", 61 => "01011100", 62 => "01011101", 63 => "01011110",
64 => "01011111", 65 => "01100000", 66 => "01100001", 67 => "01100010",
68 => "01100011", 69 => "01100100", 70 => "01100101", 71 => "01100110",
72 => "01100111", 73 => "01101000", 74 => "01101001", 75 => "01101010",
76 => "01101011", 77 => "01101100", 78 => "01101101", 79 => "01101110",
80 => "01101111", 81 => "01110000", 82 => "01110001", 83 => "01110010",
84 => "01110011", 85 => "01110100", 86 => "01110101", 87 => "01110110",
88 => "01110111", 89 => "01111000", 90 => "01111001", 91 => "01111010",
92 => "01111011", 93 => "01111100", 94 => "01111101", 95 => "01111110",
96 => "01111111", 97 => "10000000", 98 => "10000001", 99 => "10000010",
100 => "10000011", 101 => "10000100", 102 to 103=> "10000101", 104 => "10000110",
105 => "10000111", 106 => "10001000", 107 => "10001001", 108 => "10001010",
109 => "10001011", 110 => "10001100", 111 => "10001101", 112 => "10001110",
113 to 114=> "10001111", 115 => "10010000", 116 => "10010001", 117 => "10010010",
118 => "10010011", 119 => "10010100", 120 => "10010101", 121 => "10010110",
122 to 123=> "10010111", 124 => "10011000", 125 => "10011001", 126 => "10011010",
127 => "10011011", 128 => "10011100", 129 => "10011101", 130 to 131=> "10011110",
132 => "10011111", 133 => "10100000", 134 => "10100001", 135 => "10100010",
136 => "10100011", 137 to 138=> "10100100", 139 => "10100101", 140 => "10100110",
141 => "10100111", 142 => "10101000", 143 => "10101001", 144 to 145=> "10101010",
146 => "10101011", 147 => "10101100", 148 => "10101101", 149 => "10101110",
150 to 151=> "10101111", 152 => "10110000", 153 => "10110001", 154 => "10110010",
155 => "10110011", 156 to 157=> "10110100", 158 => "10110101", 159 => "10110110",
160 => "10110111", 161 to 162=> "10111000", 163 => "10111001", 164 => "10111010",
165 => "10111011", 166 to 167=> "10111100", 168 => "10111101", 169 => "10111110",
170 => "10111111", 171 to 172=> "11000000", 173 => "11000001", 174 => "11000010",
175 => "11000011", 176 to 177=> "11000100", 178 => "11000101", 179 => "11000110",
180 => "11000111", 181 to 182=> "11001000", 183 => "11001001", 184 => "11001010",
185 => "11001011", 186 to 187=> "11001100", 188 => "11001101", 189 => "11001110",
190 to 191=> "11001111", 192 => "11010000", 193 => "11010001", 194 => "11010010",
195 to 196=> "11010011", 197 => "11010100", 198 => "11010101", 199 to 200=> "11010110",
201 => "11010111", 202 => "11011000", 203 to 204=> "11011001", 205 => "11011010",
206 => "11011011", 207 to 208=> "11011100", 209 => "11011101", 210 => "11011110",
211 to 212=> "11011111", 213 => "11100000", 214 => "11100001", 215 to 216=> "11100010",
217 => "11100011", 218 => "11100100", 219 to 220=> "11100101", 221 => "11100110",
222 => "11100111", 223 to 224=> "11101000", 225 => "11101001", 226 => "11101010",
227 to 228=> "11101011", 229 => "11101100", 230 => "11101101", 231 to 232=> "11101110",
233 => "11101111", 234 => "11110000", 235 to 236=> "11110001", 237 => "11110010",
238 to 239=> "11110011", 240 => "11110100", 241 => "11110101", 242 to 243=> "11110110",
244 => "11110111", 245 => "11111000", 246 to 247=> "11111001", 248 => "11111010",
249 to 250=> "11111011", 251 => "11111100", 252 => "11111101", 253 to 254=> "11111110",
255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_fYi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_fYi is
component Loop_loop_height_fYi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_fYi_rom_U : component Loop_loop_height_fYi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
c02df47d0d8a91341898e080d053d131
| 0.546242 | 3.625948 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/ContadorEventos_tb.vhd
| 2 | 2,286 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:45:20 01/07/2015
-- Design Name:
-- Module Name: E:/ISE/Trabajo/Frecuencimentro/ContadorEventos_tb.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ContadorEventos
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ContadorEventos_tb IS
END ContadorEventos_tb;
ARCHITECTURE behavior OF ContadorEventos_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ContadorEventos
PORT(
clk : IN std_logic;
reset : IN std_logic;
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal q : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ContadorEventos PORT MAP (
clk => clk,
reset => reset,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
reset <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;
END;
|
gpl-2.0
|
f4a307d5cfe24fa4aab299ae3e33e35b
| 0.593176 | 4.14882 | false | true | false | false |
scottlbaker/Nova-SOC
|
src/soc.vhd
| 1 | 18,101 |
--========================================================================
-- soc.vhd :: Nova SOC for Latice experiments
--
-- contains:
--
-- (1) Nova core
-- (1) UART
-- (1) timer
-- (1) random number generator
-- (1) Digital I/O
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity SOC is
port (
-- Output Port A
PORTA : out std_logic_vector(7 downto 0);
-- UART
UART_RXD : in std_logic; -- receive data
UART_TXD : out std_logic; -- transmit data
-- Reset and Clock
SYSRESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end SOC;
architecture BEHAVIORAL of SOC is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
signal ADDR_15 : std_logic_vector(15 downto 1); -- for debug only
signal ADDR_OUT : std_logic_vector(15 downto 0);
signal DATA_IX : std_logic_vector(15 downto 0);
signal DATA_OX : std_logic_vector(15 downto 0);
signal DEVCODE : std_logic_vector( 5 downto 0);
signal IMSK_REG : std_logic_vector( 7 downto 0);
signal ISRC : std_logic_vector( 7 downto 0);
signal PHASE : std_logic_vector( 3 downto 0);
signal IO_RESET : std_logic; -- I/O reset (active high)
signal RESET1 : std_logic; -- short reset (active low)
signal RESET : std_logic; -- long reset (active low)
signal RW : std_logic; -- Mem 1==read 0==write
signal IORW : std_logic; -- I/O 1==read 0==write
signal IOM : std_logic; -- 1==I/O 0==memory
signal PWR_GOOD : std_logic; -- Power good
signal RDY : std_logic; -- Ready/Wait
signal BYTEOP : std_logic; -- byte operation
signal SYNC : std_logic; -- Opcode fetch status
signal FEN : std_logic; -- clock enable
signal BOOT_RE : std_logic; -- Boot RAM read enable
signal BOOT_WE : std_logic; -- Boot RAM write enable
signal IO_WE : std_logic; -- IO write enable
signal TIMR_IRQ : std_logic; -- Timer interrupt
signal UART_RRQ : std_logic; -- UART receive interrupt
signal UART_TRQ : std_logic; -- UART transmit interrupt
signal UART_RD : std_logic; -- UART read data valid
signal IRQ : std_logic; -- Interrupt (active-low)
signal TIMR_DATA : std_logic_vector(15 downto 0);
signal BOOT_DATA : std_logic_vector(15 downto 0);
signal UART_DATA : std_logic_vector( 7 downto 0);
signal PRTA_DATA : std_logic_vector( 7 downto 0);
signal RAND_DATA : std_logic_vector( 7 downto 0);
signal UART_CS : std_logic;
signal TIMR_CS : std_logic;
signal PRTA_CS : std_logic;
signal IMSK_CS : std_logic;
signal RAND_CS : std_logic;
signal DBUG1 : std_logic; -- for debug
signal DBUG2 : std_logic; -- for debug
signal DBUG3 : std_logic; -- for debug
signal DBUG4 : std_logic; -- for debug
signal DBUG5 : std_logic; -- for debug
signal DBUG6 : std_logic; -- for debug
signal DBUG7 : std_logic; -- for debug
--================================================================
-- Constant definition section
--================================================================
-- $0000 -> $3FFF Boot RAM (8kx16)
constant BOOT_SEL : std_logic_vector(15 downto 14) := "00";
-- $10 -> $17 UART registers
constant UART_SEL : std_logic_vector(5 downto 3) := "001";
-- $20 -> $21 Timer registers
constant TIMR_SEL : std_logic_vector(5 downto 1) := "01000";
-- $22 Output Register
constant PRTA_SEL : std_logic_vector(5 downto 0) := "010010";
-- $23 Interrupt mask register
constant IMSK_SEL : std_logic_vector(5 downto 0) := "010011";
-- $24 -> $25 Random number generator
constant RAND_SEL : std_logic_vector(5 downto 1) := "01010";
-- $26 Interrupt source register
constant ISRC_SEL : std_logic_vector(5 downto 0) := "010110";
--================================================================
-- Component definition section
--================================================================
--==================================
-- Nova
--==================================
component IP_NOVA
port (
ADDR_15 : out std_logic_vector(15 downto 1); -- for debug only
ADDR_OUT : out std_logic_vector(15 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
DEVCODE : out std_logic_vector( 5 downto 0);
R_W : out std_logic; -- Mem 1==read 0==write
IORW : out std_logic; -- I/O 1==read 0==write
BYTE : out std_logic; -- Byte memory operation
IOM : out std_logic; -- 1==I/O 0==memory
SYNC : out std_logic; -- Opcode fetch status
IRQ : in std_logic; -- Interrupt Request (active-low)
PWR_GOOD : in std_logic; -- Power good
RDY : in std_logic; -- Ready input
RESET : in std_logic; -- Reset input (active-low)
FEN : in std_logic; -- clock enable
CLK : in std_logic; -- System Clock
DBUG7 : out std_logic; -- for debug
DBUG6 : out std_logic; -- for debug
DBUG5 : out std_logic; -- for debug
DBUG4 : out std_logic; -- for debug
DBUG3 : out std_logic; -- for debug
DBUG2 : out std_logic; -- for debug
DBUG1 : out std_logic -- for debug
);
end component;
--===============================
-- UART (no handshake lines)
--===============================
component UART
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
REG_SEL : in std_logic_vector( 1 downto 0); -- register select
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector( 7 downto 0); -- read data
RX_IRQ : out std_logic; -- RX interrupt req
TX_IRQ : out std_logic; -- TX interrupt req
RXD : in std_logic; -- received data
TXD : out std_logic; -- transmit data
RESET : in std_logic; -- system reset
RDV : in std_logic; -- read data valid
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Timer
--==============================
component TIMER
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector(15 downto 0); -- read data
IRQ : out std_logic; -- DMA Interrupt
SEL_IC : in std_logic; -- select initial count
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Random Number Generator
--==============================
component RAND8
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
REG_SEL : in std_logic; -- register select
WR_DATA : in std_logic_vector(7 downto 0); -- write data
RD_DATA : out std_logic_vector(7 downto 0); -- read data
RESET : in std_logic; -- system reset
FEN : in std_logic; -- clock enable
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Output Port
--==============================
component OUTPORT
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(7 downto 0); -- data in
RD_DATA : out std_logic_vector(7 downto 0); -- data out
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--=========================================
-- Boot RAM (8kx16)
--=========================================
component RAM
port (
RADDR : in std_logic_vector(12 downto 0);
WADDR : in std_logic_vector(12 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
BYTEOP : in std_logic; -- byte operation
REN : in std_logic; -- read enable
WEN : in std_logic; -- write enable
WCLK : in std_logic;
RCLK : in std_logic
);
end component;
--=========================================
-- Debounce and Sync Reset
--=========================================
component XRESET
port (
RST_OUT1 : out std_logic;
RST_OUT2 : out std_logic;
RST_IN : in std_logic;
CLK : in std_logic
);
end component;
begin
--=============================================
-- Clock Phase Divider (divide by 4)
-- S0=000 S1=001 S2=010 S3=100
--=============================================
CLOCK_PHASE_DIVIDER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- count
PHASE <= PHASE(2 downto 0) & PHASE(3);
-- reset state
if (RESET1 = '0') then
PHASE <= "0001";
end if;
end if;
end process;
--==========================================================
-- System Clock Enable
--==========================================================
SYSTEM_CLOCK_ENABLE:
process(FCLK)
begin
if (FCLK = '1' and FCLK'event) then
FEN <= PHASE(3);
end if;
end process;
--==========================================================
-- Address Decoder
--==========================================================
ADDRESS_DECODER:
process(ADDR_OUT, UART_DATA, TIMR_DATA, PRTA_DATA, ISRC,
IMSK_REG, RAND_DATA, BOOT_DATA, PHASE, RW, IORW,
IOM, DEVCODE)
begin
UART_CS <= '0';
TIMR_CS <= '0';
PRTA_CS <= '0';
IMSK_CS <= '0';
RAND_CS <= '0';
BOOT_RE <= '0';
BOOT_WE <= '0';
IO_WE <= '0';
UART_RD <= '0';
DATA_IX <= BOOT_DATA;
-- Boot RAM
if (ADDR_OUT(15 downto 14) = BOOT_SEL) then
BOOT_RE <= PHASE(0) and RW;
BOOT_WE <= PHASE(3) and not RW;
end if;
-- UART registers
if ((IOM = '1') and (DEVCODE(5 downto 3) = UART_SEL)) then
UART_CS <= '1';
DATA_IX <= "00000000" & UART_DATA;
UART_RD <= PHASE(3) and IORW;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Timer registers
if ((IOM = '1') and (DEVCODE(5 downto 1) = TIMR_SEL)) then
TIMR_CS <= '1';
DATA_IX <= TIMR_DATA;
IO_WE <= PHASE(3) and not IORW;
end if;
-- output Port
if ((IOM = '1') and (DEVCODE(5 downto 0) = PRTA_SEL)) then
PRTA_CS <= '1';
DATA_IX <= "00000000" & PRTA_DATA;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Interrupt Mask register
if ((IOM = '1') and (DEVCODE(5 downto 0) = IMSK_SEL)) then
IMSK_CS <= '1';
DATA_IX <= "00000000" & IMSK_REG;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Interrupt Source register
if ((IOM = '1') and (DEVCODE(5 downto 0) = ISRC_SEL)) then
DATA_IX <= "00000000" & ISRC;
IO_WE <= PHASE(3) and not IORW;
end if;
-- Random Number registers
if ((IOM = '1') and (DEVCODE(5 downto 1) = RAND_SEL)) then
RAND_CS <= '1';
DATA_IX <= "00000000" & RAND_DATA;
IO_WE <= PHASE(3) and not IORW;
end if;
end process;
RDY <= '1'; -- Ready
IO_RESET <= not RESET;
PORTA <= PRTA_DATA;
PWR_GOOD <= '1';
--================================================
-- Interrupt mask register
--================================================
INTERRUPT_MASK_REGISTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((IMSK_CS = '1') and (IO_WE = '1')) then
IMSK_REG <= DATA_OX(7 downto 0);
end if;
-- reset state
if (RESET = '0') then
IMSK_REG <= (others => '0');
end if;
end if;
end process;
--================================================
-- Interrupt Source
--================================================
ISRC <= "00000" & UART_TRQ & UART_RRQ & TIMR_IRQ;
IRQ <= not ((IMSK_REG(7) and ISRC(7)) or
(IMSK_REG(6) and ISRC(6)) or
(IMSK_REG(5) and ISRC(5)) or
(IMSK_REG(4) and ISRC(4)) or
(IMSK_REG(3) and ISRC(3)) or
(IMSK_REG(2) and ISRC(2)) or
(IMSK_REG(1) and ISRC(1)) or
(IMSK_REG(0) and ISRC(0)));
--=========================================
-- Instantiate the nova
--=========================================
UPROC:
IP_NOVA port map (
ADDR_15 => ADDR_15,
ADDR_OUT => ADDR_OUT,
DATA_IN => DATA_IX,
DATA_OUT => DATA_OX,
DEVCODE => DEVCODE,
R_W => RW,
IORW => IORW,
BYTE => BYTEOP,
IOM => IOM,
SYNC => SYNC,
IRQ => IRQ,
PWR_GOOD => PWR_GOOD,
RDY => RDY,
RESET => RESET,
FEN => FEN,
CLK => FCLK,
DBUG7 => DBUG7,
DBUG6 => DBUG6,
DBUG5 => DBUG5,
DBUG4 => DBUG4,
DBUG3 => DBUG3,
DBUG2 => DBUG2,
DBUG1 => DBUG1
);
--===========================================
-- Instantiate the UART
--===========================================
UART1:
UART port map (
CS => UART_CS,
WE => IO_WE,
REG_SEL => DEVCODE(1 downto 0),
WR_DATA => DATA_OX,
RD_DATA => UART_DATA,
RX_IRQ => UART_RRQ,
TX_IRQ => UART_TRQ,
RXD => UART_RXD,
TXD => UART_TXD,
RESET => IO_RESET,
RDV => UART_RD,
FCLK => FCLK
);
--===========================================
-- Instantiate the TIMER
--===========================================
TIMER1:
TIMER port map (
CS => TIMR_CS,
WE => IO_WE,
WR_DATA => DATA_OX,
RD_DATA => TIMR_DATA,
IRQ => TIMR_IRQ,
SEL_IC => DEVCODE(0),
RESET => IO_RESET,
FCLK => FCLK
);
--===========================================
-- Instantiate the OUTPORT
--===========================================
PORT1:
OUTPORT port map (
CS => PRTA_CS,
WE => IO_WE,
WR_DATA => DATA_OX(7 downto 0),
RD_DATA => PRTA_DATA,
RESET => IO_RESET,
FCLK => FCLK
);
--===========================================
-- Instantiate the RAND generator
--===========================================
RAND8X:
RAND8 port map (
CS => RAND_CS,
WE => IO_WE,
REG_SEL => DEVCODE(0),
WR_DATA => DATA_OX(7 downto 0),
RD_DATA => RAND_DATA,
RESET => IO_RESET,
FEN => FEN,
FCLK => FCLK
);
--===========================================
-- Instantiate the BOOT RAM
--===========================================
BOOTRAM:
RAM port map (
RADDR => ADDR_OUT(12 downto 0),
WADDR => ADDR_OUT(12 downto 0),
DATA_IN => DATA_OX,
DATA_OUT => BOOT_DATA,
BYTEOP => BYTEOP,
REN => BOOT_RE,
WEN => BOOT_WE,
WCLK => FCLK,
RCLK => FCLK
);
--=========================================
-- Instantiate the Reset Sync
--=========================================
SDRESET:
XRESET port map (
RST_OUT1 => RESET1, -- short reset
RST_OUT2 => RESET, -- long reset
RST_IN => SYSRESET,
CLK => FCLK
);
end BEHAVIORAL;
|
gpl-3.0
|
83f27b1edb263f75a96d158cacb1c0b6
| 0.398928 | 4.306686 | false | false | false | false |
grafi-tt/Maizul
|
src/Hardware/SRAM.vhd
| 1 | 1,264 |
library ieee;
use ieee.std_logic_1164.all;
entity SRAM is
port (
clk : in std_logic;
load : in boolean;
addr : in std_logic_vector(19 downto 0);
data : inout std_logic_vector(31 downto 0);
clkPin1 : out std_logic;
clkPin2 : out std_logic;
xStorePin : out std_logic;
xMaskPin : out std_logic_vector(3 downto 0);
addrPin : out std_logic_vector(19 downto 0);
dataPin : inout std_logic_vector(31 downto 0);
xEnablePin1 : out std_logic;
enablePin2 : out std_logic;
xEnablePin3 : out std_logic;
xOutEnablePin : out std_logic;
xClkEnablePin : out std_logic;
advancePin : out std_logic;
xLinearOrderPin : out std_logic;
sleepPin : out std_logic;
xFlowThruPin : out std_logic);
end SRAM;
architecture structural of SRAM is
begin
clkPin1 <= clk;
clkPin2 <= clk;
addrPin <= addr;
xStorePin <= '1' when load else '0';
xMaskPin <= "0000";
dataPin <= data;
xEnablePin1 <= '0';
enablePin2 <= '1';
xEnablePin3 <= '0';
xOutEnablePin <= '0';
xClkEnablePin <= '0';
advancePin <= '0';
xLinearOrderPin <= '1';
sleepPin <= '0';
xFlowThruPin <= '1';
end structural;
|
bsd-2-clause
|
f22605129b18e0cd22604d6cd872caf6
| 0.584652 | 3.434783 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/CountEvents.vhd
| 2 | 1,335 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CountEvents is
port(
Entrada: in std_logic;
Reset: in std_logic;
Reset_cont: in std_logic;
Output: out std_logic_vector (31 downto 0));
end CountEvents;
architecture Behavioral of CountEvents is
signal temp: std_logic_vector (31 downto 0);
begin
process(Reset, Entrada, Reset_cont)
begin
if Reset_cont='1' then
temp <= "00000000000000000000000000000000";
elsif Reset='1' then
temp <= "00000000000000000000000000000000";
elsif(Entrada'event and Entrada='1') then
if temp="11111111111111111111111111111111" then
temp<="00000000000000000000000000000000";
else
temp <= temp + 1;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
|
gpl-2.0
|
f65152b3dea0ae932200a23fd53a25d6
| 0.606742 | 4.75089 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/tb/tb_DPHY_LaneSFEN.vhd
| 1 | 7,768 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/04/2016 05:12:32 PM
-- Design Name:
-- Module Name: tb_DPHY_LaneSFEN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
use IEEE.std_logic_textio.all; -- I/O for logic types
library STD;
use STD.textio.all; -- basic I/O
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_DPHY_LaneSFEN is
-- Port ( );
end tb_DPHY_LaneSFEN;
architecture Behavioral of tb_DPHY_LaneSFEN is
component DPHY_LaneSFEN is
Generic (
kCtlClkFreqHz : natural := 100_000_000
);
Port (
aLP : in STD_LOGIC_VECTOR (1 downto 0);
aHS : in STD_LOGIC;
CtlClk : in STD_LOGIC;
SerClkHS : in STD_LOGIC;
DivClk : in STD_LOGIC;
RxByteClkHS : out std_logic;
rbRxDataHS : out std_logic_vector(7 downto 0);
rbRxValidHS : out std_logic;
rbRxActiveHS : out std_logic;
rbRxSyncHS : out std_logic;
rbErrSotHS : out std_logic;
rbErrSotSyncHS : out std_logic;
aEnable : in std_logic; --Enable Lane Module. DivClk&SerClkHS must be stable
aForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
aStopstate : out std_logic --Lane is in Stop state.
);
end component DPHY_LaneSFEN;
function max(l : time; r : time) return time is
begin
if (l > r) then
return l;
else
return r;
end if;
end function max;
constant kSerClkPeriod : time := 2 ns;
constant kCtlClkPeriod : time := 10 ns;
constant kUI : time := kSerClkPeriod / 2;
constant kT_LPX : time := 50 ns;
constant kT_HS_PREPARE : time := 40 ns + 4*kUI;
constant kT_HS_ZERO : time := 100 ns + 6*kUI;
constant kT_HS_TRAIL : time := max(1*8*kUI, 60 ns + 1*4*kUI);
constant kT_HS_EXIT : time := 100 ns;
constant kTInit : time := 100 us;
constant kSyncSeq : std_logic_vector(7 downto 0) := "10111000"; --least significant bit
signal SerClkHS, DivClkHS, CtlClk, cHSClkLocked : std_logic := '1';
signal HS : std_logic;
signal LP : std_logic_vector(1 downto 0);
signal rbRxDataHS : std_logic_vector(7 downto 0);
signal rbRxValidHS, rbRxActiveHS, rbRxSyncHS, rbErrSotHS, rbErrSotSyncHS, aDataStopstate : std_logic;
signal RxByteClkHS : std_logic;
begin
DUT: DPHY_LaneSFEN
Port map (
aLP => LP,
aHS => HS,
CtlClk => CtlClk,
SerClkHS => SerClkHS,
DivClk => DivClkHS,
--PPI
RxByteClkHS => RxByteClkHS,
rbRxDataHS => rbRxDataHS,
rbRxValidHS => rbRxValidHS,
rbRxActiveHS => rbRxActiveHS,
rbRxSyncHS => rbRxSyncHS,
rbErrSotHS => rbErrSotHS,
rbErrSotSyncHS => rbErrSotSyncHS,
aEnable => '1',
aStopstate => aDataStopstate,
aForceRxmode => '0'
);
--Clocks
SerClkHS <= not SerClkHS after kSerClkPeriod / 2;
DivClkHS <= not DivClkHS after kSerClkPeriod / 2 * 4;
CtlClk <= not CtlClk after kCtlClkPeriod / 2;
Stimulus: process
procedure Stopstate(dur : in time) is
begin
LP <= "11";
HS <= 'X';
wait for dur;
end procedure;
procedure HS_Rqst is
begin
LP <= "01";
wait for kT_LPX;
end procedure;
procedure HS_Prepare is
begin
LP <= "00";
wait for kT_HS_PREPARE;
end procedure;
procedure HS_Zero is
begin
HS <= '0';
wait for kT_HS_ZERO;
end procedure;
procedure HS_Send0(nbits : in natural) is
begin
for i in 0 to nbits-1 loop
HS <= '0';
wait until SerClkHS'event;
end loop;
end procedure;
procedure HS_Send(byte : in std_logic_vector(7 downto 0)) is
begin
for i in 0 to 7 loop
wait for kUI / 2; --90deg phase difference between data and clock
HS <= byte(i);
wait until SerClkHS'event;
end loop;
end procedure;
procedure HS_Trail is
begin
wait for kUI / 2;
HS <= not HS;
wait for kT_HS_TRAIL;
end procedure;
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10.0; -- the range of random values created will be 0 to +1000.
variable to_send : natural;
begin
Stopstate(kTInit + 1 us);
for i in 0 to 7 loop
HS_Rqst;
HS_Prepare;
wait for kUI; -- this will test different word alignments
HS_Zero;
wait until Falling_Edge(SerClkHS);
HS_Send(kSyncSeq);
uniform(seed1, seed2, rand); -- generate random number
for j in 0 to integer(rand*range_of_rand) loop
case (j) is
when 0 => HS_Send(x"DE");
when 1 => HS_Send(x"AD");
when 2 => HS_Send(x"BE");
when 3 => HS_Send(x"EF");
when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)));
end case;
end loop;
HS_Trail;
Stopstate(kT_HS_EXIT);
end loop;
wait;
end process Stimulus;
Verification: process (LP, RxByteClkHS)
variable cnt_hs : natural := 0;
variable cnt_byte : natural := 0;
variable bit_last : std_logic := '1';
variable f_err_hold, f_err_temp, f_intrail : boolean := true;
impure function check_data(data : std_logic_vector(7 downto 0); i : natural) return boolean is
begin
if (not f_intrail) then
if (data = (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) &
(not bit_last) & (not bit_last) & (not bit_last) & (not bit_last)) then
f_intrail := true;
else
bit_last := data(7); --least-significant first
end if;
else
if (data /= (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) &
(not bit_last) & (not bit_last) & (not bit_last) & (not bit_last)) then
f_intrail := false;
bit_last := data(7); --least-significant first
end if;
end if;
case (i) is
when 0 => f_err_temp := (data = x"DE");
when 1 => f_err_temp := (data = x"AD");
when 2 => f_err_temp := (data = x"BE");
when 3 => f_err_temp := (data = x"EF");
when others => f_err_temp := (data = std_logic_vector(to_unsigned(i-4, 8)));
end case;
-- Keep the error in mind for later, we might not be in trail after all
if (f_intrail) then
f_err_hold := f_err_hold and f_err_temp;
return true;
else
return f_err_hold and f_err_temp;
end if;
end check_data;
variable my_line : line; -- type 'line' comes from textio
begin
if LP'event and LP = "00" then
cnt_hs := cnt_hs + 1;
cnt_byte := 0;
f_intrail := false;
f_err_hold := true;
bit_last := '1'; --sync sequence last bit
end if;
if LP = "00" and Rising_Edge(RxByteClkHS) then
if rbRxValidHS = '1' then
if not check_data(rbRxDataHS, cnt_byte) then
write(my_line, string'("Error at byte "));
write(my_line, cnt_byte);
write(my_line, string'(", data: "));
hwrite(my_line, rbRxDataHS);
write(my_line, string'(", time: "));
write(my_line, now);
writeline(output, my_line);
end if;
cnt_byte := cnt_byte + 1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
b055b76614c8536896c8a9b749043992
| 0.590628 | 3.596296 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
lab2_one_segment/lab2_one_segment.vhd
| 1 | 1,038 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lab2_one_segment is
Port ( d : in std_logic_vector(3 downto 0);
s : out std_logic_vector(7 downto 0));
end lab2_one_segment;
architecture Behavioral of lab2_one_segment is
begin
S <= "11000000" when D="0000" else
"11111001" when D="0001" else
"10100100" when D="0010" else
"10110000" when D="0011" else
"10011001" when D="0100" else
"10010010" when D="0101" else
"10000010" when D="0110" else
"11111000" when D="0111" else
"10000000" when D="1000" else
"10010000" when D="1001" else
"10001000" when D="1010" else
"10000011" when D="1011" else
"11000110" when D="1100" else
"10100001" when D="1101" else
"10000110" when D="1110" else
"10001110";
end Behavioral;
|
mit
|
c4cfdafdedf14eb51253b42ce60afede
| 0.67052 | 3.174312 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/motor_ascensor.vhd
| 1 | 697 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity motor_ascensor is
PORT(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
accionar_bajar: in STD_LOGIC;
accionar_subir: in STD_LOGIC;
motor_subir: out STD_LOGIC;
motor_bajar: out STD_LOGIC
);
end motor_ascensor;
architecture Behavioral of motor_ascensor is
begin
motor_ascensor:process(RST,CLK)
begin
if (RST='1') then
motor_subir <= '0';
motor_bajar <= '0';
elsif rising_edge(CLK) then
if (accionar_subir ='1') then
motor_subir <= '1';
else motor_subir <= '0';
end if;
if (accionar_bajar ='1') then
motor_bajar <= '1';
else motor_bajar <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
48a61017c8878bd832aaafe79edbf8a9
| 0.64132 | 2.788 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/sim.vhd
| 1 | 2,362 |
--======================================================================
-- sim.vhd :: SOC simulation testbench
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity TEST_TOP is
end TEST_TOP;
architecture BEHAVIORAL of TEST_TOP is
--================================================================
-- Signal and component definition section
--================================================================
-- Output Port A
signal PORTA : std_logic_vector(7 downto 0);
-- UART
signal UART_RXD : std_logic; -- receive data
signal UART_TXD : std_logic; -- transmit data
-- reset and clock
signal RESET : std_logic; -- system reset
signal FCLK : std_logic; -- fast clock
component SOC
port (
-- Output Port A
PORTA : out std_logic_vector(7 downto 0);
-- UART
UART_RXD : in std_logic; -- receive data
UART_TXD : out std_logic; -- transmit data
-- reset and clock
SYSRESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
MAKE_FCLK:
process(FCLK)
begin
if (FCLK = '1') then
FCLK <= '0' after 1 ns;
else
FCLK <= '1' after 1 ns;
end if;
end process;
MAKE_RESET:
process
begin
-- System Reset (active low)
RESET <= '0' after 0 ns, '1' after 10 ns;
wait;
end process;
-- UART_RXD <= '0';
UART_RXD <= UART_TXD; -- HACK for debug !!
--============================================
-- Instantiate the SOC
--============================================
MYSOC:
SOC port map (
PORTA => PORTA,
UART_RXD => UART_RXD,
UART_TXD => UART_TXD,
SYSRESET => RESET,
FCLK => FCLK
);
end BEHAVIORAL;
|
gpl-3.0
|
779380ada259c5cda7d36150c93b739e
| 0.38569 | 5.014862 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/tb/tb_TestTop_all.vhd
| 1 | 9,210 |
-------------------------------------------------------------------------------
--
-- File: tb_TestTop_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to instantiate the tb_TestTop test bench with
-- various options.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDAC.all;
entity tb_TestTop_all is
end tb_TestTop_all;
architecture Behavioral of tb_TestTop_all is
constant kCh1LgMultCoefStatic: std_logic_vector (17 downto 0) := "001110111010000100";
constant kCh1LgAddCoefStatic: std_logic_vector (17 downto 0) := "111111111011001100";
constant kCh1HgMultCoefStatic: std_logic_vector (17 downto 0) := "001111000001111001";
constant kCh1HgAddCoefStatic: std_logic_vector (17 downto 0) := "111111111101111111";
constant kCh2LgMultCoefStatic: std_logic_vector (17 downto 0) := "001110111110000001";
constant kCh2LgAddCoefStatic: std_logic_vector (17 downto 0) := "111111111100001000";
constant kCh2HgAddCoefStatic: std_logic_vector (17 downto 0) := "001111000011010110";
constant kCh2HgMultCoefStatic: std_logic_vector (17 downto 0) := "111111111110111101";
constant kSysClkPeriod : time := 10ns;
constant kDacClkPeriod : time := 10ns;
constant kDAC_Width : integer := 14;
begin
------------------------------------------------------------------------------------------
--Top level component instantiation
------------------------------------------------------------------------------------------
-- Instantiate the top level test bench with dynamic configuration of the scale
-- and calibration coefficients enabled.
InstExtCalibExtScale: entity work.tb_TestTop
Generic Map(
kSysClkPeriod => kSysClkPeriod,
kDacClkPeriod => kDacClkPeriod,
kDAC_Width => kDAC_Width,
kExtCalibEn => true,
kExtCmdInterfaceEn => true,
kExtScaleConfigEn => true,
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCh1ScaleStatic => '0',
kCh2ScaleStatic => '0'
);
-- Instantiate the top level test bench with static configuration of the scale
-- and dynamic configuration of the calibration coefficients.
InstStaticCalibExtScale: entity work.tb_TestTop
Generic Map(
kSysClkPeriod => kSysClkPeriod,
kDacClkPeriod => kDacClkPeriod,
kDAC_Width => kDAC_Width,
kExtCalibEn => false,
kExtCmdInterfaceEn => true,
kExtScaleConfigEn => true,
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCh1ScaleStatic => '0',
kCh2ScaleStatic => '0'
);
-- Instantiate the top level test bench with dynamic configuration of the scale
-- and calibration coefficients disabled. The scale parameter is set to '0' for
-- both channels.
InstStaticCalibStaticScale00: entity work.tb_TestTop
Generic Map(
kSysClkPeriod => kSysClkPeriod,
kDacClkPeriod => kDacClkPeriod,
kDAC_Width => kDAC_Width,
kExtCalibEn => false,
kExtCmdInterfaceEn => true,
kExtScaleConfigEn => false,
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCh1ScaleStatic => '0',
kCh2ScaleStatic => '0'
);
-- Instantiate the top level test bench with dynamic configuration of the scale
-- and calibration coefficients disabled. The scale parameter is set to '1' for
-- both channels.
InstExtCalibStaticScale11: entity work.tb_TestTop
Generic Map(
kSysClkPeriod => kSysClkPeriod,
kDacClkPeriod => kDacClkPeriod,
kDAC_Width => kDAC_Width,
kExtCalibEn => true,
kExtCmdInterfaceEn => true,
kExtScaleConfigEn => false,
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCh1ScaleStatic => '1',
kCh2ScaleStatic => '1'
);
-- Instantiate the top level test bench with dynamic configuration of the scale
-- and calibration coefficients disabled. The scale parameter is set to '0' for
-- channel 1 and to '1' for channel 2.
InstExtCalibStaticScale01: entity work.tb_TestTop
Generic Map(
kSysClkPeriod => kSysClkPeriod,
kDacClkPeriod => kDacClkPeriod,
kDAC_Width => kDAC_Width,
kExtCalibEn => true,
kExtCmdInterfaceEn => true,
kExtScaleConfigEn => false,
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCh1ScaleStatic => '0',
kCh2ScaleStatic => '1'
);
-- Instantiate the top level test bench with dynamic configuration of the scale
-- and calibration coefficients disabled. The scale parameter is set to '1' for
-- channel 1 and to '10' for channel 2.
InstExtCalibStaticScale10: entity work.tb_TestTop
Generic Map(
kSysClkPeriod => kSysClkPeriod,
kDacClkPeriod => kDacClkPeriod,
kDAC_Width => kDAC_Width,
kExtCalibEn => true,
kExtCmdInterfaceEn => true,
kExtScaleConfigEn => false,
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCh1ScaleStatic => '1',
kCh2ScaleStatic => '0'
);
end Behavioral;
|
mit
|
a69044d11424638af40de151372678da
| 0.682736 | 5.105322 | false | true | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/ULPI.vhd
| 2 | 25,696 |
-------------------------------------------------------------------------------
--
-- File: ULPI.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ULPI is
Port (
Ulpi_Clk : in STD_LOGIC; --ULPI input clock. Generated by the USB PHY
reset : in STD_LOGIC; -- Reset siganl from upper layers. Resets all logic in this module
--ULPI Bus
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
u_Ulpi_Reset : out STD_LOGIC;
--Command signals for ULPI State machine
u_Send_NOOP_CMD : in STD_LOGIC;
u_Send_NOPID_CMD : in STD_LOGIC;
u_Send_PID_CMD : in STD_LOGIC;
u_Send_EXTW_CMD : in STD_LOGIC;
u_Send_REGW_CMD : in STD_LOGIC;
u_Send_EXTR_CMD : in STD_LOGIC;
u_Send_REGR_CMD : in STD_LOGIC;
u_Send_STP_CMD : in STD_LOGIC;
u_Send_Last : in STD_LOGIC;
u_Send_Err : in STD_LOGIC;
u_USB_Mode : in STD_LOGIC;
--Interface with upper layers
u_Tx_Data : in STD_LOGIC_VECTOR (7 downto 0); -- packet data to be transmitted
u_Tx_Data_En : out STD_LOGIC; -- data strobe; indicates to the upper layers when to place valid data on tx_data
u_Tx_Pid : in STD_LOGIC_VECTOR (3 downto 0); -- PID field associated with transmit packet (PID) commands
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0); --Register data associated with the REGW, EXTW commands
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0); --Immediate address associated with the REGW, EXTW commands
u_Tx_Cmd_Done : out STD_LOGIC; --NOPID, NOOP, PID, EXTW, REGW, REGR, EXTR command completed, ready for next command
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_CRC16_En : out STD_LOGIC; --indicates to upper layers to consider the current byte as part of the sequence on which CRC16 is computed
u_Ulpi_Dir_Out : out STD_LOGIC;
u_Rx_Data : out STD_LOGIC_VECTOR (7 downto 0); --data received on the ULPI bus
u_Rx_Packet_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Cmd_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Register_Data : out STD_LOGIC_VECTOR (7 downto 0); --Data received in turn of REGR_CMD or EXTW_CMD
u_Rx_Register_Data_Received : out STD_LOGIC; -- indicates if u_Rx_Register_Data is valid
--UTMI+ signals
u_LineState : out STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : out STD_LOGIC_VECTOR (1 downto 0);
u_RxEvent : out STD_LOGIC_VECTOR (1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : out STD_LOGIC;
u_Alt_Int : out STD_LOGIC;
state_ind : out STD_LOGIC_VECTOR(5 downto 0) --for debug purposes
);
end ULPI;
architecture Behavioral of ULPI is
constant TXCMD_NOOP : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant TXCMD_NOPID : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant TXCMD_PID : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant TXCMD_REGR : STD_LOGIC_VECTOR (7 downto 0) := "11101110";
constant TXCMD_REGW : STD_LOGIC_VECTOR (7 downto 0) := "10101110";
constant TXCMD_EXTR : STD_LOGIC_VECTOR (7 downto 0) := "11101111";
constant TXCMD_EXTW : STD_LOGIC_VECTOR (7 downto 0) := "10101111";
type state_type is (IDLE, SEND_STP, REGR_END, FSM_ERROR, ABORT, RECEIVE, PID_CMD, PID_DATA, PID_DATA_LAST, PID_STP, PID_DATA_ERR, PID_WAIT_J1, PID_WAIT_J2, PID_WAIT_FSEOP1, PID_WAIT_FSEOP2, PID_WAIT_HSEOP1, PID_WAIT_HSEOP2, PID_WAIT_EOP, NOPID_CMD, NOPID_DATA, NOPID_DATA_LAST, NOPID_STP, REGR_CMD1, REGR_CMD2, REGR_TURN, REGR_DATA, REGW_CMD, REGW_DATA, REGW_STP, EXTW_CMD, EXTW_ADDR, EXTW_DATA, EXTW_STP, EXTR_CMD1, EXTR_CMD2, EXTR_ADDR, EXTR_TURN, EXTR_DATA, EXTR_STP);
signal u_Ulpi_State, u_Ulpi_Next_State : state_type;
signal u_Ulpi_Dir_q : STD_LOGIC;
signal u_Ulpi_Dir_qq : STD_LOGIC;
signal u_Ulpi_Stp_Fsm : STD_LOGIC;
signal u_Txmux_Out_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Out_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal t_data_debug : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txcmd_Code : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Ctrl_8b_Commands : STD_LOGIC; --used to select TX_CMDs made up of 8 constant bits : NOPID, EXTW, EXTR on ULPI bus
signal u_Txmux_Ctrl_Extreg_Addr : STD_LOGIC; --used to select the extended register address on the ULPI bus
signal u_Txmux_Ctrl_Register_Commands : STD_LOGIC; --used to select REGW and REGR commands on the ULPI bus
signal u_Txmux_Ctrl_Data : STD_LOGIC; --used to select data bytes on ULPI bus
signal u_Txmux_Ctrl_Reg_Data : STD_LOGIC; --used to select the register data to be written on the ULPI bus
signal u_Txmux_Ctrl_PID_Command : STD_LOGIC; --used to select PID commands : 4 constant bits (0100) + 4PID bits on ULPI bus
--signal idle_state : STD_LOGIC;
signal u_Receive_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rx_CMD : STD_LOGIC;
signal u_Rx_CMD_Fsm : STD_LOGIC;
signal u_Reg_Data_Latch: STD_LOGIC;
signal u_Packet_Received: STD_LOGIC;
signal u_Rxdemux_Register_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Receive_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rxdemux_LineState : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_Vbus : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent_q : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_ID : STD_LOGIC;
signal u_Rxdemux_Alt_Int : STD_LOGIC;
signal state_ind_fsm : STD_LOGIC_VECTOR(5 downto 0);
signal debug_clk : STD_LOGIC := '0';
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of state_ind : signal is "true";
--attribute keep of state_ind : signal is "true";
--attribute mark_debug of u_Ulpi_Dir : signal is "true";
--attribute keep of u_Ulpi_Dir : signal is "true";
--attribute mark_debug of u_Ulpi_Nxt : signal is "true";
--attribute keep of u_Ulpi_Nxt : signal is "true";
--attribute mark_debug of u_Ulpi_Stp : signal is "true";
--attribute keep of u_Ulpi_Stp : signal is "true";
--attribute mark_debug of u_Receive_Data_q : signal is "true";
--attribute keep of u_Receive_Data_q : signal is "true";
--attribute mark_debug of u_Txmux_Out_Data_q : signal is "true";
--attribute keep of u_Txmux_Out_Data_q : signal is "true";
--attribute mark_debug of u_Ulpi_Stp_Fsm : signal is "true";
--attribute keep of u_Ulpi_Stp_Fsm : signal is "true";
--attribute mark_debug of debug_clk : signal is "true";
--attribute keep of debug_clk : signal is "true";
begin
u_Ulpi_Reset <= reset;
u_Ulpi_Dir_Out <= u_Ulpi_Dir_q;
u_Rx_Register_Data_Received <= u_Reg_Data_Latch;
u_Rx_Data <= u_Receive_Data_q;
u_Rx_Register_Data <= u_Rxdemux_Register_Data;
--rx_en <= rx_data_en;
u_Rxdemux_LineState <= u_Receive_Data(1 downto 0);
u_Rxdemux_Vbus <= u_Receive_Data(3 downto 2);
u_Rxdemux_RxEvent <= u_Receive_Data(5 downto 4);
u_RxEvent <= u_Rxdemux_RxEvent_q;
u_Rxdemux_ID <= u_Receive_Data(6);
u_Rxdemux_Alt_Int <= u_Receive_Data(7);
bidirbuf: for i in 0 to 7 generate
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => u_Receive_Data(i), -- Buffer output
IO => u_Ulpi_Data(i), -- Buffer inout port (connect directly to top-level port)
I => u_Txmux_Out_Data_q(i), -- Buffer input
T => u_Ulpi_Dir_q -- 3-state enable input, high=input, low=output
);
end generate;
--decide if rx_data carries data/RXCMD
u_Packet_Received <= u_Ulpi_Dir and u_Ulpi_Nxt;
u_Rx_CMD <= (u_Ulpi_Dir_q and u_Ulpi_Dir) and (not u_Ulpi_Nxt);
RXACTIVE_PROC: process (Ulpi_Clk, u_Packet_Received, u_Rxdemux_RxEvent_q, u_Ulpi_Dir_q)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0' or u_Ulpi_Dir = '0') then
u_RxActive <= '0';
elsif (u_Ulpi_Dir_q = '1' and u_Packet_Received = '1') then
u_RxActive <= '1';
end if;
end if;
end process;
STATE_CHANGE: process (Ulpi_Clk) --For debug purposes
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
debug_clk <= not debug_clk;
end if;
end process;
--ULPI output signals are registered
DATA_STP_Q_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Txmux_Out_Data_q <= (others => '0');
u_Ulpi_Stp <= '0';
else
u_Ulpi_Stp <= u_Ulpi_Stp_Fsm;
u_Txmux_Out_Data_q <= u_Txmux_Out_Data;
end if;
end if;
end process;
--register receive data/control signals (outputs to upper layers)
RX_Q_PROC: process(Ulpi_Clk)
begin
if(Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Rx_Cmd_Received <= '0';
u_Ulpi_Dir_q <= '0';
u_Ulpi_Dir_qq <= '0';
u_Rx_Packet_Received <= '0';
u_Receive_Data_q <= (others => '0');
u_LineState <= (others => '0');
u_Vbus <= (others => '0');
u_Rxdemux_RxEvent_q <= (others => '0');
u_ID <= '0';
u_Alt_Int <= '0';
u_Rxdemux_Register_Data <= (others => '0');
t_data_debug <= (others => '0');
else
t_data_debug <= u_Txmux_Out_Data;
u_Rx_Cmd_Received <= u_Rx_CMD;
u_Ulpi_Dir_q <= u_Ulpi_Dir;
u_Ulpi_Dir_qq <= u_Ulpi_Dir_q;
u_Rx_Packet_Received <= u_Packet_Received;
u_Receive_Data_q <= u_Receive_Data;
if((u_Rx_CMD = '1') and (u_Rx_CMD_Fsm = '1')) then
u_LineState <= u_Rxdemux_LineState;
u_Vbus <= u_Rxdemux_Vbus;
u_Rxdemux_RxEvent_q <= u_Rxdemux_RxEvent;
u_ID <= u_Rxdemux_ID;
u_Alt_Int <= u_Rxdemux_Alt_Int;
elsif ( u_Reg_Data_Latch = '1') then
u_Rxdemux_Register_Data <= u_Receive_Data;
end if;
end if;
end if;
end process;
--Combinational process that selects the byte to be placed on the ULPI data bus
--It can be a TX Command, Packet Data, PID, Register Address, Register Data
TXMUX_PROC: process(Ulpi_Clk, u_Txmux_Ctrl_Data, u_Txmux_Ctrl_Extreg_Addr, u_Txmux_Ctrl_PID_Command, u_Txmux_Ctrl_8b_Commands, u_Txmux_Ctrl_Register_Commands, u_Tx_Data, u_Tx_Pid, u_Txcmd_Code, u_Tx_Reg_Addr, u_Txmux_Ctrl_Reg_Data, u_Tx_Regw_Data)
begin
if(u_Txmux_Ctrl_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Data;
elsif (u_Txmux_Ctrl_PID_Command = '1') then
u_Txmux_Out_Data(3 downto 0) <= u_Tx_Pid;
u_Txmux_Out_Data(7 downto 4) <= TXCMD_PID;
elsif (u_Txmux_Ctrl_8b_Commands = '1') then
u_Txmux_Out_Data <= u_Txcmd_Code;
elsif (u_Txmux_Ctrl_Register_Commands = '1') then
u_Txmux_Out_Data(7 downto 6) <= u_Txcmd_Code(7 downto 6);
u_Txmux_Out_Data(5 downto 0) <= u_Tx_Reg_Addr(5 downto 0);
elsif (u_Txmux_Ctrl_Extreg_Addr = '1') then
u_Txmux_Out_Data <= u_Tx_Reg_Addr;
elsif (u_Txmux_Ctrl_Reg_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Regw_Data;
else
u_Txmux_Out_Data <= (others => '0');
end if;
end process;
-- ULPI State Machine. Implements the framework required for transmit commands( NOPID,
-- PID, EXTW, REGW, EXTR, REGR) and decodes received data
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Ulpi_State <= IDLE;
state_ind <= (others => '0');
else
u_Ulpi_State <= u_Ulpi_Next_State;
state_ind <= state_ind_fsm;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Ulpi_State, u_Ulpi_Dir_q, u_Receive_Data_q ,u_Rx_CMD, u_Send_Last, u_Send_Err, u_Ulpi_Dir, u_Ulpi_Dir_qq, u_USB_Mode, u_Receive_Data, u_Ulpi_Nxt, u_Send_NOPID_CMD, u_Send_PID_CMD,u_Send_REGW_CMD,u_Send_EXTW_CMD,u_Send_REGR_CMD,u_Send_EXTR_CMD,u_Send_NOOP_CMD, u_Send_STP_CMD)
begin
--declare default state for next_state to avoid latches
u_Ulpi_Next_State <= u_Ulpi_State;
state_ind_fsm <= "000000";
u_Ulpi_Stp_Fsm <= '0';
u_Txmux_Ctrl_Data <= '0';
u_Txmux_Ctrl_Reg_Data <= '0';
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Register_Commands <= '0';
u_Tx_Data_En <= '0';
u_Txmux_Ctrl_PID_Command <= '0';
u_Txcmd_Code <= (others => '0');
u_Rx_CMD_Fsm <= '0';
u_Tx_Cmd_Done <= '0';
u_CRC16_En <= '0';
u_Txmux_Ctrl_Extreg_Addr <= '0';
u_Reg_Data_Latch <= '0';
u_Tx_Pid_Phase_Done <= '0';
case (u_Ulpi_State) is
when IDLE =>
state_ind_fsm <= "000000";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= (others => '0');
if ( u_Ulpi_Dir = '0') then
if(u_Send_NOPID_CMD = '1') then
u_Ulpi_Next_State <= NOPID_CMD;
elsif (u_Send_PID_CMD = '1') then
u_Ulpi_Next_State <= PID_CMD;
elsif (u_Send_REGW_CMD = '1') then
u_Ulpi_Next_State <= REGW_CMD;
elsif (u_Send_EXTW_CMD = '1') then
u_Ulpi_Next_State <= EXTW_CMD;
elsif (u_Send_REGR_CMD = '1') then
u_Ulpi_Next_State <= REGR_CMD1;
elsif (u_Send_EXTR_CMD = '1') then
u_Ulpi_Next_State <= EXTR_CMD1;
elsif (u_Send_NOOP_CMD = '1') then
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= IDLE;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
--SEND PID_CMD -- No support for packet abort
when PID_CMD =>
state_ind_fsm <= "000001";
u_Txmux_Ctrl_PID_Command <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_PID_Command <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Tx_Data_En <= '1';
u_CRC16_En <= '1';
if (u_Send_Last = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
else
u_Tx_Pid_Phase_Done <= '1';
u_Ulpi_Next_State <= PID_DATA;
end if;
end if;
when PID_DATA =>
state_ind_fsm <= "000010";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_CRC16_En <= '1';
u_Tx_Data_En <= '1';
if (u_Send_Last = '1') then
if (u_Send_Err = '0') then
u_Ulpi_Next_State <= PID_DATA_LAST;
else
u_Ulpi_Next_State <= PID_DATA_ERR;
end if;
end if;
else
u_Tx_Data_En <= '0';
end if;
when PID_DATA_LAST =>
state_ind_fsm <= "000011";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Data <= '0';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
end if;
when PID_STP =>
state_ind_fsm <= "000100";
u_Ulpi_Next_State <= PID_WAIT_EOP;
when PID_WAIT_EOP =>
state_ind_fsm <= "000101";
--if(ulpi_dir = '1') then
if(u_USB_Mode = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
else
u_Ulpi_Next_State <= PID_WAIT_FSEOP1;
end if;
--end if;
when PID_WAIT_HSEOP1 =>
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP2;
end if;
when PID_WAIT_HSEOP2 =>
state_ind_fsm <= "000110";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data(1 downto 0) = "00") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
end if;
end if;
when PID_WAIT_FSEOP1 =>
state_ind_fsm <= "000111";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_FSEOP2;
end if;
when PID_WAIT_FSEOP2 =>
state_ind_fsm <= "001000";
if(u_Ulpi_Dir_qq = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data_q(1 downto 0) = "00") then
u_Ulpi_Next_State <= PID_WAIT_J1;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
end if;
when PID_WAIT_J1 =>
state_ind_fsm <= "001001";
if (u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_J2;
end if;
when PID_WAIT_J2 =>
state_ind_fsm <= "001010";
if(u_Receive_Data_q(1 downto 0) = "01") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
when PID_DATA_ERR =>
state_ind_fsm <= "001011";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Txcmd_Code <= (others => '1');
u_Txmux_Ctrl_8b_Commands <= '1';
u_Ulpi_Next_State <= IDLE; --The link must wait for an RX_CMD indicating a SE0 to J transition before transmitting another packet : Not implemented
--SEND NOPID
when NOPID_CMD =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001100";
u_Txcmd_Code <= TXCMD_NOPID;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Next_State <= NOPID_DATA;
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when NOPID_DATA =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001101";
u_Txmux_Ctrl_Data <= '1';
if (u_Ulpi_Nxt = '1') then
if (u_Send_Last = '1') then
u_Ulpi_Next_State <= NOPID_DATA_LAST;
end if;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_DATA_LAST =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001110";
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= NOPID_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_STP =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001111";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGW
when REGW_CMD =>
state_ind_fsm <= "010000";
u_Txcmd_Code <= TXCMD_REGW;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= REGW_DATA;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_DATA =>
state_ind_fsm <= "010001";
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= REGW_STP;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_STP =>
state_ind_fsm <= "010010";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
--SEND EXTW Not Working!
when EXTW_CMD =>
state_ind_fsm <= "010011";
u_Txcmd_Code <= TXCMD_EXTW;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTW_ADDR;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_ADDR =>
state_ind_fsm <= "010100";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTW_DATA;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_DATA =>
state_ind_fsm <= "010101";
if (u_Ulpi_Dir = '0') then
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= EXTW_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_STP =>
state_ind_fsm <= "010110";
if (u_Ulpi_Dir = '0') then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
u_Ulpi_Stp_Fsm <= '1';
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGR
when REGR_CMD1 =>
state_ind_fsm <= "010111";
u_Txcmd_Code <= TXCMD_REGR;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Ulpi_Next_State <= REGR_TURN;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_TURN =>
state_ind_fsm <= "011000";
if(u_Ulpi_Dir = '1') then
if(u_Ulpi_Nxt = '0') then
u_Reg_Data_Latch <= '1';
u_Ulpi_Next_State <= REGR_DATA;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
end if;
when REGR_DATA =>
state_ind_fsm <= "011010";
if(u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= REGR_END;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_END =>
u_Tx_Cmd_Done <= '1';
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
--SEND EXTR Not Working!
when EXTR_CMD1 =>
state_ind_fsm <= "011011";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= TXCMD_EXTR;
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTR_ADDR;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_ADDR =>
state_ind_fsm <= "011101";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTR_TURN;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_TURN =>
state_ind_fsm <= "011110";
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= EXTR_DATA;
end if;
when EXTR_DATA =>
state_ind_fsm <= "011111";
u_Tx_Cmd_Done <= '1';
u_Reg_Data_Latch <= '1';
if (u_Ulpi_Nxt = '0') then
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
end if;
--ABORT
when ABORT =>
state_ind_fsm <= "100000";
u_Ulpi_Next_State <= IDLE;
when SEND_STP =>
state_ind_fsm <= "100010";
u_Ulpi_Stp_Fsm <= '1';
if (u_Ulpi_Dir_q = '0') then
u_Ulpi_Next_State <= IDLE;
end if;
--RECEIVE
when RECEIVE =>
state_ind_fsm <= "100001";
if(u_Ulpi_Dir = '1') then
if (u_Send_STP_CMD = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= SEND_STP;
elsif(u_Rx_CMD = '1') then
u_Rx_CMD_Fsm <= '1';
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when others =>
u_Ulpi_Next_State <= IDLE;
end case;
end process;
end Behavioral;
|
mit
|
00c7f3101aeb12c08359852bdc888690
| 0.561294 | 3.156757 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/antirrebote.vhd
| 1 | 1,671 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity antirrebote is
Port ( CLK : in STD_LOGIC; --Entrada de reloj sin pasar por el divisor
RST : in STD_LOGIC;
logic_IN : in STD_LOGIC;
logic_OUT : out STD_LOGIC);
end antirrebote;
architecture Behavioral of antirrebote is
constant contador_SIZE : integer := 20; --tamaño del contador (Para 50MHz: 19, 10ms - 20, 20ms - 21, 42ms - 22, 84ms)
signal logic_prev : std_logic := '0'; --almacena estado del boton, se usa como variable de transicion
signal contador : std_logic_vector(contador_SIZE downto 0) := (others => '0'); --vector contador para que pase el tiempo antirrebote
begin
process(CLK,RST,logic_IN)
begin
if (RST='1') then
logic_OUT <= logic_IN;
elsif (CLK'event and CLK='1') then --Si hay flanco de reloj
if (logic_prev XOR logic_in)='1' then --Si la entrada es diferente al estado previo almacenado
contador <= (others => '0'); --Contador a cero
logic_prev <= logic_in; --La entrada pasa a la variable de transicion
elsif (contador(contador_SIZE) = '0') then --Si la entrada es igual a la variable de transicion y el contador no esta lleno
contador <= std_logic_vector(UNSIGNED(contador) + 1); --Sumamos 1 al contador
else --Si la entrada es igual a la variable de transicion y el contador esta lleno
logic_out <= logic_prev; --Pasamos la variable de transicion a la salida
end if;
end if;
end process;
end Behavioral;
--El tiempo antirrebote dependerá del tamaño n del contador y de la frecuencia f segun (2^n)/f
|
gpl-3.0
|
89828b60e63c3988dd2f2f3a66673752
| 0.658288 | 3.5629 | false | false | false | false |
hangmann/fpga-heater
|
heat_core_v1_00_a/hdl/vhdl/user_logic.vhd
| 1 | 8,964 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.ALL;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library unisim;
use UNISIM.VComponents.all;
entity user_logic is
generic
(
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 8;
C_NUM_LUTS : integer := 1024
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute keep_hierarchy : string;
attribute keep_hierarchy of user_logic : entity is "true";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 7);
signal slv_reg_read_sel : std_logic_vector(0 to 7);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal offset : integer;
constant C_MAX_OFFSET : integer := C_NUM_LUTS - 31;
component lut_oscilator is
Port ( en : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal inout_bit : std_logic;
signal inout_vector : std_logic_vector (C_NUM_LUTS downto 0) := (others=>'0');
signal and_value : std_logic;
signal direction : std_logic_vector(32 downto 0) := (others => '0');
attribute keep : string;
attribute keep of inout_vector : signal is "true";
attribute keep of IMP : architecture is "true";
signal adjust : std_logic_vector (31 downto 0);
signal adjust_heaters : std_logic_vector (31 downto 0) := (others => '0');
constant block_items : integer := C_NUM_LUTS / 32;
signal enable_heater : std_logic;
signal enable_vector : std_logic_vector (C_NUM_LUTS - 1 downto 0);
signal j : integer := 0;
signal enabled_count : integer := 0;
signal temp : std_logic_vector (5 downto 0);
signal enable_count : std_logic_vector (31 downto 0);
signal int_adjust : integer := 0;
signal adjust_temp : integer;
begin
adjust_heaters <= slv_reg1;
init_proc : process( adjust_heaters, enable_heater ) is
begin
for i in 0 to 31 loop
for j in 0 to block_items - 1 loop
enable_vector(block_items * i + j) <= adjust_heaters(i) and enable_heater;
end loop;
end loop;
end process init_proc;
enable : process ( slv_reg0 ) is
begin
if slv_reg0 = 1 then
enable_heater <= '1';
else
enable_heater <= '0';
end if;
end process enable;
luts : for bit_index in 0 to C_NUM_LUTS - 1 generate
begin
lut_osc : lut_oscilator
port map ( en => enable_vector(bit_index),
Q => inout_vector(bit_index));
end generate luts;
slv_reg_write_sel <= Bus2IP_WrCE(0 to 7);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 7);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
if slv_reg2 = 0 then
adjust_heaters <= adjust_heaters(30 downto 0) & '0';
elsif slv_reg2 = 1 then
adjust_heaters <= '1' & adjust_heaters(31 downto 1);
end if;
when "00100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
offset <= conv_integer(slv_reg3);
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7 ) is
begin
case slv_reg_read_sel is
when "10000000" => slv_ip2bus_data <= "0000000000000000000000000000000" & enable_heater;
when "01000000" => slv_ip2bus_data <= adjust_heaters;
when "00100000" => slv_ip2bus_data <= slv_reg2;
when "00010000" => slv_ip2bus_data <= slv_reg3;
when "00001000" => slv_ip2bus_data <= slv_reg4;
when "00000100" => slv_ip2bus_data <= slv_reg5;
when "00000010" => slv_ip2bus_data <= slv_reg6;
when "00000001" => slv_ip2bus_data <= inout_vector(C_NUM_LUTS - offset - 1 downto C_NUM_LUTS - offset - 32);
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
mit
|
0f33c51c9ee0fce6260edba8b06bec1f
| 0.546743 | 3.182109 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/DPHY_LaneSFEN.vhd
| 1 | 12,820 |
-------------------------------------------------------------------------------
--
-- File: DPHY_LaneSFEN.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements a MIPI D-PHY 1.0 CIL-SFEN lane: slave (receiver),
-- forward high-speed, events forward escape mode (future work), no reverse
-- direction. It is architecture-independent by itself, but the instantiated
-- HS-Deserializer has its own requirements. The D-PHY physical interface is
-- assumed to be de-multiplexed into low-power LP(1:0) and high-speed HS inputs
-- by external circuitry (outside the FPGA). On the logic side data is forwarded
-- via the PPI interface as described in the D-PHY spec Annex A.
-- This data lane module requires high-speed serial and divided parallel clocks
-- as provided by the accompanying SCNN clock lane module.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
use work.DebugLib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DPHY_LaneSFEN is
Generic (
kRefClkFreqHz : natural := 200_000_000;
kAddDelay_ps : integer := 0;
kNoLP : boolean := false
);
Port (
dLP0_in : in std_logic_vector(7 downto 0);
dLP1_in : in std_logic_vector(7 downto 0);
dLP0_out : out std_logic_vector(7 downto 0);
dLP1_out : out std_logic_vector(7 downto 0);
cLP_in : in STD_LOGIC_VECTOR (1 downto 0);
cLP_out : out STD_LOGIC_VECTOR (1 downto 0);
aLP : in STD_LOGIC_VECTOR (1 downto 0);
aHS : in STD_LOGIC;
RefClk : in STD_LOGIC;
SerClkHS : in STD_LOGIC;
DivClk : in STD_LOGIC;
aRxClkActiveHS : in STD_LOGIC;
--PPI
RxByteClkHS : out std_logic;
rbRxDataHS : out std_logic_vector(7 downto 0);
rbRxValidHS : out std_logic;
rbRxActiveHS : out std_logic;
rbRxSyncHS : out std_logic;
rbErrSotHS : out std_logic;
rbErrSotSyncHS : out std_logic;
aEnable : in std_logic; --Enable Lane Module. DivClk&SerClkHS must be stable
aForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
aStopstate : out std_logic; --Lane is in Stop state.
aErrEsc : out std_logic; --Escape Entry Error.
aErrControl : out std_logic; --Control Error.
debug : out DebugSFEN_Type
-- dbg_cIntRst : out std_logic;
-- dbg_cLP : out std_logic_vector(1 downto 0);
-- dbg_state : out std_logic_vector(2 downto 0);
-- dbg_cHSClkRst : out std_logic;
-- dbg_cForceRxmode : out std_logic;
-- dbg_cInitTout : out std_logic;
-- dbg_cHSSettleTout : out std_logic;
-- dbg_cHSSettled : out std_logic;
-- dbg_cHSReset : out std_logic;
-- dbg_dSyncHard : out std_logic;
-- dbg_dSyncSoft : out std_logic;
-- dbg_dSyncErr : out std_logic
);
end DPHY_LaneSFEN;
architecture Behavioral of DPHY_LaneSFEN is
function MAX(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end;
type state_type is (stInitCountDown, stWaitForStop, stStop, stHS_Rqst, stHS_Settle, stHS_Rcv);
signal state, nstate : state_type := stInitCountDown;
alias CtlClk : std_logic is RefClk;
alias kCtlClkFreqHz : natural is kRefClkFreqHz;
signal aLP_int, cLP, cLPGlitch: std_logic_vector(1 downto 0);
constant kTInit : natural := natural(ceil(100.0 * real(kCtlClkFreqHz) / 1_000_000.0)); --100us
constant kTHSSettle : natural := natural(ceil(85.0 * real(kCtlClkFreqHz) / 1_000_000_000.0)); --85ns
constant kTMinRx : natural := natural(ceil(20.0 * real(kCtlClkFreqHz) / 1_000_000_000.0)); --20ns
constant kOffset : natural := 3 + 1 ; -- adjust timeout values above to account for late start due to CtlClk sync
signal cDelayCnt : natural range 0 to MAX(kTInit,kTHSSettle) := 0;
signal cHS_Trail, cHSReset, dDelayCntEn, cDelayCntEn : std_logic;
signal dSyncHard, dSyncSoft, dSyncErr, dIntRst, dHSReset, dStopstate, dValid : std_logic;
signal cEnable, cIntRst, cHSClkRst, cForceRxmode, cInitDone, cHSSettled, cValid : std_logic;
signal cInitTout, cHSSettleTout: std_logic; --CtlClk timeout flags
signal dSyncHard_reg, dSyncSoft_reg, dSyncErr_reg, dInitDone : std_logic; -- for pulse generation
signal dDataOut : std_logic_vector(7 downto 0);
signal aNotEnable, aNotRxClkActiveHS : std_logic;
begin
debug.cIntRst <= cIntRst;
debug.cHSClkRst <= cHSClkRst;
debug.cLP <= cLP;
debug.state <= std_logic_vector(to_unsigned(state_type'pos(state), 3));
debug.cForceRxmode <= cForceRxmode;
debug.cInitTout <= cInitTout;
debug.cHSSettleTout <= cHSSettleTout;
debug.cHSSettled <= cHSSettled;
debug.cHSReset <= cHSReset;
debug.dSyncHard <= dSyncHard;
debug.dSyncSoft <= dSyncSoft;
debug.dSyncErr <= dSyncErr;
SyncAsyncEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aEnable,
OutClk => CtlClk,
oOut => cEnable);
cIntRst <= not cEnable;
aNotRxClkActiveHS <= not aRxClkActiveHS;
RxClkActiveHSResetBridge: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aNotRxClkActiveHS,
OutClk => CtlClk,
oRst => cHSClkRst);
SyncAsyncForceRxMode: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => cIntRst,
aIn => aForceRxmode,
OutClk => CtlClk,
oOut => cForceRxmode);
UseOwnLP: if not kNoLP generate
-- Sync LP with CtlClk
-- T_LPX_min = 50ns = 4*UI_max
-- Synchronizing the LP bits separately is OK, because entering HS is done by
-- LP-11, LP-01, LP-00 sequences, so only one bit changes from one LPX period
-- to another.
-- At the end of HS, LP-00 goes to LP-11, but this is the only valid transition. So
-- spurious LP-01 or LP-10 between them can be ignored, until it stabilizes in LP-11.
GenSyncLP: for i in 0 to 1 generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aLP_int(i),
OutClk => CtlClk,
oOut => cLPGlitch(i));
GlitchFilterLPC: entity work.GlitchFilter
generic map (
kNoOfPeriodsToFilter => kTMinRx)
port map (
SampleClk => CtlClk,
sIn => cLPGlitch(i),
sOut => cLP(i),
sRst => '0');
end generate GenSyncLP;
end generate UseOwnLP;
cLP_out <= cLP;
ShareLPFromOtherLane: if kNoLP generate
cLP <= cLP_in;
end generate ShareLPFromOtherLane;
-- Time delay counter running on CtlClk, because it has a known, fixed frequency
-- We use it to keep track of timing parameters in time units rather than UIs.
DelayCounter: process(CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cDelayCntEn = '0') then
cDelayCnt <= 0;
else
cDelayCnt <= cDelayCnt + 1;
end if;
end if;
end process DelayCounter;
cInitTout <= '1' when cDelayCnt = kTInit else '0';
cHSSettleTout <= '1' when cDelayCnt = kTHSSettle-1 else '0';
--Outputs
cDelayCntEn <= '1' when state = stInitCountDown or nstate = stHS_Settle else
'0';
ModeFSM_SyncProc: process (CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cIntRst = '1') then
state <= stInitCountDown;
else
state <= nstate;
end if;
end if;
end process;
process(CtlClk, cHSClkRst)
begin
if (cHSClkRst = '1') then
cHSReset <= '1';
elsif Rising_Edge(CtlClk) then
if nstate = stHS_Settle then
cHSReset <= '0';
elsif state = stStop and cValid = '0' then
cHSReset <= '1';
end if;
end if;
end process;
process(CtlClk, cHSClkRst)
begin
if (cHSClkRst = '1') then
cHSSettled <= '0';
elsif Rising_Edge(CtlClk) then
if state = stHS_Settle and cHSSettleTout = '1' then
cHSSettled <= '1';
elsif state = stStop and cValid = '0' then
cHSSettled <= '0';
end if;
end if;
end process;
ModeFSM_NextStateProc: process (state, cLP, cInitTout, cForceRxmode, cHSSettleTout)
begin
nstate <= state;
case (state) is
when stInitCountDown =>
if cInitTout = '1' or cForceRxmode = '1' then
nstate <= stWaitForStop;
end if;
when stWaitForStop =>
if cLP = "11" then
nstate <= stStop;
end if;
when stStop =>
if cLP = "01" then -- HS-Rqst
nstate <= stHS_Rqst;
end if;
when stHS_Rqst =>
if cLP = "11" then
nstate <= stStop;
elsif cLP = "00" then
nstate <= stHS_Settle;
end if;
when stHS_Settle =>
if cLP = "11" then
nstate <= stStop;
elsif (cHSSettleTout = '1') then
nstate <= stHS_Rcv;
end if;
when stHS_Rcv =>
if cLP = "11" then
nstate <= stStop;
end if;
when others =>
null;
end case;
end process;
-----------------------------------------------------------------
-- PPI
-----------------------------------------------------------------
aStopstate <= '1' when state = stStop else '0';
RxByteClkHS <= DivClk;
--PPI requires least-significant bit to be the first one received
MakeLSF: for i in rbRxDataHS'range generate
rbRxDataHS(i) <= dDataOut(rbRxDataHS'length-1-i);
end generate MakeLSF;
rbRxValidHS <= dValid;
rbRxActiveHS <= dSyncHard or dSyncSoft;
rbRxSyncHS <= (dSyncHard and not dSyncHard_reg) or (dSyncSoft and not dSyncSoft_reg);
rbErrSotSyncHS <= (dSyncSoft and not dSyncSoft_reg);
rbErrSotHS <= dSyncErr and not dSyncErr_reg;
GenSyncPulse: process(DivClk)
begin
if Rising_Edge(DivClk) then
dSyncHard_reg <= dSyncHard;
dSyncSoft_reg <= dSyncSoft;
dSyncErr_reg <= dSyncErr;
end if;
end process;
HSDeserializerX: entity work.HS_Deserializer
Generic map (
kIs8b9b => false,
kAddDelay_ps => kAddDelay_ps,
kNoLP => kNoLP
)
Port map (
dLP0_in => dLP0_in,
dLP1_in => dLP1_in,
dLP0_out => dLP0_out,
dLP1_out => dLP1_out,
SerClk => SerClkHS,
DivClk => DivClk,
aHSIn => aHS,
aLPIn => aLP,
aLPOut => aLP_int,
dDataOut8 => dDataOut,
dValid => dValid,
dSyncHard => dSyncHard,
dSyncSoft => dSyncSoft,
dSyncErr => dSyncErr,
CtlClk => CtlClk,
cIDLY_LD => '0', --IDELAYE2 Load
cIDLY_CE => '0', --IDELAYE2 CE
cIDLY_INC => '0', --IDELAYE2 Tap Increment
cIDLY_CNT => open, --IDELAYE2 Current Tap Count
aRst => cHSReset,
aSettled => cHSSettled
);
SyncAsyncValid: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => cHSClkRst,
aIn => dValid,
OutClk => CtlClk,
oOut => cValid);
end Behavioral;
|
mit
|
c2b8767d528bef7bf7ba13b914e02766
| 0.618019 | 4.016291 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/alu.vhd
| 1 | 7,792 |
--========================================================================
-- alu.vhd :: Nova 16-bit ALU
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_types.all;
entity ALU is
port (
RBUS : out std_logic_vector(15 downto 0); -- Result bus
CBIT : out std_logic; -- carry status flop
ZBIT : out std_logic; -- zero status flop
ABUS : in std_logic_vector(15 downto 0); -- Src reg
BBUS : in std_logic_vector(15 downto 0); -- Dst reg
ALU_OP : in ALU_OP_TYPE; -- ALU op
SHIFT_CTL : in SHIFT_CTL_TYPE; -- Shifter op
CARRY_CTL : in CARRY_CTL_TYPE; -- ALU op
UPDATE_C : in std_logic; -- update Carry flag
UPDATE_Z : in std_logic; -- update Zero flag
RESTORE : in std_logic; -- restore flags
SET_C : in std_logic; -- load CBIT from ACS(0)
RESET : in std_logic; -- reset
FEN : in std_logic; -- clock enable
CLK : in std_logic -- System clock
);
end ALU;
architecture BEHAVIORAL of ALU is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
-- internal busses
signal AX : std_logic_vector(16 downto 0); -- ALU input A
signal BX : std_logic_vector(16 downto 0); -- ALU input B
signal SUM : std_logic_vector(16 downto 0); -- ALU output
signal SHF : std_logic_vector(15 downto 0); -- shifter output
-- internal carries
signal CIN : std_logic;
signal COUT : std_logic;
signal C16 : std_logic;
signal ZOUT : std_logic;
signal ALU_COUT : std_logic;
signal SHF_COUT : std_logic;
signal CBIT_FF : std_logic;
signal ZBIT_FF : std_logic;
signal OLD_CBIT : std_logic;
signal OLD_ZBIT : std_logic;
begin
--================================================================
-- Start of the behavioral description
--================================================================
--========================
-- ALU Opcode Decoding
--========================
ALU_OPCODE_DECODING:
process(ALU_OP, ABUS, BBUS, C16)
begin
-- default values
AX <= ABUS(15) & ABUS;
BX <= (others => '0');
CIN <= '0';
COUT <= '0';
case ALU_OP is
when NEG => -- 2's complement
AX <= not (ABUS(15) & ABUS);
CIN <= '1';
COUT <= C16;
when COM => -- 1's complement
AX <= not (ABUS(15) & ABUS);
when INC => -- Increment
CIN <= '1';
COUT <= C16;
when DEC => -- Decrement
BX <= (others => '1');
COUT <= C16;
when ADC => -- Add complement
AX <= not (ABUS(15) & ABUS);
BX <= BBUS(15) & BBUS;
COUT <= C16;
when SUB => -- Subtract
AX <= not (ABUS(15) & ABUS);
BX <= BBUS(15) & BBUS;
CIN <= '1';
COUT <= C16;
when ADD => -- Add
BX <= BBUS(15) & BBUS;
COUT <= C16;
when ANA => -- Logical And
BX <= BBUS(15) & BBUS;
when others => -- Transfer A
end case;
end process;
--========================
-- The ALU
--========================
ALU:
process(AX, BX, CIN, ALU_OP)
begin
SUM <= AX + BX + CIN;
if (ALU_OP = ANA) then
SUM <= AX and BX;
end if;
end process;
C16 <= SUM(16) xor AX(16) xor BX(16);
--========================
-- The ALU carry out
--========================
ALU_CARRY_CONTROL:
process(CARRY_CTL, COUT, CBIT_FF)
begin
case CARRY_CTL is
when CLEAR =>
ALU_COUT <= COUT;
when SET =>
ALU_COUT <= not COUT;
when INVERT =>
ALU_COUT <= CBIT_FF xnor COUT;
when others =>
ALU_COUT <= CBIT_FF xor COUT;
end case;
end process;
--========================
-- ALU output shifter
--========================
SHIFT_OPCODE_DECODING:
process(SHIFT_CTL, SUM, ALU_COUT)
begin
case SHIFT_CTL is
when LEFT => -- Rotate left
SHF(15 downto 1) <= SUM(14 downto 0);
SHF(0) <= ALU_COUT;
SHF_COUT <= SUM(15);
when RIGHT => -- Rotate right
SHF(14 downto 0) <= SUM(15 downto 1);
SHF(15) <= ALU_COUT;
SHF_COUT <= SUM(0);
when SWAP => -- Swap bytes
SHF(15 downto 8) <= SUM( 7 downto 0);
SHF( 7 downto 0) <= SUM(15 downto 8);
SHF_COUT <= ALU_COUT;
when others => -- No shift
SHF <= SUM(15 downto 0);
SHF_COUT <= ALU_COUT;
end case;
end process;
RBUS <= SHF;
ZOUT <= not (SHF(15) or SHF(14) or SHF(13) or SHF(12) or
SHF(11) or SHF(10) or SHF( 9) or SHF( 8) or
SHF( 7) or SHF( 6) or SHF( 5) or SHF( 4) or
SHF( 3) or SHF( 2) or SHF( 1) or SHF( 0));
--================================================================
-- carry status flip-flop
--================================================================
CARRY_STATUS_FLOP:
process(RESET, CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (UPDATE_C = '1') then
CBIT_FF <= SHF_COUT;
OLD_CBIT <= CBIT_FF;
end if;
if (RESTORE = '1') then
CBIT_FF <= OLD_CBIT;
end if;
if (SET_C = '1') then
CBIT_FF <= ABUS(15);
end if;
end if;
end if;
-- reset state
if (RESET = '1') then
CBIT_FF <= '0';
OLD_CBIT <= '0';
end if;
end process;
--================================================================
-- zero status flip-flop
--================================================================
ZERO_STATUS_FLOP:
process(RESET, CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (UPDATE_Z = '1') then
ZBIT_FF <= ZOUT;
OLD_ZBIT <= ZBIT_FF;
end if;
if (RESTORE = '1') then
ZBIT_FF <= OLD_ZBIT;
end if;
end if;
end if;
-- reset state
if (RESET = '1') then
ZBIT_FF <= '0';
OLD_ZBIT <= '0';
end if;
end process;
CBIT <= CBIT_FF;
ZBIT <= ZBIT_FF;
end BEHAVIORAL;
|
gpl-3.0
|
89823602d6f07df034377e4ba89e65cf
| 0.36114 | 4.54344 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fmul.vhd
| 1 | 2,876 |
-- written by panooz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity fmul is
port (
clk : in std_logic;
go_in : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
go_out : out std_logic);
end fmul;
architecture blackbox of fmul is
function "sra"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
begin
if (shift /= 0) then
for i in 1 to shift loop
ret := '0' & ret(val'high downto val'low+1);
end loop;
end if;
return ret;
end;
function "sla"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
begin
if (shift /= 0) then
for i in 1 to shift loop
ret := ret(val'high-1 downto val'low) & '0';
end loop;
end if;
return ret;
end;
signal state : std_logic_vector(3 downto 0) := "0000";
signal temp : std_logic_vector(47 downto 0);
signal c_sign : std_logic;
signal c_exp : std_logic_vector(8 downto 0);
signal c_frac : std_logic_vector(22 downto 0);
begin -- blackbox
setgo : process(clk)
begin
if rising_edge(clk) then
if state = "0011" then
go_out <= '1';
else
go_out <= '0';
end if;
end if;
end process;
main : process(clk)
begin
if rising_edge(clk) then
case state is
when "0000" =>
if go_in = '1' then
temp <= (others => '0');
c_sign <= a(31) xor b(31);
c_exp <= ('0' & a(30 downto 23)) + ('0' & b(30 downto 23));
state <= "0001";
end if;
when "0001" =>
if conv_integer(c_exp) > 382 then
c_exp <= (others => '1');
temp <= (others => '0');
state <= "0011";
else
if conv_integer(c_exp) < 127 then
c_exp <= (others => '0');
else
c_exp <= c_exp - 127;
end if;
temp <= ('1' & a(22 downto 0)) * ('1' & b(22 downto 0));
state <= "0010";
end if;
when "0010" =>
if temp(47) = '1' then
c_exp <= c_exp+1;
c_frac <= temp(46 downto 24);
else
c_frac <= temp(45 downto 23);
end if;
state <= "0011";
when "0011" =>
c <= c_sign & c_exp(7 downto 0) & c_frac;
state <= "0000";
when others => state <= "0000";
end case;
end if;
end process;
end blackbox;
|
bsd-2-clause
|
f0124c7b2a6db2c8ef601e784a58d30e
| 0.496175 | 3.47343 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/fifo_w12_d3_A.vhd
| 2 | 4,437 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w12_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w12_d3_A_shiftReg;
architecture rtl of fifo_w12_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w12_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w12_d3_A is
component fifo_w12_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w12_d3_A_shiftReg : fifo_w12_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
26b0a9b5e14705ca7fe898b89a981ec8
| 0.52558 | 3.4637 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fadd-grafi/fadd/top.vhd
| 1 | 6,179 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity TOP is
port (
MCLK1 : in std_logic;
RS_RX : in std_logic;
RS_TX : out std_logic);
end TOP;
architecture top_body of TOP is
component FloatAdder is
port (
fltIn1 : in std_logic_vector (31 downto 0);
fltIn2 : in std_logic_vector (31 downto 0);
fltOut : out std_logic_vector (31 downto 0));
end component;
component U232C_RECV is
generic (
--WTIME : std_logic_vector(15 downto 0) := x"1B17");
WTIME : std_logic_vector(15 downto 0) := x"0255");
port (
CLK : in std_logic;
OK : in std_logic;
RX : in std_logic;
DATA : out std_logic_vector (7 downto 0);
RECVED : out std_logic);
end component;
component U232C_SEND is
generic (
--WTIME : std_logic_vector(15 downto 0) := x"1ADB");
WTIME : std_logic_vector(15 downto 0) := x"0240");
port (
CLK : in std_logic;
GO : in std_logic;
DATA : in std_logic_vector (7 downto 0);
TX : out std_logic;
SENT : out std_logic);
end component;
signal clk, iclk: std_logic;
signal ok: std_logic := '0';
signal go: std_logic := '0';
signal recved, sent: std_logic;
signal fltIn1, fltIn2, fltOut: std_logic_vector(31 downto 0);
signal fltIn1Buf, fltIn2Buf, fltOutBuf: std_logic_vector(31 downto 0);
signal recvData: std_logic_vector(7 downto 0);
signal sendData: std_logic_vector(7 downto 0);
constant FADD_INST: std_logic_vector(7 downto 0) := x"53";
--constant HOGE_INST: std_logic_vector(7 downto 0) := x"54";
signal fetchState: integer range 0 to 8 := 8;
signal writeState: integer range 0 to 4 := 4;
signal feedState: integer range 0 to 6 := 6;
--signal myrx : std_logic;
--constant myrxrom : std_logic_vector(0 to 31) := ("11111101100101011111110001010101"); -- "\53\54"
--signal countdown : std_logic_vector(15 downto 0) := x"1B17";
--signal count : std_logic_vector(4 downto 0) := "00000";
begin
ib : IBUFG port map (i => MCLK1, o => iclk);
bg : BUFG port map (i => iclk, o => clk);
recv : U232C_RECV port map (
CLK => clk,
OK => ok,
RX => RS_RX,
DATA => recvData,
RECVED => recved);
send : U232C_SEND port map (
CLK => clk,
GO => go,
DATA => sendData,
TX => RS_TX,
SENT => sent);
--myrx <= myrxrom(conv_integer(count));
every_clock_do : process(clk)
begin
if (rising_edge(clk)) then
--if countdown = 0 then
-- countdown <= x"1B17";
-- count <= count+1;
--else
-- countdown <= countdown-1;
--end if;
case feedState is
when 0 =>
fltIn1 <= fltIn1Buf;
fltIn2 <= fltIn2Buf;
feedState <= feedState+1;
when 5 =>
fltOutBuf <= fltOut;
writeState <= 0;
feedState <= feedState+1;
when 6 =>
when others =>
feedState <= feedState+1;
end case;
if (recved = '1' and ok = '0') then
ok <= '1';
end if;
if (recved = '0' and ok = '1') then
ok <= '0';
case fetchState is
when 0 =>
fltIn1Buf(31 downto 24) <= recvData;
fetchState <= 1;
when 1 =>
fltIn1Buf(23 downto 16) <= recvData;
fetchState <= 2;
when 2 =>
fltIn1Buf(15 downto 8) <= recvData;
fetchState <= 3;
when 3 =>
fltIn1Buf( 7 downto 0) <= recvData;
fetchState <= 4;
when 4 =>
fltIn2Buf(31 downto 24) <= recvData;
fetchState <= 5;
when 5 =>
fltIn2Buf(23 downto 16) <= recvData;
fetchState <= 6;
when 6 =>
fltIn2Buf(15 downto 8) <= recvData;
fetchState <= 7;
when 7 =>
fltIn2Buf( 7 downto 0) <= recvData;
fetchState <= 8;
feedState <= 0;
when 8 =>
case recvData is
when FADD_INST =>
fetchState <= 0;
--when HOGE_INST =>
-- fetchState <= 0;
when others =>
end case;
end case;
end if;
if (sent = '1' and go = '0') then
case writeState is
when 0 =>
sendData <= fltOutBuf(31 downto 24);
writeState <= 1;
go <= '1';
when 1 =>
sendData <= fltOutBuf(23 downto 16);
writeState <= 2;
go <= '1';
when 2 =>
sendData <= fltOutBuf(15 downto 8);
writeState <= 3;
go <= '1';
when 3 =>
sendData <= fltOutBuf( 7 downto 0);
writeState <= 4;
go <= '1';
when 4 =>
end case;
end if;
if (sent = '0' and go = '1') then
go <= '0';
end if;
end if;
end process;
faddRegister: FloatAdder port map (
fltIn1 => fltIn1,
fltIn2 => fltIn2,
fltOut => fltOut);
end top_body;
|
bsd-2-clause
|
e296db71e6a952c88a1090f06e6bbd36
| 0.424826 | 4.471056 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
multiplier_booth/multiplier_booth.vhd
| 1 | 4,452 |
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
----------------------------------------------------------------------
--top level design unit
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY booth_multiplier IS
--GENERIC(k : POSITIVE := 7); --input number word length less one
GENERIC(k : POSITIVE := 3); --input number word length less one
PORT(multiplicand, multiplier : IN BIT_VECTOR(k DOWNTO 0);
clock : IN BIT; product : INOUT BIT_VECTOR((2 * k + 1) DOWNTO 0));
END booth_multiplier;
ARCHITECTURE structural OF booth_multiplier IS
SIGNAL mdreg, adderout, carries, augend, tcbuffout : BIT_VECTOR(k DOWNTO 0);
SIGNAL mrreg : BIT_VECTOR((k + 1) DOWNTO 0);
SIGNAL adder_ovfl : BIT;
SIGNAL comp ,clr_mr ,load_mr ,shift_mr ,clr_md ,load_md ,clr_pp ,load_pp ,shift_pp : BIT;
SIGNAL boostate : NATURAL RANGE 0 TO 2*(k + 1);
BEGIN
PROCESS --main clocked process containing all sequential elements
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
--register to hold multiplicand during multiplication
IF clr_md = '1' THEN
mdreg <= (OTHERS => '0'); -- clean multiplicand
ELSIF load_md = '1' THEN
mdreg <= multiplicand; -- assign multiplicand to mdreg register
ELSE
mdreg <= mdreg; -- nothing, dut to correspond "if else end if" annoying syntax.
END IF;
--register/shifter to product pair of bits used to control adder
IF clr_mr = '1' THEN
mrreg <= (OTHERS => '0'); -- clean multiplier
ELSIF load_mr = '1' THEN
mrreg((k + 1) DOWNTO 1) <= multiplier; -- assign multiplier to mrreg register
mrreg(0) <= '0';
ELSIF shift_mr = '1' THEN
mrreg <= mrreg SRL 1;
ELSE
mrreg <= mrreg; -- nothing, dut to correspond "if else end if" annoying syntax.
END IF;
--register/shifter accumulates partial product values
IF clr_pp = '1' THEN
product <= (OTHERS => '0');
ELSIF load_pp = '1' THEN
product(( 2 * k + 1 ) DOWNTO( k + 1 ) ) <= adderout; --add to top half
product(k DOWNTO 0) <= product(k DOWNTO 0); --refresh bootm half
ELSIF shift_pp = '1' THEN
product <= product SRA 1; --shift right with sign extend( arithmetic right shift )
ELSE
product <= product;
END IF;
END PROCESS;
--full adder adds/subtracts partial product to multiplicand
augend <= product( ( 2 * k + 1 ) DOWNTO( k + 1 ) ); -- high half of partial product
addgen : FOR i IN adderout'RANGE GENERATE
lsadder : IF i = 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR comp; -- sum
carries(i) <= (tcbuffout(i) AND augend(i)) OR -- carry
(tcbuffout(i) AND comp) OR
(comp AND augend(i));
END GENERATE;
otheradder : IF i /= 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR carries(i-1);-- sum
carries(i) <= (tcbuffout(i) AND augend(i)) OR -- carry
(tcbuffout(i) AND carries(i-1)) OR
(carries(i-1) AND augend(i));
END GENERATE;
END GENERATE;
--twos comp overflow bit
adder_ovfl <= carries(k-1) XOR carries(k);
--true/complement buffer to generate two's comp of mdreg
tcbuffout <= NOT mdreg WHEN (comp = '1') ELSE mdreg;
--booth multiplier state counter
PROCESS
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
IF boostate < 2*(k + 1) THEN
boostate <= boostate + 1;
ELSE
boostate <= 0;
END IF;
END PROCESS;
--assign control signal values based on state
PROCESS(boostate)
BEGIN
--assign defaults, all registers refresh
comp <= '0';
clr_mr <= '0'; -- multiplier
load_mr <= '0';
shift_mr <= '0';
clr_md <= '0'; -- multiplicand
load_md <= '0';
clr_pp <= '0'; -- partial product
load_pp <= '0';
shift_pp <= '0';
IF boostate = 0 THEN
load_mr <= '1';
load_md <= '1';
clr_pp <= '1';
ELSIF boostate MOD 2 = 0 THEN --boostate = 2,4,6,8 .... even number
shift_mr <= '1'; -- shift multiplier
shift_pp <= '1'; -- shift partial product
ELSE --boostate = 1,3,5,7...... odd number
IF mrreg(0) = mrreg(1) THEN
NULL; --refresh partial product
ELSE
load_pp <= '1'; --update product
END IF;
comp <= mrreg(1); --subract if mrreg(1 DOWNTO 0) ="10"
END IF;
END PROCESS;
END structural;
|
mit
|
d93db8b0ba8835c68a6ecbac9dd8f929
| 0.620845 | 3.191398 | false | false | false | false |
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